ninja: Entering directory `out/gn' [0/1] ACTION //clang/test:check-clang(//llvm/utils/gn/build/toolchain:unix) llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using clang: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using ld.lld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/ld.lld llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using lld-link: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/lld-link llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using ld64.lld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/ld64.lld llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using wasm-ld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/wasm-ld llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using ld.lld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/ld.lld llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using lld-link: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/lld-link llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using ld64.lld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/ld64.lld llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using wasm-ld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/wasm-ld -- Testing: 27911 tests, 64 workers -- Testing: FAIL: Clang :: CodeGen/thinlto-multi-module.ll (1 of 27911) ******************** TEST 'Clang :: CodeGen/thinlto-multi-module.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-multi-module.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-multi-module.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-multi-module.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-multi-module.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-multi-module.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-multi-module.ll # | #0 0x00005619bfe8d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005619bfe8a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005619bfe8dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa5ab505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa5ab55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa5ab505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa5ab4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005619bfe2324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005619bfe23096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005619bfe07f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005619bfab7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005619bfab6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa5ab4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa5ab4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa5ab4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005619bfab6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c (2 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16mf4x4(ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16mf2x4(ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16m1x4(ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16m2x4(ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16m1x4_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16m2x4_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale # | ... # `---data was truncated (10240/10790) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558182c5057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558182c4d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558182c50cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8c28505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8c2855c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8c28505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8c284ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558182be624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558182be6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558182bcaf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055818287a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558182879e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8c284eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8c284ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8c284ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558182879d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c (3 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_bf16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmax.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmax.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_bf16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmax.nxv8bf16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_bf16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmax.u.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmax.u.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_bf16_n_m( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fmax.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_bf16_n_z( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmax.nxv8bf16( %3, %4, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_bf16_n_x( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fmax.u.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055b7a504a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b7a5047515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b7a504acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd034d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd034d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd034d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd034d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b7a4fe024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b7a4fe0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b7a4fc4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b7a4c74176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b7a4c73e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd034d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd034d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd034d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b7a4c73d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c (4 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_i32mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_i32m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_u32mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_u32m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32mf2x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: # | ... # `---data was truncated (10240/16382) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c82972957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c829726515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c829729cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4ce8105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4ce815c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4ce8105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4ce80ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c8296bf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c8296bf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c8296a3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c829353176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c829352e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4ce80eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4ce80ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4ce80ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c829352d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/arm-mve-intrinsics/predicates.c (5 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/predicates.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp16q(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %0) # | %2 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %1) # | %3 = trunc i32 %2 to i16 # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.vctp16(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp16q_m(i32 noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load i32, ptr %a.addr, align 4 # | %4 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %3) # | %5 = and <8 x i1> %2, %4 # | %6 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %5) # | %7 = trunc i32 %6 to i16 # | ret i16 %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp32q(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %0) # | %2 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %1) # | %3 = trunc i32 %2 to i16 # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.vctp32(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp32q_m(i32 noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load i32, ptr %a.addr, align 4 # | %4 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %3) # | %5 = and <4 x i1> %2, %4 # | %6 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %5) # | %7 = trunc i32 %6 to i16 # | ret i16 %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp64q(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call <2 x i1> @llvm.arm.mve.vctp64(i32 %0) # | %2 = call i32 @llvm.arm.mve.pred.v2i.v2i1(<2 x i1> %1) # | %3 = trunc i32 %2 to i16 # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i1> @llvm.arm.mve.vctp64(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.pred.v2i.v2i1(<2 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp64q_m(i32 noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %1) # | %3 = load i32, ptr %a.addr, align 4 # | %4 = call <2 x i1> @llvm.arm.mve.vctp64(i32 %3) # | %5 = and <2 x i1> %2, %4 # | %6 = call i32 @llvm.arm.mve.pred.v2i.v2i1(<2 x i1> %5) # | %7 = trunc i32 %6 to i16 # | ret i16 %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp8q(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %0) # | %2 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %1) # | %3 = trunc i32 %2 to i16 # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.vctp8(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp8q_m(i32 noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1) # | %3 = load i32, ptr %a.addr, align 4 # | %4 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %3) # | %5 = and <16 x i1> %2, %4 # | %6 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %5) # | %7 = trunc i32 %6 to i16 # | ret i16 %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vpnot(i16 noundef zeroext %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | %1 = xor i16 %0, -1 # | ret i16 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vpselq_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load <8 x half>, ptr %a.addr, align 8 # | %4 = load <8 x half>, ptr %b.addr, align 8 # | %5 = select <8 x i1> %2, <8 x half> %3, <8 x half> %4 # | ret <8 x half> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vpselq_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load <4 x float>, ptr %a.addr, align 8 # | %4 = load <4 x float>, ptr %b.addr, align 8 # | %5 = select <4 x i1> %2, <4 x float> %3, <4 x float> %4 # | ret <4 x float> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vpselq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load <8 x i16>, ptr %a.addr, align 8 # | %4 = load <8 x i16>, ptr %b.addr, align 8 # | %5 = select <8 x i1> %2, <8 x i16> %3, <8 x i16> %4 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vpselq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load <4 x i32>, ptr %a.addr, align 8 # | %4 = load <4 x i32>, ptr %b.addr, align 8 # | %5 = select <4 x i1> %2, <4 x i32> %3, <4 x i32> %4 # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vpselq_s64(<2 x i64> noundef %a, <2 x i64> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | %b.addr = alloca <2 x i64>, align 8 # | %p.addr = alloca i16, align 2 # | store <2 x i64> %a, ptr %a.addr, align 8 # | store <2 x i64> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load <2 x i64>, ptr %a.addr, align 8 # | %4 = bitcast <2 x i64> %3 to <4 x i32> # | %5 = load <2 x i64>, ptr %b.addr, align 8 # | %6 = bitcast <2 x i64> %5 to <4 x i32> # | %7 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %6 # | %8 = bitcast <4 x i32> %7 to <2 x i64> # | ret <2 x i64> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vpselq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, ali # | ... # `---data was truncated (10240/13928) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>' # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<> # | #0 0x000055c816c2057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c816c1d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c816c20cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5d9521bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5d952725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5d9521ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5d95203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c816bb624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c816bb6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c816b9af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c81684a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c816849e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5d95204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5d952050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5d952050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c816849d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c (6 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv16i8.nxv16i16.i64.i64( poison, %0, i64 %1, i64 0, # | ... # `---data was truncated (10240/69839) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dcd346157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055dcd345e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055dcd3461cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c58333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c5838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c58333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c5831b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dcd33f724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055dcd33f7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055dcd33dbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055dcd308b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055dcd308ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2c5831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c5831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c5831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dcd308ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/riscv-xandesbfhcvt.c (7 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesbfhcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesbfhcvt -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesbfhcvt -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_fcvt_s_bf16(bfloat noundef %bf) #0 { # | entry: # | %bf.addr = alloca bfloat, align 2 # | store bfloat %bf, ptr %bf.addr, align 2 # | %0 = load bfloat, ptr %bf.addr, align 2 # | %1 = fpext bfloat %0 to float # | ret float %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local bfloat @test_fcvt_bf16_s(float noundef %sf) #0 { # | entry: # | %sf.addr = alloca float, align 4 # | store float %sf, ptr %sf.addr, align 4 # | %0 = load float, ptr %sf.addr, align 4 # | %1 = fptrunc float %0 to bfloat # | ret bfloat %1 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+f,+i,+xandesbfhcvt,+zicsr" } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_f2p2_zicsr2p0_xandesbfhcvt5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dea9fb057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055dea9fad515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055dea9fb0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faa32733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faa3278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faa32733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faa3271b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dea9f4624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055dea9f46096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055dea9f2af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055dea9bda176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055dea9bd9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007faa3271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faa3271d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faa3271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dea9bd9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c (8 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf8x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8mf8x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_ # | ... # `---data was truncated (10240/23574) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559a0dd8957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559a0dd86515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559a0dd89cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb32f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb32f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb32f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb32f231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559a0dd1f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559a0dd1f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559a0dd03f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559a0d9b3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559a0d9b2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb32f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb32f2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb32f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559a0d9b2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c (9 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature -fullfp16 -target-feature +v8a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature -fullfp16 -target-feature +v8a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | %struct.float16x4x2_t = type { [2 x <4 x half>] } # | %struct.float16x8x2_t = type { [2 x <8 x half>] } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vbsl_f16(<4 x i16> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vbsl.i = bitcast <8 x i8> %3 to <4 x i16> # | %vbsl1.i = bitcast <8 x i8> %4 to <4 x i16> # | %vbsl2.i = bitcast <8 x i8> %5 to <4 x i16> # | %vbsl3.i = and <4 x i16> %vbsl.i, %vbsl1.i # | %6 = xor <4 x i16> %vbsl.i, splat (i16 -1) # | %vbsl4.i = and <4 x i16> %6, %vbsl2.i # | %vbsl5.i = or <4 x i16> %vbsl3.i, %vbsl4.i # | %7 = bitcast <4 x i16> %vbsl5.i to <4 x half> # | store <4 x half> %7, ptr %ref.tmp.i, align 8 # | %8 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %8, ptr %__ret.i, align 8 # | %9 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vbslq_f16(<8 x i16> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <8 x half>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store <8 x half> %c, ptr %c.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | %2 = load <8 x half>, ptr %c.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vbsl.i = bitcast <16 x i8> %3 to <8 x i16> # | %vbsl1.i = bitcast <16 x i8> %4 to <8 x i16> # | %vbsl2.i = bitcast <16 x i8> %5 to <8 x i16> # | %vbsl3.i = and <8 x i16> %vbsl.i, %vbsl1.i # | %6 = xor <8 x i16> %vbsl.i, splat (i16 -1) # | %vbsl4.i = and <8 x i16> %6, %vbsl2.i # | %vbsl5.i = or <8 x i16> %vbsl3.i, %vbsl4.i # | %7 = bitcast <8 x i16> %vbsl5.i to <8 x half> # | store <8 x half> %7, ptr %ref.tmp.i, align 16 # | %8 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %8, ptr %__ret.i, align 16 # | %9 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float16x4x2_t @test_vzip_f16(<4 x half> noundef %a, <4 x half> noundef %b) #0 { # | entry: # | %retval.i = alloca %struct.float16x4x2_t, align 8 # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %retval = alloca %struct.float16x4x2_t, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %4 = bitcast <8 x i8> %2 to <4 x half> # | %5 = bitcast <8 x i8> %3 to <4 x half> # | %vzip.i = shufflevector <4 x half> %4, <4 x half> %5, <4 x i32> # | store <4 x half> %vzip.i, ptr %retval.i, align 8 # | %6 = getelementptr inbounds <4 x half>, ptr %retval.i, i32 1 # | %vzip1.i = shufflevector <4 x half> %4, <4 x half> %5, <4 x i32> # | store <4 x half> %vzip1.i, ptr %6, align 8 # | %7 = load %struct.float16x4x2_t, ptr %retval.i, align 8 # | %8 = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %retval, i32 0, i32 0 # | %9 = extractvalue %struct.float16x4x2_t %7, 0 # | store [2 x <4 x half>] %9, ptr %8, align 8 # | %10 = load %struct.float16x4x2_t, ptr %retval, align 8 # | ret %struct.float16x4x2_t %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float16x8x2_t @test_vzipq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %retval.i = alloca %struct.float16x8x2_t, align 16 # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %retval = alloca %struct.float16x8x2_t, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %4 = bitcast <16 x i8> %2 to <8 x half> # | %5 = bitcast <16 x i8> %3 to <8 x half> # | %vzip.i = shufflevector <8 x half> %4, <8 x half> %5, <8 x i32> # | store <8 x half> %vzip.i, ptr %retval.i, align 16 # | %6 = getelementptr inbounds <8 x half>, ptr %retval.i, i32 1 # | %vzip1.i = shufflevector <8 x half> %4, <8 x half> %5, <8 x i32> # | store <8 x half> %vzip1.i, ptr %6, align 16 # | %7 = load %struct.float16x8x2_t, ptr %retval.i, align 16 # | %8 = getelementptr inbounds nuw %struct.float16x8x2_t, ptr %retval, i32 0, i32 0 # | %9 = extractvalue %struct.float16x8x2_t %7, 0 # | store [2 x <8 x half>] %9, ptr %8, align 16 # | %10 = load %struct.float16x8x2_t, ptr %retval, align 16 # | ret %struct.float16x8x2_t %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float16x4x2_t @test_vuzp_f16(<4 x half> noundef %a, <4 x half> noundef %b) #0 { # | entry: # | %retval.i = alloca %struct.float16x4x2_t, align 8 # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %retval = alloca %struct.float16x4x2_t, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %4 = bitcast <8 x i8> %2 to <4 x half> # | %5 = bitcast <8 x i8> %3 to <4 x half> # | %vuzp.i = shufflevector <4 x half> %4, <4 x half> %5, <4 x i32> # | store <4 x half> %vuzp.i, ptr %retval.i, align 8 # | %6 = getelementptr inbounds <4 x half>, ptr %retval.i, i32 1 # | %vuzp1.i = shufflevector <4 x half> %4, <4 x half> %5, <4 x i32> # | store <4 x half> %vuzp1.i, ptr %6, align 8 # | %7 = load %struct.float16x4x2_t, ptr %retval.i, align 8 # | %8 = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %retval, i32 0, i32 0 # | %9 = extractvalue %struct.float16x4x2_t %7, 0 # | store [2 x <4 x half>] %9, ptr %8, align 8 # | %10 = load %struct.float16x4x2_t, ptr %retval, align 8 # | ret %struct.float16x4x2_t %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float16x8x2_t @test_vuzpq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %retval.i = alloca %struct.float16x8x2_t, align 16 # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %retval = alloca %struct.float16x8x2_t, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %4 = bitcast <16 x i8> %2 to <8 x half> # | %5 = bitcast <16 x i8> %3 to <8 x half> # | %vuzp.i = shufflevector <8 x half> %4, <8 x half> %5, <8 x i32> # | store <8 x half> %vuzp.i, ptr %retval.i, align 16 # | %6 = getelementptr inbounds <8 x half>, ptr %retval.i, i32 1 # | %vuzp1.i = shufflevector <8 x half> %4, <8 x half> %5, <8 x i32> # | store <8 x half> %vuzp1.i, ptr %6, align 16 # | %7 = load %struct.float16x8x2_t, ptr %retval.i, align 16 # | %8 = getelementptr inbounds nuw %struct.float16x8x2_t, ptr %retval, i32 0, i32 0 # | %9 = extractvalue %struct.float16x8x2_t %7, 0 # | store [2 x <8 x half>] %9, ptr %8, align 16 # | %10 = load %struct.float16x8x2_t, ptr %retval, align 16 # | ret %struct.float16x8x2_t %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float16x4x2_t @test_vtrn_f16(<4 x half> noundef %a, <4 x half> noundef # | ... # `---data was truncated (10240/31986) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000562c1697d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562c1697a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562c1697dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efe44a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efe44aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efe44a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efe44a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562c1691324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562c16913096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562c168f7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562c165a7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562c165a6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efe44a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efe44a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efe44a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562c165a6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c (10 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind w # | ... # `---data was truncated (10240/20198) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005603f2ade57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005603f2adb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005603f2adecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f84dae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f84daea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f84dae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f84dae31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005603f2a7424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005603f2a74096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005603f2a58f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005603f2708176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005603f2707e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f84dae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f84dae330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f84dae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005603f2707d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c (11 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf4_u16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf2_u16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m1_u16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m2_u16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m4_u16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m8_u16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf4_u16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfclass.mask.nxv1bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf2_u16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfclass.mask.nxv2bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m1_u16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfclass.mask.nxv4bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m2_u16m2_tum( %vm, %vd, %vs2, i64 nounde # | ... # `---data was truncated (10240/26592) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ab06a6657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ab06a63515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ab06a66cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fce69533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fce6958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fce69533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fce6951b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ab069fc24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ab069fc096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ab069e0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ab06690176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ab0668fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fce6951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fce6951d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fce6951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ab0668fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c (12 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Fun # | ... # `---data was truncated (10240/12067) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055973645457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559736451515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559736454cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f25b8333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f25b838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f25b8333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f25b831b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005597363ea24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005597363ea096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005597363cef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055973607e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055973607de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f25b831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f25b831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f25b831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055973607dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c (13 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscal # | ... # `---data was truncated (10240/12235) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005604c78de57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005604c78db515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005604c78decbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7a41249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7a412a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7a41249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7a41231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005604c787424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005604c7874096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005604c7858f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005604c7508176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005604c7507e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7a41232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7a412330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7a412330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005604c7507d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c (14 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16mf4_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16mf4_f32mf2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16mf2_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16mf2_f32m1( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16m1_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16m1_f32m2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16m2_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16m2_f32m4( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv. # | ... # `---data was truncated (10240/51804) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560adcb5057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560adcb4d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560adcb50cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f301cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f301cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f301cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f301cd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560adcae624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560adcae6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560adcacaf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560adc77a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560adc779e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f301cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f301cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f301cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560adc779d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c (15 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr % # | ... # `---data was truncated (10240/20631) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055db3327557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055db33272515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055db33275cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6f76a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6f76a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6f76a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6f76a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055db3320b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055db3320b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055db331eff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055db32e9f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055db32e9ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6f76a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6f76a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6f76a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055db32e9ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c (16 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i64.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv2i64.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv4i64.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv8i64.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056411716a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564117167515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056411716acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff860733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff86078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff860733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff86071b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056411710024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564117100096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005641170e4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564116d94176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564116d93e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff86071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff86071d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff86071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564116d93d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/2008-07-17-no-emit-on-error.c (17 of 27911) ******************** TEST 'Clang :: CodeGen/2008-07-17-no-emit-on-error.c' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 1 rm -f /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc # executed command: rm -f /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -DPASS /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2008-07-17-no-emit-on-error.c -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -DPASS /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2008-07-17-no-emit-on-error.c -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc -disable-output # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc -disable-output # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc -disable-output # | #0 0x0000556093b1d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556093b1a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556093b1dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f11fcb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f11fcb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f11fcb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f11fcb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556093ab324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556093ab3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556093a97f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556093747176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556093746e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f11fcb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f11fcb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f11fcb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556093746d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c (18 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16mf4x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16mf2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16mf4x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16mf2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8 # | ... # `---data was truncated (10240/15457) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b053d3d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b053d3a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b053d3dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2f41505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2f4155c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2f41505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2f414ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b053cd324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b053cd3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b053cb7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b053967176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b053966e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2f414eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2f414ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2f414ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b053966d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c (19 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv4i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv4i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv8i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv8i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv16i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv16i32.i64(, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e5f44f657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e5f44f3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e5f44f6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5b7f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5b7f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5b7f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5b7f831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e5f448c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e5f448c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e5f4470f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e5f4120176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e5f411fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5b7f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5b7f8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5b7f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e5f411fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c (20 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16m1x6_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a837d7357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a837d70515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a837d73cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f53d7e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f53d7ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f53d7e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f53d7e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a837d0924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a837d09096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a837cedf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a83799d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a83799ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f53d7e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f53d7e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f53d7e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a83799cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c (21 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare # | ... # `---data was truncated (10240/20141) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005645046b457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005645046b1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005645046b4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb06f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb06f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb06f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb06f231507 abort ./stdlib/abort.c:85:3 # | #7 0x000056450464a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056450464a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056450462ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005645042de176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005645042dde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb06f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb06f2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb06f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005645042ddd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c (22 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosy # | ... # `---data was truncated (10240/12666) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b5599a957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b5599a6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b5599a9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff43c905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff43c95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff43c905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff43c8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b55993f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b55993f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b559923f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b5595d3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b5595d2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff43c8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff43c8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff43c8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b5595d2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c (23 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564b23df457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564b23df1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564b23df4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f138db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f138db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f138db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f138db1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564b23d8a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564b23d8a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564b23d6ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564b23a1e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564b23a1de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f138db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f138db1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f138db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564b23a1dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c (24 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_u64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c (25 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005597ac79457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005597ac791515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005597ac794cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1301e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1301ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1301e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1301e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005597ac72a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005597ac72a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005597ac70ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005597ac3be176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005597ac3bde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1301e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1301e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1301e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005597ac3bdd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c (26 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf4x6(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf2x6(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16m1x6(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf4x6_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf2x6_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16m1x6_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a96d5b557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a96d5b2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a96d5b5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4e5b905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4e5b95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4e5b905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4e5b8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a96d54b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a96d54b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a96d52ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a96d1df176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a96d1dee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4e5b8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4e5b8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4e5b8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a96d1ded81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c (27 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563cf9b9457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563cf9b91515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563cf9b94cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4ab7d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4ab7d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4ab7d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4ab7d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563cf9b2a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563cf9b2a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563cf9b0ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563cf97be176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563cf97bde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4ab7d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4ab7d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4ab7d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563cf97bdd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c (28 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | # | ... # `---data was truncated (10240/63571) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d33199e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d33199b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d33199ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4e6c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4e6c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4e6c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4e6c51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d33193424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d331934096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d331918f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d3315c8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d3315c7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4e6c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4e6c51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4e6c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d3315c7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c (29 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosy # | ... # `---data was truncated (10240/12666) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005638ea55d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005638ea55a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005638ea55dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5c10733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5c1078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5c10733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5c1071b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005638ea4f324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005638ea4f3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005638ea4d7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005638ea187176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005638ea186e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5c1071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5c1071d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5c1071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005638ea186d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c (30 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1f64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2f64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4f64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8f64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1i64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2i64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4i64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4i64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8i64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @l # | ... # `---data was truncated (10240/62760) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005638fb24c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005638fb249515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005638fb24ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc08d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc08d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc08d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc08d51b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005638fb1e224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005638fb1e2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005638fb1c6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005638fae76176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005638fae75e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc08d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc08d51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc08d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005638fae75d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c (31 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16mf4_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16mf2_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16m1_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16m2_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c (32 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m1x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 # | ... # `---data was truncated (10240/24373) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005602c010e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005602c010b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005602c010ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f569e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f569e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f569e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f569e51b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005602c00a424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005602c00a4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005602c0088f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005602bfd38176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005602bfd37e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f569e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f569e51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f569e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005602bfd37d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c (33 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16mf4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16mf2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m1_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m8_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f32mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f32m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff # | ... # `---data was truncated (10240/44185) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555eafda457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555eafda1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555eafda4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffa04333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffa0438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffa04333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffa0431b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555eafd3a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555eafd3a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555eafd1ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555eaf9ce176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555eaf9cde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ffa0431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffa0431d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffa0431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555eaf9cdd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c (34 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c (35 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ... # `---data was truncated (10240/64958) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563d36e6a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563d36e67515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563d36e6acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4a83533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4a8358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4a83533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4a8351b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563d36e0024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563d36e00096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563d36de4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563d36a94176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563d36a93e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4a8351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4a8351d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4a8351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563d36a93d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c (36 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vs # | ... # `---data was truncated (10240/95355) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562fb7cb257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562fb7caf515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562fb7cb2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f200fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f200faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f200fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f200fa31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562fb7c4824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562fb7c48096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562fb7c2cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562fb78dc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562fb78dbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f200fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f200fa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f200fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562fb78dbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c (37 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m4( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c (38 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_i8mf4x8(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005578b7b7757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005578b7b74515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005578b7b77cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc942a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc942aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc942a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc942a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005578b7b0d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005578b7b0d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005578b7af1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005578b77a1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005578b77a0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc942a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc942a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc942a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005578b77a0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c (39 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c (40 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563db6ad857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563db6ad5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563db6ad8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f992e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f992e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f992e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f992e71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563db6a6e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563db6a6e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563db6a52f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563db6702176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563db6701e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f992e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f992e71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f992e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563db6701d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c (41 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16mf4_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16mf4_f32mf2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16mf2_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16mf2_f32m1( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16m1_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16m1_f32m2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16m2_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16m2_f32m4( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc # | ... # `---data was truncated (10240/51796) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056295b08557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056295b082515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056295b085cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc882a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc882aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc882a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc882a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056295b01b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056295b01b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056295affff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056295acaf176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056295acaee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc882a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc882a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc882a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056295acaed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c (42 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_i8mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef # | ... # `---data was truncated (10240/69988) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564c7ad7157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564c7ad6e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564c7ad71cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fde6cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fde6cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fde6cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fde6cf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564c7ad0724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564c7ad07096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564c7acebf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564c7a99b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564c7a99ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fde6cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fde6cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fde6cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564c7a99ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c (43 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf1.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv1i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf1.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv2i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf1.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv4i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf1.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv8i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf1.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv16i32.i64.i64(, , i64 immarg, i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056229a2e057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056229a2dd515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056229a2e0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fab74133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fab7418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fab74133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fab7411b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056229a27624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056229a276096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056229a25af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562299f0a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562299f09e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fab7411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fab7411d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fab7411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562299f09d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c (44 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0. # | ... # `---data was truncated (10240/82975) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b8057ea57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b8057e7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b8057eacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7080b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7080b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7080b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7080b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b80578024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b805780096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b805764f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b805414176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b805413e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7080b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7080b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7080b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b805413d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c (45 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8mf8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8mf4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv16i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv16i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv32i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv32i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv64i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv64i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_u8mf8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_u8mf4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_u8mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_u8m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr % # | ... # `---data was truncated (10240/29809) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005586bb81957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005586bb816515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005586bb819cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa341733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa34178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa341733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa34171b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005586bb7af24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005586bb7af096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005586bb793f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005586bb443176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005586bb442e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa34171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa34171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa34171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005586bb442d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c (46 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i64m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i64m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i64.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c (47 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055de5b00f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055de5b00c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055de5b00fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6bdcc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6bdcc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6bdcc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6bdcc03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055de5afa524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055de5afa5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055de5af89f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055de5ac39176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055de5ac38e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6bdcc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6bdcc050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6bdcc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055de5ac38d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c (48 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563107de657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563107de3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563107de6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb59b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb59b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb59b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb59b631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563107d7c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563107d7c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563107d60f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563107a10176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563107a0fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb59b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb59b6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb59b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563107a0fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c (49 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055abfd13557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055abfd132515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055abfd135cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbad1d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbad1d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbad1d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbad1ced507 abort ./stdlib/abort.c:85:3 # | #7 0x000055abfd0cb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055abfd0cb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055abfd0aff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055abfcd5f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055abfcd5ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbad1ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbad1cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbad1cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055abfcd5ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c (50 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556f8691b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556f86918515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556f8691bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1a21133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1a2118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1a21133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1a2111b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556f868b124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556f868b1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556f86895f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556f86545176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556f86544e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1a2111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1a2111d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1a2111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556f86544d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/builtins-loongarch.c (51 of 27911) ******************** TEST 'Clang :: CodeGen/builtins-loongarch.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple loongarch32 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple loongarch32 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "loongarch32" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_eh_return_data_regno() #0 { # | entry: # | %res = alloca i32, align 4 # | store volatile i32 4, ptr %res, align 4 # | store volatile i32 5, ptr %res, align 4 # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit" } # | # | !llvm.module.flags = !{!0} # | !llvm.ident = !{!1} # | # | !0 = !{i32 1, !"target-abi", !"ilp32d"} # | !1 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055df5495457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055df54951515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055df54954cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f916f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f916f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f916f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f916f91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055df548ea24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055df548ea096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055df548cef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055df5457e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055df5457de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f916f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f916f91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f916f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055df5457dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c (52 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055db2cca257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055db2cc9f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055db2cca2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc680c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc680ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc680c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc680c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055db2cc3824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055db2cc38096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055db2cc1cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055db2c8cc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055db2c8cbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc680c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc680c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc680c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055db2c8cbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c (53 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16mf4_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16mf4_f32mf2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16mf2_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16mf2_f32m1( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16m1_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16m1_f32m2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16m2_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16m2_f32m4( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.bf16.nxv8bf16.i6 # | ... # `---data was truncated (10240/51694) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b4bbd6957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b4bbd66515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b4bbd69cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7ea5f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7ea5f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7ea5f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7ea5f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b4bbcff24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b4bbcff096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b4bbce3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b4bb993176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b4bb992e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7ea5f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7ea5f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7ea5f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b4bb992d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c (54 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/arm-mve-intrinsics/cplusplus.cpp (55 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/cplusplus.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local arm_aapcs_vfpcc noundef <8 x i16> @_Z16test_vbicq_n_s1617__simd128_int16_t(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = and <8 x i16> %0, splat (i16 11007) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local arm_aapcs_vfpcc noundef <4 x i32> @_Z16test_vbicq_n_u3218__simd128_uint32_t(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = and <4 x i32> %0, splat (i32 -8193) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local arm_aapcs_vfpcc noundef <4 x i32> @_Z16test_vorrq_n_s3217__simd128_int32_t(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = or <4 x i32> %0, splat (i32 65536) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local arm_aapcs_vfpcc noundef <8 x i16> @_Z16test_vorrq_n_u1618__simd128_uint16_t(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = or <8 x i16> %0, splat (i16 -4096) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local arm_aapcs_vfpcc noundef zeroext i16 @_Z16test_vcmpeqq_f1619__simd128_float16_tS_(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = fcmp oeq <8 x half> %0, %1 # | %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1>) #1 # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local arm_aapcs_vfpcc noundef zeroext i16 @_Z18test_vcmpeqq_n_f1619__simd128_float16_tDh(<8 x half> noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca half, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store half %b, ptr %b.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load half, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x half> poison, half %1, i64 0 # | %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer # | %2 = fcmp oeq <8 x half> %0, %.splat # | %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local arm_aapcs_vfpcc noundef <8 x i16> @_Z14test_vld1q_u16PKt(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <8 x i16>, ptr %0, align 2 # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local arm_aapcs_vfpcc void @_Z16test_vst1q_p_s32Pi17__simd128_int32_tt(ptr noundef %base, <4 x i32> noundef %value, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %value.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store <4 x i32> %value, ptr %value.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %value.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 4 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | call void @llvm.masked.store.v4i32.p0(<4 x i32> %0, ptr align 4 %1, <4 x i1> %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr captures(none), <4 x i1>) #2 # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local arm_aapcs_vfpcc noundef <2 x i64> @_Z30test_vldrdq_gather_base_wb_s64P18__simd128_uint64_t(ptr noundef %addr) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | store ptr %addr, ptr %addr.addr, align 4 # | %0 = load ptr, ptr %addr.addr, align 4 # | %1 = load <2 x i64>, ptr %0, align 8 # | %2 = call { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.v2i64.v2i64(<2 x i64> %1, i32 576) # | %3 = extractvalue { <2 x i64>, <2 x i64> } %2, 1 # | store <2 x i64> %3, ptr %0, align 8 # | %4 = extractvalue { <2 x i64>, <2 x i64> } %2, 0 # | ret <2 x i64> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.v2i64.v2i64(<2 x i64>, i32) #3 # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local arm_aapcs_vfpcc void @_Z31test_vstrwq_scatter_base_wb_u32P18__simd128_uint32_tS_(ptr noundef %addr, <4 x i32> noundef %value) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | %value.addr = alloca <4 x i32>, align 8 # | store ptr %addr, ptr %addr.addr, align 4 # | store <4 x i32> %value, ptr %value.addr, align 8 # | %0 = load ptr, ptr %addr.addr, align 4 # | %1 = load <4 x i32>, ptr %0, align 8 # | %2 = load <4 x i32>, ptr %value.addr, align 8 # | %3 = call <4 x i32> @llvm.arm.mve.vstr.scatter.base.wb.v4i32.v4i32(<4 x i32> %1, i32 64, <4 x i32> %2) # | store <4 x i32> %3, ptr %0, align 8 # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare <4 x i32> @llvm.arm.mve.vstr.scatter.base.wb.v4i32.v4i32(<4 x i32>, i32, <4 x i32>) #4 # | # | attributes #0 = { mustprogress noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | attributes #3 = { nocallback nofree nosync nounwind willreturn memory(read) } # | attributes #4 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b77141057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b77140d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b771410cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f27d7d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f27d7d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f27d7d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f27d7d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b7713a624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b7713a6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b77138af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b77103a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b771039e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f27d7d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f27d7d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f27d7d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b771039d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c (56 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none # | ... # `---data was truncated (10240/61673) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557a23e1257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557a23e0f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557a23e12cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe773449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe7734a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe773449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe773431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557a23da824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557a23da8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557a23d8cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557a23a3c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557a23a3be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe773432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe7734330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe7734330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557a23a3bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c (57 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056423426457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564234261515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564234264cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe6cb249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe6cb2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe6cb249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe6cb231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005642341fa24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005642341fa096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005642341def49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564233e8e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564233e8de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe6cb232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe6cb2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe6cb2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564233e8dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c (58 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005569a752857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005569a7525515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005569a7528cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1934733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f193478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1934733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f193471b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005569a74be24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005569a74be096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005569a74a2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005569a7152176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005569a7151e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f193471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f193471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f193471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005569a7151d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c (59 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f32m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/128444) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b2c89e657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b2c89e3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b2c89e6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8cbc849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8cbc8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8cbc849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8cbc831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b2c897c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b2c897c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b2c8960f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b2c8610176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b2c860fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8cbc832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8cbc8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8cbc8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b2c860fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c (60 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/distributed-thin-lto/newpm.ll (61 of 27911) ******************** TEST 'Clang :: CodeGen/distributed-thin-lto/newpm.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 11 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/newpm.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/newpm.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/newpm.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/newpm.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/newpm.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/newpm.ll # | #0 0x0000555d8519357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555d85190515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555d85193cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa55441bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa5544725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa55441ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa554403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555d8512924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555d85129096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555d8510df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555d84dbd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555d84dbce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa554404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa5544050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa5544050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555d84dbcd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c (62 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m1x3_tum(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c (63 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_x_f_v_i32mf2(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c (64 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16mf4x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16mf4x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_u16mf4x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_u16mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_u16m1x6_m(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c (65 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c (66 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m1( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m8( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf4_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf2_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m1_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.mask.nxv4f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.mask.nxv4f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m2_m( %mask, %op1, float noun # | ... # `---data was truncated (10240/25091) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056270ba9e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056270ba9b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056270ba9ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9899c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9899ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9899c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9899c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056270ba3424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056270ba34096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056270ba18f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056270b6c8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056270b6c7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9899c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9899c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9899c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056270b6c7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c (67 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf4x7_tumu( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | ... # `---data was truncated (10240/18506) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565351a7657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000565351a73515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000565351a76cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4758133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f475818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4758133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f475811b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565351a0c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000565351a0c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005653519f0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005653516a0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056535169fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f475811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f475811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f475811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056535169fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c (68 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c (69 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fdf82b857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fdf82b5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fdf82b8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f264f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f264f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f264f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f264f11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fdf824e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fdf824e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fdf8232f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fdf7ee2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fdf7ee1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f264f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f264f11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f264f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fdf7ee1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c (70 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m1_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align # | ... # `---data was truncated (10240/26572) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056341208d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056341208a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056341208dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdf9e01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdf9e0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdf9e01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdf9e003507 abort ./stdlib/abort.c:85:3 # | #7 0x000056341202324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563412023096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563412007f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563411cb7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563411cb6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fdf9e004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdf9e0050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdf9e0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563411cb6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c (71 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i64m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i64m1( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv1i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i64m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i64m2( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i64m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i64m4( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i64m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i64m8( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i64m1_m( %mask, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load , ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.mask.nxv1i64.nxv1i64.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i64m1_m( %mask, %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load i64, ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call < # | ... # `---data was truncated (10240/18691) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005621f448a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005621f4487515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005621f448acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2875f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2875f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2875f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2875f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005621f442024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005621f4420096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005621f4404f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005621f40b4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005621f40b3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2875f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2875f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2875f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005621f40b3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c (72 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv4 # | ... # `---data was truncated (10240/47636) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564eb823357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564eb8230515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564eb8233cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6830249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f68302a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6830249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6830231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564eb81c924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564eb81c9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564eb81adf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564eb7e5d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564eb7e5ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6830232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f68302330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f68302330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564eb7e5cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c (73 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/48305) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dbba22d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055dbba22a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055dbba22dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1083a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1083aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1083a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1083a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dbba1c324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055dbba1c3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055dbba1a7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055dbb9e57176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055dbb9e56e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1083a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1083a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1083a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dbb9e56d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGenCoroutines/coro-gro4.cpp (74 of 27911) ******************** TEST 'Clang :: CodeGenCoroutines/coro-gro4.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 -O2 -disable-llvm-passes -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes='default,default' -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 -O2 -disable-llvm-passes -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | %struct.wrapper = type { %struct.task } # | %struct.task = type { %"struct.std::coroutine_handle" } # | %"struct.std::coroutine_handle" = type { %"struct.std::coroutine_handle.0" } # | %"struct.std::coroutine_handle.0" = type { ptr } # | %"struct.task::promise_type" = type { i8 } # | %"struct.std::suspend_always" = type { i8 } # | # | $_ZN4task12promise_type17get_return_objectEv = comdat any # | # | $_ZN4task12promise_type15initial_suspendEv = comdat any # | # | $_ZNSt14suspend_always11await_readyEv = comdat any # | # | $_ZNSt14suspend_always13await_suspendESt16coroutine_handleIvE = comdat any # | # | $_ZNSt16coroutine_handleIN4task12promise_typeEE12from_addressEPv = comdat any # | # | $_ZNSt14suspend_always12await_resumeEv = comdat any # | # | $_ZN4task12promise_type11return_voidEv = comdat any # | # | $_ZN4task12promise_type13final_suspendEv = comdat any # | # | $_ZN7wrapperC1EO4task = comdat any # | # | $_ZN4taskD1Ev = comdat any # | # | $_ZNSt16coroutine_handleIN4task12promise_typeEE12from_promiseERS1_ = comdat any # | # | $_ZN4taskC1ESt16coroutine_handleINS_12promise_typeEE = comdat any # | # | $_ZNSt16coroutine_handleIN4task12promise_typeEEC1Ev = comdat any # | # | $_ZNSt16coroutine_handleIN4task12promise_typeEEC2Ev = comdat any # | # | $_ZNSt16coroutine_handleIvEC2Ev = comdat any # | # | $_ZN4taskC2ESt16coroutine_handleINS_12promise_typeEE = comdat any # | # | $_ZN7wrapperC2EO4task = comdat any # | # | $_ZN4taskC1EOS_ = comdat any # | # | $_ZN4taskC2EOS_ = comdat any # | # | $_ZNSt16coroutine_handleIvEaSEDn = comdat any # | # | $_ZN4taskD2Ev = comdat any # | # | $_ZNKSt16coroutine_handleIvEcvbEv = comdat any # | # | $_ZNKSt16coroutine_handleIvE7destroyEv = comdat any # | # | ; Function Attrs: mustprogress nounwind presplitcoroutine # | define dso_local void @_Z2fnv(ptr dead_on_unwind noalias writable sret(%struct.wrapper) align 8 %agg.result) #0 { # | entry: # | %result.ptr = alloca ptr, align 8 # | %gro.active = alloca i1, align 1 # | %__promise = alloca %"struct.task::promise_type", align 1 # | %__coro_gro = alloca %struct.task, align 8, !coro.outside.frame !6 # | %ref.tmp = alloca %"struct.std::suspend_always", align 1 # | %undef.agg.tmp = alloca %"struct.std::suspend_always", align 1 # | %ref.tmp2 = alloca %"struct.std::suspend_always", align 1 # | %undef.agg.tmp3 = alloca %"struct.std::suspend_always", align 1 # | store ptr %agg.result, ptr %result.ptr, align 8 # | %0 = call token @llvm.coro.id(i32 16, ptr %__promise, ptr null, ptr null) # | %1 = call i1 @llvm.coro.alloc(token %0) # | br i1 %1, label %coro.alloc, label %coro.init # | # | coro.alloc: ; preds = %entry # | %2 = call i64 @llvm.coro.size.i64() # | %call = call noalias noundef nonnull ptr @_Znwm(i64 noundef %2) #14 # | br label %coro.init # | # | coro.init: ; preds = %coro.alloc, %entry # | %3 = phi ptr [ null, %entry ], [ %call, %coro.alloc ] # | %4 = call ptr @llvm.coro.begin(token %0, ptr %3) # | store i1 false, ptr %gro.active, align 1 # | call void @llvm.lifetime.start.p0(ptr %__promise) #9 # | call void @llvm.lifetime.start.p0(ptr %__coro_gro) #9 # | call void @_ZN4task12promise_type17get_return_objectEv(ptr dead_on_unwind writable sret(%struct.task) align 8 %__coro_gro, ptr noundef nonnull align 1 dereferenceable(1) %__promise) #9 # | store i1 true, ptr %gro.active, align 1 # | call void @llvm.lifetime.start.p0(ptr %ref.tmp) #9 # | call void @_ZN4task12promise_type15initial_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise) #9 # | %call1 = call noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp) #9 # | br i1 %call1, label %init.ready, label %init.suspend # | # | init.suspend: ; preds = %coro.init # | %5 = call token @llvm.coro.save(ptr null) # | call void @llvm.coro.await.suspend.void(ptr %ref.tmp, ptr %4, ptr @_Z2fnv.__await_suspend_wrapper__init) #9 # | %6 = call i8 @llvm.coro.suspend(token %5, i1 false) # | switch i8 %6, label %pre.gvo.conv [ # | i8 0, label %init.ready # | i8 1, label %init.cleanup # | ] # | # | init.cleanup: ; preds = %init.suspend # | br label %cleanup # | # | init.ready: ; preds = %init.suspend, %coro.init # | call void @_ZNSt14suspend_always12await_resumeEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp) #9 # | br label %cleanup # | # | cleanup: ; preds = %init.ready, %init.cleanup # | %cleanup.dest.slot.0 = phi i32 [ 0, %init.ready ], [ 2, %init.cleanup ] # | call void @llvm.lifetime.end.p0(ptr %ref.tmp) #9 # | switch i32 %cleanup.dest.slot.0, label %unreachable [ # | i32 0, label %cleanup.cont # | i32 2, label %coro.cleanup # | ] # | # | cleanup.cont: ; preds = %cleanup # | call void @_ZN4task12promise_type11return_voidEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise) #9 # | br label %coro.final # | # | coro.final: ; preds = %cleanup.cont # | call void @llvm.lifetime.start.p0(ptr %ref.tmp2) #9 # | call void @_ZN4task12promise_type13final_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise) #9 # | %call4 = call noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp2) #9 # | br i1 %call4, label %final.ready, label %final.suspend # | # | final.suspend: ; preds = %coro.final # | %7 = call token @llvm.coro.save(ptr null) # | call void @llvm.coro.await.suspend.void(ptr %ref.tmp2, ptr %4, ptr @_Z2fnv.__await_suspend_wrapper__final) #9 # | %8 = call i8 @llvm.coro.suspend(token %7, i1 true) # | switch i8 %8, label %pre.gvo.conv [ # | i8 0, label %final.ready # | i8 1, label %final.cleanup # | ] # | # | final.cleanup: ; preds = %final.suspend # | br label %cleanup5 # | # | final.ready: ; preds = %final.suspend, %coro.final # | call void @_ZNSt14suspend_always12await_resumeEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp2) #9 # | br label %cleanup5 # | # | cleanup5: ; preds = %final.ready, %final.cleanup # | %cleanup.dest.slot.1 = phi i32 [ 0, %final.ready ], [ 2, %final.cleanup ] # | call void @llvm.lifetime.end.p0(ptr %ref.tmp2) #9 # | switch i32 %cleanup.dest.slot.1, label %unreachable [ # | i32 0, label %pre.gvo.conv # | i32 2, label %coro.cleanup # | ] # | # | pre.gvo.conv: ; preds = %cleanup5, %final.suspend, %init.suspend # | %9 = phi i1 [ true, %cleanup5 ], [ false, %final.suspend ], [ false, %init.suspend ] # | %InRamp = call i1 @llvm.coro.is_in_ramp() # | br i1 %InRamp, label %gro.conv, label %after.gro.conv # | # | gro.conv: ; preds = %pre.gvo.conv # | call void @_ZN7wrapperC1EO4task(ptr noundef nonnull align 8 dereferenceable(8) %agg.result, ptr noundef nonnull align 8 dereferenceable(8) %__coro_gro) #9 # | %cleanup.is_active = load i1, ptr %gro.active, align 1 # | br i1 %cleanup.is_active, label %cleanup.action, label %cleanup.done # | # | cleanup.action: ; preds = %gro.conv # | call void @_ZN4taskD1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) %__coro_gro) #9 # | br label %cleanup.done # | # | cleanup.done: ; preds = %cleanup.action, %gro.conv # | br label %after.gro.conv # | # | after.gro.conv: ; preds = %cleanup.done, %pre.gvo.conv # | br i1 %9, label %cleanup.cont7, label %coro.ret # | # | cleanup.cont7: ; preds = %after.gro.conv # | br label %coro.cleanup # | # | coro.cleanup: ; preds = %cleanup.cont7, %cleanup5, %cleanup # | call void @llvm.lifetime.end.p0(ptr %__coro_gro) #9 # | call void @llvm.lifetime.end.p0(ptr %__promise) #9 # | %10 = call ptr @llvm.coro.free(token %0, ptr %4) # | %11 = icmp ne ptr %10, null # | br i1 %11, label %coro.free, label %after.coro.free # | # | coro.free: ; preds = %coro.cleanup # | %12 = call i64 @llvm.coro.size.i64() # | call void @_ZdlPvm(ptr noundef %10, i64 noundef %12) #9 # | br label %after.coro.free # | # | after.coro.free: ; preds = %coro.cleanup, %coro.free # | call void @llvm.coro.dead(ptr %4) # | br label %coro.ret # | # | coro.ret: ; preds = %after.coro.free, %after.gro.conv # | call void @llvm.coro.end(ptr null, i1 false, token none) # | ret void # | # | unreachable: ; preds = %cleanup5, %cleanup # | unreachable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare token @llvm.coro.id(i32, ptr readnone, ptr readonly captures(none), ptr) #1 # | # | ; Function Attrs: nounwind memory(none) # | declare i1 @llvm.coro.alloc(token) #2 # | # | ; Function Attrs: nobuiltin allocsize(0) # | declare noundef nonnull ptr @_Znwm(i64 noundef) #3 # | # | ; Function Attrs: nounwind memory(none) # | declare i64 @llvm.coro.size.i64() #2 # | # | ; Function Attrs: nounwind memory(argmem: readwrite) # | declare ptr @llvm.coro.begin(token, ptr writeonly) #4 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.lifetime.start.p0(ptr captures(none)) #5 # | # | ; Function Attrs: mustprogress nounwind # | define linkonce_odr void @_ZN4task12promise_type17get_return_objectEv(ptr dead_on_unwind noalias writable sret(%struct.task) align 8 %agg.result, ptr noundef nonnull align 1 dereferenceable(1) %this) #6 comdat align 2 { # | entry: # | %result.ptr = alloca ptr, align 8 # | %this.addr = alloca ptr, align 8 # | %agg.tmp = alloca %"struct.std::coroutine_handle", align 8 # | store ptr %agg.result, ptr %result.ptr, align 8 # | store ptr %this, ptr %this.addr, align 8, !tbaa !7 # | %this1 = load ptr, ptr %this.addr, align 8 # | %call = call ptr @_ZNSt16coroutine_handleIN4task12promise_typeEE12from_promiseERS1_(ptr noundef nonnull align 1 dereferenceable(1) %this1) # | %coerce.dive = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %agg.tmp, i32 0, i32 0 # | %coerce.dive2 = getelementptr inbounds nuw %"s # | ... # `---data was truncated (10240/31146) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt '-passes=default,default' -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=default,default -S # | #0 0x000055565c60d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055565c60a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055565c60dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1b96b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1b96b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1b96b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1b96b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055565c5a324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055565c5a3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055565c587f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055565c237176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055565c236e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1b96b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1b96b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1b96b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055565c236d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c (75 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv16f16 # | ... # `---data was truncated (10240/69305) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a3aeac957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a3aeac6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a3aeac9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdef0133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdef018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdef0133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdef011b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a3aea5f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a3aea5f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a3aea43f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a3ae6f3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a3ae6f2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fdef011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdef011d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdef011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a3ae6f2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c (76 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c (77 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m4_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c (78 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_i8mf4x7(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ba04fe057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ba04fdd515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ba04fe0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2d3d21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2d3d2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2d3d21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2d3d203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ba04f7624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ba04f76096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ba04f5af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ba04c0a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ba04c09e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2d3d204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2d3d2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2d3d2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ba04c09d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c (79 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005633488da57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005633488d7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005633488dacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6754649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f67546a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6754649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6754631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056334887024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563348870096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563348854f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563348504176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563348503e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6754632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f67546330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f67546330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563348503d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c (80 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c95adb157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c95adae515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c95adb1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa3fb449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa3fb4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa3fb449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa3fb431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c95ad4724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c95ad47096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c95ad2bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c95a9db176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c95a9dae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa3fb432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa3fb4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa3fb4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c95a9dad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/neon-fma.c (81 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon-fma.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vmla_n_f32(<2 x float> noundef %a, <2 x float> noundef %b, float noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__p2.addr.i = alloca float, align 4 # | %__ret.i = alloca <2 x float>, align 8 # | %.compoundliteral.i = alloca <2 x float>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | %c.addr = alloca float, align 4 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | store float %c, ptr %c.addr, align 4 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | %2 = load float, ptr %c.addr, align 4 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | store float %2, ptr %__p2.addr.i, align 4 # | %3 = load <2 x float>, ptr %__p0.addr.i, align 8 # | %4 = load <2 x float>, ptr %__p1.addr.i, align 8 # | %5 = load float, ptr %__p2.addr.i, align 4 # | %vecinit.i = insertelement <2 x float> poison, float %5, i32 0 # | %6 = load float, ptr %__p2.addr.i, align 4 # | %vecinit1.i = insertelement <2 x float> %vecinit.i, float %6, i32 1 # | store <2 x float> %vecinit1.i, ptr %.compoundliteral.i, align 8 # | %7 = load <2 x float>, ptr %.compoundliteral.i, align 8 # | %mul.i = fmul <2 x float> %4, %7 # | %add.i = fadd <2 x float> %3, %mul.i # | store <2 x float> %add.i, ptr %__ret.i, align 8 # | %8 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vmlaq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <4 x float>, align 16 # | %__p2.addr.i = alloca float, align 4 # | %__ret.i = alloca <4 x float>, align 16 # | %.compoundliteral.i = alloca <4 x float>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <4 x float>, align 16 # | %c.addr = alloca float, align 4 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <4 x float> %b, ptr %b.addr, align 16 # | store float %c, ptr %c.addr, align 4 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | %2 = load float, ptr %c.addr, align 4 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <4 x float> %1, ptr %__p1.addr.i, align 16 # | store float %2, ptr %__p2.addr.i, align 4 # | %3 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %4 = load <4 x float>, ptr %__p1.addr.i, align 16 # | %5 = load float, ptr %__p2.addr.i, align 4 # | %vecinit.i = insertelement <4 x float> poison, float %5, i32 0 # | %6 = load float, ptr %__p2.addr.i, align 4 # | %vecinit1.i = insertelement <4 x float> %vecinit.i, float %6, i32 1 # | %7 = load float, ptr %__p2.addr.i, align 4 # | %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %7, i32 2 # | %8 = load float, ptr %__p2.addr.i, align 4 # | %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %8, i32 3 # | store <4 x float> %vecinit3.i, ptr %.compoundliteral.i, align 16 # | %9 = load <4 x float>, ptr %.compoundliteral.i, align 16 # | %mul.i = fmul <4 x float> %4, %9 # | %add.i = fadd <4 x float> %3, %mul.i # | store <4 x float> %add.i, ptr %__ret.i, align 16 # | %10 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vmlsq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <4 x float>, align 16 # | %__p2.addr.i = alloca float, align 4 # | %__ret.i = alloca <4 x float>, align 16 # | %.compoundliteral.i = alloca <4 x float>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <4 x float>, align 16 # | %c.addr = alloca float, align 4 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <4 x float> %b, ptr %b.addr, align 16 # | store float %c, ptr %c.addr, align 4 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | %2 = load float, ptr %c.addr, align 4 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <4 x float> %1, ptr %__p1.addr.i, align 16 # | store float %2, ptr %__p2.addr.i, align 4 # | %3 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %4 = load <4 x float>, ptr %__p1.addr.i, align 16 # | %5 = load float, ptr %__p2.addr.i, align 4 # | %vecinit.i = insertelement <4 x float> poison, float %5, i32 0 # | %6 = load float, ptr %__p2.addr.i, align 4 # | %vecinit1.i = insertelement <4 x float> %vecinit.i, float %6, i32 1 # | %7 = load float, ptr %__p2.addr.i, align 4 # | %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %7, i32 2 # | %8 = load float, ptr %__p2.addr.i, align 4 # | %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %8, i32 3 # | store <4 x float> %vecinit3.i, ptr %.compoundliteral.i, align 16 # | %9 = load <4 x float>, ptr %.compoundliteral.i, align 16 # | %mul.i = fmul <4 x float> %4, %9 # | %sub.i = fsub <4 x float> %3, %mul.i # | store <4 x float> %sub.i, ptr %__ret.i, align 16 # | %10 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vmls_n_f32(<2 x float> noundef %a, <2 x float> noundef %b, float noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__p2.addr.i = alloca float, align 4 # | %__ret.i = alloca <2 x float>, align 8 # | %.compoundliteral.i = alloca <2 x float>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | %c.addr = alloca float, align 4 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | store float %c, ptr %c.addr, align 4 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | %2 = load float, ptr %c.addr, align 4 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | store float %2, ptr %__p2.addr.i, align 4 # | %3 = load <2 x float>, ptr %__p0.addr.i, align 8 # | %4 = load <2 x float>, ptr %__p1.addr.i, align 8 # | %5 = load float, ptr %__p2.addr.i, align 4 # | %vecinit.i = insertelement <2 x float> poison, float %5, i32 0 # | %6 = load float, ptr %__p2.addr.i, align 4 # | %vecinit1.i = insertelement <2 x float> %vecinit.i, float %6, i32 1 # | store <2 x float> %vecinit1.i, ptr %.compoundliteral.i, align 8 # | %7 = load <2 x float>, ptr %.compoundliteral.i, align 8 # | %mul.i = fmul <2 x float> %4, %7 # | %sub.i = fsub <2 x float> %3, %mul.i # | store <2 x float> %sub.i, ptr %__ret.i, align 8 # | %8 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vmla_lane_f32_0(<2 x float> noundef %a, <2 x float> noundef %b, <2 x float> noundef %v) #0 { # | entry: # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | %v.addr = alloca <2 x float>, align 8 # | %__ret_68 = alloca <2 x float>, align 8 # | %__s0_68 = alloca <2 x float>, align 8 # | %__s1_68 = alloca <2 x float>, align 8 # | %__s2_68 = alloca <2 x float>, align 8 # | %__ret = alloca <2 x float>, align 8 # | %__s0 = alloca <2 x float>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x float>, align 8 # | %tmp1 = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | store <2 x float> %v, ptr %v.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__s0_68, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | store <2 x float> %1, ptr %__s1_68, align 8 # | %2 = load <2 x float>, ptr %v.addr, align 8 # | store <2 x float> %2, ptr %__s2_68, align 8 # | %3 = load <2 x float>, ptr %__s0_68, align 8 # | %4 = load <2 x float>, ptr %__s1_68, align 8 # | %5 = load <2 x float>, ptr %__s2_68, align 8 # | store <2 x float> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x float> # | %lane = shufflevector <2 x float> %7, <2 x float> %7, <2 x i32> zeroinitializer # | store <2 x float> %lane, ptr %ref.tmp, align 8 # | %8 = load <2 x float>, ptr %ref.tmp, align 8 # | store <2 x float> %8, ptr %__ret, align 8 # | %9 = load <2 x float>, ptr %__ret, align 8 # | store <2 x float> %9, ptr %tmp, align 8 # | %10 = load <2 x float>, ptr %tmp, align 8 # | %mul = fmul <2 x float> %4, %10 # | %add = fadd <2 x float> %3, %mul # | store <2 x float> %add, ptr %__ret_68, align 8 # | %11 = load <2 x float>, ptr %__ret_68, align 8 # | store <2 x float> %11, ptr %tmp1, align 8 # | %12 = load <2 x float>, ptr %tmp1, align 8 # | ret <2 x float> %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vmlaq_lane_f32_0(<4 x float> noundef %a, <4 x float> noundef %b, <2 x float> noundef %v) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <4 x float>, align 16 # | %v.addr = alloca <2 x float>, align 8 # | %__ret_58 = alloca <4 x float>, align 16 # | %__s0_58 = alloca <4 x float>, align 16 # | %__s1_58 = alloca <4 x float>, align 16 # | %__s2_58 = alloca <2 x float>, align 8 # | %__ret = alloca <4 x float>, align 16 # | %__s0 = alloca <2 x float>, align 8 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <4 x float>, align 16 # | %tmp1 = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <4 x float> %b, ptr %b.addr, align 16 # | store <2 x float> %v, ptr %v.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__s0_58, align 16 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | store <4 x float> %1, ptr %__s1_58, align 16 # | %2 = load <2 x float>, ptr %v.addr, align 8 # | store <2 x float> %2, ptr %__s2_58, align 8 # | %3 = load <4 x float>, ptr %__s0_58, align 16 # | %4 = load <4 x float>, ptr %__s1_58, align 16 # | %5 = load <2 x float>, ptr %__s2_58, align 8 # | store <2 x f # | ... # `---data was truncated (10240/44730) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000556c7016d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556c7016a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556c7016dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5792849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f57928a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5792849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5792831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556c7010324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556c70103096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556c700e7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556c6fd97176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556c6fd96e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5792832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f57928330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f57928330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556c6fd96d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c (82 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c (83 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv1i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv2i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv4i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv8i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv16i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005572f8d9857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005572f8d95515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005572f8d98cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4dfba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4dfbaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4dfba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4dfba31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005572f8d2e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005572f8d2e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005572f8d12f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005572f89c2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005572f89c1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4dfba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4dfba330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4dfba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005572f89c1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c (84 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i64m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i64m1( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv1i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i64m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i64m2( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i64m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i64m4( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i64m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i64m8( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i64m1_m( %mask, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load , ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i64m1_m( %mask, %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load i64, ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.mask.nxv1i64.i64.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c (85 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a02871757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a028714515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a028717cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f68d3133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f68d318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f68d3133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f68d311b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a0286ad24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a0286ad096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a028691f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a028341176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a028340e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f68d311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f68d311d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f68d311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a028340d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c (86 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16m4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Fu # | ... # `---data was truncated (10240/68429) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ad677d357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ad677d0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ad677d3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3469d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3469d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3469d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3469d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ad6776924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ad67769096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ad6774df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ad673fd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ad673fce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3469d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3469d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3469d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ad673fcd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c (87 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f32m1x2_tu(target("riscv # | ... # `---data was truncated (10240/295533) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c5f930e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c5f930b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c5f930ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efe3d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efe3d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efe3d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efe3d91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c5f92a424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c5f92a4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c5f9288f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c5f8f38176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c5f8f37e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efe3d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efe3d91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efe3d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c5f8f37d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c (88 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m8_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff. # | ... # `---data was truncated (10240/288058) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ebc993957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ebc9936515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ebc9939cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fda7d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fda7d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fda7d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fda7d91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ebc98cf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ebc98cf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ebc98b3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ebc9563176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ebc9562e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fda7d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fda7d91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fda7d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ebc9562d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c (89 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_i8mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef # | ... # `---data was truncated (10240/69988) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557ffd8e657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557ffd8e3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557ffd8e6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa14a105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa14a15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa14a105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa14a0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557ffd87c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557ffd87c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557ffd860f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557ffd510176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557ffd50fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa14a0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa14a0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa14a0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557ffd50fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c (90 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor # | ... # `---data was truncated (10240/113039) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559bb604f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559bb604c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559bb604fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f60cfb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f60cfb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f60cfb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f60cfb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559bb5fe524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559bb5fe5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559bb5fc9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559bb5c79176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559bb5c78e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f60cfb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f60cfb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f60cfb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559bb5c78d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c (91 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i64.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv2i64.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv4i64.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv8i64.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565004f8b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000565004f88515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000565004f8bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9db9533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9db958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9db9533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9db951b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565004f2124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000565004f21096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000565004f05f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000565004bb5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000565004bb4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9db951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9db951d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9db951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565004bb4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c (92 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32mf2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1f32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2f32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4f32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8f32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv16f32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32mf2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1i32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2i32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4i32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8i32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv16i32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_u32mf2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1i32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_u32m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2i32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_u32m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4i32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_u32m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8i32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_u32m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv16i32.p0.i64( p # | ... # `---data was truncated (10240/24606) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563e1213357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563e12130515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563e12133cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7e17f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7e17f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7e17f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7e17f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563e120c924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563e120c9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563e120adf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563e11d5d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563e11d5ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7e17f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7e17f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7e17f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563e11d5cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c (93 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function A # | ... # `---data was truncated (10240/68067) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005612080a557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005612080a2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005612080a5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1ed6249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1ed62a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1ed6249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1ed6231507 abort ./stdlib/abort.c:85:3 # | #7 0x000056120803b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056120803b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056120801ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561207ccf176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561207ccee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1ed6232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1ed62330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1ed62330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561207cced81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c (94 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64( %1, %2, float %3, %0, i64 2, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64( %1, %2, float %3, %0, i64 2, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c (95 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c (96 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range # | ... # `---data was truncated (10240/302397) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bf22c3657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bf22c33515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bf22c36cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5a1181bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5a118725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5a1181ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5a11803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bf22bcc24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bf22bcc096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bf22bb0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bf22860176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bf2285fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5a11804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5a118050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5a118050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bf2285fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c (97 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.add # | ... # `---data was truncated (10240/94157) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005594526a457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005594526a1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005594526a4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe384d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe384d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe384d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe384ced507 abort ./stdlib/abort.c:85:3 # | #7 0x000055945263a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055945263a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055945261ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005594522ce176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005594522cde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe384ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe384cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe384cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005594522cdd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c (98 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Funct # | ... # `---data was truncated (10240/64950) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ebbbd3657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ebbbd33515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ebbbd36cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb4d3449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb4d34a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb4d3449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb4d3431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ebbbccc24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ebbbccc096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ebbbcb0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ebbb960176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ebbb95fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb4d3432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb4d34330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb4d34330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ebbb95fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c (99 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16m2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c (100 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/97647) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e2aca7b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e2aca78515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e2aca7bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f915cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f915cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f915cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f915cd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e2aca1124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e2aca11096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e2ac9f5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e2ac6a5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e2ac6a4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f915cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f915cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f915cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e2ac6a4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c (101 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560b9ca9957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560b9ca96515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560b9ca99cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f24fea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f24feaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f24fea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f24fea31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560b9ca2f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560b9ca2f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560b9ca13f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560b9c6c3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560b9c6c2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f24fea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f24fea330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f24fea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560b9c6c2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c (102 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16m2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , # | ... # `---data was truncated (10240/154207) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ef0f7e157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ef0f7de515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ef0f7e1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2edc41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2edc4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2edc41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2edc403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ef0f77724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ef0f777096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ef0f75bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ef0f40b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ef0f40ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2edc404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2edc4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2edc4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ef0f40ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/arm_acle.c (103 of 27911) ******************** TEST 'Clang :: CodeGen/arm_acle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple armv8a-none-eabi -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c -check-prefixes=ARM,AArch32 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple armv8a-none-eabi -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8a-unknown-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_dmb() #0 { # | entry: # | call void @llvm.arm.dmb(i32 1) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.dmb(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_dsb() #0 { # | entry: # | call void @llvm.arm.dsb(i32 2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.dsb(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_isb() #0 { # | entry: # | call void @llvm.arm.isb(i32 3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.isb(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_yield() #0 { # | entry: # | call void @llvm.arm.hint(i32 1) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.hint(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_wfe() #0 { # | entry: # | call void @llvm.arm.hint(i32 2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_wfi() #0 { # | entry: # | call void @llvm.arm.hint(i32 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sev() #0 { # | entry: # | call void @llvm.arm.hint(i32 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sevl() #0 { # | entry: # | call void @llvm.arm.hint(i32 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_dbg() #0 { # | entry: # | call void @llvm.arm.dbg(i32 0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.dbg(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_swp(i32 noundef %x, ptr noundef %p) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__p.addr.i = alloca ptr, align 4 # | %__v.i = alloca i32, align 4 # | %.atomictmp.i = alloca i32, align 4 # | %atomic-temp.i = alloca i32, align 4 # | %x.addr = alloca i32, align 4 # | %p.addr = alloca ptr, align 4 # | store i32 %x, ptr %x.addr, align 4 # | store ptr %p, ptr %p.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %1 = load ptr, ptr %p.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store ptr %1, ptr %__p.addr.i, align 4 # | %2 = load ptr, ptr %__p.addr.i, align 4 # | %3 = load i32, ptr %__x.addr.i, align 4 # | store i32 %3, ptr %.atomictmp.i, align 4 # | %4 = load i32, ptr %.atomictmp.i, align 4 # | %5 = atomicrmw volatile xchg ptr %2, i32 %4 monotonic, align 4 # | store i32 %5, ptr %atomic-temp.i, align 4 # | %6 = load i32, ptr %atomic-temp.i, align 4 # | store i32 %6, ptr %__v.i, align 4 # | %7 = load i32, ptr %__v.i, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_pld() #0 { # | entry: # | call void @llvm.prefetch.p0(ptr null, i32 0, i32 3, i32 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) # | declare void @llvm.prefetch.p0(ptr readonly captures(none), i32 immarg range(i32 0, 2), i32 immarg range(i32 0, 4), i32 immarg range(i32 0, 2)) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_pldx() #0 { # | entry: # | call void @llvm.prefetch.p0(ptr null, i32 1, i32 3, i32 1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_pli() #0 { # | entry: # | call void @llvm.prefetch.p0(ptr null, i32 0, i32 3, i32 0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_plix() #0 { # | entry: # | call void @llvm.prefetch.p0(ptr null, i32 0, i32 3, i32 0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_nop() #0 { # | entry: # | call void @llvm.arm.hint(i32 0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ror(i32 noundef %x, i32 noundef %y) #0 { # | entry: # | %retval.i = alloca i32, align 4 # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %x.addr = alloca i32, align 4 # | %y.addr = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | store i32 %y, ptr %y.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %1 = load i32, ptr %y.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__y.addr.i, align 4 # | %rem.i = urem i32 %2, 32 # | store i32 %rem.i, ptr %__y.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %cmp.i = icmp eq i32 %3, 0 # | br i1 %cmp.i, label %if.then.i, label %if.end.i # | # | if.then.i: ; preds = %entry # | %4 = load i32, ptr %__x.addr.i, align 4 # | store i32 %4, ptr %retval.i, align 4 # | br label %__ror.exit # | # | if.end.i: ; preds = %entry # | %5 = load i32, ptr %__x.addr.i, align 4 # | %6 = load i32, ptr %__y.addr.i, align 4 # | %shr.i = lshr i32 %5, %6 # | %7 = load i32, ptr %__x.addr.i, align 4 # | %8 = load i32, ptr %__y.addr.i, align 4 # | %sub.i = sub i32 32, %8 # | %shl.i = shl i32 %7, %sub.i # | %or.i = or i32 %shr.i, %shl.i # | store i32 %or.i, ptr %retval.i, align 4 # | br label %__ror.exit # | # | __ror.exit: ; preds = %if.then.i, %if.end.i # | %9 = load i32, ptr %retval.i, align 4 # | ret i32 %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_rorl(i32 noundef %x, i32 noundef %y) #0 { # | entry: # | %retval.i.i = alloca i32, align 4 # | %__x.addr.i.i = alloca i32, align 4 # | %__y.addr.i.i = alloca i32, align 4 # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %x.addr = alloca i32, align 4 # | %y.addr = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | store i32 %y, ptr %y.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %1 = load i32, ptr %y.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | store i32 %2, ptr %__x.addr.i.i, align 4 # | store i32 %3, ptr %__y.addr.i.i, align 4 # | %4 = load i32, ptr %__y.addr.i.i, align 4 # | %rem.i.i = urem i32 %4, 32 # | store i32 %rem.i.i, ptr %__y.addr.i.i, align 4 # | %5 = load i32, ptr %__y.addr.i.i, align 4 # | %cmp.i.i = icmp eq i32 %5, 0 # | br i1 %cmp.i.i, label %if.then.i.i, label %if.end.i.i # | # | if.then.i.i: ; preds = %entry # | %6 = load i32, ptr %__x.addr.i.i, align 4 # | store i32 %6, ptr %retval.i.i, align 4 # | br label %__rorl.exit # | # | if.end.i.i: ; preds = %entry # | %7 = load i32, ptr %__x.addr.i.i, align 4 # | %8 = load i32, ptr %__y.addr.i.i, align 4 # | %shr.i.i = lshr i32 %7, %8 # | %9 = load i32, ptr %__x.addr.i.i, align 4 # | %10 = load i32, ptr %__y.addr.i.i, align 4 # | %sub.i.i = sub i32 32, %10 # | %shl.i.i = shl i32 %9, %sub.i.i # | %or.i.i = or i32 %shr.i.i, %shl.i.i # | store i32 %or.i.i, ptr %retval.i.i, align 4 # | br label %__rorl.exit # | # | __rorl.exit: ; preds = %if.then.i.i, %if.end.i.i # | %11 = load i32, ptr %retval.i.i, align 4 # | ret i32 %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_rorll(i64 noundef %x, i32 noundef %y) #0 { # | entry: # | %retval.i = alloca i64, align 8 # | %__x.addr.i = alloca i64, align 8 # | %__y.addr.i = alloca i32, align 4 # | %x.addr = alloca i64, align 8 # | %y.addr = alloca i32, align 4 # | store i64 %x, ptr %x.addr, align 8 # | store i32 %y, ptr %y.addr, align 4 # | %0 = load i64, ptr %x.addr, align 8 # | %1 = load i32, ptr %y.addr, align 4 # | store i64 %0, ptr %__x.addr.i, align 8 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__y.addr.i, align 4 # | %rem.i = urem i32 %2, 64 # | store i32 %rem.i, ptr %__y.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %cmp.i = icmp eq i32 %3, 0 # | br i1 %cmp.i, label %if.then.i, label %if.end.i # | # | if.then.i: ; preds = %entry # | %4 = load i64, ptr %__x.addr.i, align 8 # | store i64 %4, ptr %retval.i, align 8 # | br label %__rorll.exit # | # | if.end.i: ; preds = %entry # | %5 = load i64, ptr %__x.addr.i, align 8 # | %6 = load i32, ptr %__y.addr.i, align 4 # | %sh_prom.i = zext i32 %6 to i64 # | %shr.i = lshr i64 %5, %sh_prom.i # | %7 = load i64, ptr %__x.addr.i, align 8 # | %8 = load i32, ptr %__y.addr.i, align 4 # | %sub.i = sub i32 64, %8 # | %sh_prom1.i = zext i32 %sub.i to i64 # | %shl.i = shl i64 %7, %sh_prom1.i # | %or.i = or i64 %shr.i, %shl.i # | store i64 %or.i, ptr %retval.i, align 8 # | br label %__rorll.exit # | # | __rorll.exit: ; preds = %if.then.i, %if.end.i # | %9 = load i64, ptr %retval.i, align 8 # | ret i64 %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_clz(i32 noundef %t) #0 { # | entry: # | %__t.addr.i = alloca i32, align 4 # | %t.addr = alloca i32, align 4 # | store i32 %t, ptr %t.addr, align 4 # | %0 = load i32, ptr %t.addr, align 4 # | store i32 %0, ptr %__t.addr.i, align 4 # | %1 = load i32, ptr %__t.addr.i, align 4 # | %2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_clzl(i32 noundef %t) #0 { # | entry: # | %__t.addr.i = alloca i32, align 4 # | %t.addr = alloca i32, align 4 # | store i32 %t, ptr %t.addr, align 4 # | %0 = load i32, ptr %t.addr, align 4 # | store i32 %0, ptr %__t.addr.i, align 4 # | %1 = load i32, ptr %__t.addr.i, align 4 # | %2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_clzll(i64 noundef %t) #0 { # | entry: # | %__t.addr.i = alloca i64, align 8 # | %t.addr = alloca i64, align 8 # | store i64 %t, ptr %t.addr, align 8 # | %0 = load i64, ptr %t.addr, align 8 # | store i64 %0, ptr %__t.addr.i, align 8 # | %1 = load i64, ptr %__t.addr.i, align 8 # | %2 = call i64 @llvm.ctlz.i64(i64 %1, i1 false) # | %3 = trunc i64 %2 to i32 # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_cls(i32 noundef %t) #0 { # | entry: # | %__t.addr.i = alloca i32, align 4 # | %t.addr = alloca i32, align 4 # | store i32 %t, ptr %t.addr, align 4 # | %0 = load i32, ptr %t.addr, align 4 # | store i32 %0, ptr %__t.addr.i, align 4 # | %1 = load i32, ptr %__t.addr.i, align 4 # | %cls.i = call i32 @llvm.arm.cls(i32 %1) # | ret i32 %cls.i # | } # | # | ; Function Attrs: noinline # | ... # `---data was truncated (10240/86891) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564c1745757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564c17454515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564c17457cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb2b7e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb2b7ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb2b7e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb2b7e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564c173ed24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564c173ed096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564c173d1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564c17081176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564c17080e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb2b7e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb2b7e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb2b7e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564c17080d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c -check-prefixes=ARM,AArch32 # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c -check-prefixes=ARM,AArch32 # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c (104 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory # | ... # `---data was truncated (10240/69669) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ae0a4f657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ae0a4f3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ae0a4f6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f368501bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f36850725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f368501ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3685003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ae0a48c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ae0a48c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ae0a470f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ae0a120176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ae0a11fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3685004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f36850050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f36850050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ae0a11fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c (105 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load # | ... # `---data was truncated (10240/29062) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562e23ea057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562e23e9d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562e23ea0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7af4449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7af44a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7af4449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7af4431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562e23e3624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562e23e36096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562e23e1af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562e23aca176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562e23ac9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7af4432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7af44330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7af44330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562e23ac9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c (106 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16mf4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16mf2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m1_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m8_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f32mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f32m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, al # | ... # `---data was truncated (10240/81312) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555eaaf4357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555eaaf40515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555eaaf43cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f519601bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f51960725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f519601ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5196003507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555eaaed924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555eaaed9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555eaaebdf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555eaab6d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555eaab6ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5196004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f51960050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f51960050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555eaab6cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c (107 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/225655) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558377a8557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558377a82515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558377a85cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f859f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f859f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f859f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f859f71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558377a1b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558377a1b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005583779fff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005583776af176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005583776aee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f859f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f859f71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f859f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005583776aed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c (108 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla2_f32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.fmla.vg1x2.nxv4f32(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fmla.vg1x2.nxv4f32(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla4_f32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm.coerce0, %zm.coerce1, %zm.coerce2, %zm.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zm = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | %4 = insertvalue { , , , } poison, %zm.coerce0, 0 # | %5 = insertvalue { , , , } %4, %zm.coerce1, 1 # | %6 = insertvalue { , , , } %5, %zm.coerce2, 2 # | %7 = insertvalue { , , , } %6, %zm.coerce3, 3 # | store { , , , } %7, ptr %zm, align 16 # | %zm2 = load { , , , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store { , , , } %zm2, ptr %zm.addr, align 16 # | %8 = load i32, ptr %slice_base.addr, align 4 # | %9 = load { , , , }, ptr %zn.addr, align 16 # | %10 = extractvalue { , , , } %9, 0 # | %11 = extractvalue { , , , } %9, 1 # | %12 = extractvalue { , , , } %9, 2 # | %13 = extractvalue { , , , } %9, 3 # | %14 = load { , , , }, ptr %zm.addr, align 16 # | %15 = extractvalue { , , , } %14, 0 # | %16 = extractvalue { , , , } %14, 1 # | %17 = extractvalue { , , , } %14, 2 # | %18 = extractvalue { , , , } %14, 3 # | call void @llvm.aarch64.sme.fmla.vg1x4.nxv4f32(i32 %8, %10, %11, %12, %13, %15, %16, %17, %18) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fmla.vg1x4.nxv4f32(i32, , , , , , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_single2_f32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.fmla.single.vg1x2.nxv4f32(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fmla.single.vg1x2.nxv4f32(i32, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_single4_f32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c (109 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c (110 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_u8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv16i8( %0, %1, i32 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.extq.nxv16i8(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_s8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv16i8( %0, %1, i32 4) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_u16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv8i16( %0, %1, i32 1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.extq.nxv8i16(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_s16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv8i16( %0, %1, i32 5) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_u32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv4i32( %0, %1, i32 2) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.extq.nxv4i32(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_s32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv4i32( %0, %1, i32 3) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_u64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv2i64( %0, %1, i32 1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.extq.nxv2i64(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_s64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv2i64( %0, %1, i32 0) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_f16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv8f16( %0, %1, i32 7) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.extq.nxv8f16(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_f32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv4f32( %0, %1, i32 2) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.extq.nxv4f32(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_f64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv2f64( %0, %1, i32 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.extq.nxv2f64(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_bf16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv8bf16( %0, %1, i32 6) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.extq.nxv8bf16(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_mf8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, # | ... # `---data was truncated (10240/11061) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005625f98da57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005625f98d7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005625f98dacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fab85733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fab8578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fab85733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fab8571b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005625f987024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005625f9870096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005625f9854f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005625f9504176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005625f9503e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fab8571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fab8571d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fab8571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005625f9503d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c (111 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16mf4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv16f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv16f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv32f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv32f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_i16mf4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_i16mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_i16m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4i16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_i16m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | cal # | ... # `---data was truncated (10240/39578) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555689fce57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555689fcb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555689fcecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f606dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f606dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f606dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f606dd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555689f6424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555689f64096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555689f48f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555689bf8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555689bf7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f606dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f606dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f606dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555689bf7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c (112 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svorr_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.orr.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.orr.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svorr_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.orr.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.orr.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svorr_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.orr.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.orr.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svorr_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.orr.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.orr.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svorr_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.orr.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svorr_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.orr.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svorr_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.orr.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svorr_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.orr.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svorr_s8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, pt # | ... # `---data was truncated (10240/52880) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000557a7593b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557a75938515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557a7593bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7b71a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7b71aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7b71a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7b71a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557a758d124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557a758d1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557a758b5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557a75565176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557a75564e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7b71a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7b71a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7b71a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557a75564d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c (113 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8mf8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota # | ... # `---data was truncated (10240/94681) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c76873b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c768738515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c76873bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe5ed333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe5ed38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe5ed333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe5ed31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c7686d124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c7686d1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c7686b5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c768365176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c768364e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe5ed31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe5ed31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe5ed31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c768364d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c (114 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple # | ... # `---data was truncated (10240/108848) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564a1ad8a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564a1ad87515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564a1ad8acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f21e2b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f21e2b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f21e2b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f21e2aed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564a1ad2024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564a1ad20096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564a1ad04f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564a1a9b4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564a1a9b3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f21e2aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f21e2aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f21e2aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564a1a9b3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c (115 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556e1e98f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556e1e98c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556e1e98fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7dfa933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7dfa98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7dfa933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7dfa91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556e1e92524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556e1e925096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556e1e909f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556e1e5b9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556e1e5b8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7dfa91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7dfa91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7dfa91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556e1e5b8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c (116 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f93c0ec57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f93c0e9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f93c0eccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8f18c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8f18ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8f18c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8f18c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f93c08224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f93c082096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f93c066f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f93bd16176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f93bd15e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8f18c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8f18c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8f18c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f93bd15d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c (117 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nx # | ... # `---data was truncated (10240/18660) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005651f105657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005651f1053515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005651f1056cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff0a1133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff0a118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff0a1133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff0a111b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005651f0fec24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005651f0fec096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005651f0fd0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005651f0c80176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005651f0c7fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff0a111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff0a111d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff0a111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005651f0c7fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c (118 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ... # `---data was truncated (10240/34438) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bfc151057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bfc150d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bfc1510cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fac64e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fac64e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fac64e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fac64e03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bfc14a624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bfc14a6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bfc148af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bfc113a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bfc1139e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fac64e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fac64e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fac64e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bfc1139d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c (119 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf4_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m1_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m4_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m8_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf4_tum( %mask, %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load float, ptr %op2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf2_tum( %mask, %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load float, ptr %op2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64( %1, %2, float %3, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c (120 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64( %0, %1, bfloat %2, # | ... # `---data was truncated (10240/65194) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561c8fe0b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561c8fe08515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561c8fe0bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f61a2133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f61a218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f61a2133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f61a211b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561c8fda124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561c8fda1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561c8fd85f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561c8fa35176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561c8fa34e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f61a211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f61a211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f61a211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561c8fa34d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c (121 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_i8mf4x7(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561d17d5757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561d17d54515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561d17d57cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feb67a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feb67aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feb67a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feb67a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561d17ced24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561d17ced096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561d17cd1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561d17981176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561d17980e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007feb67a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feb67a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feb67a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561d17980d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c (122 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtmad_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ftmad.x.nxv8f16( %0, %1, i32 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ftmad.x.nxv8f16(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtmad_f16_1( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ftmad.x.nxv8f16( %0, %1, i32 7) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtmad_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ftmad.x.nxv4f32( %0, %1, i32 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ftmad.x.nxv4f32(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtmad_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ftmad.x.nxv2f64( %0, %1, i32 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ftmad.x.nxv2f64(, , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055a7ac39957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a7ac396515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a7ac399cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb6a4c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb6a4ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb6a4c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb6a4c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a7ac32f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a7ac32f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a7ac313f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a7abfc3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a7abfc2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb6a4c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb6a4c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb6a4c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a7abfc2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c (123 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ... # `---data was truncated (10240/34438) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555f3072f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555f3072c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555f3072fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2916449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f29164a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2916449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2916431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555f306c524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555f306c5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555f306a9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555f30359176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555f30358e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2916432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f29164330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f29164330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555f30358d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics.c (124 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.2a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.2a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vabs_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vabs.i = bitcast <8 x i8> %1 to <4 x half> # | %vabs1.i = call <4 x half> @llvm.fabs.v4f16(<4 x half> %vabs.i) # | store <4 x half> %vabs1.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %2, ptr %__ret.i, align 8 # | %3 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vabsq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vabs.i = bitcast <16 x i8> %1 to <8 x half> # | %vabs1.i = call <8 x half> @llvm.fabs.v8f16(<8 x half> %vabs.i) # | store <8 x half> %vabs1.i, ptr %ref.tmp.i, align 16 # | %2 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %2, ptr %__ret.i, align 16 # | %3 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vceqz_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fcmp oeq <4 x half> %2, zeroinitializer # | %vceqz.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vceqz.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vceqzq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %3 = fcmp oeq <8 x half> %2, zeroinitializer # | %vceqz.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vceqz.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vcgez_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fcmp oge <4 x half> %2, zeroinitializer # | %vcgez.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vcgez.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcgezq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %3 = fcmp oge <8 x half> %2, zeroinitializer # | %vcgez.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vcgez.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vcgtz_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fcmp ogt <4 x half> %2, zeroinitializer # | %vcgtz.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vcgtz.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcgtzq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %3 = fcmp ogt <8 x half> %2, zeroinitializer # | %vcgtz.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vcgtz.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vclez_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fcmp ole <4 x half> %2, zeroinitializer # | %vclez.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vclez.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vclezq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %3 = fcmp ole <8 x half> %2, zeroinitializer # | %vclez.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vclez.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vcltz_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fcmp olt <4 x half> %2, zeroinitializer # | %vcltz.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vcltz.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcltzq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %3 = fcmp olt <8 x half> %2, zeroinitializer # | %vcltz.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vcltz.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vcvt_f16_s16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, # | ... # `---data was truncated (10240/159327) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055d3b3d4057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d3b3d3d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d3b3d40cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9c49133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9c4918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9c49133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9c4911b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d3b3cd624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d3b3cd6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d3b3cbaf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d3b396a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d3b3969e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9c4911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9c4911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9c4911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d3b3969d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c (125 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16mf4_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16mf2_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16m1_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16m2_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c (126 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_i8mf4x8(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e9c1b8057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e9c1b7d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e9c1b80cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fefdbe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fefdbea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fefdbe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fefdbe31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e9c1b1624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e9c1b16096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e9c1afaf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e9c17aa176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e9c17a9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fefdbe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fefdbe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fefdbe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e9c17a9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c (127 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_i8mf8x6 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559267ed757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559267ed4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559267ed7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa8abf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa8abf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa8abf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa8abf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559267e6d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559267e6d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559267e51f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559267b01176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559267b00e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa8abf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa8abf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa8abf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559267b00d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c (128 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +f8f32mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +f8f32mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_f32mf8( %acc, %a, %b, i64 noundef %fpmr) #0 { # | entry: # | %acc.addr = alloca , align 16 # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | store %acc, ptr %acc.addr, align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load , ptr %acc.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %2 = load , ptr %b.addr, align 16 # | %3 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fmmla.nxv4f32( %0, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fmmla.nxv4f32(, , ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f8f32mm,+sve,+sve2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000560d915df57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560d915dc515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560d915dfcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3f2af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3f2af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3f2af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3f2af1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560d9157524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560d91575096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560d91559f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560d91209176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560d91208e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3f2af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3f2af1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3f2af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560d91208d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c (129 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscal # | ... # `---data was truncated (10240/12235) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005603924ae57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005603924ab515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005603924aecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1cb6133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1cb618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1cb6133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1cb611b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056039244424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560392444096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560392428f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005603920d8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005603920d7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1cb611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1cb611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1cb611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005603920d7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c (130 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561c95b2b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561c95b28515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561c95b2bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f04d8105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f04d815c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f04d8105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f04d80ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561c95ac124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561c95ac1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561c95aa5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561c95755176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561c95754e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f04d80eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f04d80ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f04d80ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561c95754d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c (131 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv16i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv32i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv32i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv64i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv64i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.a # | ... # `---data was truncated (10240/63518) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555e3b09757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555e3b094515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555e3b097cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb735449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb7354a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb735449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb735431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555e3b02d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555e3b02d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555e3b011f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555e3acc1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555e3acc0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb735432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb7354330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb7354330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555e3acc0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c (132 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u64m1(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 %0, i64 64, i64 0, i64 %1) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 immarg, i64 immarg, i64 immarg, i64, i64 immarg, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u64m2(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 %0, i64 64, i64 1, i64 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u64m4(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 %0, i64 64, i64 2, i64 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u64m8(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 %0, i64 64, i64 3, i64 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_x_se_u64m1(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vc.v.x.se.nxv1i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.x.se.nxv1i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_x_se_u64m2(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vc.v.x.se.nxv2i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.x.se.nxv2i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_x_se_u64m4(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vc.v.x.se.nxv4i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.x.se.nxv4i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_x_se_u64m8(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vc.v.x.se.nxv8i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.x.se.nxv8i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_x_u64m1(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vc.v.x.nxv1i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nounwind memory(none) # | declare @llvm.riscv.sf.vc.v.x.nxv1i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_x_u64m2(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vc.v.x.nxv2i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nounwind memory(none) # | declare @llvm.riscv.sf.vc.v.x.nxv2i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_x_u64m4(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vc.v.x.nxv4i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nounwind memory(none) # | declare @llvm.riscv.sf.vc.v.x.nxv4i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_x_u64m8(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vc.v.x.nxv8i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nounwind memory(none) # | declare @llvm.riscv.sf.vc.v.x.nxv8i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #2 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvcp,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nounwind } # | attributes #2 = { nounwind memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvcp1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556b3855657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556b38553515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556b38556cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdb75d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdb75d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdb75d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdb75d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556b384ec24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556b384ec096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556b384d0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556b38180176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556b3817fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fdb75d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdb75d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdb75d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556b3817fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c (133 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", # | ... # `---data was truncated (10240/63169) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f4789c557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f4789c2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f4789c5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbe6f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbe6f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbe6f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbe6f51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f47895b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f47895b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f47893ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f4785ef176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f4785eee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbe6f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbe6f51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbe6f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f4785eed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c (134 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_i8mf8x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_i8mf4x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_i8mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_i8m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_i8m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_u8mf8x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_u8mf4x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_u8mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_u8m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_u8m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @ # | ... # `---data was truncated (10240/23479) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558f6be4a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558f6be47515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558f6be4acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5022b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5022b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5022b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5022b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558f6bde024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558f6bde0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558f6bdc4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558f6ba74176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558f6ba73e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5022b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5022b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5022b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558f6ba73d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c (135 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv1i8.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1i8.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv2i8.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv2i8.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv4i8.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv4i8.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m1_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv8i8.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv8i8.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv16i8.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv16i8.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv32i8.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv32i8.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv64i8.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv64i8.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_u8mf8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv1i8.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | # | ... # `---data was truncated (10240/17236) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558d7fc2457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558d7fc21515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558d7fc24cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f34e3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f34e338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f34e3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f34e331b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558d7fbba24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558d7fbba096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558d7fb9ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558d7f84e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558d7f84de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f34e331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f34e331d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f34e331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558d7f84dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c (136 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16mf4x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16mf2x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16m1x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16m1x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eae924d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055eae924a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055eae924dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1722e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1722ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1722e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1722e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eae91e324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055eae91e3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055eae91c7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055eae8e77176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055eae8e76e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1722e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1722e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1722e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eae8e76d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c (137 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c (138 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsr_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.lsr.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.lsr.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsr_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.lsr.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.lsr.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsr_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.lsr.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.lsr.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsr_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.lsr.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.lsr.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsr_u8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.lsr.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsr_u16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.lsr.nxv8i16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsr_u32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.lsr.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsr_u64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.lsr.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsr_u8_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.lsr.u.nxv16i8( %0, %1, %2) # | # | ... # `---data was truncated (10240/33353) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005653bfe5757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005653bfe54515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005653bfe57cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f983f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f983f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f983f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f983f51b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005653bfded24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005653bfded096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005653bfdd1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005653bfa81176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005653bfa80e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f983f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f983f51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f983f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005653bfa80d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c (139 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055750214e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055750214b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055750214ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbe88905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbe8895c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbe88905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbe888ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005575020e424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005575020e4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005575020c8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557501d78176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557501d77e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbe888eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbe888ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbe888ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557501d77d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/arm-mve-intrinsics/vshlc.c (140 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vshlc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlcq_s8(<16 x i8> noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca ptr, align 4 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <16 x i8>, ptr %a.addr, align 8 # | %3 = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.v16i8(<16 x i8> %2, i32 %1, i32 18) # | %4 = extractvalue { i32, <16 x i8> } %3, 0 # | store i32 %4, ptr %0, align 4 # | %5 = extractvalue { i32, <16 x i8> } %3, 1 # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, <16 x i8> } @llvm.arm.mve.vshlc.v16i8(<16 x i8>, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlcq_s16(<8 x i16> noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca ptr, align 4 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <8 x i16>, ptr %a.addr, align 8 # | %3 = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.v8i16(<8 x i16> %2, i32 %1, i32 16) # | %4 = extractvalue { i32, <8 x i16> } %3, 0 # | store i32 %4, ptr %0, align 4 # | %5 = extractvalue { i32, <8 x i16> } %3, 1 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, <8 x i16> } @llvm.arm.mve.vshlc.v8i16(<8 x i16>, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlcq_s32(<4 x i32> noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca ptr, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <4 x i32>, ptr %a.addr, align 8 # | %3 = call { i32, <4 x i32> } @llvm.arm.mve.vshlc.v4i32(<4 x i32> %2, i32 %1, i32 4) # | %4 = extractvalue { i32, <4 x i32> } %3, 0 # | store i32 %4, ptr %0, align 4 # | %5 = extractvalue { i32, <4 x i32> } %3, 1 # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, <4 x i32> } @llvm.arm.mve.vshlc.v4i32(<4 x i32>, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlcq_u8(<16 x i8> noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca ptr, align 4 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <16 x i8>, ptr %a.addr, align 8 # | %3 = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.v16i8(<16 x i8> %2, i32 %1, i32 17) # | %4 = extractvalue { i32, <16 x i8> } %3, 0 # | store i32 %4, ptr %0, align 4 # | %5 = extractvalue { i32, <16 x i8> } %3, 1 # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlcq_u16(<8 x i16> noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca ptr, align 4 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <8 x i16>, ptr %a.addr, align 8 # | %3 = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.v8i16(<8 x i16> %2, i32 %1, i32 17) # | %4 = extractvalue { i32, <8 x i16> } %3, 0 # | store i32 %4, ptr %0, align 4 # | %5 = extractvalue { i32, <8 x i16> } %3, 1 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlcq_u32(<4 x i32> noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca ptr, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <4 x i32>, ptr %a.addr, align 8 # | %3 = call { i32, <4 x i32> } @llvm.arm.mve.vshlc.v4i32(<4 x i32> %2, i32 %1, i32 20) # | %4 = extractvalue { i32, <4 x i32> } %3, 0 # | store i32 %4, ptr %0, align 4 # | %5 = extractvalue { i32, <4 x i32> } %3, 1 # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlcq_m_s8(<16 x i8> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <16 x i8>, ptr %a.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4) # | %6 = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.predicated.v16i8.v16i1(<16 x i8> %2, i32 %1, i32 29, <16 x i1> %5) # | %7 = extractvalue { i32, <16 x i8> } %6, 0 # | store i32 %7, ptr %0, align 4 # | %8 = extractvalue { i32, <16 x i8> } %6, 1 # | ret <16 x i8> %8 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, <16 x i8> } @llvm.arm.mve.vshlc.predicated.v16i8.v16i1(<16 x i8>, i32, i32, <16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlcq_m_s16(<8 x i16> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <8 x i16>, ptr %a.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4) # | %6 = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.predicated.v8i16.v8i1(<8 x i16> %2, i32 %1, i32 17, <8 x i1> %5) # | %7 = extractvalue { i32, <8 x i16> } %6, 0 # | store i32 %7, ptr %0, align 4 # | %8 = extractvalue { i32, <8 x i16> } %6, 1 # | ret <8 x i16> %8 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, <8 x i16> } @llvm.arm.mve.vshlc.predicated.v8i16.v8i1(<8 x i16>, i32, i32, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlcq_m_s32(<4 x i32> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <4 x i32>, ptr %a.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4) # | %6 = call { i32, <4 x i32> } @llvm.arm.mve.vshlc.predicated.v4i32.v4i1(<4 x i32> %2, i32 %1, i32 9, <4 x i1> %5) # | %7 = extractvalue { i32, <4 x i32> } %6, 0 # | store i32 %7, ptr %0, align 4 # | %8 = extractvalue { i32, <4 x i32> } %6, 1 # | ret <4 x i32> %8 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, <4 x i32> } @llvm.arm.mve.vshlc.predicated.v4i32.v4i1(<4 x i32>, i32, i32, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlcq_m_u8(<16 x i8> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <16 x i8>, ptr %a.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4) # | %6 = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.predicated.v16i8.v16i1(<16 x i8> %2, i32 %1, i32 21, <16 x i1> %5) # | %7 = extractvalue { i32, <16 x i8> } %6, 0 # | store i32 %7, ptr %0, align 4 # | %8 = extractvalue { i32, <16 x i8> } %6, 1 # | ret <16 x i8> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlcq_m_u16(<8 x i16> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <8 x i16>, ptr %a.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4) # | %6 = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.predicated.v8i16.v8i1(<8 x i16> %2, i32 %1, i32 24, <8 x i1> %5) # | %7 = extractvalue { i32, <8 x i16> } %6, 0 # | store i32 %7, ptr %0, align 4 # | %8 = extractvalue { i32, <8 x i16> } %6, 1 # | ret <8 x i16> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlcq_m_u32(<4 x i32> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | # | ... # `---data was truncated (10240/11454) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056462a69057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056462a68d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056462a690cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe0a2b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe0a2b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe0a2b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe0a2aed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056462a62624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056462a626096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056462a60af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056462a2ba176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056462a2b9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe0a2aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe0a2aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe0a2aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056462a2b9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c (141 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv64i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv64i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv32i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv32i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv16i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv16i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv8i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv8i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv4i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv4i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv2i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv2i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv1i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv1i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv64i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.mask.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv32i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.mask.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv16i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.mask.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv8i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.mask.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b16_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv4i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.mask.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b32_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv2i1.i64( %1, %0, i64 %2) # | ret i6 # | ... # `---data was truncated (10240/11946) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005628419e857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005628419e5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005628419e8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7232049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f72320a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7232049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7232031507 abort ./stdlib/abort.c:85:3 # | #7 0x000056284197e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056284197e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562841962f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562841612176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562841611e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7232032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f72320330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f72320330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562841611d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c (142 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsudot_s32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.usdot.nxv4i32( %0, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.usdot.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsudot_n_s32( %x, %y, i8 noundef %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca i8, align 1 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store i8 %z, ptr %z.addr, align 1 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load i8, ptr %z.addr, align 1 # | %.splatinsert = insertelement poison, i8 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.usdot.nxv4i32( %0, %.splat, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsudot_lane_s32_0( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.sudot.lane.nxv4i32( %0, %1, %2, i32 0) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sudot.lane.nxv4i32(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsudot_lane_s32_1( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.sudot.lane.nxv4i32( %0, %1, %2, i32 1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsudot_lane_s32_2( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.sudot.lane.nxv4i32( %0, %1, %2, i32 2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsudot_lane_s32_3( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.sudot.lane.nxv4i32( %0, %1, %2, i32 3) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+i8mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055b5f480857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b5f4805515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b5f4808cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdb8ab05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdb8ab5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdb8ab05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdb8aaed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b5f479e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b5f479e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b5f4782f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b5f4432176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b5f4431e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fdb8aaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdb8aaef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdb8aaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b5f4431d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c (143 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_u16mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_u16mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector. # | ... # `---data was truncated (10240/26921) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b0756c957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b0756c6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b0756c9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f30d1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f30d178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f30d1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f30d171b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b07565f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b07565f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b075643f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b0752f3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b0752f2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f30d171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f30d171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f30d171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b0752f2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c (144 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmmla_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmmla.nxv4f32.nxv8bf16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmmla.nxv4f32.nxv8bf16(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055765204257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055765203f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557652042cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcc07733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcc0778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcc07733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcc0771b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557651fd824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557651fd8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557651fbcf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557651c6c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557651c6be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcc0771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcc0771d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcc0771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557651c6bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c (145 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.2a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.2a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vfms_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i1 = alloca <4 x half>, align 8 # | %__p1.addr.i2 = alloca <4 x half>, align 8 # | %__p2.addr.i3 = alloca <4 x half>, align 8 # | %__ret.i4 = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <4 x half>, ptr %__p0.addr.i, align 8 # | %4 = load <4 x half>, ptr %__p1.addr.i, align 8 # | %fneg.i = fneg <4 x half> %4 # | %5 = load <4 x half>, ptr %__p2.addr.i, align 8 # | store <4 x half> %3, ptr %__p0.addr.i1, align 8 # | store <4 x half> %fneg.i, ptr %__p1.addr.i2, align 8 # | store <4 x half> %5, ptr %__p2.addr.i3, align 8 # | %6 = load <8 x i8>, ptr %__p0.addr.i1, align 8 # | %7 = load <8 x i8>, ptr %__p1.addr.i2, align 8 # | %8 = load <8 x i8>, ptr %__p2.addr.i3, align 8 # | %9 = bitcast <8 x i8> %6 to <4 x half> # | %10 = bitcast <8 x i8> %7 to <4 x half> # | %11 = bitcast <8 x i8> %8 to <4 x half> # | %12 = call <4 x half> @llvm.fma.v4f16(<4 x half> %10, <4 x half> %11, <4 x half> %9) # | store <4 x half> %12, ptr %ref.tmp.i, align 8 # | %13 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %13, ptr %__ret.i4, align 8 # | %14 = load <4 x half>, ptr %__ret.i4, align 8 # | store <4 x half> %14, ptr %__ret.i, align 8 # | %15 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %15 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vfmsq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i1 = alloca <8 x half>, align 16 # | %__p1.addr.i2 = alloca <8 x half>, align 16 # | %__p2.addr.i3 = alloca <8 x half>, align 16 # | %__ret.i4 = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store <8 x half> %c, ptr %c.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | %2 = load <8 x half>, ptr %c.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <8 x half>, ptr %__p0.addr.i, align 16 # | %4 = load <8 x half>, ptr %__p1.addr.i, align 16 # | %fneg.i = fneg <8 x half> %4 # | %5 = load <8 x half>, ptr %__p2.addr.i, align 16 # | store <8 x half> %3, ptr %__p0.addr.i1, align 16 # | store <8 x half> %fneg.i, ptr %__p1.addr.i2, align 16 # | store <8 x half> %5, ptr %__p2.addr.i3, align 16 # | %6 = load <16 x i8>, ptr %__p0.addr.i1, align 16 # | %7 = load <16 x i8>, ptr %__p1.addr.i2, align 16 # | %8 = load <16 x i8>, ptr %__p2.addr.i3, align 16 # | %9 = bitcast <16 x i8> %6 to <8 x half> # | %10 = bitcast <16 x i8> %7 to <8 x half> # | %11 = bitcast <16 x i8> %8 to <8 x half> # | %12 = call <8 x half> @llvm.fma.v8f16(<8 x half> %10, <8 x half> %11, <8 x half> %9) # | store <8 x half> %12, ptr %ref.tmp.i, align 16 # | %13 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %13, ptr %__ret.i4, align 16 # | %14 = load <8 x half>, ptr %__ret.i4, align 16 # | store <8 x half> %14, ptr %__ret.i, align 16 # | %15 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %15 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vfma_n_f16(<4 x half> noundef %a, <4 x half> noundef %b, half noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca half, align 2 # | %__ret = alloca <4 x half>, align 8 # | %__s0 = alloca <4 x half>, align 8 # | %__s1 = alloca <4 x half>, align 8 # | %__s2 = alloca half, align 2 # | %.compoundliteral = alloca <4 x half>, align 8 # | %tmp = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store half %c, ptr %c.addr, align 2 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__s0, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %1, ptr %__s1, align 8 # | %2 = load half, ptr %c.addr, align 2 # | store half %2, ptr %__s2, align 2 # | %3 = load <4 x half>, ptr %__s0, align 8 # | %4 = load <4 x half>, ptr %__s1, align 8 # | %5 = load half, ptr %__s2, align 2 # | %vecinit = insertelement <4 x half> poison, half %5, i32 0 # | %6 = load half, ptr %__s2, align 2 # | %vecinit1 = insertelement <4 x half> %vecinit, half %6, i32 1 # | %7 = load half, ptr %__s2, align 2 # | %vecinit2 = insertelement <4 x half> %vecinit1, half %7, i32 2 # | %8 = load half, ptr %__s2, align 2 # | %vecinit3 = insertelement <4 x half> %vecinit2, half %8, i32 3 # | store <4 x half> %vecinit3, ptr %.compoundliteral, align 8 # | %9 = load <4 x half>, ptr %.compoundliteral, align 8 # | store <4 x half> %3, ptr %__p0.addr.i, align 8 # | store <4 x half> %4, ptr %__p1.addr.i, align 8 # | store <4 x half> %9, ptr %__p2.addr.i, align 8 # | %10 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %11 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %12 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %13 = bitcast <8 x i8> %10 to <4 x half> # | %14 = bitcast <8 x i8> %11 to <4 x half> # | %15 = bitcast <8 x i8> %12 to <4 x half> # | %16 = call <4 x half> @llvm.fma.v4f16(<4 x half> %14, <4 x half> %15, <4 x half> %13) # | store <4 x half> %16, ptr %ref.tmp.i, align 8 # | %17 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %17, ptr %__ret.i, align 8 # | %18 = load <4 x half>, ptr %__ret.i, align 8 # | store <4 x half> %18, ptr %__ret, align 8 # | %19 = load <4 x half>, ptr %__ret, align 8 # | store <4 x half> %19, ptr %tmp, align 8 # | %20 = load <4 x half>, ptr %tmp, align 8 # | ret <4 x half> %20 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vfmaq_n_f16(<8 x half> noundef %a, <8 x half> noundef %b, half noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca half, align 2 # | %__ret = alloca <8 x half>, align 16 # | %__s0 = alloca <8 x half>, align 16 # | %__s1 = alloca <8 x half>, align 16 # | %__s2 = alloca half, align 2 # | %.compoundliteral = alloca <8 x half>, align 16 # | %tmp = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store half %c, ptr %c.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__s0, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %1, ptr %__s1, align 16 # | %2 = load half, ptr %c.addr, align 2 # | store half %2, ptr %__s2, align 2 # | %3 = load <8 x half>, ptr %__s0, align 16 # | %4 = load <8 x half>, ptr %__s1, align 16 # | %5 = load half, ptr %__s2, align 2 # | %vecinit = insertelement <8 x half> poison, half %5, i32 0 # | %6 = load half, ptr %__s2, align 2 # | %vecinit1 = insertelement <8 x half> %vecinit, half %6, i32 1 # | %7 = load half, ptr %__s2, align 2 # | %vecinit2 = insertelement <8 x half> %vecinit1, half %7, i32 2 # | %8 = load half, ptr %__s2, align 2 # | %vecinit3 = insertelement <8 x half> %vecinit2, half %8, i32 3 # | %9 = load half, ptr %__s2, align 2 # | %vecinit4 = insertelement <8 x half> %vecinit3, half %9, i32 4 # | %10 = load half, ptr %__s2, align 2 # | %vecinit5 = insertelement <8 x half> %vecinit4, half %10, i32 5 # | %11 = load half, ptr %__s2, align 2 # | %vecinit6 = insertelement <8 x half> %vecinit5, half %11, i32 6 # | %12 = load half, ptr %__s2, align 2 # | %vecinit7 = insertelement <8 x half> %vecinit6, half %12, i32 7 # | store <8 x half> %vecinit7, ptr %.compoundliteral, align 16 # | %13 = load <8 x half>, ptr %.compoundliteral, align 16 # | store <8 x half> %3, ptr %__p0.addr.i, align 16 # | store <8 x half> %4, ptr %__p1.addr.i, align 16 # | store <8 x half> %13, ptr %__p2.addr.i, align 16 # | %14 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %15 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %16 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %17 = bitcast <16 x i8> %14 to <8 x half> # | %18 = bitcast <16 x i8> %15 to <8 x half> # | %19 = bitcast <16 x i8> %16 to <8 x half> # | %20 = call <8 x half> @llvm.fma.v8f16(<8 x half> %18, <8 x half> %19, <8 x half> %17) # | store <8 x half> %20, ptr %ref.tmp.i, align 16 # | %21 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %21, ptr %__ret.i, align 16 # | %22 = load <8 x half>, ptr %__ret.i, align 16 # | store <8 x half> %22, ptr %__ret, align 16 # | %23 = load <8 x half>, ptr %__ret, align 16 # | store <8 x half> %23, ptr %tmp, align 16 # | %24 = load <8 x half>, ptr %tmp, align 16 # | ret <8 x half # | ... # `---data was truncated (10240/31903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000563b58b5a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563b58b57515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563b58b5acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa4b7e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa4b7ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa4b7e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa4b7e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563b58af024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563b58af0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563b58ad4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563b58784176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563b58783e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa4b7e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa4b7e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa4b7e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563b58783d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c (146 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv8i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv8i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv4i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv2i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv8i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_vnum_s16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv8i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv4i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv2i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_vnum_u16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv8i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c (147 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacle_f16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.facge.nxv8f16( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facge.nxv8f16(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacle_f32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.facge.nxv4f32( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facge.nxv4f32(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacle_f64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.facge.nxv2f64( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facge.nxv2f64(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacle_n_f32( %pg, %op1, float noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca float, align 4 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store float %op2, ptr %op2.addr, align 4 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %.splatinsert = insertelement poison, float %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.facge.nxv4f32( %3, %.splat, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacle_n_f64( %pg, %op1, double noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca double, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store double %op2, ptr %op2.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load double, ptr %op2.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %.splatinsert = insertelement poison, double %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.facge.nxv2f64( %3, %.splat, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055c6adc8a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c6adc87515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c6adc8acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6905049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f69050a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6905049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6905031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c6adc2024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c6adc20096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c6adc04f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c6ad8b4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c6ad8b3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6905032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f69050330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f69050330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c6ad8b3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c (148 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e1191a257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e11919f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e1191a2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f091a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f091a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f091a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f091a431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e11913824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e119138096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e11911cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e118dcc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e118dcbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f091a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f091a4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f091a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e118dcbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c (149 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0. # | ... # `---data was truncated (10240/87884) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005564913f257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005564913ef515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005564913f2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8afb933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8afb98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8afb933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8afb91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055649138824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556491388096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055649136cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055649101c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055649101be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8afb91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8afb91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8afb91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055649101bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c (150 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf8_b64( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf4_b32( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf2_b16( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8m1_b8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8m2_b4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.n # | ... # `---data was truncated (10240/95355) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e44adbb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e44adb8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e44adbbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f95bcc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f95bcca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f95bcc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f95bcc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e44ad5124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e44ad51096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e44ad35f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e44a9e5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e44a9e4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f95bcc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f95bcc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f95bcc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e44a9e4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c (151 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556fad27757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556fad274515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556fad277cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f996ae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f996aea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f996ae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f996ae31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556fad20d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556fad20d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556fad1f1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556facea1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556facea0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f996ae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f996ae330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f996ae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556facea0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c (152 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv8i8.nxv8i8.i64(, , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c (153 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_i8mf4x8(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bdb21f857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bdb21f5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bdb21f8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3ebfb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3ebfb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3ebfb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3ebfaed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bdb218e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bdb218e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bdb2172f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bdb1e22176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bdb1e21e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3ebfaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3ebfaef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3ebfaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bdb1e21d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c (154 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrh_u32base_s32index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrh.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.adrh.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrh_u64base_s64index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrh.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.adrh.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrh_u32base_u32index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrh.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrh_u64base_u64index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrh.nxv2i64( %0, %1) # | ret %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056104a87057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056104a86d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056104a870cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb5c1249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb5c12a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb5c1249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb5c1231507 abort ./stdlib/abort.c:85:3 # | #7 0x000056104a80624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056104a806096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056104a7eaf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056104a49a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056104a499e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb5c1232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb5c12330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb5c12330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056104a499d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c (155 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/48313) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055de52ba457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055de52ba1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055de52ba4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f58f4305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f58f435c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f58f4305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f58f42ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055de52b3a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055de52b3a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055de52b1ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055de527ce176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055de527cde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f58f42eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f58f42ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f58f42ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055de527cdd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c (156 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_sveor_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.eor.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.eor.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_sveor_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.eor.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.eor.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_sveor_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.eor.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.eor.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_sveor_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.eor.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.eor.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_sveor_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.eor.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_sveor_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.eor.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_sveor_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.eor.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_sveor_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.eor.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_sveor_s8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, pt # | ... # `---data was truncated (10240/52880) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055ecb9b3c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ecb9b39515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ecb9b3ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff77c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff77c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff77c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff77c31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ecb9ad224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ecb9ad2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ecb9ab6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ecb9766176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ecb9765e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff77c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff77c31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff77c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ecb9765d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c (157 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_svldr_zt(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sme.ldr.zt.p0(i32 0, ptr %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, target_mem0: readwrite) # | declare void @llvm.aarch64.sme.ldr.zt.p0(i32, ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_svstr_zt(ptr noundef %base) #2 { # | entry: # | %base.addr = alloca ptr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sme.str.zt.p0(i32 0, ptr %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write, target_mem0: readwrite) # | declare void @llvm.aarch64.sme.str.zt.p0(i32, ptr) #3 # | # | attributes #0 = { noinline nounwind "aarch64_out_zt0" "aarch64_pstate_sm_compatible" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, target_mem0: readwrite) } # | attributes #2 = { noinline nounwind "aarch64_in_zt0" "aarch64_pstate_sm_compatible" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #3 = { nocallback nofree nosync nounwind willreturn memory(argmem: write, target_mem0: readwrite) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055d8ee71e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d8ee71b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d8ee71ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1cd0305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1cd035c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1cd0305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1cd02ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d8ee6b424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d8ee6b4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d8ee698f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d8ee348176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d8ee347e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1cd02eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1cd02ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1cd02ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d8ee347d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c (158 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbic_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.bic.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.bic.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbic_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.bic.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.bic.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbic_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.bic.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.bic.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbic_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.bic.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.bic.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbic_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.bic.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbic_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.bic.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbic_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.bic.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbic_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.bic.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbic_s8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, pt # | ... # `---data was truncated (10240/52880) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000559ffb6a057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559ffb69d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559ffb6a0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff2cad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff2cad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff2cad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff2cad1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559ffb63624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559ffb636096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559ffb61af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559ffb2ca176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559ffb2c9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff2cad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff2cad1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff2cad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559ffb2c9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c (159 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpfirst_b( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.pfirst.nxv16i1( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pfirst.nxv16i1(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055d8566f957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d8566f6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d8566f9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe809a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe809a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe809a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe809a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d85668f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d85668f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d856673f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d856323176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d856322e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe809a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe809a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe809a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d856322d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c (160 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/87892) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056225ec8c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056225ec89515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056225ec8ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7917249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f79172a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7917249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7917231507 abort ./stdlib/abort.c:85:3 # | #7 0x000056225ec2224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056225ec22096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056225ec06f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056225e8b6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056225e8b5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7917232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f79172330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f79172330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056225e8b5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-vls-arith-ops.c (161 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-arith-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <64 x i8>, align 16 # | %a.addr = alloca <64 x i8>, align 16 # | %b.addr = alloca <64 x i8>, align 16 # | %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %a.coerce, i64 0) # | %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %b.coerce, i64 0) # | store <64 x i8> %a, ptr %a.addr, align 16 # | store <64 x i8> %b, ptr %b.addr, align 16 # | %0 = load <64 x i8>, ptr %a.addr, align 16 # | %1 = load <64 x i8>, ptr %b.addr, align 16 # | %add = add <64 x i8> %0, %1 # | store <64 x i8> %add, ptr %retval, align 16 # | %2 = load <64 x i8>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv16i8.v64i8( poison, <64 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16i8.v64i8(, <64 x i8>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_i16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i16>, align 16 # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca <32 x i16>, align 16 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %b.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store <32 x i16> %b, ptr %b.addr, align 16 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load <32 x i16>, ptr %b.addr, align 16 # | %add = add <32 x i16> %0, %1 # | store <32 x i16> %add, ptr %retval, align 16 # | %2 = load <32 x i16>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv8i16.v32i16( poison, <32 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8i16.v32i16(, <32 x i16>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_i32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i32>, align 16 # | %a.addr = alloca <16 x i32>, align 16 # | %b.addr = alloca <16 x i32>, align 16 # | %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %a.coerce, i64 0) # | %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %b.coerce, i64 0) # | store <16 x i32> %a, ptr %a.addr, align 16 # | store <16 x i32> %b, ptr %b.addr, align 16 # | %0 = load <16 x i32>, ptr %a.addr, align 16 # | %1 = load <16 x i32>, ptr %b.addr, align 16 # | %add = add <16 x i32> %0, %1 # | store <16 x i32> %add, ptr %retval, align 16 # | %2 = load <16 x i32>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv4i32.v16i32( poison, <16 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4i32.v16i32(, <16 x i32>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_i64( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i64>, align 16 # | %a.addr = alloca <8 x i64>, align 16 # | %b.addr = alloca <8 x i64>, align 16 # | %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64( %a.coerce, i64 0) # | %b = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64( %b.coerce, i64 0) # | store <8 x i64> %a, ptr %a.addr, align 16 # | store <8 x i64> %b, ptr %b.addr, align 16 # | %0 = load <8 x i64>, ptr %a.addr, align 16 # | %1 = load <8 x i64>, ptr %b.addr, align 16 # | %add = add <8 x i64> %0, %1 # | store <8 x i64> %add, ptr %retval, align 16 # | %2 = load <8 x i64>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv2i64.v8i64( poison, <8 x i64> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2i64.v8i64(, <8 x i64>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_u8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <64 x i8>, align 16 # | %a.addr = alloca <64 x i8>, align 16 # | %b.addr = alloca <64 x i8>, align 16 # | %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %a.coerce, i64 0) # | %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %b.coerce, i64 0) # | store <64 x i8> %a, ptr %a.addr, align 16 # | store <64 x i8> %b, ptr %b.addr, align 16 # | %0 = load <64 x i8>, ptr %a.addr, align 16 # | %1 = load <64 x i8>, ptr %b.addr, align 16 # | %add = add <64 x i8> %0, %1 # | store <64 x i8> %add, ptr %retval, align 16 # | %2 = load <64 x i8>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv16i8.v64i8( poison, <64 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_u16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i16>, align 16 # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca <32 x i16>, align 16 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %b.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store <32 x i16> %b, ptr %b.addr, align 16 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load <32 x i16>, ptr %b.addr, align 16 # | %add = add <32 x i16> %0, %1 # | store <32 x i16> %add, ptr %retval, align 16 # | %2 = load <32 x i16>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv8i16.v32i16( poison, <32 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_u32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i32>, align 16 # | %a.addr = alloca <16 x i32>, align 16 # | %b.addr = alloca <16 x i32>, align 16 # | %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %a.coerce, i64 0) # | %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %b.coerce, i64 0) # | store <16 x i32> %a, ptr %a.addr, align 16 # | store <16 x i32> %b, ptr %b.addr, align 16 # | %0 = load <16 x i32>, ptr %a.addr, align 16 # | %1 = load <16 x i32>, ptr %b.addr, align 16 # | %add = add <16 x i32> %0, %1 # | store <16 x i32> %add, ptr %retval, align 16 # | %2 = load <16 x i32>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv4i32.v16i32( poison, <16 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_u64( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i64>, align 16 # | %a.addr = alloca <8 x i64>, align 16 # | %b.addr = alloca <8 x i64>, align 16 # | %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64( %a.coerce, i64 0) # | %b = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64( %b.coerce, i64 0) # | store <8 x i64> %a, ptr %a.addr, align 16 # | store <8 x i64> %b, ptr %b.addr, align 16 # | %0 = load <8 x i64>, ptr %a.addr, align 16 # | %1 = load <8 x i64>, ptr %b.addr, align 16 # | %add = add <8 x i64> %0, %1 # | store <8 x i64> %add, ptr %retval, align 16 # | %2 = load <8 x i64>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv2i64.v8i64( poison, <8 x i64> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_f16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x half>, align 16 # | %a.addr = alloca <32 x half>, align 16 # | %b.addr = alloca <32 x half>, align 16 # | %a = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16( %a.coerce, i64 0) # | %b = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16( %b.coerce, i64 0) # | store <32 x half> %a, ptr %a.addr, align 16 # | store <32 x half> %b, ptr %b.addr, align 16 # | %0 = load <32 x ha # | ... # `---data was truncated (10240/161192) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x000055943a1c857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055943a1c5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055943a1c8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2416b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2416b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2416b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2416b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055943a15e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055943a15e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055943a142f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559439df2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559439df1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2416b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2416b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2416b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559439df1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c (162 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005573b1de857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005573b1de5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005573b1de8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbf32049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbf320a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbf32049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbf32031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005573b1d7e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005573b1d7e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005573b1d62f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005573b1a12176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005573b1a11e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbf32032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbf320330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbf320330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005573b1a11d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c (163 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_f16( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fclamp.nxv8f16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fclamp.nxv8f16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_f32( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fclamp.nxv4f32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fclamp.nxv4f32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_f64( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fclamp.nxv2f64( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fclamp.nxv2f64(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055e23f83957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e23f836515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e23f839cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f183a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f183a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f183a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f183a631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e23f7cf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e23f7cf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e23f7b3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e23f463176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e23f462e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f183a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f183a6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f183a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e23f462d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c (164 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind w # | ... # `---data was truncated (10240/20198) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005561a077257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005561a076f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005561a0772cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f97f6733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f97f678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f97f6733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f97f671b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005561a070824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005561a0708096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005561a06ecf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005561a039c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005561a039be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f97f671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f97f671d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f97f671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005561a039bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c (165 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbrkn_b_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.brkn.z.nxv16i1( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.brkn.z.nxv16i1(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055e6734c857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e6734c5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e6734c8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0ca3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0ca338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0ca3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0ca331b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e67345e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e67345e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e673442f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e6730f2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e6730f1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0ca331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0ca331d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0ca331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e6730f1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c (166 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a13f0ae57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a13f0ab515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a13f0aecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd327e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd327e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd327e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd327e03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a13f04424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a13f044096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a13f028f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a13ecd8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a13ecd7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd327e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd327e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd327e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a13ecd7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c (167 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", # | ... # `---data was truncated (10240/19492) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e5da90c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e5da909515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e5da90ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4ccd733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4ccd78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4ccd733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4ccd71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e5da8a224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e5da8a2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e5da886f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e5da536176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e5da535e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4ccd71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4ccd71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4ccd71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e5da535d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c (168 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmsb_s8_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = select %0, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.msb.nxv16i8( %0, %4, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.msb.nxv16i8(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmsb_s16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.msb.nxv8i16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.msb.nxv8i16(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmsb_s32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.msb.nxv4i32( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.msb.nxv4i32(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmsb_s64_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.msb.nxv2i64( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.msb.nxv2i64(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmsb_u8_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = select %0, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.msb.nxv16i8( %0, %4, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmsb_u16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.msb.nxv8i16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmsb_u32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.msb.nxv4i32( %4, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c (169 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558d535ff57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558d535fc515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558d535ffcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6ec3a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6ec3aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6ec3a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6ec3a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558d5359524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558d53595096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558d53579f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558d53229176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558d53228e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6ec3a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6ec3a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6ec3a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558d53228d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c (170 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f8f267a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f8f2677515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f8f267acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f00da133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f00da18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f00da133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f00da11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f8f261024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f8f2610096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f8f25f4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f8f22a4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f8f22a3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f00da11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f00da11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f00da11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f8f22a3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c (171 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c (172 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1q_scatter_u64base_offset_u64( %pg, %base, i64 noundef %offset, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv2i64.nxv2i64( %3, %4, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv2i64.nxv2i64(, , , i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv1i1() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1q_scatter_u64base_offset_s64( %pg, %base, i64 noundef %offset, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv2i64.nxv2i64( %3, %4, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1q_scatter_u64base_offset_u32( %pg, %base, i64 noundef %offset, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv4i32.nxv2i64( %3, %4, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv4i32.nxv2i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1q_scatter_u64base_offset_s32( %pg, %base, i64 noundef %offset, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv4i32.nxv2i64( %3, %4, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1q_scatter_u64base_offset_u16( %pg, %base, i64 noundef %offset, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv8i16.nxv2i64( %3, %4, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv8i16.nxv2i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1q_scatter_u64base_offset_s16( %pg, %base, i64 noundef %offset, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv8i16.nxv2i64( %3, %4, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1q_scatter_u64base_offset_u8( %pg, %base, i64 noundef %offset, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv16i8.nxv2i64( %3, %4, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv16i8.nxv2i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1q_scatter_u64base_offset_s8( %pg, %base, i64 noundef %offset, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv16i8.nxv2i64( %3, % # | ... # `---data was truncated (10240/93831) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055aa0f07757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055aa0f074515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055aa0f077cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd938a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd938a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd938a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd938a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aa0f00d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055aa0f00d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055aa0eff1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055aa0eca1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055aa0eca0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd938a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd938a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd938a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aa0eca0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c (173 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv16f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv16f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m8_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv32f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv32f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32mf2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv1f32.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32m1_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv2f32.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32m2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = all # | ... # `---data was truncated (10240/147390) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fe339ce57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fe339cb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fe339cecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4589533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f458958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4589533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f458951b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fe3396424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fe33964096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fe33948f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fe335f8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fe335f7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f458951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f458951d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f458951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fe335f7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c (174 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svwrite_ver_za8_u8_vg2(i32 noundef %base, %val.coerce0, %val.coerce1) #0 { # | entry: # | %val = alloca { , }, align 16 # | %base.addr = alloca i32, align 4 # | %val.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %val.coerce0, 0 # | %1 = insertvalue { , } %0, %val.coerce1, 1 # | store { , } %1, ptr %val, align 16 # | %val1 = load { , }, ptr %val, align 16 # | store i32 %base, ptr %base.addr, align 4 # | store { , } %val1, ptr %val.addr, align 16 # | %2 = load i32, ptr %base.addr, align 4 # | %3 = load { , }, ptr %val.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.write.ver.vg2.nxv16i8(i32 0, i32 %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.write.ver.vg2.nxv16i8(i32 immarg, i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svwrite_ver_za8_s8_vg2(i32 noundef %base, %val.coerce0, %val.coerce1) #0 { # | entry: # | %val = alloca { , }, align 16 # | %base.addr = alloca i32, align 4 # | %val.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %val.coerce0, 0 # | %1 = insertvalue { , } %0, %val.coerce1, 1 # | store { , } %1, ptr %val, align 16 # | %val1 = load { , }, ptr %val, align 16 # | store i32 %base, ptr %base.addr, align 4 # | store { , } %val1, ptr %val.addr, align 16 # | %2 = load i32, ptr %base.addr, align 4 # | %3 = load { , }, ptr %val.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.write.ver.vg2.nxv16i8(i32 0, i32 %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svwrite_ver_za8_mf8_vg2(i32 noundef %base, %val.coerce0, %val.coerce1) #0 { # | entry: # | %val = alloca { , }, align 16 # | %base.addr = alloca i32, align 4 # | %val.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %val.coerce0, 0 # | %1 = insertvalue { , } %0, %val.coerce1, 1 # | store { , } %1, ptr %val, align 16 # | %val1 = load { , }, ptr %val, align 16 # | store i32 %base, ptr %base.addr, align 4 # | store { , } %val1, ptr %val.addr, align 16 # | %2 = load i32, ptr %base.addr, align 4 # | %3 = load { , }, ptr %val.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.write.ver.vg2.nxv16i8(i32 0, i32 %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svwrite_hor_za8_u8_vg2(i32 noundef %base, %val.coerce0, %val.coerce1) #0 { # | entry: # | %val = alloca { , }, align 16 # | %base.addr = alloca i32, align 4 # | %val.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %val.coerce0, 0 # | %1 = insertvalue { , } %0, %val.coerce1, 1 # | store { , } %1, ptr %val, align 16 # | %val1 = load { , }, ptr %val, align 16 # | store i32 %base, ptr %base.addr, align 4 # | store { , } %val1, ptr %val.addr, align 16 # | %2 = load i32, ptr %base.addr, align 4 # | %3 = load { , }, ptr %val.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.write.hor.vg2.nxv16i8(i32 0, i32 %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.write.hor.vg2.nxv16i8(i32 immarg, i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svwrite_hor_za8_s8_vg2(i32 noundef %base, %val.coerce0, %val.coerce1) #0 { # | entry: # | %val = alloca { , }, align 16 # | %base.addr = alloca i32, align 4 # | %val.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %val.coerce0, 0 # | %1 = insertvalue { , } %0, %val.coerce1, 1 # | store { , } %1, ptr %val, align 16 # | %val1 = load { , }, ptr %val, align 16 # | store i32 %base, ptr %base.addr, align 4 # | store { , } %val1, ptr %val.addr, align 16 # | %2 = load i32, ptr %base.addr, align 4 # | %3 = load { , }, ptr %val.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.write.hor.vg2.nxv16i8(i32 0, i32 %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svwrite_hor_za8_mf8_vg2(i32 noundef %base, %val.coerce0, %val.coerce1) #0 { # | entry: # | %val = alloca { , }, align 16 # | %base.addr = alloca i32, align 4 # | %val.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %val.coerce0, 0 # | %1 = insertvalue { , } %0, %val.coerce1, 1 # | store { , } %1, ptr %val, align 16 # | %val1 = load { , }, ptr %val, align 16 # | store i32 %base, ptr %base.addr, align 4 # | store { , } %val1, ptr %val.addr, align 16 # | %2 = load i32, ptr %base.addr, align 4 # | %3 = load { , }, ptr %val.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.write.hor.vg2.nxv16i8(i32 0, i32 %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svwrite_hor_za8_u8_vg4(i32 noundef %base, %val.coerce0, %val.coerce1, %val.coerce2, %val.coerce3) #0 { # | entry: # | %val = alloca { , , , }, align 16 # | %base.addr = alloca i32, align 4 # | %val.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %val.coerce0, 0 # | %1 = insertvalue { , , , } %0, %val.coerce1, 1 # | %2 = insertvalue { , , , } %1, %val.coerce2, 2 # | %3 = insertvalue { , , , } %2, %val.coerce3, 3 # | store { , , , } %3, ptr %val, align 16 # | %val1 = load { , , , }, ptr %val, align 16 # | store i32 %base, ptr %base.addr, align 4 # | store { , , , } %val1, ptr %val.addr, align 16 # | %4 = load i32, ptr %base.addr, align 4 # | %5 = load { , , , }, ptr %val.addr, align 16 # | %6 = extractvalue { , , , } %5, 0 # | %7 = extractvalue { , , , } %5, 1 # | %8 = extractvalue { , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/neon/intrinsics.c (175 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon/intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c --check-prefixes=ALL,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vmaxnmv_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca float, align 4 # | %ref.tmp.i = alloca float, align 4 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <2 x float>, ptr %__p0.addr.i, align 8 # | %vmaxnmv_f32.i = call float @llvm.aarch64.neon.fmaxnmv.f32.v2f32(<2 x float> %1) # | store float %vmaxnmv_f32.i, ptr %ref.tmp.i, align 4 # | %2 = load float, ptr %ref.tmp.i, align 4 # | store float %2, ptr %__ret.i, align 4 # | %3 = load float, ptr %__ret.i, align 4 # | ret float %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vmaxnmvq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca float, align 4 # | %ref.tmp.i = alloca float, align 4 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %vmaxnmvq_f32.i = call float @llvm.aarch64.neon.fmaxnmv.f32.v4f32(<4 x float> %1) # | store float %vmaxnmvq_f32.i, ptr %ref.tmp.i, align 4 # | %2 = load float, ptr %ref.tmp.i, align 4 # | store float %2, ptr %__ret.i, align 4 # | %3 = load float, ptr %__ret.i, align 4 # | ret float %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_vmaxnmvq_f64(<2 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca double, align 8 # | %ref.tmp.i = alloca double, align 8 # | %a.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x double>, ptr %__p0.addr.i, align 16 # | %vmaxnmvq_f64.i = call double @llvm.aarch64.neon.fmaxnmv.f64.v2f64(<2 x double> %1) # | store double %vmaxnmvq_f64.i, ptr %ref.tmp.i, align 8 # | %2 = load double, ptr %ref.tmp.i, align 8 # | store double %2, ptr %__ret.i, align 8 # | %3 = load double, ptr %__ret.i, align 8 # | ret double %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i8 @test_vqrshrunh_n_s16(i16 noundef %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %__ret = alloca i8, align 1 # | %__s0 = alloca i16, align 2 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | store i16 %0, ptr %__s0, align 2 # | %1 = load i16, ptr %__s0, align 2 # | %2 = insertelement <8 x i16> poison, i16 %1, i64 0 # | %vqrshrunh_n_s16 = call <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16> %2, i32 8) # | %3 = extractelement <8 x i8> %vqrshrunh_n_s16, i64 0 # | store i8 %3, ptr %ref.tmp, align 1 # | %4 = load i8, ptr %ref.tmp, align 1 # | store i8 %4, ptr %__ret, align 1 # | %5 = load i8, ptr %__ret, align 1 # | store i8 %5, ptr %tmp, align 1 # | %6 = load i8, ptr %tmp, align 1 # | ret i8 %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vqrshruns_n_s32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %__ret = alloca i16, align 2 # | %__s0 = alloca i32, align 4 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__s0, align 4 # | %1 = load i32, ptr %__s0, align 4 # | %2 = insertelement <4 x i32> poison, i32 %1, i64 0 # | %vqrshruns_n_s32 = call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> %2, i32 16) # | %3 = extractelement <4 x i16> %vqrshruns_n_s32, i64 0 # | store i16 %3, ptr %ref.tmp, align 2 # | %4 = load i16, ptr %ref.tmp, align 2 # | store i16 %4, ptr %__ret, align 2 # | %5 = load i16, ptr %__ret, align 2 # | store i16 %5, ptr %tmp, align 2 # | %6 = load i16, ptr %tmp, align 2 # | ret i16 %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i8 @test_vqrshrnh_n_s16(i16 noundef %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %__ret = alloca i8, align 1 # | %__s0 = alloca i16, align 2 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | store i16 %0, ptr %__s0, align 2 # | %1 = load i16, ptr %__s0, align 2 # | %2 = insertelement <8 x i16> poison, i16 %1, i64 0 # | %vqrshrnh_n_s16 = call <8 x i8> @llvm.aarch64.neon.sqrshrn.v8i8(<8 x i16> %2, i32 8) # | %3 = extractelement <8 x i8> %vqrshrnh_n_s16, i64 0 # | store i8 %3, ptr %ref.tmp, align 1 # | %4 = load i8, ptr %ref.tmp, align 1 # | store i8 %4, ptr %__ret, align 1 # | %5 = load i8, ptr %__ret, align 1 # | store i8 %5, ptr %tmp, align 1 # | %6 = load i8, ptr %tmp, align 1 # | ret i8 %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i8> @llvm.aarch64.neon.sqrshrn.v8i8(<8 x i16>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vqrshrns_n_s32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %__ret = alloca i16, align 2 # | %__s0 = alloca i32, align 4 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__s0, align 4 # | %1 = load i32, ptr %__s0, align 4 # | %2 = insertelement <4 x i32> poison, i32 %1, i64 0 # | %vqrshrns_n_s32 = call <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32> %2, i32 16) # | %3 = extractelement <4 x i16> %vqrshrns_n_s32, i64 0 # | store i16 %3, ptr %ref.tmp, align 2 # | %4 = load i16, ptr %ref.tmp, align 2 # | store i16 %4, ptr %__ret, align 2 # | %5 = load i16, ptr %__ret, align 2 # | store i16 %5, ptr %tmp, align 2 # | %6 = load i16, ptr %tmp, align 2 # | ret i16 %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i8 @test_vqrshrnh_n_u16(i16 noundef %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %__ret = alloca i8, align 1 # | %__s0 = alloca i16, align 2 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | store i16 %0, ptr %__s0, align 2 # | %1 = load i16, ptr %__s0, align 2 # | %2 = insertelement <8 x i16> poison, i16 %1, i64 0 # | %vqrshrnh_n_u16 = call <8 x i8> @llvm.aarch64.neon.uqrshrn.v8i8(<8 x i16> %2, i32 8) # | %3 = extractelement <8 x i8> %vqrshrnh_n_u16, i64 0 # | store i8 %3, ptr %ref.tmp, align 1 # | %4 = load i8, ptr %ref.tmp, align 1 # | store i8 %4, ptr %__ret, align 1 # | %5 = load i8, ptr %__ret, align 1 # | store i8 %5, ptr %tmp, align 1 # | %6 = load i8, ptr %tmp, align 1 # | ret i8 %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i8> @llvm.aarch64.neon.uqrshrn.v8i8(<8 x i16>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vqrshrns_n_u32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %__ret = alloca i16, align 2 # | %__s0 = alloca i32, align 4 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__s0, align 4 # | %1 = load i32, ptr %__s0, align 4 # | %2 = insertelement <4 x i32> poison, i32 %1, i64 0 # | %vqrshrns_n_u32 = call <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32> %2, i32 16) # | %3 = extractelement <4 x i16> %vqrshrns_n_u32, i64 0 # | store i16 %3, ptr %ref.tmp, align 2 # | %4 = load i16, ptr %ref.tmp, align 2 # | store i16 %4, ptr %__ret, align 2 # | %5 = load i16, ptr %__ret, align 2 # | store i16 %5, ptr %tmp, align 2 # | %6 = load i16, ptr %tmp, align 2 # | ret i16 %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vqrshrun_n_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 16 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i16>, align 16 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__s0, align 16 # | %1 = load <16 x i8>, ptr %__s0, align 16 # | %vqrshrun_n = bitcast <16 x i8> %1 to <8 x i16> # | %vqrshrun_n1 = call <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16> %vqrshrun_n, i32 3) # | store <8 x i8> %vqrshrun_n1, ptr %ref.tmp, align 8 # | %2 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %2, ptr %__ret, align 8 # | %3 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %3, ptr %tmp, align 8 # | %4 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vqrshrun_n_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 16 # | %__ret = alloca <4 x i16>, align 8 # | %__s0 = alloca <4 x i32>, align 16 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x i16>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__s0, align 16 # | %1 = load <16 x i8>, ptr %__s0, align 16 # | %vqrshrun_n = bitcast <16 x i8> %1 to <4 x i32> # | %vqrshrun_n1 = call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> %vqrshrun_n, i32 9) # | store <4 x i16> %vqrshrun_n1, ptr %ref.tmp, align 8 # | %2 = load <4 x i16>, ptr %ref.tmp, align 8 # | store <4 x i16> %2, ptr %__ret, align 8 # | %3 = load <4 x i16>, p # | ... # `---data was truncated (10240/770739) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055656094357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556560940515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556560943cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f83c0649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f83c06a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f83c0649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f83c0631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005565608d924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005565608d9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005565608bdf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055656056d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055656056ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f83c0632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f83c06330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f83c06330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055656056cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c --check-prefixes=ALL,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c --check-prefixes=ALL,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c (176 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vvm_i8mf8_b64( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vxm_i8mf8_b64( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadc.carry.in.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.carry.in.nxv1i8.i8.i64(, i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmadc.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmadc.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vvm_i8mf4_b32( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vxm_i8mf4_b32( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadc.carry.in.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.carry.in.nxv2i8.i8.i64(, i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmadc.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmadc.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vvm_i8mf2_b16( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vxm_i8mf2_b16( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | # | ... # `---data was truncated (10240/169917) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ed6c7af57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ed6c7ac515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ed6c7afcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbc04533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbc0458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbc04533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbc0451b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ed6c74524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ed6c745096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ed6c729f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ed6c3d9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ed6c3d8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbc0451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbc0451d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbc0451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ed6c3d8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c (177 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svstnt1_s8( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | call void @llvm.aarch64.sve.stnt1.nxv16i8.p0( %2, %0, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.stnt1.nxv16i8.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svstnt1_s16( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.stnt1.nxv8i16.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.stnt1.nxv8i16.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svstnt1_s32( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.stnt1.nxv4i32.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.stnt1.nxv4i32.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svstnt1_s64( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.stnt1.nxv2i64.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.stnt1.nxv2i64.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svstnt1_u8( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | call void @llvm.aarch64.sve.stnt1.nxv16i8.p0( %2, %0, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svstnt1_u16( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.stnt1.nxv8i16.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svstnt1_u32( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.stnt1.nxv4i32.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svstnt1_u64( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.stnt1.nxv2i64.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svstnt1_f16( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.stnt1.nxv8f16.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.stnt1.nxv8f16.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svstnt1_f32( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.stnt1.nxv4f32.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.stnt1.nxv4f32.p0(, , ptr # | ... # `---data was truncated (10240/26796) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000563b6a0ef57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563b6a0ec515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563b6a0efcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3d96933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3d9698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3d96933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3d9691b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563b6a08524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563b6a085096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563b6a069f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563b69d19176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563b69d18e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3d9691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3d9691d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3d9691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563b69d18d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c (178 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_cvt_f16_x2( %zn.coerce0, %zn.coerce1, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %5) # | %6 = call @llvm.aarch64.sve.fp8.cvt.x2.nxv8f16( %3, %4) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvt.x2.nxv8f16(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_cvt_f32_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %9) # | %10 = call @llvm.aarch64.sve.fp8.cvt.x4( %5, %6, %7, %8) # | ret %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvt.x4(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_cvtn_f32_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %9) # | %10 = call @llvm.aarch64.sve.fp8.cvtn.x4( %5, %6, %7, %8) # | ret %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvtn.x4(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_cvt_bf16_x2( %zn.coerce0, %zn.coerce1, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %5) # | %6 = call @llvm.aarch64.sve.fp8.cvt.x2.nxv8bf16( %3, %4) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvt.x2.nxv8bf16(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_cvt1_f16_x2( %zn, i64 noundef %fpmr) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %1) # | %2 = call { , } @llvm.aarch64.sve.fp8.cvt1.x2.nxv8f16( %0) # | ret { , } %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare { , } @llvm.aarch64.sve.fp8.cvt1.x2.nxv8f16() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_cvt2_f16_x2( %zn, i64 noundef %fpmr) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr # | ... # `---data was truncated (10240/17058) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000557b0486557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557b04862515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557b04865cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1c4a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1c4a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1c4a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1c4a51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557b047fb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557b047fb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557b047dff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557b0448f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557b0448ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1c4a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1c4a51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1c4a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557b0448ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c (179 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/175163) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056096c4ab57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056096c4a8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056096c4abcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa2b4933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa2b498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa2b4933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa2b491b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056096c44124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056096c441096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056096c425f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056096c0d5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056096c0d4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa2b491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa2b491d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa2b491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056096c0d4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c (180 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls2_f16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.fmlsl.vg2x2.nxv8f16(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fmlsl.vg2x2.nxv8f16(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls2_bf16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.fmlsl.vg2x2.nxv8bf16(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fmlsl.vg2x2.nxv8bf16(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls2_u16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.umlsl.vg2x2.nxv8i16(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umlsl.vg2x2.nxv8i16(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls2_s16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.smlsl.vg2x2.nxv8i16(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smlsl.vg2x2.nxv8i16(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls4 # | ... # `---data was truncated (10240/73614) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005568b094b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005568b0948515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005568b094bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f15f7b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f15f7b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f15f7b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f15f7b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005568b08e124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005568b08e1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005568b08c5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005568b0575176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005568b0574e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f15f7b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f15f7b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f15f7b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005568b0574d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c (181 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 # | ... # `---data was truncated (10240/66565) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055693f17c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055693f179515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055693f17ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3ff4f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3ff4f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3ff4f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3ff4f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055693f11224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055693f112096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055693f0f6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055693eda6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055693eda5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3ff4f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3ff4f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3ff4f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055693eda5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c (182 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_b8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.zip2.nxv16i1( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_b16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.zip2.b16( %0, %1) # | ret %2 # | ... # `---data was truncated (10240/13404) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000561eb3fa957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561eb3fa6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561eb3fa9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faea9249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faea92a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faea9249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faea9231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561eb3f3f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561eb3f3f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561eb3f23f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561eb3bd3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561eb3bd2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007faea9232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faea92330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faea92330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561eb3bd2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/X86/avx-cmp-builtins.c (183 of 27911) ******************** TEST 'Clang :: CodeGen/X86/avx-cmp-builtins.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -flax-vector-conversions=none -ffreestanding /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c -triple=x86_64-- -target-feature +avx -disable-O0-optnone -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -flax-vector-conversions=none -ffreestanding /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c -triple=x86_64-- -target-feature +avx -disable-O0-optnone -emit-llvm -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-unknown" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_cmp_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 { # | entry: # | %a.addr = alloca <2 x double>, align 16 # | %b.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | store <2 x double> %b, ptr %b.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | %1 = load <2 x double>, ptr %b.addr, align 16 # | %2 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %0, <2 x double> %1, i8 13) # | ret <2 x double> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double>, <2 x double>, i8 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_cmp_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <4 x float> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | %2 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %0, <4 x float> %1, i8 13) # | ret <4 x float> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.x86.sse.cmp.ss(<4 x float>, <4 x float>, i8 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_cmpgt_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %__a.addr.i = alloca <4 x float>, align 16 # | %__b.addr.i = alloca <4 x float>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <4 x float> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | store <4 x float> %0, ptr %__a.addr.i, align 16 # | store <4 x float> %1, ptr %__b.addr.i, align 16 # | %2 = load <4 x float>, ptr %__a.addr.i, align 16 # | %3 = load <4 x float>, ptr %__b.addr.i, align 16 # | %4 = load <4 x float>, ptr %__a.addr.i, align 16 # | %5 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %3, <4 x float> %4, i8 1) # | %shuffle.i = shufflevector <4 x float> %2, <4 x float> %5, <4 x i32> # | ret <4 x float> %shuffle.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_cmpge_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %__a.addr.i = alloca <4 x float>, align 16 # | %__b.addr.i = alloca <4 x float>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <4 x float> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | store <4 x float> %0, ptr %__a.addr.i, align 16 # | store <4 x float> %1, ptr %__b.addr.i, align 16 # | %2 = load <4 x float>, ptr %__a.addr.i, align 16 # | %3 = load <4 x float>, ptr %__b.addr.i, align 16 # | %4 = load <4 x float>, ptr %__a.addr.i, align 16 # | %5 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %3, <4 x float> %4, i8 2) # | %shuffle.i = shufflevector <4 x float> %2, <4 x float> %5, <4 x i32> # | ret <4 x float> %shuffle.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_cmpngt_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %__a.addr.i = alloca <4 x float>, align 16 # | %__b.addr.i = alloca <4 x float>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <4 x float> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | store <4 x float> %0, ptr %__a.addr.i, align 16 # | store <4 x float> %1, ptr %__b.addr.i, align 16 # | %2 = load <4 x float>, ptr %__a.addr.i, align 16 # | %3 = load <4 x float>, ptr %__b.addr.i, align 16 # | %4 = load <4 x float>, ptr %__a.addr.i, align 16 # | %5 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %3, <4 x float> %4, i8 5) # | %shuffle.i = shufflevector <4 x float> %2, <4 x float> %5, <4 x i32> # | ret <4 x float> %shuffle.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_cmpnge_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %__a.addr.i = alloca <4 x float>, align 16 # | %__b.addr.i = alloca <4 x float>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <4 x float> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | store <4 x float> %0, ptr %__a.addr.i, align 16 # | store <4 x float> %1, ptr %__b.addr.i, align 16 # | %2 = load <4 x float>, ptr %__a.addr.i, align 16 # | %3 = load <4 x float>, ptr %__b.addr.i, align 16 # | %4 = load <4 x float>, ptr %__a.addr.i, align 16 # | %5 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %3, <4 x float> %4, i8 6) # | %shuffle.i = shufflevector <4 x float> %2, <4 x float> %5, <4 x i32> # | ret <4 x float> %shuffle.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_cmpgt_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 { # | entry: # | %__a.addr.i = alloca <2 x double>, align 16 # | %__b.addr.i = alloca <2 x double>, align 16 # | %__c.i = alloca <2 x double>, align 16 # | %.compoundliteral.i = alloca <2 x double>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | %b.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | store <2 x double> %b, ptr %b.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | %1 = load <2 x double>, ptr %b.addr, align 16 # | store <2 x double> %0, ptr %__a.addr.i, align 16 # | store <2 x double> %1, ptr %__b.addr.i, align 16 # | %2 = load <2 x double>, ptr %__b.addr.i, align 16 # | %3 = load <2 x double>, ptr %__a.addr.i, align 16 # | %4 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %2, <2 x double> %3, i8 1) # | store <2 x double> %4, ptr %__c.i, align 16 # | %5 = load <2 x double>, ptr %__c.i, align 16 # | %vecext.i = extractelement <2 x double> %5, i32 0 # | %vecinit.i = insertelement <2 x double> poison, double %vecext.i, i32 0 # | %6 = load <2 x double>, ptr %__a.addr.i, align 16 # | %vecext1.i = extractelement <2 x double> %6, i32 1 # | %vecinit2.i = insertelement <2 x double> %vecinit.i, double %vecext1.i, i32 1 # | store <2 x double> %vecinit2.i, ptr %.compoundliteral.i, align 16 # | %7 = load <2 x double>, ptr %.compoundliteral.i, align 16 # | ret <2 x double> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_cmpge_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 { # | entry: # | %__a.addr.i = alloca <2 x double>, align 16 # | %__b.addr.i = alloca <2 x double>, align 16 # | %__c.i = alloca <2 x double>, align 16 # | %.compoundliteral.i = alloca <2 x double>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | %b.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | store <2 x double> %b, ptr %b.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | %1 = load <2 x double>, ptr %b.addr, align 16 # | store <2 x double> %0, ptr %__a.addr.i, align 16 # | store <2 x double> %1, ptr %__b.addr.i, align 16 # | %2 = load <2 x double>, ptr %__b.addr.i, align 16 # | %3 = load <2 x double>, ptr %__a.addr.i, align 16 # | %4 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %2, <2 x double> %3, i8 2) # | store <2 x double> %4, ptr %__c.i, align 16 # | %5 = load <2 x double>, ptr %__c.i, align 16 # | %vecext.i = extractelement <2 x double> %5, i32 0 # | %vecinit.i = insertelement <2 x double> poison, double %vecext.i, i32 0 # | %6 = load <2 x double>, ptr %__a.addr.i, align 16 # | %vecext1.i = extractelement <2 x double> %6, i32 1 # | %vecinit2.i = insertelement <2 x double> %vecinit.i, double %vecext1.i, i32 1 # | store <2 x double> %vecinit2.i, ptr %.compoundliteral.i, align 16 # | %7 = load <2 x double>, ptr %.compoundliteral.i, align 16 # | ret <2 x double> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_cmpngt_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 { # | entry: # | %__a.addr.i = alloca <2 x double>, align 16 # | %__b.addr.i = alloca <2 x double>, align 16 # | %__c.i = alloca <2 x double>, align 16 # | %.compoundliteral.i = alloca <2 x double>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | %b.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | store <2 x double> %b, ptr %b.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | %1 = load <2 x double>, ptr %b.addr, align 16 # | store <2 x double> %0, ptr %__a.addr.i, align 16 # | store <2 x double> %1, ptr %__b.addr.i, align 16 # | %2 = load <2 x double>, ptr %__b.addr.i, align 16 # | %3 = load <2 x double>, ptr %__a.addr.i, align 16 # | %4 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %2, <2 x double> %3, i8 5) # | store <2 x double> %4, ptr %__c.i, align 16 # | %5 = load <2 x double>, ptr %__c.i, align 16 # | %vecext.i = extractelement <2 x double> %5, i32 0 # | %vecinit.i = insertelement <2 x double> poison, double %vecext.i, i32 0 # | %6 = load <2 x double>, ptr %__a.addr.i, align 16 # | %vecext1.i = extractelement <2 x double> %6, i32 1 # | %vecinit2.i = insertelement <2 x double> %vecinit.i, double %vecext1.i, i32 1 # | store <2 x double> %vecinit2.i, ptr %.compoundliteral.i, align 16 # | %7 = load <2 x double>, ptr %.compoundliteral.i, align 16 # | ret <2 x double> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_cmpnge_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 { # | entry: # | %__a.addr.i = alloca <2 x double>, align 16 # | %__b.addr.i = alloca <2 x double>, align 16 # | %__c.i = alloca <2 x double>, align 16 # | %.compoundlit # | ... # `---data was truncated (10240/11780) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c3f63f957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c3f63f6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c3f63f9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7e96f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7e96f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7e96f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7e96f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c3f638f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c3f638f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c3f6373f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c3f6023176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c3f6022e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7e96f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7e96f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7e96f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c3f6022d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c (184 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv2f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32m2_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c (185 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv8bf16.nxv8f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv8bf16.nxv8f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv16bf16.nxv16f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @ # | ... # `---data was truncated (10240/18570) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005630b7d5157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005630b7d4e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005630b7d51cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4d74733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4d7478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4d74733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4d7471b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005630b7ce724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005630b7ce7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005630b7ccbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005630b797b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005630b797ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4d7471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4d7471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4d7471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005630b797ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c (186 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasr_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.asr.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.asr.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasr_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.asr.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.asr.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasr_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.asr.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.asr.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasr_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.asr.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.asr.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasr_s8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.asr.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasr_s16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.asr.nxv8i16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasr_s32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.asr.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasr_s64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.asr.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasr_s8_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.asr.u.nxv16i8( %0, %1, %2) # | # | ... # `---data was truncated (10240/46416) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000564bcdca357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564bcdca0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564bcdca3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa7e5b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa7e5b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa7e5b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa7e5b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564bcdc3924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564bcdc39096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564bcdc1df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564bcd8cd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564bcd8cce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa7e5b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa7e5b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa7e5b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564bcd8ccd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c (187 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf4x5(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf2x5(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16m1x5(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16m1x5_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005583d623957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005583d6236515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005583d6239cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3caff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3caff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3caff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3caff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005583d61cf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005583d61cf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005583d61b3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005583d5e63176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005583d5e62e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3caff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3caff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3caff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005583d5e62d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c (188 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_i64m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_i64m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_u64m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_u64m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005579314ae57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005579314ab515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005579314aecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe6d441bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe6d44725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe6d441ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe6d4403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055793144424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557931444096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557931428f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005579310d8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005579310d7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe6d4404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe6d44050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe6d44050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005579310d7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c (189 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c (190 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3 # | ... # `---data was truncated (10240/64366) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055946359e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055946359b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055946359ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9b0ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9b0eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9b0ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9b0ea31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055946353424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559463534096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559463518f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005594631c8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005594631c7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9b0ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9b0ea330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9b0ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005594631c7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c (191 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti2_lane_zt_u8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv16i8(i32 0, %0, i32 3) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv16i8(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti2_lane_zt_s8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv16i8(i32 0, %0, i32 3) # | ret { , , , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti2_lane_zt_mf8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv16i8(i32 0, %0, i32 3) # | ret { , , , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti2_lane_zt_u16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8i16(i32 0, %0, i32 3) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8i16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti2_lane_zt_s16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8i16(i32 0, %0, i32 3) # | ret { , , , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti2_lane_zt_f16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8f16(i32 0, %0, i32 3) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8f16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti2_lane_zt_bf16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8bf16(i32 0, %0, i32 3) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8bf16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti2_lane_zt_u32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4i32(i32 0, %0, i32 3) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4i32(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti2_lane_zt_s32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4i32(i32 0, %0, i32 3) # | ret { , , , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti2_lane_zt_f32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4f32(i32 0, %0, i32 3) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4f32(i32 immarg, , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055e598fd057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e598fcd515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e598fd0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffae0933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffae098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffae0933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffae091b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e598f6624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e598f66096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e598f4af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e598bfa176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e598bf9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ffae091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffae091d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffae091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e598bf9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c (192 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv16f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv16f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv32f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv32f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32mf2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv1f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv1f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32m1( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv2f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv2f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32m2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv4f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv4f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32m4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv8f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv8f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c (193 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f64m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f64.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f64.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f64m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f64.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f64.p0.nxv2i64.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c (194 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -O0 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=O0 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -O0 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c -o - # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=O0 # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=AFTER_MEM2REG # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @foo() #0 { # | entry: # | %v_tuple = alloca target("riscv.vector.tuple", , 2), align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local target("riscv.vector.tuple", , 2) @bar() #0 { # | entry: # | %v_tuple = alloca target("riscv.vector.tuple", , 2), align 4 # | %0 = load target("riscv.vector.tuple", , 2), ptr %v_tuple, align 4 # | ret target("riscv.vector.tuple", , 2) %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @baz(target("riscv.vector.tuple", , 2) %v_tuple) #0 { # | entry: # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local target("riscv.vector.tuple", , 2) @qux(target("riscv.vector.tuple", , 2) %v_tuple) #0 { # | entry: # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | %0 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | ret target("riscv.vector.tuple", , 2) %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local target("riscv.vector.tuple", , 2) @quux(target("riscv.vector.tuple", , 2) %v_tuple) #0 { # | entry: # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | %0 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %call = call target("riscv.vector.tuple", , 2) @qux(target("riscv.vector.tuple", , 2) %0) # | ret target("riscv.vector.tuple", , 2) %call # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zicsr,+zve32x,+zvl32b" } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558a6869357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558a68690515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558a68693cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe960a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe960aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe960a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe960a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558a6862924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558a68629096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558a6860df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558a682bd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558a682bce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe960a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe960a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe960a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558a682bcd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=AFTER_MEM2REG # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=AFTER_MEM2REG # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c (195 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_i8mf8x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_i8mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_i8mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_i8m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_i8m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_u8mf8x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_u8mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_u8mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_u8m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, a # | ... # `---data was truncated (10240/26721) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056462eb1b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056462eb18515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056462eb1bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa59c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa59c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa59c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa59c11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056462eab124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056462eab1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056462ea95f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056462e745176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056462e744e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa59c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa59c11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa59c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056462e744d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c (196 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16mf4x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16mf2x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16m1x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16m1x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fb718d257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fb718cf515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fb718d2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2e68249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2e682a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2e68249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2e68231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fb7186824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fb71868096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fb7184cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fb714fc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fb714fbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2e68232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2e682330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2e682330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fb714fbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c (197 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +faminmax -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +faminmax -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svamax_f16_x2( %zdn.coerce0, %zdn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | %10 = call { , } @llvm.aarch64.sme.famax.x2.nxv8f16( %5, %6, %8, %9) # | ret { , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sme.famax.x2.nxv8f16(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svamax_f32_x2( %zdn.coerce0, %zdn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | %10 = call { , } @llvm.aarch64.sme.famax.x2.nxv4f32( %5, %6, %8, %9) # | ret { , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sme.famax.x2.nxv4f32(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svamax_f64_x2( %zdn.coerce0, %zdn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | %10 = call { , } @llvm.aarch64.sme.famax.x2.nxv2f64( %5, %6, %8, %9) # | ret { , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sme.famax.x2.nxv2f64(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svamin_f16_x2( %zdn.coerce0, %zdn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | %10 = call { , } @llvm.aarch64.sme.famin.x2.nxv8f16( %5, %6, %8, %9) # | ret { , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sme.famin.x2.nxv8f16(, , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c (198 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwi # | ... # `---data was truncated (10240/44369) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bac8efa57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bac8ef7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bac8efacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0e92933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0e9298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0e92933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0e9291b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bac8e9024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bac8e90096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bac8e74f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bac8b24176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bac8b23e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0e9291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0e9291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0e9291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bac8b23d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c (199 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2q.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2q.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2q.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2q.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2q.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2q.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2q.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_bf16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2q.nxv8bf16(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000564f9cfa457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564f9cfa1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564f9cfa4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3272133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f327218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3272133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f327211b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564f9cf3a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564f9cf3a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564f9cf1ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564f9cbce176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564f9cbcde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f327211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f327211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f327211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564f9cbcdd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c (200 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_bf16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fadd.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fadd.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_bf16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fadd.nxv8bf16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_bf16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fadd.u.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fadd.u.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_bf16_n_m( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fadd.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_bf16_n_z( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fadd.nxv8bf16( %3, %4, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_bf16_n_x( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fadd.u.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000559a0af6457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559a0af61515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559a0af64cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efd9b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efd9b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efd9b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efd9b91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559a0aefa24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559a0aefa096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559a0aedef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559a0ab8e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559a0ab8de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efd9b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efd9b91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efd9b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559a0ab8dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/arm-mve-intrinsics/vsubq.c (201 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vsubq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c --check-prefixes=CHECK,CHECK-NONSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsubq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = sub <4 x i32> %0, %1 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vsubq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = fsub <8 x half> %0, %1 # | ret <8 x half> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vsubq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.sub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.sub.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vsubq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x float>, ptr %inactive.addr, align 8 # | %6 = call <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4, <4 x float> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vsubq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.sub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.sub.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vsubq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x half> @llvm.arm.mve.sub.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4, <8 x half> undef) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.sub.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsubq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = sub <4 x i32> %0, %.splat # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vsubq_n_f16(<8 x half> noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca half, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store half %b, ptr %b.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load half, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x half> poison, half %1, i64 0 # | %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer # | %2 = fsub <8 x half> %0, %.splat # | ret <8 x half> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vsubq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.sub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vsubq_m_n_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, float noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca float, align 4 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store float %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load float, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x float> poison, float %1, i64 0 # | %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x float>, ptr %inactive.addr, align 8 # | %6 = call <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %.splat, <4 x i1> %4, <4 x float> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vsubq_x_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.sub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @t # | ... # `---data was truncated (10240/11617) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x0000562829e1757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562829e14515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562829e17cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1b14049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1b140a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1b14049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1b14031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562829dad24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562829dad096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562829d91f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562829a41176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562829a40e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1b14032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1b140330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1b140330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562829a40d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c --check-prefixes=CHECK,CHECK-NONSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c --check-prefixes=CHECK,CHECK-NONSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c (202 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8mf8x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8mf4x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_u8mf8x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_u8mf4x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_u8mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_u8m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8mf8x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8mf4x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, pt # | ... # `---data was truncated (10240/18980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c035a8b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c035a88515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c035a8bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faa91133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faa9118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faa91133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faa9111b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c035a2124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c035a21096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c035a05f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c0356b5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c0356b4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007faa9111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faa9111d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faa9111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c0356b4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c (203 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_i8mf4x7(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fbafef557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fbafef2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fbafef5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6df0b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6df0b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6df0b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6df0b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fbafe8b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fbafe8b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fbafe6ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fbafb1f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fbafb1ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6df0b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6df0b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6df0b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fbafb1ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon/intrinsics-constrained.c (204 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon/intrinsics-constrained.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=maytrap -DEXCEPT=1 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c --check-prefix=LLVM --implicit-check-not=fpexcept.maytrap --implicit-check-not=' @llvm.sqrt.' # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=maytrap -DEXCEPT=1 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <4 x half> @test_vsqrt_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %vsqrt.i = call <4 x half> @llvm.experimental.constrained.sqrt.v4f16(<4 x half> %2, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store <4 x half> %vsqrt.i, ptr %ref.tmp.i, align 8 # | %3 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %3, ptr %__ret.i, align 8 # | %4 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %4 # | } # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <8 x half> @test_vsqrtq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %vsqrt.i = call <8 x half> @llvm.experimental.constrained.sqrt.v8f16(<8 x half> %2, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store <8 x half> %vsqrt.i, ptr %ref.tmp.i, align 16 # | %3 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %3, ptr %__ret.i, align 16 # | %4 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %4 # | } # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <2 x double> @test_vsqrtq_f64(<2 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <2 x double> # | %vsqrt.i = call <2 x double> @llvm.experimental.constrained.sqrt.v2f64(<2 x double> %2, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store <2 x double> %vsqrt.i, ptr %ref.tmp.i, align 16 # | %3 = load <2 x double>, ptr %ref.tmp.i, align 16 # | store <2 x double> %3, ptr %__ret.i, align 16 # | %4 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare <4 x half> @llvm.experimental.constrained.sqrt.v4f16(<4 x half>, metadata, metadata) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare <8 x half> @llvm.experimental.constrained.sqrt.v8f16(<8 x half>, metadata, metadata) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare <2 x double> @llvm.experimental.constrained.sqrt.v2f64(<2 x double>, metadata, metadata) #1 # | # | attributes #0 = { noinline nounwind strictfp "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon" } # | attributes #1 = { nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) } # | attributes #2 = { strictfp } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000558fd19bc57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558fd19b9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558fd19bccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2290d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2290d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2290d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2290d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558fd195224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558fd1952096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558fd1936f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558fd15e6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558fd15e5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2290d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2290d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2290d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558fd15e5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c --check-prefix=LLVM --implicit-check-not=fpexcept.maytrap '--implicit-check-not= @llvm.sqrt.' # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c --check-prefix=LLVM --implicit-check-not=fpexcept.maytrap --implicit-check-not= @llvm.sqrt. # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c (205 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_u8_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_s8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_u8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_f16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_bf16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_f32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_f64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_u16_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s32_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_u32_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s64_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_u64_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_f16_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_bf16_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_f32_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_f64_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 t # | ... # `---data was truncated (10240/168193) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg # | #0 0x000055d4ba5d057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d4ba5cd515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d4ba5d0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f75c3133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f75c318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f75c3133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f75c311b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d4ba56624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d4ba566096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d4ba54af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d4ba1fa176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d4ba1f9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f75c311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f75c311d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f75c311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d4ba1f9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c (206 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_multi_za32_vg1x2_u16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.udot.za32.vg1x2.nxv8i16(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.udot.za32.vg1x2.nxv8i16(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_multi_za32_vg1x4_u16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm.coerce0, %zm.coerce1, %zm.coerce2, %zm.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zm = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | %4 = insertvalue { , , , } poison, %zm.coerce0, 0 # | %5 = insertvalue { , , , } %4, %zm.coerce1, 1 # | %6 = insertvalue { , , , } %5, %zm.coerce2, 2 # | %7 = insertvalue { , , , } %6, %zm.coerce3, 3 # | store { , , , } %7, ptr %zm, align 16 # | %zm2 = load { , , , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store { , , , } %zm2, ptr %zm.addr, align 16 # | %8 = load i32, ptr %slice_base.addr, align 4 # | %9 = load { , , , }, ptr %zn.addr, align 16 # | %10 = extractvalue { , , , } %9, 0 # | %11 = extractvalue { , , , } %9, 1 # | %12 = extractvalue { , , , } %9, 2 # | %13 = extractvalue { , , , } %9, 3 # | %14 = load { , , , }, ptr %zm.addr, align 16 # | %15 = extractvalue { , , , } %14, 0 # | %16 = extractvalue { , , , } %14, 1 # | %17 = extractvalue { , , , } %14, 2 # | %18 = extractvalue { , , , } %14, 3 # | call void @llvm.aarch64.sme.udot.za32.vg1x4.nxv8i16(i32 %8, %10, %11, %12, %13, %15, %16, %17, %18) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.udot.za32.vg1x4.nxv8i16(i32, , , , , , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_multi_za32_vg1x2_u8(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.udot.za32.vg1x2.nxv16i8(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.udot.za32.vg1x2.nxv16i8(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_multi_za32_vg1x4_u8(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm.coerce0, %zm.coerce1, %zm.coerce2, %zm.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align # | ... # `---data was truncated (10240/127452) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055d55b7d057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d55b7cd515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d55b7d0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd596849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd5968a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd596849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd596831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d55b76624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d55b766096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d55b74af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d55b3fa176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d55b3f9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd596832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd5968330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd5968330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d55b3f9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c (207 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrb_u32base_s32offset( %bases, %offsets) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %offsets.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %offsets.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrb.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.adrb.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrb_u64base_s64offset( %bases, %offsets) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %offsets.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %offsets.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrb.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.adrb.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrb_u32base_u32offset( %bases, %offsets) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %offsets.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %offsets.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrb.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrb_u64base_u64offset( %bases, %offsets) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %offsets.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %offsets.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrb.nxv2i64( %0, %1) # | ret %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056503883557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000565038832515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000565038835cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5674d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5674d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5674d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5674d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005650387cb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005650387cb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005650387aff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056503845f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056503845ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5674d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5674d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5674d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056503845ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm.c (208 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_n_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shl <16 x i8> %0, splat (i8 5) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_n_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shl <8 x i16> %0, splat (i16 5) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_n_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = shl <4 x i32> %0, splat (i32 18) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_n_s8_trivial(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shl <16 x i8> %0, zeroinitializer # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_n_s16_trivial(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shl <8 x i16> %0, zeroinitializer # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_n_s32_trivial(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = shl <4 x i32> %0, zeroinitializer # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_n_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shl <16 x i8> %0, splat (i8 3) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_n_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shl <8 x i16> %0, splat (i16 11) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_n_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = shl <4 x i32> %0, splat (i32 7) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_n_u8_trivial(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shl <16 x i8> %0, zeroinitializer # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_n_u16_trivial(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shl <8 x i16> %0, zeroinitializer # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_n_u32_trivial(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = shl <4 x i32> %0, zeroinitializer # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrq_n_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = ashr <16 x i8> %0, splat (i8 4) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrq_n_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = ashr <8 x i16> %0, splat (i16 10) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshrq_n_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = ashr <4 x i32> %0, splat (i32 19) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrq_n_s8_trivial(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = ashr <16 x i8> %0, splat (i8 7) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrq_n_s16_trivial(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = ashr <8 x i16> %0, splat (i16 15) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshrq_n_s32_trivial(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = ashr <4 x i32> %0, splat (i32 31) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrq_n_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = lshr <16 x i8> %0, splat (i8 1) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrq_n_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = lshr <8 x i16> %0, splat (i16 10) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshrq_n_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = lshr <4 x i32> %0, splat (i32 10) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrq_n_u8_trivial(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | ret <16 x i8> zeroinitializer # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrq_n_u16_trivial(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | ret <8 x i16> zeroinitializer # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshrq_n_u32_trivial(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | ret <4 x i32> zeroinitializer # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = load <16 x i8>, ptr %inactive.addr, align 8 # | %5 = call <16 x i8> @llvm.arm.mve.shl.imm.predicated.v16i8.v16i1(<16 x i8> %0, i32 6, <16 x i1> %3, <16 x i8> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.shl.imm.predicated.v16i8.v16i1(<16 x i8>, i32, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_m_n_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.shl.imm.predicated.v8i16.v8i1(<8 x i16> %0, i32 13, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.shl.imm.predicated.v8i16.v8i1(<8 x i16>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinlin # | ... # `---data was truncated (10240/66359) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056270f3e057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056270f3dd515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056270f3e0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fabd321bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fabd32725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fabd321ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fabd3203507 abort ./stdlib/abort.c:85:3 # | #7 0x000056270f37624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056270f376096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056270f35af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056270f00a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056270f009e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fabd3204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fabd32050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fabd32050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056270f009d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c (209 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf8_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf4_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf2_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8m1_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/addv.c (210 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve/addv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svaddv_s8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i64 @llvm.aarch64.sve.saddv.nxv16i8( %0, %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.saddv.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svaddv_s16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i64 @llvm.aarch64.sve.saddv.nxv8i16( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.saddv.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svaddv_s32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i64 @llvm.aarch64.sve.saddv.nxv4i32( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.saddv.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svaddv_s64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.saddv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.saddv.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svaddv_u8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i64 @llvm.aarch64.sve.uaddv.nxv16i8( %0, %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uaddv.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svaddv_u16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i64 @llvm.aarch64.sve.uaddv.nxv8i16( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uaddv.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svaddv_u32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i64 @llvm.aarch64.sve.uaddv.nxv4i32( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uaddv.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svaddv_u64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.uaddv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uaddv.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local half @test_svaddv_f16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call half @llvm.aarch64.sve.faddv.nxv8f16( %2, %1) # | ret half %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.aarch64.sve.faddv.nxv8f16(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local float @test_svaddv_f32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call float @llvm.aarch64.sve.faddv.nxv4f32( %2, %1) # | ret float %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.aarch64.sve.faddv.nxv4f32(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local double @test_svaddv_f64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call double @llvm.aarch64.sve.faddv.nxv2f64( %2, %1) # | ret double %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.aarch64.sve.faddv.nxv2f64(, ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | a # | ... # `---data was truncated (10240/10826) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S # | #0 0x00005654d025757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005654d0254515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005654d0257cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa3a5449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa3a54a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa3a5449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa3a5431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005654d01ed24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005654d01ed096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005654d01d1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005654cfe81176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005654cfe80e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa3a5432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa3a54330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa3a54330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005654cfe80d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c (211 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, # | ... # `---data was truncated (10240/223801) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056363f1a757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056363f1a4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056363f1a7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9739f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9739f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9739f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9739f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056363f13d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056363f13d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056363f121f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056363edd1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056363edd0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9739f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9739f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9739f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056363edd0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c (212 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 31) # | ret i64 %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.cntd(i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_1() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_2() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_3() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 3) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_4() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 4) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_5() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 5) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_6() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 6) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_7() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_8() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 8) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_9() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 9) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_10() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 10) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_11() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 11) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_12() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 12) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_13() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 13) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_14() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 29) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_15() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 30) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_16() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 31) # | ret i64 %0 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x000055ab8976b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ab89768515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ab8976bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb11d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb11d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb11d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb11d51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ab8970124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ab89701096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ab896e5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ab89395176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ab89394e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb11d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb11d51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb11d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ab89394d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c (213 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmov_b_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.and.z.nxv16i1( %0, %1, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.and.z.nxv16i1(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000555f680a157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555f6809e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555f680a1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f711eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f711eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f711eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f711eb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555f6803724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555f68037096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555f6801bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555f67ccb176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555f67ccae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f711eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f711eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f711eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555f67ccad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c (214 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1h_s32( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv4i16.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv4i16.p0(, , ptr captures(none)) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1h_s64( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv2i16.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv2i16.p0(, , ptr captures(none)) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1h_u32( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv4i16.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1h_u64( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv2i16.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1h_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = getelementptr , ptr %1, i64 %2 # | %6 = trunc %3 to # | call void @llvm.aarch64.sve.st1.nxv4i16.p0( %6, %4, ptr %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1h_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = getelementptr , ptr %1, i64 %2 # | %6 = trunc %3 to # | call void @llvm.aarch64.sve.st1.nxv2i16.p0( %6, %4, ptr %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1h_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = getelementptr , ptr %1, i64 %2 # | %6 = trunc %3 to # | call void @llvm.aarch64.sve.st1.nxv4i16.p0( %6, %4, ptr %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1h_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = getelementptr , ptr %1, i64 %2 # | %6 = trunc %3 to # | call void @llvm.aarch64.sve.st1.nxv2i16.p0( %6, %4, ptr %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1h_scatter_u32base_s32( %pg, %bases, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = trunc %2 to # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv4i16.nxv4i32( %3, %4, %1, i64 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv4i16.nxv4i32(, , , i64) # # | ... # `---data was truncated (10240/43213) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x000055e6d89b457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e6d89b1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e6d89b4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff24c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff24c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff24c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff24c91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e6d894a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e6d894a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e6d892ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e6d85de176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e6d85dde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff24c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff24c91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff24c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e6d85ddd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c (215 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti4_lane_zt_u8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 0, %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti4_lane_zt_s8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 0, %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti4_lane_zt_mf8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 0, %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti4_lane_zt_u16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti4.lane.zt.nxv8i16(i32 0, %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti4.lane.zt.nxv8i16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti4_lane_zt_s16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti4.lane.zt.nxv8i16(i32 0, %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti4_lane_zt_f16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti4.lane.zt.nxv8f16(i32 0, %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti4.lane.zt.nxv8f16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti4_lane_zt_bf16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti4.lane.zt.nxv8bf16(i32 0, %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti4.lane.zt.nxv8bf16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti4_lane_zt_u32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti4.lane.zt.nxv4i32(i32 0, %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti4.lane.zt.nxv4i32(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti4_lane_zt_s32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti4.lane.zt.nxv4i32(i32 0, %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti4_lane_zt_f32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti4.lane.zt.nxv4f32(i32 0, %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti4.lane.zt.nxv4f32(i32 immarg, , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055f9ef9a457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f9ef9a1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f9ef9a4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6ef1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6ef178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6ef1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6ef171b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f9ef93a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f9ef93a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f9ef91ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f9ef5ce176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f9ef5cde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6ef171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6ef171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6ef171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f9ef5cdd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/andv.c (216 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve/andv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svandv_s8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.andv.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i8 @llvm.aarch64.sve.andv.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svandv_s16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.andv.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.aarch64.sve.andv.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svandv_s32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.andv.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.andv.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svandv_s64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.andv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.andv.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svandv_u8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.andv.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svandv_u16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.andv.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svandv_u32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.andv.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svandv_u64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.andv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S # | #0 0x000055629b4c857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055629b4c5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055629b4c8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1973f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1973f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1973f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1973f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055629b45e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055629b45e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055629b442f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055629b0f2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055629b0f1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1973f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1973f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1973f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055629b0f1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon/add.c (217 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon/add.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c --check-prefix=LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vadd_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %add.i = add <8 x i8> %2, %3 # | store <8 x i8> %add.i, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vadd_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %add.i = add <4 x i16> %2, %3 # | store <4 x i16> %add.i, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vadd_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <2 x i32> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | %1 = load <2 x i32>, ptr %b.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %add.i = add <2 x i32> %2, %3 # | store <2 x i32> %add.i, ptr %__ret.i, align 8 # | %4 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vadd_s64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | %1 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <1 x i64>, ptr %__p0.addr.i, align 8 # | %3 = load <1 x i64>, ptr %__p1.addr.i, align 8 # | %add.i = add <1 x i64> %2, %3 # | store <1 x i64> %add.i, ptr %__ret.i, align 8 # | %4 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vadd_f32(<2 x float> noundef %a, <2 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x float>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x float>, ptr %__p1.addr.i, align 8 # | %add.i = fadd <2 x float> %2, %3 # | store <2 x float> %add.i, ptr %__ret.i, align 8 # | %4 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vadd_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %add.i = add <8 x i8> %2, %3 # | store <8 x i8> %add.i, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vadd_u16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %add.i = add <4 x i16> %2, %3 # | store <4 x i16> %add.i, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vadd_u32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <2 x i32> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | %1 = load <2 x i32>, ptr %b.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %add.i = add <2 x i32> %2, %3 # | store <2 x i32> %add.i, ptr %__ret.i, align 8 # | %4 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vadd_u64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | %1 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <1 x i64>, ptr %__p0.addr.i, align 8 # | %3 = load <1 x i64>, ptr %__p1.addr.i, align 8 # | %add.i = add <1 x i64> %2, %3 # | store <1 x i64> %add.i, ptr %__ret.i, align 8 # | %4 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vaddq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | %1 = load <16 x i8>, ptr %b.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %add.i = add <16 x i8> %2, %3 # | store <16 x i8> %add.i, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vaddq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | store <8 x i16> %b, ptr %b.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | %1 = load <8 x i16>, ptr %b.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | store <8 x i16> %1, ptr %__p1.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %3 = load <8 x i16>, ptr %__p1.addr.i, align 16 # | %add.i = add <8 x i16> %2, %3 # | store <8 x i16> %add.i, ptr %__ret.i, align 16 # | %4 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vaddq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | %b.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | store <4 x i32> %b, ptr %b.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | %1 = load <4 x i32>, ptr %b # | ... # `---data was truncated (10240/221881) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine # | #0 0x0000558aaef9857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558aaef95515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558aaef98cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffaa6133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffaa618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffaa6133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffaa611b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558aaef2e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558aaef2e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558aaef12f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558aaebc2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558aaebc1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ffaa611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffaa611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffaa611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558aaebc1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c --check-prefix=LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c --check-prefix=LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c (218 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_svzero_zt() #0 { # | entry: # | call void @llvm.aarch64.sme.zero.zt(i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write) # | declare void @llvm.aarch64.sme.zero.zt(i32 immarg) #1 # | # | attributes #0 = { noinline nounwind "aarch64_out_zt0" "aarch64_pstate_sm_compatible" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: write) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005632a314457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005632a3141515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005632a3144cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f20e1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f20e1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f20e1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f20e1d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005632a30da24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005632a30da096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005632a30bef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005632a2d6e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005632a2d6de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f20e1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f20e1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f20e1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005632a2d6dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c (219 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_s8( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv16i8( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dupq.lane.nxv16i8(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_s16( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv8i16( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dupq.lane.nxv8i16(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_s32( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv4i32( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dupq.lane.nxv4i32(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_s64( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv2i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dupq.lane.nxv2i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_u8( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv16i8( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_u16( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv8i16( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_u32( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv4i32( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_u64( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv2i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_f16( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv8f16( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dupq.lane.nxv8f16(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_f32( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv4f32( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dupq.lane.nxv4f32(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_f64( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv2f64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dupq.lane.nxv2f64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_n_s8(i8 noundef %x0, i8 noundef %x1, i8 noundef %x2, i8 noundef %x3, i8 noundef %x4, i8 noundef %x5, i8 noundef %x6, i8 noundef %x7, i8 noundef %x8, i8 noundef %x9, i8 noundef %x10, i8 noundef %x11, i8 noundef %x12, i8 noundef %x13, i8 noundef %x14, i8 noundef %x15) #0 { # | entry: # | %x0.addr = alloca i8, align 1 # | %x1.addr = alloca i8, align 1 # | %x2.addr = alloca i8, align 1 # | %x3.addr = alloca i8, align 1 # | %x4.addr = alloca i8, align 1 # | %x5.addr = alloca i8, align 1 # | %x6.addr = alloca i8, align 1 # | %x7.addr = alloca i8, align 1 # | %x8.addr = alloca i8, align 1 # | %x9.addr = alloca i8, align 1 # | %x10.addr = alloca i8, align 1 # | %x11.addr = alloca i8, align 1 # | %x12.addr = alloca i8, align 1 # | %x13.addr = alloca i8, align 1 # | %x14.addr = alloca i8, align 1 # | %x15.addr = alloca i8, align 1 # | store i8 %x0, ptr %x0.addr, align 1 # | store i8 %x1, ptr %x1.addr, align 1 # | store i8 %x2, ptr %x2.addr, align 1 # | store i8 %x3, ptr %x3.addr, align 1 # | store i8 %x4, ptr %x4.addr, align 1 # | store i8 %x5, ptr %x5.addr, align 1 # | store i8 %x6, ptr %x6.addr, align 1 # | store i8 %x7, ptr %x7.addr, align 1 # | store i8 %x8, ptr %x8.addr, align 1 # | store i8 %x9, ptr %x9.addr, align 1 # | store i8 %x10, ptr %x10.addr, align 1 # | store i8 %x11, ptr %x11.addr, align 1 # | store i8 %x12, ptr %x12.addr, align 1 # | store i8 %x13, ptr %x13.addr, align 1 # | store i8 %x14, ptr %x14.addr, align 1 # | store i8 %x15, ptr %x15.addr, align 1 # | %0 = load i8, ptr %x0.addr, align 1 # | %1 = load i8, ptr %x1.addr, align 1 # | %2 = load i8, ptr %x2.addr, align 1 # | %3 = load i8, ptr %x3.addr, align 1 # | %4 = load i8, ptr %x4.addr, align 1 # | %5 = load i8, ptr %x5.addr, align 1 # | %6 = load i8, ptr %x6.addr, align 1 # | %7 = load i8, ptr %x7.addr, align 1 # | %8 = load i8, ptr %x8.addr, align 1 # | %9 = load i8, ptr %x9.addr, align 1 # | %10 = load i8, ptr %x10.addr, align 1 # | %11 = load i8, ptr %x11.addr, align 1 # | %12 = load i8, ptr %x12.addr, align 1 # | %13 = load i8, ptr # | ... # `---data was truncated (10240/42600) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056472f28057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056472f27d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056472f280cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f78dca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f78dcaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f78dca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f78dca31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056472f21624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056472f216096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056472f1faf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056472eeaa176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056472eea9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f78dca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f78dca330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f78dca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056472eea9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c (220 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_i32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_i32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_u32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_u32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32mf2x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c (221 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpne_s8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmpne.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpne.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpne_s16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmpne.nxv8i16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpne.nxv8i16(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpne_s32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmpne.nxv4i32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpne.nxv4i32(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpne_s64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.cmpne.nxv2i64( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpne.nxv2i64(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpne_u8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmpne.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpne_u16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmpne.nxv8i16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpne_u32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmpne.nxv4i32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpne_u64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.cmpne.nxv2i64( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_r # | ... # `---data was truncated (10240/34127) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000556e7675557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556e76752515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556e76755cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fef68249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fef682a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fef68249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fef68231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556e766eb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556e766eb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556e766cff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556e7637f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556e7637ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fef68232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fef682330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fef682330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556e7637ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c (222 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecp_n_s32_b8(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv16i1(i32 %0, %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqdecp.n32.nxv16i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecp_n_s32_b16(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %3 = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv8i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqdecp.n32.nxv8i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecp_n_s32_b32(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %3 = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv4i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqdecp.n32.nxv4i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecp_n_s32_b64(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %3 = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv2i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqdecp.n32.nxv2i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecp_n_s64_b8(i64 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | %pg.addr = alloca , align 2 # | store i64 %op, ptr %op.addr, align 8 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call i64 @llvm.aarch64.sve.sqdecp.n64.nxv16i1(i64 %0, %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqdecp.n64.nxv16i1(i64, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecp_n_s64_b16(i64 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | %pg.addr = alloca , align 2 # | store i64 %op, ptr %op.addr, align 8 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %3 = call i64 @llvm.aarch64.sve.sqdecp.n64.nxv8i1(i64 %0, %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqdecp.n64.nxv8i1(i64, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecp_n_s64_b32(i64 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | %pg.addr = alloca , align 2 # | store i64 %op, ptr %op.addr, align 8 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %3 = call i64 @llvm.aarch64.sve.sqdecp.n64.nxv4i1(i64 %0, %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqdecp.n64.nxv4i1(i64, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecp_n_s64_b64(i64 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | %pg.addr = alloca , align 2 # | store i64 %op, ptr %op.addr, align 8 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %3 = call i64 @llvm.aarch64.sve.sqdecp.n64.nxv2i1(i64 %0, %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqdecp.n64.nxv2i1(i64, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecp_n_u32_b8(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv16i1(i32 %0, %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv16i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecp_n_u32_b16(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %3 = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv8i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv8i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecp_n_u32_b32(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %3 = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv4i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv4i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecp_n_u32_b64(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %3 = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv2i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv2i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecp_n_u64_b8(i64 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | %pg.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c (223 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve-b16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve-b16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bf16( %acc, %a, %b) #0 { # | entry: # | %acc.addr = alloca , align 16 # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %acc, ptr %acc.addr, align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %acc.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %2 = load , ptr %b.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmmla.nxv8bf16.nxv8bf16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmmla.nxv8bf16.nxv8bf16(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16mm" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000558a022b757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558a022b4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558a022b7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8ecff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8ecff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8ecff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8ecff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558a0224d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558a0224d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558a02231f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558a01ee1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558a01ee0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8ecff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8ecff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8ecff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558a01ee0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon-intrinsics.c (224 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vmul_s8(<8 x i8> noundef %v1, <8 x i8> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %v1.addr = alloca <8 x i8>, align 8 # | %v2.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %v1, ptr %v1.addr, align 8 # | store <8 x i8> %v2, ptr %v2.addr, align 8 # | %0 = load <8 x i8>, ptr %v1.addr, align 8 # | %1 = load <8 x i8>, ptr %v2.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %mul.i = mul <8 x i8> %2, %3 # | store <8 x i8> %mul.i, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vmul_s16(<4 x i16> noundef %v1, <4 x i16> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %v1.addr = alloca <4 x i16>, align 8 # | %v2.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %v1, ptr %v1.addr, align 8 # | store <4 x i16> %v2, ptr %v2.addr, align 8 # | %0 = load <4 x i16>, ptr %v1.addr, align 8 # | %1 = load <4 x i16>, ptr %v2.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %mul.i = mul <4 x i16> %2, %3 # | store <4 x i16> %mul.i, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vmul_s32(<2 x i32> noundef %v1, <2 x i32> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %v1.addr = alloca <2 x i32>, align 8 # | %v2.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %v1, ptr %v1.addr, align 8 # | store <2 x i32> %v2, ptr %v2.addr, align 8 # | %0 = load <2 x i32>, ptr %v1.addr, align 8 # | %1 = load <2 x i32>, ptr %v2.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %mul.i = mul <2 x i32> %2, %3 # | store <2 x i32> %mul.i, ptr %__ret.i, align 8 # | %4 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vmul_f32(<2 x float> noundef %v1, <2 x float> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %v1.addr = alloca <2 x float>, align 8 # | %v2.addr = alloca <2 x float>, align 8 # | store <2 x float> %v1, ptr %v1.addr, align 8 # | store <2 x float> %v2, ptr %v2.addr, align 8 # | %0 = load <2 x float>, ptr %v1.addr, align 8 # | %1 = load <2 x float>, ptr %v2.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x float>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x float>, ptr %__p1.addr.i, align 8 # | %mul.i = fmul <2 x float> %2, %3 # | store <2 x float> %mul.i, ptr %__ret.i, align 8 # | %4 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vmul_u8(<8 x i8> noundef %v1, <8 x i8> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %v1.addr = alloca <8 x i8>, align 8 # | %v2.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %v1, ptr %v1.addr, align 8 # | store <8 x i8> %v2, ptr %v2.addr, align 8 # | %0 = load <8 x i8>, ptr %v1.addr, align 8 # | %1 = load <8 x i8>, ptr %v2.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %mul.i = mul <8 x i8> %2, %3 # | store <8 x i8> %mul.i, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vmul_u16(<4 x i16> noundef %v1, <4 x i16> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %v1.addr = alloca <4 x i16>, align 8 # | %v2.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %v1, ptr %v1.addr, align 8 # | store <4 x i16> %v2, ptr %v2.addr, align 8 # | %0 = load <4 x i16>, ptr %v1.addr, align 8 # | %1 = load <4 x i16>, ptr %v2.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %mul.i = mul <4 x i16> %2, %3 # | store <4 x i16> %mul.i, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vmul_u32(<2 x i32> noundef %v1, <2 x i32> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %v1.addr = alloca <2 x i32>, align 8 # | %v2.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %v1, ptr %v1.addr, align 8 # | store <2 x i32> %v2, ptr %v2.addr, align 8 # | %0 = load <2 x i32>, ptr %v1.addr, align 8 # | %1 = load <2 x i32>, ptr %v2.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %mul.i = mul <2 x i32> %2, %3 # | store <2 x i32> %mul.i, ptr %__ret.i, align 8 # | %4 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vmulq_s8(<16 x i8> noundef %v1, <16 x i8> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %v1.addr = alloca <16 x i8>, align 16 # | %v2.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v1, ptr %v1.addr, align 16 # | store <16 x i8> %v2, ptr %v2.addr, align 16 # | %0 = load <16 x i8>, ptr %v1.addr, align 16 # | %1 = load <16 x i8>, ptr %v2.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %mul.i = mul <16 x i8> %2, %3 # | store <16 x i8> %mul.i, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vmulq_s16(<8 x i16> noundef %v1, <8 x i16> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %v1.addr = alloca <8 x i16>, align 16 # | %v2.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %v1, ptr %v1.addr, align 16 # | store <8 x i16> %v2, ptr %v2.addr, align 16 # | %0 = load <8 x i16>, ptr %v1.addr, align 16 # | %1 = load <8 x i16>, ptr %v2.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | store <8 x i16> %1, ptr %__p1.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %3 = load <8 x i16>, ptr %__p1.addr.i, align 16 # | %mul.i = mul <8 x i16> %2, %3 # | store <8 x i16> %mul.i, ptr %__ret.i, align 16 # | %4 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vmulq_s32(<4 x i32> noundef %v1, <4 x i32> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %v1.addr = alloca <4 x i32>, align 16 # | %v2.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %v1, ptr %v1.addr, align 16 # | store <4 x i32> %v2, ptr %v2.addr, align 16 # | %0 = load <4 x i32>, ptr %v1.addr, align 16 # | %1 = load <4 x i32>, ptr %v2.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | store <4 x i32> %1, ptr %__p1.addr.i, align 16 # | %2 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %3 = load <4 x i32>, ptr %__p1.addr.i, align 16 # | %mul.i = mul <4 x i32> %2, %3 # | store <4 x i32> %mul.i, ptr %__ret.i, align 16 # | %4 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vmulq_u8(<16 x i8> noundef %v1, <16 x i8> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %v1.addr = alloca <16 x i8>, align 16 # | %v2.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v1, ptr %v1.addr, align 16 # | store <16 x i8> %v2, ptr %v2.addr, align 16 # | %0 = load <16 x i8>, ptr %v1.addr, align 16 # | %1 = load <16 x i8>, ptr %v2.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %mul.i = mul <16 x i8> %2, %3 # | store <16 x i8> %mul.i, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vmulq_u16(<8 x i16> noundef %v1, <8 x i16> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %v1.addr = alloca <8 x i16>, align 16 # | %v2.addr = alloca <8 x i16>, align 16 # | s # | ... # `---data was truncated (10240/798827) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055e914f7a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e914f77515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e914f7acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9475f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9475f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9475f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9475f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e914f1024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e914f10096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e914ef4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e914ba4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e914ba3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9475f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9475f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9475f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e914ba3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c (225 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_i32mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_i32m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_u32mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_u32m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005648e0c4f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005648e0c4c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005648e0c4fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0d47249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0d472a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0d47249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0d47231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005648e0be524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005648e0be5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005648e0bc9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005648e0879176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005648e0878e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0d47232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0d472330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0d472330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005648e0878d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c (226 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmaxnm_single_bf16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fmaxnm.single.x2.nxv8bf16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fmaxnm.single.x2.nxv8bf16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmaxnm_single_f16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fmaxnm.single.x2.nxv8f16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fmaxnm.single.x2.nxv8f16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmaxnm_single_f32_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fmaxnm.single.x2.nxv4f32( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fmaxnm.single.x2.nxv4f32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmaxnm_single_f64_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fmaxnm.single.x2.nxv2f64( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fmaxnm.single.x2.nxv2f64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svmaxnm_single_bf16_x4( %zdn.coerce0, %zdn.coerce1, %zdn.coerce2, %zdn.coerce3, %zm) #0 { # | entry: # | %zdn = alloca { , , , }, align 16 # | %zdn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zdn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zdn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zdn.coerce3, 3 # | store { , , , } %3, ptr %zdn, align 16 # | %zdn1 = load { , , , }, ptr %zdn, align 16 # | store { , , , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %4 = load { , , , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = load , ptr %zm.addr, align 16 # | %10 = call { , , , } @llvm.aarch64.sve.fmaxnm.single.x4.nxv8bf16( %5, %6, %7, %8, %9) # | ret { , , , } %10 # | } # | # | ; Funct # | ... # `---data was truncated (10240/50311) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055fef2ad757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fef2ad4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fef2ad7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff8f3133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff8f318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff8f3133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff8f311b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fef2a6d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fef2a6d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fef2a51f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fef2701176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fef2700e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff8f311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff8f311d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff8f311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fef2700d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c (227 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m4_tu( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c (228 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_f16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_f16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_f16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_i16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_i16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_i16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_u16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_u16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_u16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", # | ... # `---data was truncated (10240/23365) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005575123df57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005575123dc515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005575123dfcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbc5561bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbc556725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbc5561ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbc55603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055751237524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557512375096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557512359f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557512009176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557512008e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbc55604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbc556050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbc556050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557512008d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c (229 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Funct # | ... # `---data was truncated (10240/64950) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dc592d357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055dc592d0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055dc592d3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffa10133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffa1018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffa10133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffa1011b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dc5926924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055dc59269096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055dc5924df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055dc58efd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055dc58efce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ffa1011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffa1011d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffa1011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dc58efcd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-vls-bitwise-ops.c (230 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-bitwise-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_bool( noundef %0, noundef %1) #0 { # | entry: # | %retval = alloca <8 x i8>, align 2 # | %a.addr = alloca <8 x i8>, align 2 # | %b.addr = alloca <8 x i8>, align 2 # | %a.coerce = bitcast %0 to # | %a = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8( %a.coerce, i64 0) # | %b.coerce = bitcast %1 to # | %b = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8( %b.coerce, i64 0) # | store <8 x i8> %a, ptr %a.addr, align 2 # | store <8 x i8> %b, ptr %b.addr, align 2 # | %2 = load <8 x i8>, ptr %a.addr, align 2 # | %3 = load <8 x i8>, ptr %b.addr, align 2 # | %and = and <8 x i8> %2, %3 # | store <8 x i8> %and, ptr %retval, align 2 # | %4 = load <8 x i8>, ptr %retval, align 2 # | %cast.scalable = call @llvm.vector.insert.nxv2i8.v8i8( poison, <8 x i8> %4, i64 0) # | %5 = bitcast %cast.scalable to # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2i8.v8i8(, <8 x i8>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <64 x i8>, align 16 # | %a.addr = alloca <64 x i8>, align 16 # | %b.addr = alloca <64 x i8>, align 16 # | %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %a.coerce, i64 0) # | %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %b.coerce, i64 0) # | store <64 x i8> %a, ptr %a.addr, align 16 # | store <64 x i8> %b, ptr %b.addr, align 16 # | %0 = load <64 x i8>, ptr %a.addr, align 16 # | %1 = load <64 x i8>, ptr %b.addr, align 16 # | %and = and <64 x i8> %0, %1 # | store <64 x i8> %and, ptr %retval, align 16 # | %2 = load <64 x i8>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv16i8.v64i8( poison, <64 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16i8.v64i8(, <64 x i8>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_i16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i16>, align 16 # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca <32 x i16>, align 16 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %b.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store <32 x i16> %b, ptr %b.addr, align 16 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load <32 x i16>, ptr %b.addr, align 16 # | %and = and <32 x i16> %0, %1 # | store <32 x i16> %and, ptr %retval, align 16 # | %2 = load <32 x i16>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv8i16.v32i16( poison, <32 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8i16.v32i16(, <32 x i16>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_i32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i32>, align 16 # | %a.addr = alloca <16 x i32>, align 16 # | %b.addr = alloca <16 x i32>, align 16 # | %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %a.coerce, i64 0) # | %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %b.coerce, i64 0) # | store <16 x i32> %a, ptr %a.addr, align 16 # | store <16 x i32> %b, ptr %b.addr, align 16 # | %0 = load <16 x i32>, ptr %a.addr, align 16 # | %1 = load <16 x i32>, ptr %b.addr, align 16 # | %and = and <16 x i32> %0, %1 # | store <16 x i32> %and, ptr %retval, align 16 # | %2 = load <16 x i32>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv4i32.v16i32( poison, <16 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4i32.v16i32(, <16 x i32>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_i64( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i64>, align 16 # | %a.addr = alloca <8 x i64>, align 16 # | %b.addr = alloca <8 x i64>, align 16 # | %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64( %a.coerce, i64 0) # | %b = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64( %b.coerce, i64 0) # | store <8 x i64> %a, ptr %a.addr, align 16 # | store <8 x i64> %b, ptr %b.addr, align 16 # | %0 = load <8 x i64>, ptr %a.addr, align 16 # | %1 = load <8 x i64>, ptr %b.addr, align 16 # | %and = and <8 x i64> %0, %1 # | store <8 x i64> %and, ptr %retval, align 16 # | %2 = load <8 x i64>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv2i64.v8i64( poison, <8 x i64> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2i64.v8i64(, <8 x i64>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_u8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <64 x i8>, align 16 # | %a.addr = alloca <64 x i8>, align 16 # | %b.addr = alloca <64 x i8>, align 16 # | %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %a.coerce, i64 0) # | %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %b.coerce, i64 0) # | store <64 x i8> %a, ptr %a.addr, align 16 # | store <64 x i8> %b, ptr %b.addr, align 16 # | %0 = load <64 x i8>, ptr %a.addr, align 16 # | %1 = load <64 x i8>, ptr %b.addr, align 16 # | %and = and <64 x i8> %0, %1 # | store <64 x i8> %and, ptr %retval, align 16 # | %2 = load <64 x i8>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv16i8.v64i8( poison, <64 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_u16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i16>, align 16 # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca <32 x i16>, align 16 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %b.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store <32 x i16> %b, ptr %b.addr, align 16 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load <32 x i16>, ptr %b.addr, align 16 # | %and = and <32 x i16> %0, %1 # | store <32 x i16> %and, ptr %retval, align 16 # | %2 = load <32 x i16>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv8i16.v32i16( poison, <32 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_u32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i32>, align 16 # | %a.addr = alloca <16 x i32>, align 16 # | %b.addr = alloca <16 x i32>, align 16 # | %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %a.coerce, i64 0) # | %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %b.coerce, i64 0) # | store <16 x i32> %a, ptr %a.addr, align 16 # | store <16 x i32> %b, ptr %b.addr, align 16 # | %0 = load <16 x i32>, ptr %a.addr, align 16 # | %1 = load <16 x i32>, ptr %b.addr, align 16 # | %and = and <16 x i32> %0, %1 # | store <16 x i32> %and, ptr %retval, align 16 # | %2 = load <16 x i32>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv4i32.v16i32( poison, <16 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_u64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c (231 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf4x6_tumu( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | ... # `---data was truncated (10240/18506) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a2263eb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a2263e8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a2263ebcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd6b8049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd6b80a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd6b8049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd6b8031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a22638124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a226381096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a226365f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a226015176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a226014e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd6b8032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd6b80330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd6b80330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a226014d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c (232 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtssel_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ftssel.x.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ftssel.x.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtssel_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ftssel.x.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ftssel.x.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtssel_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ftssel.x.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ftssel.x.nxv2f64(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005606ef90c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005606ef909515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005606ef90ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f088dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f088dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f088dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f088dd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005606ef8a224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005606ef8a2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005606ef886f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005606ef536176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005606ef535e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f088dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f088dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f088dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005606ef535d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c (233 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrt_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.fsqrt.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fsqrt.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrt_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.fsqrt.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fsqrt.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrt_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.fsqrt.nxv2f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fsqrt.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrt_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.fsqrt.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrt_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.fsqrt.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrt_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.fsqrt.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrt_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.fsqrt.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrt_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.fsqrt.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrt_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.fsqrt.nxv2f64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056414d5b957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056414d5b6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056414d5b9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcf0bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcf0bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcf0bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcf0bf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056414d54f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056414d54f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056414d533f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056414d1e3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056414d1e2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcf0bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcf0bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcf0bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056414d1e2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c (234 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(targe # | ... # `---data was truncated (10240/53734) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005561dd38957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005561dd386515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005561dd389cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1b1d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1b1d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1b1d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1b1d71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005561dd31f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005561dd31f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005561dd303f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005561dcfb3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005561dcfb2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1b1d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1b1d71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1b1d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005561dcfb2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c (235 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svzip_s8_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.zip.x2.nxv16i8( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.zip.x2.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svzip_u8_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.zip.x2.nxv16i8( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svzip_mf8_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.zip.x2.nxv16i8( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svzip_s16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.zip.x2.nxv8i16( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.zip.x2.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svzip_u16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.zip.x2.nxv8i16( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svzip_f16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.zip.x2.nxv8f16( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.zip.x2.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svzip_bf16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.zip.x2.nxv8bf16( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.zip.x2.nxv8bf16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svzip_s32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.c # | ... # `---data was truncated (10240/35785) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055ba0a1a557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ba0a1a2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ba0a1a5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7f3e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7f3e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7f3e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7f3e71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ba0a13b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ba0a13b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ba0a11ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ba09dcf176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ba09dcee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7f3e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7f3e71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7f3e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ba09dced81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c (236 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4e # | ... # `---data was truncated (10240/216250) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055be8aa2057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055be8aa1d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055be8aa20cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd462733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd46278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd462733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd46271b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055be8a9b624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055be8a9b6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055be8a99af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055be8a64a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055be8a649e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd46271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd46271d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd46271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055be8a649d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c (237 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti4_lane_zt_u8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32 0, %0, i32 3) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti4_lane_zt_s8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32 0, %0, i32 3) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti4_lane_zt_mf8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32 0, %0, i32 3) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti4_lane_zt_u16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8i16(i32 0, %0, i32 3) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8i16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti4_lane_zt_s16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8i16(i32 0, %0, i32 3) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti4_lane_zt_f16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8f16(i32 0, %0, i32 3) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8f16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti4_lane_zt_bf16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8bf16(i32 0, %0, i32 3) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8bf16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti4_lane_zt_u32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4i32(i32 0, %0, i32 3) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4i32(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti4_lane_zt_s32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4i32(i32 0, %0, i32 3) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti4_lane_zt_f32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4f32(i32 0, %0, i32 3) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4f32(i32 immarg, , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000056080a86257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056080a85f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056080a862cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1938d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1938d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1938d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1938d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056080a7f824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056080a7f8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056080a7dcf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056080a48c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056080a48be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1938d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1938d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1938d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056080a48bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c (238 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16m8(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i16.i64( %2, ptr %0, %1, i6 # | ... # `---data was truncated (10240/132470) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005568caba457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005568caba1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005568caba4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8eb7133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8eb718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8eb7133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8eb711b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005568cab3a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005568cab3a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005568cab1ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005568ca7ce176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005568ca7cde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8eb711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8eb711d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8eb711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005568ca7cdd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c (239 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1_s8( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | call void @llvm.aarch64.sve.st1.nxv16i8.p0( %2, %0, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv16i8.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1_s16( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.st1.nxv8i16.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv8i16.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1_s32( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.st1.nxv4i32.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv4i32.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1_s64( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.st1.nxv2i64.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv2i64.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1_u8( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | call void @llvm.aarch64.sve.st1.nxv16i8.p0( %2, %0, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1_u16( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.st1.nxv8i16.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1_u32( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.st1.nxv4i32.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1_u64( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.st1.nxv2i64.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1_f16( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.st1.nxv8f16.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv8f16.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1_f32( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.st1.nxv4f32.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv4f32.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind # | ... # `---data was truncated (10240/75656) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x000055aea2ed457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055aea2ed1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055aea2ed4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe1ccf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe1ccf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe1ccf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe1ccf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aea2e6a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055aea2e6a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055aea2e4ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055aea2afe176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055aea2afde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe1ccf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe1ccf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe1ccf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aea2afdd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c (240 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 # | ... # `---data was truncated (10240/66565) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d44ead757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d44ead4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d44ead7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f94f5d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f94f5d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f94f5d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f94f5d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d44ea6d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d44ea6d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d44ea51f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d44e701176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d44e700e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f94f5d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f94f5d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f94f5d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d44e700d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c (241 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbrkb_b_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.brkb.z.nxv16i1( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.brkb.z.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbrkb_b_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 2 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %inactive, ptr %inactive.addr, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %inactive.addr, align 2 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 2 # | %3 = call @llvm.aarch64.sve.brkb.nxv16i1( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.brkb.nxv16i1(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055ed8bd4257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ed8bd3f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ed8bd42cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff512f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff512f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff512f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff512f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ed8bcd824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ed8bcd8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ed8bcbcf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ed8b96c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ed8b96be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff512f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff512f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff512f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ed8b96bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c (242 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uh_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv4i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uh_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv2i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uh_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uh_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uh_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv4i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uh_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv2i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uh_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv4i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uh_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv2i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055f6fbbba57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f6fbbb7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f6fbbbacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5d21a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5d21a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5d21a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5d21a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f6fbb5024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f6fbb50096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f6fbb34f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f6fb7e4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f6fb7e3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5d21a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5d21a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5d21a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f6fb7e3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/arm-bf16-convert-intrinsics.c (243 of 27911) ******************** TEST 'Clang :: CodeGen/arm-bf16-convert-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +bf16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +bf16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vcvt_f32_bf16(<4 x bfloat> noundef %a) #0 { # | entry: # | %__p0_824.addr.i = alloca <4 x bfloat>, align 8 # | %__ret_824.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %__s0.i = alloca <4 x i16>, align 8 # | %ref.tmp1.i = alloca <16 x i8>, align 16 # | %tmp.i = alloca <4 x i32>, align 16 # | %a.addr = alloca <4 x bfloat>, align 8 # | store <4 x bfloat> %a, ptr %a.addr, align 8 # | %0 = load <4 x bfloat>, ptr %a.addr, align 8 # | store <4 x bfloat> %0, ptr %__p0_824.addr.i, align 8 # | %1 = load <4 x i16>, ptr %__p0_824.addr.i, align 8 # | store <4 x i16> %1, ptr %__s0.i, align 8 # | %2 = load <8 x i8>, ptr %__s0.i, align 8 # | %3 = bitcast <8 x i8> %2 to <4 x i16> # | %4 = zext <4 x i16> %3 to <4 x i32> # | %vshll_n.i = shl <4 x i32> %4, splat (i32 16) # | store <4 x i32> %vshll_n.i, ptr %ref.tmp1.i, align 16 # | %5 = load <4 x i32>, ptr %ref.tmp1.i, align 16 # | store <4 x i32> %5, ptr %__ret.i, align 16 # | %6 = load <4 x i32>, ptr %__ret.i, align 16 # | store <4 x i32> %6, ptr %tmp.i, align 16 # | %7 = load <4 x i32>, ptr %tmp.i, align 16 # | store <4 x i32> %7, ptr %ref.tmp.i, align 16 # | %8 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %8, ptr %__ret_824.i, align 16 # | %9 = load <4 x float>, ptr %__ret_824.i, align 16 # | ret <4 x float> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vcvtq_low_f32_bf16(<8 x bfloat> noundef %a) #0 { # | entry: # | %__p0.addr.i1 = alloca <8 x bfloat>, align 16 # | %__ret.i2 = alloca <4 x bfloat>, align 8 # | %__p0_824.addr.i.i = alloca <4 x bfloat>, align 8 # | %__ret_824.i.i = alloca <4 x float>, align 16 # | %ref.tmp.i.i = alloca <4 x i32>, align 16 # | %__ret.i.i = alloca <4 x i32>, align 16 # | %__s0.i.i = alloca <4 x i16>, align 8 # | %ref.tmp1.i.i = alloca <16 x i8>, align 16 # | %tmp.i.i = alloca <4 x i32>, align 16 # | %__p0.addr.i = alloca <8 x bfloat>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %a.addr = alloca <8 x bfloat>, align 16 # | store <8 x bfloat> %a, ptr %a.addr, align 16 # | %0 = load <8 x bfloat>, ptr %a.addr, align 16 # | store <8 x bfloat> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16 # | store <8 x bfloat> %1, ptr %__p0.addr.i1, align 16 # | %2 = load <8 x bfloat>, ptr %__p0.addr.i1, align 16 # | %3 = load <8 x bfloat>, ptr %__p0.addr.i1, align 16 # | %shuffle.i = shufflevector <8 x bfloat> %2, <8 x bfloat> %3, <4 x i32> # | store <4 x bfloat> %shuffle.i, ptr %__ret.i2, align 8 # | %4 = load <4 x bfloat>, ptr %__ret.i2, align 8 # | store <4 x bfloat> %4, ptr %__p0_824.addr.i.i, align 8 # | %5 = load <4 x i16>, ptr %__p0_824.addr.i.i, align 8 # | store <4 x i16> %5, ptr %__s0.i.i, align 8 # | %6 = load <8 x i8>, ptr %__s0.i.i, align 8 # | %7 = bitcast <8 x i8> %6 to <4 x i16> # | %8 = zext <4 x i16> %7 to <4 x i32> # | %vshll_n.i.i = shl <4 x i32> %8, splat (i32 16) # | store <4 x i32> %vshll_n.i.i, ptr %ref.tmp1.i.i, align 16 # | %9 = load <4 x i32>, ptr %ref.tmp1.i.i, align 16 # | store <4 x i32> %9, ptr %__ret.i.i, align 16 # | %10 = load <4 x i32>, ptr %__ret.i.i, align 16 # | store <4 x i32> %10, ptr %tmp.i.i, align 16 # | %11 = load <4 x i32>, ptr %tmp.i.i, align 16 # | store <4 x i32> %11, ptr %ref.tmp.i.i, align 16 # | %12 = load <4 x float>, ptr %ref.tmp.i.i, align 16 # | store <4 x float> %12, ptr %__ret_824.i.i, align 16 # | %13 = load <4 x float>, ptr %__ret_824.i.i, align 16 # | store <4 x float> %13, ptr %__ret.i, align 16 # | %14 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vcvtq_high_f32_bf16(<8 x bfloat> noundef %a) #0 { # | entry: # | %__p0.addr.i1 = alloca <8 x bfloat>, align 16 # | %__ret.i2 = alloca <4 x bfloat>, align 8 # | %__p0_824.addr.i.i = alloca <4 x bfloat>, align 8 # | %__ret_824.i.i = alloca <4 x float>, align 16 # | %ref.tmp.i.i = alloca <4 x i32>, align 16 # | %__ret.i.i = alloca <4 x i32>, align 16 # | %__s0.i.i = alloca <4 x i16>, align 8 # | %ref.tmp1.i.i = alloca <16 x i8>, align 16 # | %tmp.i.i = alloca <4 x i32>, align 16 # | %__p0.addr.i = alloca <8 x bfloat>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %a.addr = alloca <8 x bfloat>, align 16 # | store <8 x bfloat> %a, ptr %a.addr, align 16 # | %0 = load <8 x bfloat>, ptr %a.addr, align 16 # | store <8 x bfloat> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16 # | store <8 x bfloat> %1, ptr %__p0.addr.i1, align 16 # | %2 = load <8 x bfloat>, ptr %__p0.addr.i1, align 16 # | %3 = load <8 x bfloat>, ptr %__p0.addr.i1, align 16 # | %shuffle.i = shufflevector <8 x bfloat> %2, <8 x bfloat> %3, <4 x i32> # | store <4 x bfloat> %shuffle.i, ptr %__ret.i2, align 8 # | %4 = load <4 x bfloat>, ptr %__ret.i2, align 8 # | store <4 x bfloat> %4, ptr %__p0_824.addr.i.i, align 8 # | %5 = load <4 x i16>, ptr %__p0_824.addr.i.i, align 8 # | store <4 x i16> %5, ptr %__s0.i.i, align 8 # | %6 = load <8 x i8>, ptr %__s0.i.i, align 8 # | %7 = bitcast <8 x i8> %6 to <4 x i16> # | %8 = zext <4 x i16> %7 to <4 x i32> # | %vshll_n.i.i = shl <4 x i32> %8, splat (i32 16) # | store <4 x i32> %vshll_n.i.i, ptr %ref.tmp1.i.i, align 16 # | %9 = load <4 x i32>, ptr %ref.tmp1.i.i, align 16 # | store <4 x i32> %9, ptr %__ret.i.i, align 16 # | %10 = load <4 x i32>, ptr %__ret.i.i, align 16 # | store <4 x i32> %10, ptr %tmp.i.i, align 16 # | %11 = load <4 x i32>, ptr %tmp.i.i, align 16 # | store <4 x i32> %11, ptr %ref.tmp.i.i, align 16 # | %12 = load <4 x float>, ptr %ref.tmp.i.i, align 16 # | store <4 x float> %12, ptr %__ret_824.i.i, align 16 # | %13 = load <4 x float>, ptr %__ret_824.i.i, align 16 # | store <4 x float> %13, ptr %__ret.i, align 16 # | %14 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vcvt_bf16_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <4 x float> # | %3 = fptrunc <4 x float> %2 to <4 x bfloat> # | store <4 x bfloat> %3, ptr %ref.tmp.i, align 8 # | %4 = load <4 x bfloat>, ptr %ref.tmp.i, align 8 # | store <4 x bfloat> %4, ptr %__ret.i, align 8 # | %5 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcvtq_low_bf16_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <4 x float> # | %3 = fptrunc <4 x float> %2 to <4 x bfloat> # | %4 = shufflevector <4 x bfloat> %3, <4 x bfloat> zeroinitializer, <8 x i32> # | store <8 x bfloat> %4, ptr %ref.tmp.i, align 16 # | %5 = load <8 x bfloat>, ptr %ref.tmp.i, align 16 # | store <8 x bfloat> %5, ptr %__ret.i, align 16 # | %6 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcvtq_high_bf16_f32(<8 x bfloat> noundef %inactive, <4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x bfloat>, align 16 # | %__p1.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %inactive.addr = alloca <8 x bfloat>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <8 x bfloat> %inactive, ptr %inactive.addr, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <8 x bfloat>, ptr %inactive.addr, align 16 # | %1 = load <4 x float>, ptr %a.addr, align 16 # | store <8 x bfloat> %0, ptr %__p0.addr.i, align 16 # | store <4 x float> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %4 = bitcast <16 x i8> %2 to <8 x bfloat> # | %5 = shufflevector <8 x bfloat> %4, <8 x bfloat> poison, <4 x i32> # | %6 = bitcast <16 x i8> %3 to <4 x float> # | %7 = fptrunc <4 x float> %6 to <4 x bfloat> # | %8 = shufflevector <4 x bfloat> %5, <4 x bfloat> %7, <8 x i32> # | store <8 x bfloat> %8, ptr %ref.tmp.i, align 16 # | %9 = load <8 x bfloat>, ptr %ref.tmp.i, align 16 # | store <8 x bfloat> %9, ptr %__ret.i, align 16 # | %10 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local bfloat @test_vcvth_bf16_f32(float noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca float, align 4 # | %__ret.i = alloca bfloat, align 2 # | %ref.tmp.i = alloca bfloat, align 2 # | %a.addr = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__p0.addr.i, align 4 # | %1 = load float, ptr %__p0.addr.i, align 4 # | %2 = fptrunc float %1 to bfloat # | store bfloat %2, ptr %ref.tmp.i, align 2 # | %3 = load bfloat, ptr %ref.tmp.i, align 2 # | store bfloat %3, ptr %__ret.i, align 2 # | %4 = load bfloat, ptr %__ret.i, align 2 # | ret bfloat %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vcvtah_f32_bf16(bfloat noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca bfloat, align 2 # | %__ret.i = alloca float, align 4 # | %ref.tmp.i = alloca i32, align 4 # | %a.addr = alloca bfloat, align 2 # | store bfloat %a, ptr %a.addr, align 2 # | %0 = load # | ... # `---data was truncated (10240/10974) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x00005645a590f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005645a590c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005645a590fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feabdf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feabdf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feabdf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feabdf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005645a58a524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005645a58a5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005645a5889f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005645a5539176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005645a5538e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007feabdf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feabdf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feabdf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005645a5538d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c (244 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1wq_u32( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr, align 16 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %zt.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1wq.nxv4i32.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv1i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.aarch64.sve.st1wq.nxv4i32.p0(, , ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1wq_vnum_u32( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr, align 16 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %zt.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = getelementptr , ptr %1, i64 1 # | call void @llvm.aarch64.sve.st1wq.nxv4i32.p0( %2, %3, ptr %4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1wq_s32( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr, align 16 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %zt.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1wq.nxv4i32.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1wq_vnum_s32( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr, align 16 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %zt.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = getelementptr , ptr %1, i64 1 # | call void @llvm.aarch64.sve.st1wq.nxv4i32.p0( %2, %3, ptr %4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1wq_f32( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr, align 16 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %zt.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1wq.nxv4f32.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.aarch64.sve.st1wq.nxv4f32.p0(, , ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1wq_vnum_f32( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr, align 16 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %zt.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = getelementptr , ptr %1, i64 1 # | call void @llvm.aarch64.sve.st1wq.nxv4f32.p0( %2, %3, ptr %4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1dq_u64( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr, align 16 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %zt.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1dq.nxv2i64.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.aarch64.sve.st1dq.nxv2i64.p0(, , ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1dq_vnum_u64( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr, align 16 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %zt.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = getelementptr , ptr %1, i64 -8 # | call void @llvm.aarch64.sve.st1dq.nxv2i64.p0( %2, %3, ptr %4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1dq_s64( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr, align 16 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %zt.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1dq.nxv2i64.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1dq_vnum_s64( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr, align 16 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %zt.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = getelementptr , ptr %1, i64 -8 # | call void @llvm.aarch64.sve.st1dq.nxv2i64.p0( %2, %3, ptr %4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1dq_f64( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr # | ... # `---data was truncated (10240/12466) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055bdf6adb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bdf6ad8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bdf6adbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0f3b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0f3b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0f3b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0f3b91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bdf6a7124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bdf6a71096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bdf6a55f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bdf6705176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bdf6704e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0f3b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0f3b91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0f3b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bdf6704d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c (245 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svbmopa_u32( %pn, %pm, %zn, %zm) #0 { # | entry: # | %pn.addr = alloca , align 2 # | %pm.addr = alloca , align 2 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %pn, ptr %pn.addr, align 2 # | store %pm, ptr %pm.addr, align 2 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %pn.addr, align 2 # | %1 = load , ptr %pm.addr, align 2 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load , ptr %zm.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | call void @llvm.aarch64.sme.bmopa.za32.nxv4i32(i32 3, %4, %5, %2, %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.bmopa.za32.nxv4i32(i32 immarg, , , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svbmopa_s32( %pn, %pm, %zn, %zm) #0 { # | entry: # | %pn.addr = alloca , align 2 # | %pm.addr = alloca , align 2 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %pn, ptr %pn.addr, align 2 # | store %pm, ptr %pm.addr, align 2 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %pn.addr, align 2 # | %1 = load , ptr %pm.addr, align 2 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load , ptr %zm.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | call void @llvm.aarch64.sme.bmopa.za32.nxv4i32(i32 3, %4, %5, %2, %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svbmops_u32( %pn, %pm, %zn, %zm) #0 { # | entry: # | %pn.addr = alloca , align 2 # | %pm.addr = alloca , align 2 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %pn, ptr %pn.addr, align 2 # | store %pm, ptr %pm.addr, align 2 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %pn.addr, align 2 # | %1 = load , ptr %pm.addr, align 2 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load , ptr %zm.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | call void @llvm.aarch64.sme.bmops.za32.nxv4i32(i32 3, %4, %5, %2, %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.bmops.za32.nxv4i32(i32 immarg, , , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svbmops_s32( %pn, %pm, %zn, %zm) #0 { # | entry: # | %pn.addr = alloca , align 2 # | %pm.addr = alloca , align 2 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %pn, ptr %pn.addr, align 2 # | store %pm, ptr %pm.addr, align 2 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %pn.addr, align 2 # | %1 = load , ptr %pm.addr, align 2 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load , ptr %zm.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | call void @llvm.aarch64.sme.bmops.za32.nxv4i32(i32 3, %4, %5, %2, %3) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000056311dc6f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056311dc6c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056311dc6fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd024649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd0246a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd024649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd024631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056311dc0524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056311dc05096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056311dbe9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056311d899176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056311d898e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd024632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd0246330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd0246330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056311d898d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c (246 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16m2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store # | ... # `---data was truncated (10240/79497) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005593f7d7957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005593f7d76515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005593f7d79cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7675449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f76754a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7675449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7675431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005593f7d0f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005593f7d0f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005593f7cf3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005593f79a3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005593f79a2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7675432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f76754330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f76754330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005593f79a2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c (247 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.mul.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mul.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mul.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mul.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mul.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mul.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mul.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mul.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.mul.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mul.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mul.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mul.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_s8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, pt # | ... # `---data was truncated (10240/77120) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000558d5a1a357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558d5a1a0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558d5a1a3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c84305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c8435c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c84305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c842ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558d5a13924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558d5a139096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558d5a11df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558d59dcd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558d59dcce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2c842eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c842ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c842ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558d59dccd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c (248 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti2_lane_zt_u8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 0, %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti2_lane_zt_s8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 0, %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti2_lane_zt_u16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti2.lane.zt.nxv8i16(i32 0, %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti2.lane.zt.nxv8i16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti2_lane_zt_mf8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 0, %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti2_lane_zt_s16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti2.lane.zt.nxv8i16(i32 0, %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti2_lane_zt_f16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti2.lane.zt.nxv8f16(i32 0, %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti2.lane.zt.nxv8f16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti2_lane_zt_bf16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti2.lane.zt.nxv8bf16(i32 0, %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti2.lane.zt.nxv8bf16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti2_lane_zt_u32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti2.lane.zt.nxv4i32(i32 0, %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti2.lane.zt.nxv4i32(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti2_lane_zt_s32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti2.lane.zt.nxv4i32(i32 0, %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti2_lane_zt_f32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti2.lane.zt.nxv4f32(i32 0, %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti2.lane.zt.nxv4f32(i32 immarg, , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055c041d9a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c041d97515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c041d9acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff8b7849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff8b78a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff8b7849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff8b7831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c041d3024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c041d30096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c041d14f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c0419c4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c0419c3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff8b7832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff8b78330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff8b78330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c0419c3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c (249 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_mf8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ldnf1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv16i8.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_s8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ldnf1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv8i16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv4i32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv2i64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_u8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ldnf1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_f16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv8f16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv8f16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_f32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4f32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv4f32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_f64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2f64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv2f64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_vnum_mf8( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | # | ... # `---data was truncated (10240/22483) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005647b163b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005647b1638515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005647b163bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff6fb733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff6fb78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff6fb733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff6fb71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005647b15d124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005647b15d1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005647b15b5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005647b1265176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005647b1264e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff6fb71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff6fb71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff6fb71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005647b1264d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c (250 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls2_f32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.fmls.vg1x2.nxv4f32(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fmls.vg1x2.nxv4f32(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls4_f32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm.coerce0, %zm.coerce1, %zm.coerce2, %zm.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zm = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | %4 = insertvalue { , , , } poison, %zm.coerce0, 0 # | %5 = insertvalue { , , , } %4, %zm.coerce1, 1 # | %6 = insertvalue { , , , } %5, %zm.coerce2, 2 # | %7 = insertvalue { , , , } %6, %zm.coerce3, 3 # | store { , , , } %7, ptr %zm, align 16 # | %zm2 = load { , , , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store { , , , } %zm2, ptr %zm.addr, align 16 # | %8 = load i32, ptr %slice_base.addr, align 4 # | %9 = load { , , , }, ptr %zn.addr, align 16 # | %10 = extractvalue { , , , } %9, 0 # | %11 = extractvalue { , , , } %9, 1 # | %12 = extractvalue { , , , } %9, 2 # | %13 = extractvalue { , , , } %9, 3 # | %14 = load { , , , }, ptr %zm.addr, align 16 # | %15 = extractvalue { , , , } %14, 0 # | %16 = extractvalue { , , , } %14, 1 # | %17 = extractvalue { , , , } %14, 2 # | %18 = extractvalue { , , , } %14, 3 # | call void @llvm.aarch64.sme.fmls.vg1x4.nxv4f32(i32 %8, %10, %11, %12, %13, %15, %16, %17, %18) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fmls.vg1x4.nxv4f32(i32, , , , , , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls_single2_f32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.fmls.single.vg1x2.nxv4f32(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fmls.single.vg1x2.nxv4f32(i32, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls_single4_f32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c (251 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/175163) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dc42d0657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055dc42d03515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055dc42d06cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2e71f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2e71f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2e71f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2e71f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dc42c9c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055dc42c9c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055dc42c80f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055dc42930176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055dc4292fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2e71f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2e71f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2e71f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dc4292fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c (252 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c (253 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_b_0( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 2 # | %tuple.addr = alloca { , }, align 2 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 2 # | %tuple1 = load { , }, ptr %tuple, align 2 # | store { , } %tuple1, ptr %tuple.addr, align 2 # | %2 = load { , }, ptr %tuple.addr, align 2 # | %3 = extractvalue { , } %2, 0 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_b_1( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 2 # | %tuple.addr = alloca { , }, align 2 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 2 # | %tuple1 = load { , }, ptr %tuple, align 2 # | store { , } %tuple1, ptr %tuple.addr, align 2 # | %2 = load { , }, ptr %tuple.addr, align 2 # | %3 = extractvalue { , } %2, 1 # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000556087fbd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556087fba515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556087fbdcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f05f1449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f05f14a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f05f1449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f05f1431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556087f5324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556087f53096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556087f37f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556087be7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556087be6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f05f1432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f05f14330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f05f14330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556087be6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c (254 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintz_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frintz.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintz.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintz_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frintz.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintz.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintz_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frintz.nxv2f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintz.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintz_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.frintz.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintz_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.frintz.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintz_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.frintz.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintz_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frintz.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintz_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frintz.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintz_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frintz.nxv2f64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000564dd9e4457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564dd9e41515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564dd9e44cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8946a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8946aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8946a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8946a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564dd9dda24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564dd9dda096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564dd9dbef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564dd9a6e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564dd9a6de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8946a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8946a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8946a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564dd9a6dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c (255 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsel_s8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.sel.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sel.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsel_s16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.sel.nxv8i16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sel.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsel_s32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.sel.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sel.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsel_s64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.sel.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sel.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsel_u8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.sel.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsel_u16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.sel.nxv8i16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsel_u32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.sel.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsel_u64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.sel.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsel_f16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.sel.nxv8f16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sel.nxv8f16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_ # | ... # `---data was truncated (10240/15264) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x0000555dac08657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555dac083515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555dac086cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2103533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f210358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2103533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f210351b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555dac01c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555dac01c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555dac000f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555dabcb0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555dabcafe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f210351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f210351d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f210351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555dabcafd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/eorv.c (256 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve/eorv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_sveorv_s8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.eorv.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i8 @llvm.aarch64.sve.eorv.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_sveorv_s16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.eorv.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.aarch64.sve.eorv.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_sveorv_s32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.eorv.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.eorv.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_sveorv_s64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.eorv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.eorv.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_sveorv_u8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.eorv.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_sveorv_u16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.eorv.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_sveorv_u32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.eorv.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_sveorv_u64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.eorv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x000056077f19957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056077f196515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056077f199cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff30ce1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff30ce725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff30ce1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff30ce03507 abort ./stdlib/abort.c:85:3 # | #7 0x000056077f12f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056077f12f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056077f113f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056077edc3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056077edc2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff30ce04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff30ce050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff30ce050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056077edc2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c (257 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c (258 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uw_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i32.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv2i32.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uw_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i32.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uw_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv2i32.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uw_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv2i32.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uw_gather_u64base_s64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64( %2, %1, i64 0) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64(, , i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uw_gather_u64base_u64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64( %2, %1, i64 0) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uw_gather_s64offset_s64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = zext %4 to # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(, ptr, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uw_gather_s64offset_u64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = zext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uw_gather_u64offset_s64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = zext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uw_gather_u64offset_u64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = zext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff # | ... # `---data was truncated (10240/18920) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000557b8b9ca57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557b8b9c7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557b8b9cacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4a59333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4a5938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4a59333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4a5931b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557b8b96024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557b8b960096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557b8b944f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557b8b5f4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557b8b5f3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4a5931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4a5931d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4a5931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557b8b5f3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c (259 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpkhi_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sunpkhi.nxv8i16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sunpkhi.nxv8i16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpkhi_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sunpkhi.nxv4i32( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sunpkhi.nxv4i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpkhi_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sunpkhi.nxv2i64( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sunpkhi.nxv2i64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpkhi_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uunpkhi.nxv8i16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uunpkhi.nxv8i16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpkhi_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uunpkhi.nxv4i32( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uunpkhi.nxv4i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpkhi_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uunpkhi.nxv2i64( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uunpkhi.nxv2i64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpkhi_b( %op) #0 { # | entry: # | %op.addr = alloca , align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %op.addr, align 2 # | %1 = call @llvm.aarch64.sve.punpkhi.nxv16i1( %0) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.punpkhi.nxv16i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055d2505b457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d2505b1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d2505b4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4cf8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4cf898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4cf8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4cf891b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d25054a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d25054a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d25052ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d2501de176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d2501dde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4cf891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4cf891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4cf891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d2501ddd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c (260 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_v # | ... # `---data was truncated (10240/228865) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005555d03ce57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005555d03cb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005555d03cecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7003a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7003aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7003a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7003a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005555d036424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005555d0364096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005555d0348f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005555cfff8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005555cfff7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7003a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7003a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7003a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005555cfff7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c (261 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_b8() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) # | ret %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ptrue.nxv16i1(i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_b16() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) # | %1 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ptrue.nxv8i1(i32 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_b32() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) # | %1 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ptrue.nxv4i1(i32 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_b64() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) # | %1 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ptrue.nxv2i1(i32 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 0) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_1() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 1) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_2() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 2) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_3() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 3) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_4() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 4) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_5() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 5) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_6() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 6) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_7() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 7) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_8() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 8) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_9() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 9) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_10() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 10) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_11() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 11) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_12() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 12) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_13() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 13) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_14() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 29) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_15() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 30) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_16() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b16() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv8i1(i32 0) # | %1 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b32() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv4i1(i32 1) # | %1 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b64() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv2i1(i32 2) # | %1 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %0) # | ret %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056482f71357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056482f710515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056482f713cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fce38b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fce38b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fce38b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fce38aed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056482f6a924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056482f6a9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056482f68df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056482f33d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056482f33ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fce38aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fce38aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fce38aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056482f33cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c (262 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtsmul_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ftsmul.x.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ftsmul.x.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtsmul_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ftsmul.x.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ftsmul.x.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtsmul_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ftsmul.x.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ftsmul.x.nxv2f64(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005638fa73e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005638fa73b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005638fa73ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f95c6649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f95c66a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f95c6649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f95c6631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005638fa6d424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005638fa6d4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005638fa6b8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005638fa368176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005638fa367e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f95c6632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f95c66330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f95c66330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005638fa367d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c (263 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2q_u8( %pg, ptr noundef %base, %zt.coerce0, %zt.coerce1) #0 { # | entry: # | %zt = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zt.coerce0, 0 # | %1 = insertvalue { , } %0, %zt.coerce1, 1 # | store { , } %1, ptr %zt, align 16 # | %zt1 = load { , }, ptr %zt, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %zt1, ptr %zt.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %zt.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | call void @llvm.aarch64.sve.st2q.nxv16i8.p0( %5, %6, %2, ptr %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st2q.nxv16i8.p0(, , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2q_s8( %pg, ptr noundef %base, %zt.coerce0, %zt.coerce1) #0 { # | entry: # | %zt = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zt.coerce0, 0 # | %1 = insertvalue { , } %0, %zt.coerce1, 1 # | store { , } %1, ptr %zt, align 16 # | %zt1 = load { , }, ptr %zt, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %zt1, ptr %zt.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %zt.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | call void @llvm.aarch64.sve.st2q.nxv16i8.p0( %5, %6, %2, ptr %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2q_u16( %pg, ptr noundef %base, %zt.coerce0, %zt.coerce1) #0 { # | entry: # | %zt = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zt.coerce0, 0 # | %1 = insertvalue { , } %0, %zt.coerce1, 1 # | store { , } %1, ptr %zt, align 16 # | %zt1 = load { , }, ptr %zt, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %zt1, ptr %zt.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %zt.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %2) # | call void @llvm.aarch64.sve.st2q.nxv8i16.p0( %5, %6, %7, ptr %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st2q.nxv8i16.p0(, , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2q_s16( %pg, ptr noundef %base, %zt.coerce0, %zt.coerce1) #0 { # | entry: # | %zt = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zt.coerce0, 0 # | %1 = insertvalue { , } %0, %zt.coerce1, 1 # | store { , } %1, ptr %zt, align 16 # | %zt1 = load { , }, ptr %zt, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %zt1, ptr %zt.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %zt.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %2) # | call void @llvm.aarch64.sve.st2q.nxv8i16.p0( %5, %6, %7, ptr %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2q_u32( %pg, ptr noundef %base, %zt.coerce0, %zt.coerce1) #0 { # | entry: # | %zt = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zt.coerce0, 0 # | %1 = insertvalue { , } %0, %zt.coerce1, 1 # | store { , } %1, ptr %zt, align 16 # | %zt1 = load { , }, ptr %zt, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %zt1, ptr %zt.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %zt.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %2) # | call void @llvm.aarch64.sve.st2q.nxv4i32.p0( %5, %6, %7, ptr %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st2q.nxv4i32.p0(, , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2q_s32( %pg, ptr noundef %base, %zt.coerce0, %zt.coerce1) #0 { # | entry: # | %zt = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zt.coerce0, 0 # | %1 = insertvalue { , } %0, %zt.coerce1, 1 # | store { , } %1, ptr %zt, align 16 # | %zt1 = load { , }, ptr %zt, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %zt1, ptr %zt.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %zt.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %2) # | call void @llvm.aarch64.sve.st2q.nxv4i32.p0(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/arm-vector_type-params-returns.c (264 of 27911) ******************** TEST 'Clang :: CodeGen/arm-vector_type-params-returns.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -DSVE_HEADER -triple aarch64 -target-feature +sve -emit-llvm -O2 -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -DSVE_HEADER -triple aarch64 -target-feature +sve -emit-llvm -O2 -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <8 x half> @test_ret_v8f16(<8 x half> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <8 x half> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <4 x float> @test_ret_v4f32(<4 x float> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <4 x float> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <2 x double> @test_ret_v2f64(<2 x double> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <2 x double> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <8 x bfloat> @test_ret_v8bf16(<8 x bfloat> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <8 x bfloat> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <16 x i8> @test_ret_v16s8(<16 x i8> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <16 x i8> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <8 x i16> @test_ret_v8s16(<8 x i16> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <8 x i16> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <4 x i32> @test_ret_v32s4(<4 x i32> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <4 x i32> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <2 x i64> @test_ret_v64s2(<2 x i64> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <2 x i64> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <16 x i8> @test_ret_v16u8(<16 x i8> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <16 x i8> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <8 x i16> @test_ret_v8u16(<8 x i16> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <8 x i16> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <4 x i32> @test_ret_v32u4(<4 x i32> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <4 x i32> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <2 x i64> @test_ret_v64u2(<2 x i64> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <2 x i64> %v # | } # | # | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | !llvm.errno.tbaa = !{!4} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # | !4 = !{!5, !6, i64 0} # | !5 = !{!"__libc_errno", !6, i64 0} # | !6 = !{!"int", !7, i64 0} # | !7 = !{!"omnipotent char", !8, i64 0} # | !8 = !{!"Simple C/C++ TBAA"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000564ed810157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564ed80fe515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564ed8101cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc70c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc70c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc70c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc70c91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564ed809724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564ed8097096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564ed807bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564ed7d2b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564ed7d2ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc70c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc70c91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc70c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564ed7d2ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c (265 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_u8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq2.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_u16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq2.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_u32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq2.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_u64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq2.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_s8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_s16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_s32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_s64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_f16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq2.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_f32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq2.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_f64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq2.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_bf16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq2.nxv8bf16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_mf8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv16i8( %0, %1) # | ret % # | ... # `---data was truncated (10240/10910) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005585180d457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005585180d1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005585180d4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb8aba1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb8aba725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb8aba1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb8aba03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055851806a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055851806a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055851804ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558517cfe176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558517cfde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb8aba04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb8aba050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb8aba050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558517cfdd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c (266 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv64i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv32i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv16i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv8i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv4i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv2i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv1i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556647bc157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556647bbe515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556647bc1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3b7c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3b7c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3b7c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3b7c631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556647b5724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556647b57096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556647b3bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005566477eb176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005566477eae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3b7c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3b7c6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3b7c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005566477ead81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c (267 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_luti4_zt_u8_x4( %op.coerce0, %op.coerce1) #0 { # | entry: # | %op = alloca { , }, align 16 # | %op.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %op.coerce0, 0 # | %1 = insertvalue { , } %0, %op.coerce1, 1 # | store { , } %1, ptr %op, align 16 # | %op1 = load { , }, ptr %op, align 16 # | store { , } %op1, ptr %op.addr, align 16 # | %2 = load { , }, ptr %op.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , , , } @llvm.aarch64.sme.luti4.zt.x4.nxv16i8(i32 0, %3, %4) # | ret { , , , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti4.zt.x4.nxv16i8(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_luti4_zt_s8_x4( %op.coerce0, %op.coerce1) #0 { # | entry: # | %op = alloca { , }, align 16 # | %op.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %op.coerce0, 0 # | %1 = insertvalue { , } %0, %op.coerce1, 1 # | store { , } %1, ptr %op, align 16 # | %op1 = load { , }, ptr %op, align 16 # | store { , } %op1, ptr %op.addr, align 16 # | %2 = load { , }, ptr %op.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , , , } @llvm.aarch64.sme.luti4.zt.x4.nxv16i8(i32 0, %3, %4) # | ret { , , , } %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme-lutv2,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005600f3e8f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005600f3e8c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005600f3e8fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0ada81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0ada8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0ada81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0ada803507 abort ./stdlib/abort.c:85:3 # | #7 0x00005600f3e2524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005600f3e25096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005600f3e09f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005600f3ab9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005600f3ab8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0ada804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0ada8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0ada8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005600f3ab8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c (268 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_s8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.expand.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.expand.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_s16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.expand.nxv8i16( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.expand.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_u8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.expand.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_u16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.expand.nxv8i16( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_mf8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.expand.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_f16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.expand.nxv8f16( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.expand.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_bf16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.expand.nxv8bf16( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.expand.nxv8bf16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_s32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.expand.nxv4i32( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.expand.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_s64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.expand.nxv2i64( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.expand.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_u32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.expand.nxv4i32( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_u64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.expand.nxv2i64( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_f32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, al # | ... # `---data was truncated (10240/12168) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000559a1cfaa57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559a1cfa7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559a1cfaacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f46b8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f46b898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f46b8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f46b891b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559a1cf4024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559a1cf40096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559a1cf24f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559a1cbd4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559a1cbd3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f46b891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f46b891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f46b891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559a1cbd3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c (269 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_u8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq1.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_u16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq1.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_u32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq1.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_u64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq1.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_s8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_s16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_s32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_s64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_f16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq1.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_f32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq1.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_f64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq1.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_bf16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq1.nxv8bf16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_mf8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv16i8( %0, %1) # | ret % # | ... # `---data was truncated (10240/10910) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005577a7b9557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005577a7b92515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005577a7b95cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fade4a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fade4aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fade4a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fade4a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005577a7b2b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005577a7b2b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005577a7b0ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005577a77bf176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005577a77bee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fade4a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fade4a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fade4a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005577a77bed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c (270 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_i8mf8x7 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c01372d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c01372a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c01372dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4ebf449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4ebf4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4ebf449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4ebf431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c0136c324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c0136c3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c0136a7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c013357176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c013356e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4ebf432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4ebf4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4ebf4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c013356d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c (271 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincp_n_s32_b8(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call i32 @llvm.aarch64.sve.sqincp.n32.nxv16i1(i32 %0, %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqincp.n32.nxv16i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincp_n_s32_b16(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %3 = call i32 @llvm.aarch64.sve.sqincp.n32.nxv8i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqincp.n32.nxv8i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincp_n_s32_b32(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %3 = call i32 @llvm.aarch64.sve.sqincp.n32.nxv4i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqincp.n32.nxv4i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincp_n_s32_b64(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %3 = call i32 @llvm.aarch64.sve.sqincp.n32.nxv2i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqincp.n32.nxv2i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincp_n_s64_b8(i64 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | %pg.addr = alloca , align 2 # | store i64 %op, ptr %op.addr, align 8 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call i64 @llvm.aarch64.sve.sqincp.n64.nxv16i1(i64 %0, %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqincp.n64.nxv16i1(i64, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincp_n_s64_b16(i64 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | %pg.addr = alloca , align 2 # | store i64 %op, ptr %op.addr, align 8 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %3 = call i64 @llvm.aarch64.sve.sqincp.n64.nxv8i1(i64 %0, %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqincp.n64.nxv8i1(i64, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincp_n_s64_b32(i64 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | %pg.addr = alloca , align 2 # | store i64 %op, ptr %op.addr, align 8 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %3 = call i64 @llvm.aarch64.sve.sqincp.n64.nxv4i1(i64 %0, %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqincp.n64.nxv4i1(i64, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincp_n_s64_b64(i64 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | %pg.addr = alloca , align 2 # | store i64 %op, ptr %op.addr, align 8 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %3 = call i64 @llvm.aarch64.sve.sqincp.n64.nxv2i1(i64 %0, %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqincp.n64.nxv2i1(i64, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincp_n_u32_b8(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call i32 @llvm.aarch64.sve.uqincp.n32.nxv16i1(i32 %0, %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqincp.n32.nxv16i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincp_n_u32_b16(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %3 = call i32 @llvm.aarch64.sve.uqincp.n32.nxv8i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqincp.n32.nxv8i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincp_n_u32_b32(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %3 = call i32 @llvm.aarch64.sve.uqincp.n32.nxv4i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqincp.n32.nxv4i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincp_n_u32_b64(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %3 = call i32 @llvm.aarch64.sve.uqincp.n32.nxv2i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqincp.n32.nxv2i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincp_n_u64_b8(i64 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | %pg.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c (272 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_s32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.compact.nxv4i32( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.compact.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_s64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.compact.nxv2i64( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.compact.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_u32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.compact.nxv4i32( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_u64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.compact.nxv2i64( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_f32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.compact.nxv4f32( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.compact.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_f64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.compact.nxv2f64( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.compact.nxv2f64(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000555e7fcf757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555e7fcf4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555e7fcf7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb87d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb87d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb87d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb87d91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555e7fc8d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555e7fc8d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555e7fc71f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555e7f921176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555e7f920e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb87d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb87d91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb87d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555e7f920d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c (273 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvtn_f8_bf16( %zn_zm.coerce0, %zn_zm.coerce1, i64 noundef %fpm) #0 { # | entry: # | %zn_zm = alloca { , }, align 16 # | %zn_zm.addr = alloca { , }, align 16 # | %fpm.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn_zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zn_zm.coerce1, 1 # | store { , } %1, ptr %zn_zm, align 16 # | %zn_zm1 = load { , }, ptr %zn_zm, align 16 # | store { , } %zn_zm1, ptr %zn_zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %2 = load { , }, ptr %zn_zm.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %5) # | %6 = call @llvm.aarch64.sve.fp8.cvtn.nxv8bf16( %3, %4) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvtn.nxv8bf16(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvtn_f8_f16( %zn_zm.coerce0, %zn_zm.coerce1, i64 noundef %fpm) #0 { # | entry: # | %zn_zm = alloca { , }, align 16 # | %zn_zm.addr = alloca { , }, align 16 # | %fpm.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn_zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zn_zm.coerce1, 1 # | store { , } %1, ptr %zn_zm, align 16 # | %zn_zm1 = load { , }, ptr %zn_zm, align 16 # | store { , } %zn_zm1, ptr %zn_zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %2 = load { , }, ptr %zn_zm.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %5) # | %6 = call @llvm.aarch64.sve.fp8.cvtn.nxv8f16( %3, %4) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvtn.nxv8f16(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvtnb_f8_f32( %zn_zm.coerce0, %zn_zm.coerce1, i64 noundef %fpm) #0 { # | entry: # | %zn_zm = alloca { , }, align 16 # | %zn_zm.addr = alloca { , }, align 16 # | %fpm.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn_zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zn_zm.coerce1, 1 # | store { , } %1, ptr %zn_zm, align 16 # | %zn_zm1 = load { , }, ptr %zn_zm, align 16 # | store { , } %zn_zm1, ptr %zn_zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %2 = load { , }, ptr %zn_zm.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %5) # | %6 = call @llvm.aarch64.sve.fp8.cvtnb.nxv4f32( %3, %4) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvtnb.nxv4f32(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvtnt_f8_f32( %zd, %zn_zm.coerce0, %zn_zm.coerce1, i64 noundef %fpm) #0 { # | entry: # | %zn_zm = alloca { , }, align 16 # | %zd.addr = alloca , align 16 # | %zn_zm.addr = alloca { , }, align 16 # | %fpm.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn_zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zn_zm.coerce1, 1 # | store { , } %1, ptr %zn_zm, align 16 # | %zn_zm1 = load { , }, ptr %zn_zm, align 16 # | store %zd, ptr %zd.addr, align 16 # | store { , } %zn_zm1, ptr %zn_zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %2 = load , ptr %zd.addr, align 16 # | %3 = load { , }, ptr %zn_zm.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %6) # | %7 = call @llvm.aarch64.sve.fp8.cvtnt.nxv4f32( %2, %4, %5) # | ret %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvtnt.nxv4f32(, , ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp8,+sve,+sve2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055e9e845557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e9e8452515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e9e8455cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbf6e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbf6e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbf6e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbf6e631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e9e83eb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e9e83eb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e9e83cff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e9e807f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e9e807ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbf6e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbf6e6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbf6e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e9e807ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c (274 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sh_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv4i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sh_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv2i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sh_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sh_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sh_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv4i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sh_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv2i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sh_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv4i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sh_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv2i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005602814bc57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005602814b9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005602814bccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f70d8b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f70d8b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f70d8b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f70d8b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056028145224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560281452096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560281436f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005602810e6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005602810e5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f70d8b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f70d8b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f70d8b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005602810e5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c (275 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincd_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqincd.n32(i32 %0, i32 31, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqincd.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincd_n_s32_1(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqincd.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincd_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqincd.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqincd.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincd_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqincd.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqincd.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincd_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqincd.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uqincd.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincd_pat_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqincd.n32(i32 %0, i32 9, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincd_pat_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqincd.n64(i64 %0, i32 10, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincd_pat_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqincd.n32(i32 %0, i32 11, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincd_pat_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqincd.n64(i64 %0, i32 12, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqincd_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqincd.nxv2i64( %0, i32 31, i32 16) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqincd.nxv2i64(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqincd_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqincd.nxv2i64( %0, i32 31, i32 1) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqincd.nxv2i64(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqincd_pat_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqincd.nxv2i64( %0, i32 13, i32 16) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqincd_pat_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqincd.nxv2i64( %0, i32 29, i32 1) # | ret %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055d5278b457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d5278b1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d5278b4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f79d9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f79d9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f79d9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f79d9b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d52784a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d52784a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d52782ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d5274de176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d5274dde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f79d9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f79d9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f79d9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d5274ddd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c (276 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %o # | ... # `---data was truncated (10240/427567) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055658938e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055658938b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055658938ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f848ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f848eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f848ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f848ea31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055658932424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556589324096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556589308f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556588fb8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556588fb7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f848ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f848ea330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f848ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556588fb7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/X86/avx-shuffle-builtins.c (277 of 27911) ******************** TEST 'Clang :: CodeGen/X86/avx-shuffle-builtins.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c -triple=x86_64-- -target-feature +avx -disable-O0-optnone -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c -triple=x86_64-- -target-feature +avx -disable-O0-optnone -emit-llvm -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-unknown" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x float> @x(<8 x float> noundef %a, <8 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x float>, align 32 # | %b.addr = alloca <8 x float>, align 32 # | store <8 x float> %a, ptr %a.addr, align 32 # | store <8 x float> %b, ptr %b.addr, align 32 # | %0 = load <8 x float>, ptr %a.addr, align 32 # | %1 = load <8 x float>, ptr %b.addr, align 32 # | %shufp = shufflevector <8 x float> %0, <8 x float> %1, <8 x i32> # | ret <8 x float> %shufp # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_mm_permute_pd(<2 x double> noundef %a) #1 { # | entry: # | %a.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | %permil = shufflevector <2 x double> %0, <2 x double> poison, <2 x i32> # | ret <2 x double> %permil # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x double> @test_mm256_permute_pd(<4 x double> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x double>, align 32 # | store <4 x double> %a, ptr %a.addr, align 32 # | %0 = load <4 x double>, ptr %a.addr, align 32 # | %permil = shufflevector <4 x double> %0, <4 x double> poison, <4 x i32> # | ret <4 x double> %permil # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_mm_permute_ps(<4 x float> noundef %a) #1 { # | entry: # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %permil = shufflevector <4 x float> %0, <4 x float> poison, <4 x i32> # | ret <4 x float> %permil # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_mm_permute_ps2(<4 x float> noundef %a) #1 { # | entry: # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %permil = shufflevector <4 x float> %0, <4 x float> poison, <4 x i32> # | ret <4 x float> %permil # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x float> @test_mm256_permute_ps(<8 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x float>, align 32 # | store <8 x float> %a, ptr %a.addr, align 32 # | %0 = load <8 x float>, ptr %a.addr, align 32 # | %permil = shufflevector <8 x float> %0, <8 x float> poison, <8 x i32> # | ret <8 x float> %permil # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x double> @test_mm256_permute2f128_pd(<4 x double> noundef %a, <4 x double> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x double>, align 32 # | %b.addr = alloca <4 x double>, align 32 # | store <4 x double> %a, ptr %a.addr, align 32 # | store <4 x double> %b, ptr %b.addr, align 32 # | %0 = load <4 x double>, ptr %a.addr, align 32 # | %1 = load <4 x double>, ptr %b.addr, align 32 # | %vperm = shufflevector <4 x double> %0, <4 x double> %1, <4 x i32> # | ret <4 x double> %vperm # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x float> @test_mm256_permute2f128_ps(<8 x float> noundef %a, <8 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x float>, align 32 # | %b.addr = alloca <8 x float>, align 32 # | store <8 x float> %a, ptr %a.addr, align 32 # | store <8 x float> %b, ptr %b.addr, align 32 # | %0 = load <8 x float>, ptr %a.addr, align 32 # | %1 = load <8 x float>, ptr %b.addr, align 32 # | %vperm = shufflevector <8 x float> %1, <8 x float> %0, <8 x i32> # | ret <8 x float> %vperm # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i64> @test_mm256_permute2f128_si256(<4 x i64> noundef %a, <4 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i64>, align 32 # | %b.addr = alloca <4 x i64>, align 32 # | store <4 x i64> %a, ptr %a.addr, align 32 # | store <4 x i64> %b, ptr %b.addr, align 32 # | %0 = load <4 x i64>, ptr %a.addr, align 32 # | %1 = bitcast <4 x i64> %0 to <8 x i32> # | %2 = load <4 x i64>, ptr %b.addr, align 32 # | %3 = bitcast <4 x i64> %2 to <8 x i32> # | %vperm = shufflevector <8 x i32> %1, <8 x i32> %3, <8 x i32> # | %4 = bitcast <8 x i32> %vperm to <4 x i64> # | ret <4 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_mm_broadcast_ss(ptr noundef %__a) #1 { # | entry: # | %__a.addr.i = alloca ptr, align 8 # | %__f.i = alloca float, align 4 # | %.compoundliteral.i = alloca <4 x float>, align 16 # | %__a.addr = alloca ptr, align 8 # | store ptr %__a, ptr %__a.addr, align 8 # | %0 = load ptr, ptr %__a.addr, align 8 # | store ptr %0, ptr %__a.addr.i, align 8 # | %1 = load ptr, ptr %__a.addr.i, align 8 # | %2 = load float, ptr %1, align 1 # | store float %2, ptr %__f.i, align 4 # | %3 = load float, ptr %__f.i, align 4 # | %vecinit.i = insertelement <4 x float> poison, float %3, i32 0 # | %4 = load float, ptr %__f.i, align 4 # | %vecinit2.i = insertelement <4 x float> %vecinit.i, float %4, i32 1 # | %5 = load float, ptr %__f.i, align 4 # | %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %5, i32 2 # | %6 = load float, ptr %__f.i, align 4 # | %vecinit4.i = insertelement <4 x float> %vecinit3.i, float %6, i32 3 # | store <4 x float> %vecinit4.i, ptr %.compoundliteral.i, align 16 # | %7 = load <4 x float>, ptr %.compoundliteral.i, align 16 # | ret <4 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x double> @test_mm256_broadcast_sd(ptr noundef %__a) #0 { # | entry: # | %__a.addr.i = alloca ptr, align 8 # | %__d.i = alloca double, align 8 # | %.compoundliteral.i = alloca <4 x double>, align 32 # | %__a.addr = alloca ptr, align 8 # | store ptr %__a, ptr %__a.addr, align 8 # | %0 = load ptr, ptr %__a.addr, align 8 # | store ptr %0, ptr %__a.addr.i, align 8 # | %1 = load ptr, ptr %__a.addr.i, align 8 # | %2 = load double, ptr %1, align 1 # | store double %2, ptr %__d.i, align 8 # | %3 = load double, ptr %__d.i, align 8 # | %vecinit.i = insertelement <4 x double> poison, double %3, i32 0 # | %4 = load double, ptr %__d.i, align 8 # | %vecinit2.i = insertelement <4 x double> %vecinit.i, double %4, i32 1 # | %5 = load double, ptr %__d.i, align 8 # | %vecinit3.i = insertelement <4 x double> %vecinit2.i, double %5, i32 2 # | %6 = load double, ptr %__d.i, align 8 # | %vecinit4.i = insertelement <4 x double> %vecinit3.i, double %6, i32 3 # | store <4 x double> %vecinit4.i, ptr %.compoundliteral.i, align 32 # | %7 = load <4 x double>, ptr %.compoundliteral.i, align 32 # | ret <4 x double> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x float> @test_mm256_broadcast_ss(ptr noundef %__a) #0 { # | entry: # | %__a.addr.i = alloca ptr, align 8 # | %__f.i = alloca float, align 4 # | %.compoundliteral.i = alloca <8 x float>, align 32 # | %__a.addr = alloca ptr, align 8 # | store ptr %__a, ptr %__a.addr, align 8 # | %0 = load ptr, ptr %__a.addr, align 8 # | store ptr %0, ptr %__a.addr.i, align 8 # | %1 = load ptr, ptr %__a.addr.i, align 8 # | %2 = load float, ptr %1, align 1 # | store float %2, ptr %__f.i, align 4 # | %3 = load float, ptr %__f.i, align 4 # | %vecinit.i = insertelement <8 x float> poison, float %3, i32 0 # | %4 = load float, ptr %__f.i, align 4 # | %vecinit2.i = insertelement <8 x float> %vecinit.i, float %4, i32 1 # | %5 = load float, ptr %__f.i, align 4 # | %vecinit3.i = insertelement <8 x float> %vecinit2.i, float %5, i32 2 # | %6 = load float, ptr %__f.i, align 4 # | %vecinit4.i = insertelement <8 x float> %vecinit3.i, float %6, i32 3 # | %7 = load float, ptr %__f.i, align 4 # | %vecinit5.i = insertelement <8 x float> %vecinit4.i, float %7, i32 4 # | %8 = load float, ptr %__f.i, align 4 # | %vecinit6.i = insertelement <8 x float> %vecinit5.i, float %8, i32 5 # | %9 = load float, ptr %__f.i, align 4 # | %vecinit7.i = insertelement <8 x float> %vecinit6.i, float %9, i32 6 # | %10 = load float, ptr %__f.i, align 4 # | %vecinit8.i = insertelement <8 x float> %vecinit7.i, float %10, i32 7 # | store <8 x float> %vecinit8.i, ptr %.compoundliteral.i, align 32 # | %11 = load <8 x float>, ptr %.compoundliteral.i, align 32 # | ret <8 x float> %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x float> @test_mm256_insertf128_ps_0(<8 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x float>, align 32 # | %b.addr = alloca <4 x float>, align 16 # | store <8 x float> %a, ptr %a.addr, align 32 # | store <4 x float> %b, ptr %b.addr, align 16 # | %0 = load <8 x float>, ptr %a.addr, align 32 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | %widen = shufflevector <4 x float> %1, <4 x float> poison, <8 x i32> # | %insert = shufflevector <8 x float> %0, <8 x float> %widen, <8 x i32> # | ret <8 x float> %insert # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x double> @test_mm256_insertf128_pd_0(<4 x double> noundef %a, <2 x double> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x double>, align 32 # | %b.addr = alloca <2 x double>, align 16 # | store <4 x double> %a, ptr %a.addr, align 32 # | store <2 x double> %b, ptr %b.addr, align 16 # | %0 = load <4 x double>, ptr %a.addr, align 32 # | %1 = load <2 x double>, ptr %b.addr, align 16 # | %widen = shufflevector <2 x double> %1, <2 x double> poison, <4 x i32> # | %insert = shufflevector <4 x double> %0, <4 x double> %widen, <4 x i32> # | ret <4 x double> %insert # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i64> @test_mm256_insertf128_si256_0(<4 x i64> noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i64>, align 32 # | %b.addr = alloca <2 x i64>, align 16 # | store <4 x i64> %a, ptr %a.addr, align 32 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <4 x i64>, ptr %a.addr, align 32 # | %1 = bitcast <4 x i64> %0 to <8 x i32> # | %2 = load <2 x i64>, ptr # | ... # `---data was truncated (10240/21933) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e5d23e157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e5d23de515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e5d23e1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff3eef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff3eef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff3eef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff3eef1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e5d237724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e5d2377096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e5d235bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e5d200b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e5d200ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff3eef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff3eef1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff3eef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e5d200ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c (278 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacge_f16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.facge.nxv8f16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facge.nxv8f16(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacge_f32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.facge.nxv4f32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facge.nxv4f32(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacge_f64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.facge.nxv2f64( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facge.nxv2f64(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacge_n_f32( %pg, %op1, float noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca float, align 4 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store float %op2, ptr %op2.addr, align 4 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %.splatinsert = insertelement poison, float %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.facge.nxv4f32( %3, %1, %.splat) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacge_n_f64( %pg, %op1, double noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca double, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store double %op2, ptr %op2.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load double, ptr %op2.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %.splatinsert = insertelement poison, double %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.facge.nxv2f64( %3, %1, %.splat) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005572d350d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005572d350a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005572d350dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8bb8c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8bb8ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8bb8c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8bb8c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005572d34a324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005572d34a3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005572d3487f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005572d3137176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005572d3136e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8bb8c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8bb8c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8bb8c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005572d3136d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c (279 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmin_single_s8_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.smin.single.x2.nxv16i8( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.smin.single.x2.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmin_single_s16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.smin.single.x2.nxv8i16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.smin.single.x2.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmin_single_s32_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.smin.single.x2.nxv4i32( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.smin.single.x2.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmin_single_s64_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.smin.single.x2.nxv2i64( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.smin.single.x2.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmin_single_u8_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.umin.single.x2.nxv16i8( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.umin.single.x2.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmin_single_u16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.umin.single.x2.nxv8i16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.umin.single.x # | ... # `---data was truncated (10240/142195) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055678237f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055678237c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055678237fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe724905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe72495c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe724905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe7248ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055678231524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556782315096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005567822f9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556781fa9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556781fa8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe7248eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe7248ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe7248ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556781fa8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon-2velem.c (280 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon-2velem.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vmla_lane_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %v) #0 { # | entry: # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | %v.addr = alloca <4 x i16>, align 8 # | %__ret_72 = alloca <4 x i16>, align 8 # | %__s0_72 = alloca <4 x i16>, align 8 # | %__s1_72 = alloca <4 x i16>, align 8 # | %__s2_72 = alloca <4 x i16>, align 8 # | %__ret = alloca <4 x i16>, align 8 # | %__s0 = alloca <4 x i16>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x i16>, align 8 # | %tmp1 = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | store <4 x i16> %v, ptr %v.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__s0_72, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %1, ptr %__s1_72, align 8 # | %2 = load <4 x i16>, ptr %v.addr, align 8 # | store <4 x i16> %2, ptr %__s2_72, align 8 # | %3 = load <4 x i16>, ptr %__s0_72, align 8 # | %4 = load <4 x i16>, ptr %__s1_72, align 8 # | %5 = load <4 x i16>, ptr %__s2_72, align 8 # | store <4 x i16> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <4 x i16> # | %lane = shufflevector <4 x i16> %7, <4 x i16> %7, <4 x i32> # | store <4 x i16> %lane, ptr %ref.tmp, align 8 # | %8 = load <4 x i16>, ptr %ref.tmp, align 8 # | store <4 x i16> %8, ptr %__ret, align 8 # | %9 = load <4 x i16>, ptr %__ret, align 8 # | store <4 x i16> %9, ptr %tmp, align 8 # | %10 = load <4 x i16>, ptr %tmp, align 8 # | %mul = mul <4 x i16> %4, %10 # | %add = add <4 x i16> %3, %mul # | store <4 x i16> %add, ptr %__ret_72, align 8 # | %11 = load <4 x i16>, ptr %__ret_72, align 8 # | store <4 x i16> %11, ptr %tmp1, align 8 # | %12 = load <4 x i16>, ptr %tmp1, align 8 # | ret <4 x i16> %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vmlaq_lane_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, <4 x i16> noundef %v) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x i16>, align 16 # | %v.addr = alloca <4 x i16>, align 8 # | %__ret_62 = alloca <8 x i16>, align 16 # | %__s0_62 = alloca <8 x i16>, align 16 # | %__s1_62 = alloca <8 x i16>, align 16 # | %__s2_62 = alloca <4 x i16>, align 8 # | %__ret = alloca <8 x i16>, align 16 # | %__s0 = alloca <4 x i16>, align 8 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x i16>, align 16 # | %tmp1 = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | store <8 x i16> %b, ptr %b.addr, align 16 # | store <4 x i16> %v, ptr %v.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__s0_62, align 16 # | %1 = load <8 x i16>, ptr %b.addr, align 16 # | store <8 x i16> %1, ptr %__s1_62, align 16 # | %2 = load <4 x i16>, ptr %v.addr, align 8 # | store <4 x i16> %2, ptr %__s2_62, align 8 # | %3 = load <8 x i16>, ptr %__s0_62, align 16 # | %4 = load <8 x i16>, ptr %__s1_62, align 16 # | %5 = load <4 x i16>, ptr %__s2_62, align 8 # | store <4 x i16> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <4 x i16> # | %lane = shufflevector <4 x i16> %7, <4 x i16> %7, <8 x i32> # | store <8 x i16> %lane, ptr %ref.tmp, align 16 # | %8 = load <8 x i16>, ptr %ref.tmp, align 16 # | store <8 x i16> %8, ptr %__ret, align 16 # | %9 = load <8 x i16>, ptr %__ret, align 16 # | store <8 x i16> %9, ptr %tmp, align 16 # | %10 = load <8 x i16>, ptr %tmp, align 16 # | %mul = mul <8 x i16> %4, %10 # | %add = add <8 x i16> %3, %mul # | store <8 x i16> %add, ptr %__ret_62, align 16 # | %11 = load <8 x i16>, ptr %__ret_62, align 16 # | store <8 x i16> %11, ptr %tmp1, align 16 # | %12 = load <8 x i16>, ptr %tmp1, align 16 # | ret <8 x i16> %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vmla_lane_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <2 x i32> noundef %v) #0 { # | entry: # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <2 x i32>, align 8 # | %v.addr = alloca <2 x i32>, align 8 # | %__ret_70 = alloca <2 x i32>, align 8 # | %__s0_70 = alloca <2 x i32>, align 8 # | %__s1_70 = alloca <2 x i32>, align 8 # | %__s2_70 = alloca <2 x i32>, align 8 # | %__ret = alloca <2 x i32>, align 8 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x i32>, align 8 # | %tmp1 = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <2 x i32> %b, ptr %b.addr, align 8 # | store <2 x i32> %v, ptr %v.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__s0_70, align 8 # | %1 = load <2 x i32>, ptr %b.addr, align 8 # | store <2 x i32> %1, ptr %__s1_70, align 8 # | %2 = load <2 x i32>, ptr %v.addr, align 8 # | store <2 x i32> %2, ptr %__s2_70, align 8 # | %3 = load <2 x i32>, ptr %__s0_70, align 8 # | %4 = load <2 x i32>, ptr %__s1_70, align 8 # | %5 = load <2 x i32>, ptr %__s2_70, align 8 # | store <2 x i32> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x i32> # | %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> # | store <2 x i32> %lane, ptr %ref.tmp, align 8 # | %8 = load <2 x i32>, ptr %ref.tmp, align 8 # | store <2 x i32> %8, ptr %__ret, align 8 # | %9 = load <2 x i32>, ptr %__ret, align 8 # | store <2 x i32> %9, ptr %tmp, align 8 # | %10 = load <2 x i32>, ptr %tmp, align 8 # | %mul = mul <2 x i32> %4, %10 # | %add = add <2 x i32> %3, %mul # | store <2 x i32> %add, ptr %__ret_70, align 8 # | %11 = load <2 x i32>, ptr %__ret_70, align 8 # | store <2 x i32> %11, ptr %tmp1, align 8 # | %12 = load <2 x i32>, ptr %tmp1, align 8 # | ret <2 x i32> %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vmlaq_lane_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, <2 x i32> noundef %v) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 16 # | %b.addr = alloca <4 x i32>, align 16 # | %v.addr = alloca <2 x i32>, align 8 # | %__ret_60 = alloca <4 x i32>, align 16 # | %__s0_60 = alloca <4 x i32>, align 16 # | %__s1_60 = alloca <4 x i32>, align 16 # | %__s2_60 = alloca <2 x i32>, align 8 # | %__ret = alloca <4 x i32>, align 16 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <4 x i32>, align 16 # | %tmp1 = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | store <4 x i32> %b, ptr %b.addr, align 16 # | store <2 x i32> %v, ptr %v.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__s0_60, align 16 # | %1 = load <4 x i32>, ptr %b.addr, align 16 # | store <4 x i32> %1, ptr %__s1_60, align 16 # | %2 = load <2 x i32>, ptr %v.addr, align 8 # | store <2 x i32> %2, ptr %__s2_60, align 8 # | %3 = load <4 x i32>, ptr %__s0_60, align 16 # | %4 = load <4 x i32>, ptr %__s1_60, align 16 # | %5 = load <2 x i32>, ptr %__s2_60, align 8 # | store <2 x i32> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x i32> # | %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <4 x i32> # | store <4 x i32> %lane, ptr %ref.tmp, align 16 # | %8 = load <4 x i32>, ptr %ref.tmp, align 16 # | store <4 x i32> %8, ptr %__ret, align 16 # | %9 = load <4 x i32>, ptr %__ret, align 16 # | store <4 x i32> %9, ptr %tmp, align 16 # | %10 = load <4 x i32>, ptr %tmp, align 16 # | %mul = mul <4 x i32> %4, %10 # | %add = add <4 x i32> %3, %mul # | store <4 x i32> %add, ptr %__ret_60, align 16 # | %11 = load <4 x i32>, ptr %__ret_60, align 16 # | store <4 x i32> %11, ptr %tmp1, align 16 # | %12 = load <4 x i32>, ptr %tmp1, align 16 # | ret <4 x i32> %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vmla_laneq_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <8 x i16> noundef %v) #0 { # | entry: # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | %v.addr = alloca <8 x i16>, align 16 # | %__ret_482 = alloca <4 x i16>, align 8 # | %__s0_482 = alloca <4 x i16>, align 8 # | %__s1_482 = alloca <4 x i16>, align 8 # | %__s2_482 = alloca <8 x i16>, align 16 # | %__ret = alloca <4 x i16>, align 8 # | %__s0 = alloca <8 x i16>, align 16 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x i16>, align 8 # | %tmp1 = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %v, ptr %v.addr, align 16 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__s0_482, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %1, ptr %__s1_482, align 8 # | %2 = load <8 x i16>, ptr %v.addr, align 16 # | store <8 x i16> %2, ptr %__s2_482, align 16 # | %3 = load <4 x i16>, ptr %__s0_482, align 8 # | %4 = load <4 x i16>, ptr %__s1_482, align 8 # | %5 = load <8 x i16>, ptr %__s2_482, align 16 # | store <8 x i16> %5, ptr %__s0, align 16 # | %6 = load <16 x i8>, ptr %__s0, align 16 # | %7 = bitcast <16 x i8> %6 to <8 x i16> # | %lane = shufflevector <8 x i16> %7, <8 x i16> %7, <4 x i32> # | store <4 x i16> %lane, ptr %ref.tmp, align 8 # | %8 = load <4 x i16>, ptr %ref.tmp, align 8 # | store <4 x i16> %8, ptr %__ret, align 8 # | %9 = load <4 x i16>, ptr %__ret, align 8 # | store <4 x i16> %9, ptr %tmp, align 8 # | %10 = load <4 x i16>, ptr %tmp, align 8 # | %mul = mul <4 x i16> %4, %10 # | %add = add <4 x i16> %3, %mul # | store <4 x i16> %add, ptr %__ret_482, align 8 # | %11 = load <4 x i16>, ptr %__ret_482, align 8 # | store <4 x i16> %11, ptr %tmp1, align 8 # | %12 = load <4 x i16>, ptr %tmp1, align 8 # | ret <4 x i16> %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vmlaq_laneq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %v) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x i16>, align 16 # | %v.addr = alloca <8 x i16>, align 16 # | %__ret_472 = alloca <8 x i16>, align 16 # | %__s0_472 = alloca <8 x i16>, align 16 # | %__s1_472 = alloca <8 # | ... # `---data was truncated (10240/857511) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000557f708d657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557f708d3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557f708d6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f295fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f295fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f295fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f295fe31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557f7086c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557f7086c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557f70850f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557f70500176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557f704ffe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f295fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f295fe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f295fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557f704ffd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c (281 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpklo_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sunpklo.nxv8i16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sunpklo.nxv8i16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpklo_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sunpklo.nxv4i32( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sunpklo.nxv4i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpklo_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sunpklo.nxv2i64( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sunpklo.nxv2i64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpklo_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uunpklo.nxv8i16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uunpklo.nxv8i16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpklo_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uunpklo.nxv4i32( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uunpklo.nxv4i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpklo_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uunpklo.nxv2i64( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uunpklo.nxv2i64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpklo_b( %op) #0 { # | entry: # | %op.addr = alloca , align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %op.addr, align 2 # | %1 = call @llvm.aarch64.sve.punpklo.nxv16i1( %0) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.punpklo.nxv16i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055c6ef3d557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c6ef3d2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c6ef3d5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f19bf105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f19bf15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f19bf105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f19bf0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c6ef36b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c6ef36b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c6ef34ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c6eefff176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c6eeffee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f19bf0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f19bf0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f19bf0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c6eeffed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/arm-mfp8.c (282 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mfp8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -emit-llvm -triple aarch64-arm-none-eabi -target-feature -fp8 -target-feature +neon -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c --check-prefixes=CHECK-C # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -emit-llvm -triple aarch64-arm-none-eabi -target-feature -fp8 -target-feature +neon -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-arm-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_ret_mfloat8x16_t(<16 x i8> %v) #0 { # | entry: # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | ret <16 x i8> %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_ret_mfloat8x8_t(<8 x i8> %v) #0 { # | entry: # | %v.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %v, ptr %v.addr, align 8 # | %0 = load <8 x i8>, ptr %v.addr, align 8 # | ret <8 x i8> %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i8> @func1n(<1 x i8> %mfp8) #0 { # | entry: # | %mfp8.addr = alloca <1 x i8>, align 1 # | %f1n = alloca [10 x <1 x i8>], align 1 # | store <1 x i8> %mfp8, ptr %mfp8.addr, align 1 # | %0 = load <1 x i8>, ptr %mfp8.addr, align 1 # | %arrayidx = getelementptr inbounds [10 x <1 x i8>], ptr %f1n, i64 0, i64 2 # | store <1 x i8> %0, ptr %arrayidx, align 1 # | %arrayidx1 = getelementptr inbounds [10 x <1 x i8>], ptr %f1n, i64 0, i64 2 # | %1 = load <1 x i8>, ptr %arrayidx1, align 1 # | ret <1 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i8> @test_extract_element(<16 x i8> %x, i32 noundef %i) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 16 # | %i.addr = alloca i32, align 4 # | store <16 x i8> %x, ptr %x.addr, align 16 # | store i32 %i, ptr %i.addr, align 4 # | %0 = load <16 x i8>, ptr %x.addr, align 16 # | %1 = load i32, ptr %i.addr, align 4 # | %vecext = extractelement <16 x i8> %0, i32 %1 # | %mfp8ext = insertelement <1 x i8> poison, i8 %vecext, i64 0 # | ret <1 x i8> %mfp8ext # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_insert_element(<16 x i8> %x, i32 noundef %i, <1 x i8> %v) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 16 # | %i.addr = alloca i32, align 4 # | %v.addr = alloca <1 x i8>, align 1 # | store <16 x i8> %x, ptr %x.addr, align 16 # | store i32 %i, ptr %i.addr, align 4 # | store <1 x i8> %v, ptr %v.addr, align 1 # | %0 = load <1 x i8>, ptr %v.addr, align 1 # | %1 = load i32, ptr %i.addr, align 4 # | %2 = load <16 x i8>, ptr %x.addr, align 16 # | %3 = bitcast <1 x i8> %0 to i8 # | %vecins = insertelement <16 x i8> %2, i8 %3, i32 %1 # | store <16 x i8> %vecins, ptr %x.addr, align 16 # | %4 = load <16 x i8>, ptr %x.addr, align 16 # | ret <16 x i8> %4 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon,-fp8" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=mem2reg # | #0 0x000055c8595fb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c8595f8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c8595fbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdd00533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdd0058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdd00533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdd0051b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c85959124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c859591096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c859575f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c859225176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c859224e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fdd0051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdd0051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdd0051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c859224d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c --check-prefixes=CHECK-C # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c --check-prefixes=CHECK-C # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c (283 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmls_f16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmls.nxv8f16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmls.nxv8f16(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmls_f32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmls.nxv4f32( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmls.nxv4f32(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmls_f64_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmls.nxv2f64( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmls.nxv2f64(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmls_f16_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fnmls.nxv8f16( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmls_f32_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = call @llvm.aarch64.sve.fnmls.nxv4f32( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmls_f64_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = call @llvm.aarch64.sve.fnmls.nxv2f64( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmls_f16_x( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fnmls.u.nxv8f16( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind w # | ... # `---data was truncated (10240/26173) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055932a7e657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055932a7e3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055932a7e6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1105533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f110558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1105533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f110551b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055932a77c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055932a77c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055932a760f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055932a410176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055932a40fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f110551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f110551d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f110551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055932a40fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vbicq.c (284 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vbicq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vbicq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = xor <16 x i8> %1, splat (i8 -1) # | %3 = and <16 x i8> %0, %2 # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = xor <8 x i16> %1, splat (i16 -1) # | %3 = and <8 x i16> %0, %2 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = xor <4 x i32> %1, splat (i32 -1) # | %3 = and <4 x i32> %0, %2 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vbicq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = bitcast <4 x float> %2 to <4 x i32> # | %4 = xor <4 x i32> %3, splat (i32 -1) # | %5 = and <4 x i32> %1, %4 # | %6 = bitcast <4 x i32> %5 to <4 x float> # | ret <4 x float> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vbicq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.bic.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.bic.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vbicq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = bitcast <8 x half> %0 to <8 x i16> # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = bitcast <8 x half> %2 to <8 x i16> # | %4 = load i16, ptr %p.addr, align 2 # | %5 = zext i16 %4 to i32 # | %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5) # | %7 = load <8 x half>, ptr %inactive.addr, align 8 # | %8 = bitcast <8 x half> %7 to <8 x i16> # | %9 = call <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8) # | %10 = bitcast <8 x i16> %9 to <8 x half> # | ret <8 x half> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vbicq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.bic.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vbicq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = bitcast <4 x float> %2 to <4 x i32> # | %4 = load i16, ptr %p.addr # | ... # `---data was truncated (10240/11060) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005648fafb857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005648fafb5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005648fafb8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f08ac649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f08ac6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f08ac649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f08ac631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005648faf4e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005648faf4e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005648faf32f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005648fabe2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005648fabe1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f08ac632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f08ac6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f08ac6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005648fabe1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c (285 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_u8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq1.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_u16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq1.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_u32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq1.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_u64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq1.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_s8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_s16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_s32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_s64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_f16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq1.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_f32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq1.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_f64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq1.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_bf16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq1.nxv8bf16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_mf8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv16i8( %0, %1) # | ret % # | ... # `---data was truncated (10240/10910) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055a0ef9f157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a0ef9ee515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a0ef9f1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2292e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2292ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2292e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2292e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a0ef98724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a0ef987096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a0ef96bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a0ef61b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a0ef61ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2292e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2292e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2292e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a0ef61ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c (286 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_single_x1_s8(i32 noundef %slice_base, %zn, %zm) #0 { # | entry: # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load i32, ptr %slice_base.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.smla.za32.single.vg4x1.nxv16i8(i32 %0, %1, %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smla.za32.single.vg4x1.nxv16i8(i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_single_x1_s16(i32 noundef %slice_base, %zn, %zm) #0 { # | entry: # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load i32, ptr %slice_base.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.smla.za64.single.vg4x1.nxv8i16(i32 %0, %1, %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smla.za64.single.vg4x1.nxv8i16(i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_uvmlal_single_x1_u8(i32 noundef %slice_base, %zn, %zm) #0 { # | entry: # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load i32, ptr %slice_base.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.umla.za32.single.vg4x1.nxv16i8(i32 %0, %1, %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umla.za32.single.vg4x1.nxv16i8(i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_uvmlal_single_x1_u16(i32 noundef %slice_base, %zn, %zm) #0 { # | entry: # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load i32, ptr %slice_base.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.umla.za64.single.vg4x1.nxv8i16(i32 %0, %1, %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umla.za64.single.vg4x1.nxv8i16(i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls_single_x1_s8(i32 noundef %slice_base, %zn, %zm) #0 { # | entry: # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load i32, ptr %slice_base.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.smls.za32.single.vg4x1.nxv16i8(i32 %0, %1, %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smls.za32.single.vg4x1.nxv16i8(i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls_single_x1_s16(i32 noundef %slice_base, %zn, %zm) #0 { # | entry: # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load i32, ptr %slice_base.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.smls.za64.single.vg4x1.nxv8i16(i32 %0, %1, %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smls.za64.single.vg4x1.nxv8i16(i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_uvmlsl_single_x1_u8(i32 noundef %slice_base, %zn, %zm) #0 { # | entry: # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load i32, ptr %slice_base.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.umls.za32.single.vg4x1.nxv16i8(i32 %0, %1, %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umls.za32.single.vg4x1.nxv16i8(i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_uvmlsl_single_x1_u16(i32 noundef %slice_base, %zn, %zm) #0 { # | entry: # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load i32, ptr %slice_base.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.umls.za64.single.vg4x1.nxv8i16(i32 %0, %1, %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umls.za64.single.vg4x1.nxv8i16(i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_sumlall_single_x1_s8(i32 noundef %slice_base, %zn, %zm) #0 { # | entry: # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load i32, ptr %slice_base.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.usmla.za32.single.vg4x1.nxv16i8(i32 %0, %2, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.usmla.za32.single.vg4x1.nxv16i8(i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_usmlall_single_x1_u8(i32 noundef %slice_base, %zn, %zm) #0 { # | entry: # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load i32, ptr %slice_base.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.usmla.za32.single.vg4x1.nxv16i8(i32 %0, %1, %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_single_x2_s8(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | # | ... # `---data was truncated (10240/178306) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005585db58b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005585db588515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005585db58bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7d9a305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7d9a35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7d9a305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7d9a2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005585db52124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005585db521096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005585db505f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005585db1b5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005585db1b4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7d9a2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7d9a2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7d9a2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005585db1b4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c (287 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_b() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_b() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | !llvm.errno.tbaa = !{!4} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # | !4 = !{!5, !6, i64 0} # | !5 = !{!"__libc_errno", !6, i64 0} # | !6 = !{!"int", !7, i64 0} # | !7 = !{!"omnipotent char", !8, i64 0} # | !8 = !{!"Simple C/C++ TBAA"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055b8a1f8857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b8a1f85515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b8a1f88cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe7f8733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe7f878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe7f8733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe7f871b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b8a1f1e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b8a1f1e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b8a1f02f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b8a1bb2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b8a1bb1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe7f871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe7f871d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe7f871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b8a1bb1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c (288 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpgt_s8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmpgt.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpgt.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpgt_s16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmpgt.nxv8i16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpgt.nxv8i16(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpgt_s32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmpgt.nxv4i32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpgt.nxv4i32(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpgt_s64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.cmpgt.nxv2i64( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpgt.nxv2i64(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpgt_u8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmphi.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphi.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpgt_u16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmphi.nxv8i16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphi.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpgt_u32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmphi.nxv4i32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphi.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpgt_u64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, # | ... # `---data was truncated (10240/41923) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055bdbfb5d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bdbfb5a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bdbfb5dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcf50533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcf5058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcf50533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcf5051b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bdbfaf324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bdbfaf3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bdbfad7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bdbf787176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bdbf786e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcf5051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcf5051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcf5051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bdbf786d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/2005-09-24-AsmUserPrefix.c (289 of 27911) ******************** TEST 'Clang :: CodeGen/2005-09-24-AsmUserPrefix.c' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-09-24-AsmUserPrefix.c -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 | llc | not grep _foo2 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-09-24-AsmUserPrefix.c -emit-llvm -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-09-24-AsmUserPrefix.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-09-24-AsmUserPrefix.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @bar() #0 { # | entry: # | call void @foo2() # | ret void # | } # | # | declare void @foo2() #1 # | # | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 # | #0 0x0000561273fb757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561273fb4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561273fb7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5bf8b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5bf8b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5bf8b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5bf8b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561273f4d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561273f4d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561273f31f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561273be1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561273be0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5bf8b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5bf8b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5bf8b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561273be0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: llc # executed command: not grep _foo2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c (290 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | # | ... # `---data was truncated (10240/424835) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fab8d1d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fab8d1a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fab8d1dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f867f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f867f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f867f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f867f231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fab8cb324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fab8cb3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fab8c97f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fab8947176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fab8946e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f867f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f867f2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f867f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fab8946d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c (291 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv4i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv2i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv4i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv2i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv4i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv2i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_gather_u32base_s32( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32( %2, %1, i64 0) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32(, , i64) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_gather_u64base_s64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64( %2, %1, i64 0) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64(, , i64) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_gather_u32base_u32( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.a # | ... # `---data was truncated (10240/36974) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x0000555b197ab57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555b197a8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555b197abcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f73ddb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f73ddb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f73ddb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f73ddb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555b1974124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555b19741096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555b19725f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555b193d5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555b193d4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f73ddb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f73ddb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f73ddb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555b193d4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c (292 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdech_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdech.n32(i32 %0, i32 31, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqdech.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdech_n_s32_1(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdech.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdech_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqdech.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqdech.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdech_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqdech.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqdech.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdech_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqdech.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uqdech.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdech_pat_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdech.n32(i32 %0, i32 10, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdech_pat_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqdech.n64(i64 %0, i32 11, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdech_pat_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqdech.n32(i32 %0, i32 12, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdech_pat_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqdech.n64(i64 %0, i32 13, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdech_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqdech.nxv8i16( %0, i32 31, i32 16) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqdech.nxv8i16(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdech_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqdech.nxv8i16( %0, i32 31, i32 1) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqdech.nxv8i16(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdech_pat_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqdech.nxv8i16( %0, i32 29, i32 16) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdech_pat_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqdech.nxv8i16( %0, i32 30, i32 1) # | ret %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056110fc9757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056110fc94515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056110fc97cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f630df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f630df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f630df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f630df1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056110fc2d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056110fc2d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056110fc11f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056110f8c1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056110f8c0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f630df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f630df1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f630df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056110f8c0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c (293 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_lane_za16_vg2x1(i32 noundef %slice, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store i32 %slice, ptr %slice.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x1(i32 %0, %1, %2, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x1(i32, , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_lane_za16_vg2x2(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zm, i64 noundef %fpm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice, ptr %slice.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %2 = load i32, ptr %slice.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | %7 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x2(i32 %2, %4, %5, %6, i32 15) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x2(i32, , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_lane_za16_vg2x4(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm, i64 noundef %fpm) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store i32 %slice, ptr %slice.addr, align 4 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %4 = load i32, ptr %slice.addr, align 4 # | %5 = load { , , , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , , , } %5, 0 # | %7 = extractvalue { , , , } %5, 1 # | %8 = extractvalue { , , , } %5, 2 # | %9 = extractvalue { , , , } %5, 3 # | %10 = load , ptr %zm.addr, align 16 # | %11 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %11) # | call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x4(i32 %4, %6, %7, %8, %9, %10, i32 7) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x4(i32, , , , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_lane_za32_vg4x1(i32 noundef %slice, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store i32 %slice, ptr %slice.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | call void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x1(i32 %0, %1, %2, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x1(i32, , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_lane_za32_vg4x2(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zm, i64 noundef %fpm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice, ptr %slice.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %2 = load i32, ptr %slice.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | %7 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | call void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x2(i32 %2, %4, %5, %6, i32 15) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x2(i32, , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_lane_za32_vg4x4(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm, i64 noundef %fpm) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | %0 # | ... # `---data was truncated (10240/39820) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x00005619c520e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005619c520b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005619c520ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f70bc533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f70bc58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f70bc533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f70bc51b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005619c51a424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005619c51a4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005619c5188f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005619c4e38176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005619c4e37e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f70bc51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f70bc51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f70bc51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005619c4e37d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c (294 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrw_u32base_s32index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrw.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.adrw.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrw_u64base_s64index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrw.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.adrw.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrw_u32base_u32index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrw.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrw_u64base_u64index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrw.nxv2i64( %0, %1) # | ret %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056050364d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056050364a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056050364dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f927fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f927faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f927fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f927fa31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005605035e324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005605035e3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005605035c7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560503277176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560503276e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f927fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f927fa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f927fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560503276d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c (295 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/296943) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b3f872b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b3f8728515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b3f872bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdec1649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdec16a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdec1649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdec1631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b3f86c124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b3f86c1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b3f86a5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b3f8355176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b3f8354e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fdec1632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdec16330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdec16330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b3f8354d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c (296 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svadd_vector_single2_s8( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.add.single.x2.nxv16i8( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.add.single.x2.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svadd_vector_single2_u8( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.add.single.x2.nxv16i8( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svadd_vector_single2_s16( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.add.single.x2.nxv8i16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.add.single.x2.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svadd_vector_single2_u16( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.add.single.x2.nxv8i16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svadd_vector_single2_s32( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.add.single.x2.nxv4i32( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.add.single.x2.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svadd_vector_single2_u32( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.add.single.x2.nxv4i32( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svadd_vector_single2_s64( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c (297 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_s8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ldnt1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ldnt1.nxv16i8.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldnt1.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ldnt1.nxv8i16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnt1.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ldnt1.nxv4i32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnt1.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ldnt1.nxv2i64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_u8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ldnt1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldnt1.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnt1.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnt1.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_f16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldnt1.nxv8f16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ldnt1.nxv8f16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_f32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnt1.nxv4f32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ldnt1.nxv4f32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_f64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnt1.nxv2f64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ldnt1.nxv2f64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_mf8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ldnt1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_vnum_s8( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %b # | ... # `---data was truncated (10240/22231) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055f93dfb257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f93dfaf515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f93dfb2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc54c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc54c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc54c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc54c31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f93df4824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f93df48096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f93df2cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f93dbdc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f93dbdbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc54c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc54c31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc54c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f93dbdbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c (298 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, pt # | ... # `---data was truncated (10240/174721) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562054b4c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562054b49515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562054b4ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff3f5f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff3f5f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff3f5f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff3f5f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562054ae224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562054ae2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562054ac6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562054776176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562054775e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff3f5f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff3f5f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff3f5f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562054775d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/minv.c (299 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve/minv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svminv_s8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.sminv.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i8 @llvm.aarch64.sve.sminv.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svminv_s16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.sminv.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.aarch64.sve.sminv.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svminv_s32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.sminv.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sminv.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svminv_s64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.sminv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sminv.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svminv_u8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.uminv.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i8 @llvm.aarch64.sve.uminv.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svminv_u16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.uminv.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.aarch64.sve.uminv.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svminv_u32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.uminv.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uminv.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svminv_u64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.uminv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uminv.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local half @test_svminv_f16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call half @llvm.aarch64.sve.fminv.nxv8f16( %2, %1) # | ret half %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.aarch64.sve.fminv.nxv8f16(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local float @test_svminv_f32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call float @llvm.aarch64.sve.fminv.nxv4f32( %2, %1) # | ret float %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.aarch64.sve.fminv.nxv4f32(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local double @test_svminv_f64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call double @llvm.aarch64.sve.fminv.nxv2f64( %2, %1) # | ret double %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.aarch64.sve.fminv.nxv2f64(, ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attribute # | ... # `---data was truncated (10240/10818) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x0000559bbefa557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559bbefa2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559bbefa5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f24a2049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f24a20a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f24a2049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f24a2031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559bbef3b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559bbef3b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559bbef1ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559bbebcf176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559bbebcee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f24a2032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f24a20330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f24a20330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559bbebced81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c (300 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1q_gather_u64base_offset_u64( %pg, %base, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = call @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2i64.nxv2i64( %3, %1, i64 %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2i64.nxv2i64(, , i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv1i1() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1q_gather_u64base_offset_s64( %pg, %base, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = call @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2i64.nxv2i64( %3, %1, i64 %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1q_gather_u64base_offset_u32( %pg, %base, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = call @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv4i32.nxv2i64( %3, %1, i64 %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv4i32.nxv2i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1q_gather_u64base_offset_s32( %pg, %base, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = call @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv4i32.nxv2i64( %3, %1, i64 %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1q_gather_u64base_offset_u16( %pg, %base, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = call @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv8i16.nxv2i64( %3, %1, i64 %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv8i16.nxv2i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1q_gather_u64base_offset_s16( %pg, %base, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = call @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv8i16.nxv2i64( %3, %1, i64 %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1q_gather_u64base_offset_u8( %pg, %base, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = call @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv16i8.nxv2i64( %3, %1, i64 %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv16i8.nxv2i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1q_gather_u64base_offset_s8( %pg, %base, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = call @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv16i8.nxv2i64( %3, %1, i64 %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1q_gather_u64base_offset_f64( %pg, %base, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = call @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2f64.nxv2i64( %3, %1, i64 %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2f64.nxv2i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1q_gather_u64base_offset_f32( %pg, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c (301 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i1 @test_svptest_any( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call i1 @llvm.aarch64.sve.ptest.any.nxv16i1( %0, %1) # | ret i1 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i1 @llvm.aarch64.sve.ptest.any.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i1 @test_svptest_first( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call i1 @llvm.aarch64.sve.ptest.first.nxv16i1( %0, %1) # | ret i1 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i1 @llvm.aarch64.sve.ptest.first.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i1 @test_svptest_last( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call i1 @llvm.aarch64.sve.ptest.last.nxv16i1( %0, %1) # | ret i1 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i1 @llvm.aarch64.sve.ptest.last.nxv16i1(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005641cb08f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005641cb08c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005641cb08fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7c23849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7c238a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7c23849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7c23831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005641cb02524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005641cb025096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005641cb009f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005641cacb9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005641cacb8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7c23832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7c238330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7c238330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005641cacb8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c (302 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv8i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv8i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv4i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv2i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv8i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_vnum_s16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv8i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv4i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv2i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_vnum_u16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv8i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv4i8.p0( %3, ptr %4) # | %6 = zext ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c (303 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_lane_bf16_idx1( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmls.lane.nxv8bf16( %0, %1, %2, i32 1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmls.lane.nxv8bf16(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_lane_bf16_idx3( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmls.lane.nxv8bf16( %0, %1, %2, i32 3) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_lane_bf16_idx7( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmls.lane.nxv8bf16( %0, %1, %2, i32 7) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16b16,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000558b3404c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558b34049515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558b3404ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2e9d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2e9d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2e9d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2e9d031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558b33fe224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558b33fe2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558b33fc6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558b33c76176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558b33c75e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2e9d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2e9d0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2e9d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558b33c75d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c (304 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_s8( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_s16( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_s32( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_s64( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_u8( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_u16( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_u32( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_u64( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_f16( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_f32( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_f64( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_mf8( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_bf16( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c (305 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_u8( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.uclamp.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uclamp.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_u16( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.uclamp.nxv8i16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uclamp.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_u32( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.uclamp.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uclamp.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_u64( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.uclamp.nxv2i64( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uclamp.nxv2i64(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005645c449a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005645c4497515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005645c449acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8224a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8224aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8224a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8224a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005645c443024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005645c4430096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005645c4414f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005645c40c4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005645c40c3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8224a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8224a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8224a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005645c40c3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGenCXX/aarch64-sve-vector-conditional-op.cpp (306 of 27911) ******************** TEST 'Clang :: CodeGenCXX/aarch64-sve-vector-conditional-op.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z9cond_boolu10__SVBool_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 2 # | %b.addr = alloca , align 2 # | store %a, ptr %a.addr, align 2 # | store %b, ptr %b.addr, align 2 # | %0 = load , ptr %a.addr, align 2 # | %1 = load , ptr %b.addr, align 2 # | %cmp = icmp ult %0, %1 # | %2 = load , ptr %a.addr, align 2 # | %3 = load , ptr %b.addr, align 2 # | %vector_select = select %cmp, %2, %3 # | ret %vector_select # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z7cond_i8u10__SVInt8_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp slt %0, %1 # | %sext = sext %cmp to # | %2 = load , ptr %a.addr, align 16 # | %3 = load , ptr %b.addr, align 16 # | %vector_cond = icmp ne %sext, zeroinitializer # | %vector_select = select %vector_cond, %2, %3 # | ret %vector_select # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z7cond_u8u11__SVUint8_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp ult %0, %1 # | %sext = sext %cmp to # | %2 = load , ptr %a.addr, align 16 # | %3 = load , ptr %b.addr, align 16 # | %vector_cond = icmp ne %sext, zeroinitializer # | %vector_select = select %vector_cond, %2, %3 # | ret %vector_select # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z8cond_i16u11__SVInt16_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp slt %0, %1 # | %sext = sext %cmp to # | %2 = load , ptr %a.addr, align 16 # | %3 = load , ptr %b.addr, align 16 # | %vector_cond = icmp ne %sext, zeroinitializer # | %vector_select = select %vector_cond, %2, %3 # | ret %vector_select # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z8cond_u16u12__SVUint16_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp ult %0, %1 # | %sext = sext %cmp to # | %2 = load , ptr %a.addr, align 16 # | %3 = load , ptr %b.addr, align 16 # | %vector_cond = icmp ne %sext, zeroinitializer # | %vector_select = select %vector_cond, %2, %3 # | ret %vector_select # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z8cond_i32u11__SVInt32_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp slt %0, %1 # | %sext = sext %cmp to # | %2 = load , ptr %a.addr, align 16 # | %3 = load , ptr %b.addr, align 16 # | %vector_cond = icmp ne %sext, zeroinitializer # | %vector_select = select %vector_cond, %2, %3 # | ret %vector_select # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z8cond_u32u12__SVUint32_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp ult %0, %1 # | %sext = sext %cmp to # | %2 = load , ptr %a.addr, align 16 # | %3 = load , ptr %b.addr, align 16 # | %vector_cond = icmp ne %sext, zeroinitializer # | %vector_select = select %vector_cond, %2, %3 # | ret %vector_select # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z8cond_i64u11__SVInt64_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp slt %0, %1 # | %sext = sext %cmp to # | %2 = load , ptr %a.addr, align 16 # | %3 = load , ptr %b.addr, align 16 # | %vector_cond = icmp ne %sext, zeroinitializer # | %vector_select = select %vector_cond, %2, %3 # | ret %vector_select # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z8cond_u64u12__SVUint64_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp ult %0, %1 # | %sext = sext %cmp to # | %2 = load , ptr %a.addr, align 16 # | %3 = load , ptr %b.addr, align 16 # | %vector_cond = icmp ne %sext, zeroinitializer # | %vector_select = select %vector_cond, %2, %3 # | ret %vector_select # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z8cond_f16u13__SVFloat16_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = fcmp olt %0, %1 # | %sext = sext %cmp to # | %2 = load , ptr %a.addr, align 16 # | %3 = load , ptr %b.addr, align 16 # | %vector_cond = icmp ne %sext, zeroinitializer # | %vector_select = select %vector_cond, %2, %3 # | ret %vector_select # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z8cond_f32u13__SVFloat32_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = fcmp olt %0, %1 # | %sext = sext %cmp to # | %2 = load , ptr %a.addr, align 16 # | %3 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c (307 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 3) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { ta # | ... # `---data was truncated (10240/27858) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555ccf2bb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555ccf2b8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555ccf2bbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9512505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f951255c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9512505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f95124ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555ccf25124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555ccf251096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555ccf235f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555cceee5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555cceee4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f95124eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f95124ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f95124ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555cceee4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c (308 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8mf8x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8mf4x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_u8mf8x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_u8mf4x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_u8mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_u8m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8mf8x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8mf4x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask. # | ... # `---data was truncated (10240/18972) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056493371a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564933717515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056493371acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f53a221bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f53a22725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f53a221ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f53a2203507 abort ./stdlib/abort.c:85:3 # | #7 0x00005649336b024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005649336b0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564933694f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564933344176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564933343e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f53a2204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f53a22050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f53a22050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564933343d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c (309 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_s16_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_s16_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_s16_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_u16_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.fcvtzu.nxv8i16.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcvtzu.nxv8i16.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_u16_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.fcvtzu.nxv8i16.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_u16_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.fcvtzu.nxv8i16.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_s32_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.fcvtzs.i32f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcvtzs.i32f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_s32_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.fcvtzs.nxv4i32.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcvtzs.nxv4i32.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_s32_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.fcvtzs.i32f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcvtzs.i32f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_s32_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.fcvtzs.i32f16( %0, %3, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c (310 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincw_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqincw.n32(i32 %0, i32 31, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqincw.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincw_n_s32_1(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqincw.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincw_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqincw.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqincw.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincw_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqincw.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqincw.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincw_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqincw.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uqincw.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincw_pat_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqincw.n32(i32 %0, i32 4, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincw_pat_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqincw.n64(i64 %0, i32 5, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincw_pat_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqincw.n32(i32 %0, i32 6, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincw_pat_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqincw.n64(i64 %0, i32 7, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqincw_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqincw.nxv4i32( %0, i32 31, i32 16) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqincw.nxv4i32(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqincw_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqincw.nxv4i32( %0, i32 31, i32 1) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqincw.nxv4i32(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqincw_pat_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqincw.nxv4i32( %0, i32 8, i32 16) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqincw_pat_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqincw.nxv4i32( %0, i32 9, i32 1) # | ret %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055aca3df657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055aca3df3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055aca3df6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5af6249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5af62a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5af6249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5af6231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aca3d8c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055aca3d8c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055aca3d70f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055aca3a20176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055aca3a1fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5af6232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5af62330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5af62330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aca3a1fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c (311 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16mf4_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m4_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m8_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f32mf2_f64m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f32m1_f64m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca # | ... # `---data was truncated (10240/60342) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005640d1d4457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005640d1d41515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005640d1d44cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffaaa333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffaaa38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffaaa333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffaaa31b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005640d1cda24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005640d1cda096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005640d1cbef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005640d196e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005640d196de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ffaaa31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffaaa31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffaaa31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005640d196dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c (312 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m1( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m8( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf4_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf2_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m1_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.mask.nxv4f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.mask.nxv4f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m2_m( %mask, %op1, float noun # | ... # `---data was truncated (10240/25091) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005563822ee57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005563822eb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005563822eecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f574c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f574c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f574c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f574c11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055638228424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556382284096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556382268f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556381f18176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556381f17e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f574c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f574c11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f574c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556381f17d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c (313 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_bf16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmul.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmul.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_bf16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmul.nxv8bf16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_bf16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmul.u.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmul.u.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_bf16_n_m( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fmul.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_bf16_n_z( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmul.nxv8bf16( %3, %4, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_bf16_n_x( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fmul.u.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000564318e8457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564318e81515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564318e84cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efc6481bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efc648725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efc6481ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efc64803507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564318e1a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564318e1a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564318dfef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564318aae176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564318aade93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efc64804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efc648050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efc648050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564318aadd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c (314 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve-f16f32mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve-f16f32mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_f32f16( %acc, %a, %b) #0 { # | entry: # | %acc.addr = alloca , align 16 # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %acc, ptr %acc.addr, align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %acc.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %2 = load , ptr %b.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmmla.nxv4f32.nxv8f16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmmla.nxv4f32.nxv8f16(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-f16f32mm" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000561425be357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561425be0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561425be3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6376733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f637678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6376733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f637671b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561425b7924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561425b79096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561425b5df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056142580d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056142580ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f637671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f637671d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f637671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056142580cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c (315 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-f8f32 -target-feature +sme-f8f16 -target-feature +sme-mop4 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-f8f32 -target-feature +sme-f8f16 -target-feature +sme-mop4 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x1_za16_mf8_mf8_fpm( %zn, %zm, i64 noundef %fpmr) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %2) # | call void @llvm.aarch64.sme.fp8.fmop4a.za16.1x1.nxv16i8(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmop4a.za16.1x1.nxv16i8(i32 immarg, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x2_za16_mf8_mf8_fpm( %zn, %zm.coerce0, %zm.coerce1, i64 noundef %fpmr) #0 { # | entry: # | %zm = alloca { , }, align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca { , }, align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zm.coerce1, 1 # | store { , } %1, ptr %zm, align 16 # | %zm1 = load { , }, ptr %zm, align 16 # | store %zn, ptr %zn.addr, align 16 # | store { , } %zm1, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load { , }, ptr %zm.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %6) # | call void @llvm.aarch64.sme.fp8.fmop4a.za16.1x2.nxv16i8(i32 1, %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmop4a.za16.1x2.nxv16i8(i32 immarg, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_2x1_za16_mf8_mf8_fpm( %zn.coerce0, %zn.coerce1, %zm, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %6) # | call void @llvm.aarch64.sme.fp8.fmop4a.za16.2x1.nxv16i8(i32 1, %3, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmop4a.za16.2x1.nxv16i8(i32 immarg, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_2x2_za16_mf8_mf8_fpm( %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %4 = load { , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | %10 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %10) # | call void @llvm.aarch64.sme.fp8.fmop4a.za16.2x2.nxv16i8(i32 1, %5, %6, %8, %9) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmop4a.za16.2x2.nxv16i8(i32 immarg, , , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x1_za32_mf8_mf8_fpm( %zn, %zm, i64 noundef %fpmr) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %2) # | call void @llvm.aarch64.sme.fp8.fmop4a.za32.1x1.nxv16i8(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmop4a.za32.1x1.nxv16i8(i32 immarg, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x2_za32_mf8_mf8_fpm( %zn, %zm.coerce0, %zm.coerce1, i64 noundef %fpmr) #0 { # | entry: # | %zm = alloca { , }, align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca { , }, align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zm.coerce1, 1 # | store { , } %1, ptr %zm, align 16 # | %zm1 = load { , }, ptr %zm, align 16 # | store %zn, ptr %zn.addr, align 16 # | store { , } %zm1, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load { , }, ptr %zm.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %6) # | call void @llvm.aarch64.sme.fp8.fmop4a.za32.1x2.nxv16i8(i32 1, %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmop4a.za32.1x2.nxv16i8(i32 immarg, , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c (316 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x1_za32_s8_s8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.smop4a.wide.1x1.nxv16i8(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smop4a.wide.1x1.nxv16i8(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_1x1_za32_s8_s8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.smop4s.wide.1x1.nxv16i8(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smop4s.wide.1x1.nxv16i8(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x1_za32_u8_u8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.umop4a.wide.1x1.nxv16i8(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umop4a.wide.1x1.nxv16i8(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_1x1_za32_u8_u8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.umop4s.wide.1x1.nxv16i8(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umop4s.wide.1x1.nxv16i8(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x1_za32_s8_u8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.sumop4a.wide.1x1.nxv16i8(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.sumop4a.wide.1x1.nxv16i8(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_1x1_za32_s8_u8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.sumop4s.wide.1x1.nxv16i8(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.sumop4s.wide.1x1.nxv16i8(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x1_za32_u8_s8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.usmop4a.wide.1x1.nxv16i8(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.usmop4a.wide.1x1.nxv16i8(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_1x1_za32_u8_s8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.usmop4s.wide.1x1.nxv16i8(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.usmop4s.wide.1x1.nxv16i8(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x1_za32_s16_s16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.smop4a.wide.1x1.nxv8i16(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smop4a.wide.1x1.nxv8i16(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_1x1_za32_s16_s16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.smop4s.wide.1x1.nxv8i16(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smop4s.wide.1x1.nxv8i16(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x1_za32_u16_u16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.umop4a.wide.1x1.nxv8i16(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umop4a.wide.1x1.nxv8i16(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_1x1_za32_u16_u16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.umop4s.wide.1x1.nxv8i16(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umop4s.wide.1x1.nxv8i16(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x1_za32_f16_f16( # | ... # `---data was truncated (10240/27272) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055bf59ed057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bf59ecd515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bf59ed0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6627049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f66270a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6627049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6627031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bf59e6624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bf59e66096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bf59e4af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bf59afa176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bf59af9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6627032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f66270330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f66270330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bf59af9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c (317 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsplice_s8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.splice.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.splice.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsplice_s16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.splice.nxv8i16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.splice.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsplice_s32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.splice.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.splice.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsplice_s64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.splice.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.splice.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsplice_u8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.splice.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsplice_u16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.splice.nxv8i16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsplice_u32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.splice.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsplice_u64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.splice.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsplice_f16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.splice.nxv8f16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.splice.nxv8f16(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c (318 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/87892) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555ffef8d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555ffef8a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555ffef8dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa038d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa038d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa038d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa038d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555ffef2324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555ffef23096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555ffef07f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555ffebb7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555ffebb6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa038d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa038d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa038d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555ffebb6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c (319 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabd_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.sabd.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sabd.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabd_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sabd.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sabd.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabd_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sabd.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sabd.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabd_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sabd.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sabd.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabd_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.uabd.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uabd.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabd_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.uabd.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uabd.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabd_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.uabd.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uabd.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabd_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c (320 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst3_s8( %pg, ptr noundef %base, %data.coerce0, %data.coerce1, %data.coerce2) #0 { # | entry: # | %data = alloca { , , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %data.coerce0, 0 # | %1 = insertvalue { , , } %0, %data.coerce1, 1 # | %2 = insertvalue { , , } %1, %data.coerce2, 2 # | store { , , } %2, ptr %data, align 16 # | %data1 = load { , , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , , } %data1, ptr %data.addr, align 16 # | %3 = load , ptr %pg.addr, align 2 # | %4 = load ptr, ptr %base.addr, align 8 # | %5 = load { , , }, ptr %data.addr, align 16 # | %6 = extractvalue { , , } %5, 0 # | %7 = extractvalue { , , } %5, 1 # | %8 = extractvalue { , , } %5, 2 # | call void @llvm.aarch64.sve.st3.nxv16i8.p0( %6, %7, %8, %3, ptr %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st3.nxv16i8.p0(, , , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst3_s16( %pg, ptr noundef %base, %data.coerce0, %data.coerce1, %data.coerce2) #0 { # | entry: # | %data = alloca { , , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %data.coerce0, 0 # | %1 = insertvalue { , , } %0, %data.coerce1, 1 # | %2 = insertvalue { , , } %1, %data.coerce2, 2 # | store { , , } %2, ptr %data, align 16 # | %data1 = load { , , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , , } %data1, ptr %data.addr, align 16 # | %3 = load , ptr %pg.addr, align 2 # | %4 = load ptr, ptr %base.addr, align 8 # | %5 = load { , , }, ptr %data.addr, align 16 # | %6 = extractvalue { , , } %5, 0 # | %7 = extractvalue { , , } %5, 1 # | %8 = extractvalue { , , } %5, 2 # | %9 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %3) # | call void @llvm.aarch64.sve.st3.nxv8i16.p0( %6, %7, %8, %9, ptr %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st3.nxv8i16.p0(, , , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst3_s32( %pg, ptr noundef %base, %data.coerce0, %data.coerce1, %data.coerce2) #0 { # | entry: # | %data = alloca { , , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %data.coerce0, 0 # | %1 = insertvalue { , , } %0, %data.coerce1, 1 # | %2 = insertvalue { , , } %1, %data.coerce2, 2 # | store { , , } %2, ptr %data, align 16 # | %data1 = load { , , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , , } %data1, ptr %data.addr, align 16 # | %3 = load , ptr %pg.addr, align 2 # | %4 = load ptr, ptr %base.addr, align 8 # | %5 = load { , , }, ptr %data.addr, align 16 # | %6 = extractvalue { , , } %5, 0 # | %7 = extractvalue { , , } %5, 1 # | %8 = extractvalue { , , } %5, 2 # | %9 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %3) # | call void @llvm.aarch64.sve.st3.nxv4i32.p0( %6, %7, %8, %9, ptr %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st3.nxv4i32.p0(, , , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst3_s64( %pg, ptr noundef %base, %data.coerce0, %data.coerce1, %data.coerce2) #0 { # | entry: # | %data = alloca { , , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %data.coerce0, 0 # | %1 = insertvalue { , , } %0, %data.coerce1, 1 # | %2 = insertvalue { , , } %1, %data.coerce2, 2 # | store { , , } %2, ptr %data, align 16 # | %data1 = load { , , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , , } %data1, ptr %data.addr, align 16 # | %3 = load , ptr %pg.addr, align 2 # | %4 = load ptr, ptr %base.addr, align 8 # | %5 = load { , , }, ptr %data.addr, align 16 # | %6 = extractvalue { , , } %5, 0 # | %7 = extractvalue { , , } %5, 1 # | %8 = extractvalue { , , } %5, 2 # | %9 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %3) # | call void @llvm.aarch64.sve.st3.nxv2i64.p0( %6, %7, %8, %9, ptr %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st3.nxv2i64.p0(, , , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst3_u8( %pg, ptr noundef %base, %data.coerce0, %data.coerce1, %data.coerce2) #0 { # | entry: # | %data = alloca { , , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = al # | ... # `---data was truncated (10240/58378) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056083962657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560839623515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560839626cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc83bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc83bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc83bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc83bf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005608395bc24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005608395bc096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005608395a0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560839250176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056083924fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc83bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc83bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc83bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056083924fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c (321 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m1_f16m2( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv8f16.nxv4f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m1_f16m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv16f16.nxv4f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m2_f16m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv16f16.nxv8f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv8f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m1_f16m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32f16.nxv4f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m2_f16m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32f16.nxv8f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv8f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m4_f16m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32f16.nxv16f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv16f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f32m1_f32m2( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 4 # | store %dest, ptr %dest.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 4 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %val.addr, align 4 # | %2 = call @llvm.vector.insert.nxv4f32.nxv2f32( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4f32.nxv2f32(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f32m1_f32m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 4 # | store %dest, ptr %dest.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 4 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %val.addr, align 4 # | %2 = call @llvm.vector.insert.nxv8f32.nxv2f32( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f32.nxv2f32(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f32m2_f32m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 4 # | store %dest, ptr %dest.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 4 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %val.addr, align 4 # | %2 = call @llvm.vector.insert.nxv8f32.nxv4f32( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f32.nxv4f32(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f32m1_f32m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 4 # | store %dest, ptr %dest.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 4 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %val.addr, align 4 # | %2 = call @llvm.vector.insert.nxv16f32.nxv2f32( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c (322 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbxq_u8( %passthru, %zn, %zm) #0 { # | entry: # | %passthru.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %passthru, ptr %passthru.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %passthru.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.tbxq.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbxq.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbxq_u16( %passthru, %zn, %zm) #0 { # | entry: # | %passthru.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %passthru, ptr %passthru.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %passthru.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.tbxq.nxv8i16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbxq.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbxq_u32( %passthru, %zn, %zm) #0 { # | entry: # | %passthru.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %passthru, ptr %passthru.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %passthru.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.tbxq.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbxq.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbxq_u64( %passthru, %zn, %zm) #0 { # | entry: # | %passthru.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %passthru, ptr %passthru.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %passthru.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.tbxq.nxv2i64( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbxq.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbxq_s8( %passthru, %zn, %zm) #0 { # | entry: # | %passthru.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %passthru, ptr %passthru.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %passthru.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.tbxq.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbxq_s16( %passthru, %zn, %zm) #0 { # | entry: # | %passthru.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %passthru, ptr %passthru.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %passthru.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.tbxq.nxv8i16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbxq_s32( %passthru, %zn, %zm) #0 { # | entry: # | %passthru.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %passthru, ptr %passthru.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %passthru.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.tbxq.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbxq_s64( %passthru, %zn, %zm) #0 { # | entry: # | %passthru.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %passthru, ptr %passthru.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %passthru.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.tbxq.nxv2i64( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbxq_f16( %passthru, %zn, %zm) #0 { # | entry: # | %passthru.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %passthru, ptr %passthru.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %passthru.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.tbxq.nxv8f16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbxq.nxv8f16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbxq_f32( %passthru, %zn, %zm) #0 { # | entry: # | %passthru.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %passthru, ptr %passthru.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %passthru.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.tbxq.nxv4f32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm. # | ... # `---data was truncated (10240/14102) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000557e7f0fd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557e7f0fa515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557e7f0fdcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efda6333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efda638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efda6333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efda631b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557e7f09324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557e7f093096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557e7f077f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557e7ed27176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557e7ed26e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efda631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efda631d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efda631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557e7ed26d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-vls-compare-ops.c (323 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-compare-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_bool( noundef %0, noundef %1) #0 { # | entry: # | %retval = alloca <8 x i8>, align 2 # | %a.addr = alloca <8 x i8>, align 2 # | %b.addr = alloca <8 x i8>, align 2 # | %a.coerce = bitcast %0 to # | %a = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8( %a.coerce, i64 0) # | %b.coerce = bitcast %1 to # | %b = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8( %b.coerce, i64 0) # | store <8 x i8> %a, ptr %a.addr, align 2 # | store <8 x i8> %b, ptr %b.addr, align 2 # | %2 = load <8 x i8>, ptr %a.addr, align 2 # | %3 = load <8 x i8>, ptr %b.addr, align 2 # | %cmp = icmp eq <8 x i8> %2, %3 # | %sext = sext <8 x i1> %cmp to <8 x i8> # | store <8 x i8> %sext, ptr %retval, align 2 # | %4 = load <8 x i8>, ptr %retval, align 2 # | %cast.scalable = call @llvm.vector.insert.nxv2i8.v8i8( poison, <8 x i8> %4, i64 0) # | %5 = bitcast %cast.scalable to # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2i8.v8i8(, <8 x i8>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <64 x i8>, align 16 # | %a.addr = alloca <64 x i8>, align 16 # | %b.addr = alloca <64 x i8>, align 16 # | %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %a.coerce, i64 0) # | %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %b.coerce, i64 0) # | store <64 x i8> %a, ptr %a.addr, align 16 # | store <64 x i8> %b, ptr %b.addr, align 16 # | %0 = load <64 x i8>, ptr %a.addr, align 16 # | %1 = load <64 x i8>, ptr %b.addr, align 16 # | %cmp = icmp eq <64 x i8> %0, %1 # | %sext = sext <64 x i1> %cmp to <64 x i8> # | store <64 x i8> %sext, ptr %retval, align 16 # | %2 = load <64 x i8>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv16i8.v64i8( poison, <64 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16i8.v64i8(, <64 x i8>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_i16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i16>, align 16 # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca <32 x i16>, align 16 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %b.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store <32 x i16> %b, ptr %b.addr, align 16 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load <32 x i16>, ptr %b.addr, align 16 # | %cmp = icmp eq <32 x i16> %0, %1 # | %sext = sext <32 x i1> %cmp to <32 x i16> # | store <32 x i16> %sext, ptr %retval, align 16 # | %2 = load <32 x i16>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv8i16.v32i16( poison, <32 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8i16.v32i16(, <32 x i16>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_i32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i32>, align 16 # | %a.addr = alloca <16 x i32>, align 16 # | %b.addr = alloca <16 x i32>, align 16 # | %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %a.coerce, i64 0) # | %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %b.coerce, i64 0) # | store <16 x i32> %a, ptr %a.addr, align 16 # | store <16 x i32> %b, ptr %b.addr, align 16 # | %0 = load <16 x i32>, ptr %a.addr, align 16 # | %1 = load <16 x i32>, ptr %b.addr, align 16 # | %cmp = icmp eq <16 x i32> %0, %1 # | %sext = sext <16 x i1> %cmp to <16 x i32> # | store <16 x i32> %sext, ptr %retval, align 16 # | %2 = load <16 x i32>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv4i32.v16i32( poison, <16 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4i32.v16i32(, <16 x i32>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_i64( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i64>, align 16 # | %a.addr = alloca <8 x i64>, align 16 # | %b.addr = alloca <8 x i64>, align 16 # | %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64( %a.coerce, i64 0) # | %b = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64( %b.coerce, i64 0) # | store <8 x i64> %a, ptr %a.addr, align 16 # | store <8 x i64> %b, ptr %b.addr, align 16 # | %0 = load <8 x i64>, ptr %a.addr, align 16 # | %1 = load <8 x i64>, ptr %b.addr, align 16 # | %cmp = icmp eq <8 x i64> %0, %1 # | %sext = sext <8 x i1> %cmp to <8 x i64> # | store <8 x i64> %sext, ptr %retval, align 16 # | %2 = load <8 x i64>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv2i64.v8i64( poison, <8 x i64> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2i64.v8i64(, <8 x i64>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_u8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <64 x i8>, align 16 # | %a.addr = alloca <64 x i8>, align 16 # | %b.addr = alloca <64 x i8>, align 16 # | %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %a.coerce, i64 0) # | %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %b.coerce, i64 0) # | store <64 x i8> %a, ptr %a.addr, align 16 # | store <64 x i8> %b, ptr %b.addr, align 16 # | %0 = load <64 x i8>, ptr %a.addr, align 16 # | %1 = load <64 x i8>, ptr %b.addr, align 16 # | %cmp = icmp eq <64 x i8> %0, %1 # | %sext = sext <64 x i1> %cmp to <64 x i8> # | store <64 x i8> %sext, ptr %retval, align 16 # | %2 = load <64 x i8>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv16i8.v64i8( poison, <64 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_u16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i16>, align 16 # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca <32 x i16>, align 16 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %b.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store <32 x i16> %b, ptr %b.addr, align 16 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load <32 x i16>, ptr %b.addr, align 16 # | %cmp = icmp eq <32 x i16> %0, %1 # | %sext = sext <32 x i1> %cmp to <32 x i16> # | store <32 x i16> %sext, ptr %retval, align 16 # | %2 = load <32 x i16>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv8i16.v32i16( poison, <32 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_u32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i32>, align 16 # | %a.addr = alloca <16 x i32>, align 16 # | %b.addr = alloca <16 x i32>, align 16 # | %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %a.coerce, i64 0) # | %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %b.coerce, i64 0) # | store <16 x i32> %a, ptr %a.addr, align 16 # | store <16 x i32> %b, ptr %b.addr, align 16 # | %0 = load <16 x i32>, ptr %a.addr, align 16 # | %1 = load <16 x i32>, ptr %b.addr, align 16 # | %cmp = icmp eq <16 x i32> %0, %1 # | %sext = sext <16 x i1> %cmp to <16 x # | ... # `---data was truncated (10240/78785) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x000055b2aa68357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b2aa680515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b2aa683cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9742249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f97422a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9742249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9742231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b2aa61924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b2aa619096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b2aa5fdf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b2aa2ad176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b2aa2ace93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9742232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f97422330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f97422330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b2aa2acd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c (324 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svuzp_s8_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call { , , , } @llvm.aarch64.sve.uzp.x4.nxv16i8( %5, %6, %7, %8) # | ret { , , , } %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.uzp.x4.nxv16i8(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svuzp_u8_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call { , , , } @llvm.aarch64.sve.uzp.x4.nxv16i8( %5, %6, %7, %8) # | ret { , , , } %9 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svuzp_mf8_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call { , , , } @llvm.aarch64.sve.uzp.x4.nxv16i8( %5, %6, %7, %8) # | ret { , , , } %9 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svuzp_s16_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call { , , , } @llvm.aarch64.sve.uzp.x4.nxv8i16( %5, %6, %7, %8) # | ret { , , , } %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.uzp.x4.nxv8i16(, , , ) #1 # | ... # `---data was truncated (10240/67329) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055a20792457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a207921515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a207924cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9efc505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9efc55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9efc505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9efc4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a2078ba24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a2078ba096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a20789ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a20754e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a20754de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9efc4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9efc4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9efc4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a20754dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c (325 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16m8(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i16.i64( %2, ptr %0, %1, i64 %3) # | # | ... # `---data was truncated (10240/132462) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055987642957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559876426515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559876429cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffa43505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffa4355c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffa43505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffa434ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005598763bf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005598763bf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005598763a3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559876053176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559876052e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ffa434eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffa434ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffa434ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559876052d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c (326 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_s8() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_s16() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_s32() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_s64() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_u8() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_u16() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_u32() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_u64() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_f16() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_f32() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_f64() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_mf8() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_bf16() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | !llvm.errno.tbaa = !{!4} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # | !4 = !{!5, !6, i64 0} # | !5 = !{!"__libc_errno", !6, i64 0} # | !6 = !{!"int", !7, i64 0} # | !7 = !{!"omnipotent char", !8, i64 0} # | !8 = !{!"Simple C/C++ TBAA"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055edf414557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055edf4142515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055edf4145cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f993481bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f99348725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f993481ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9934803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055edf40db24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055edf40db096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055edf40bff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055edf3d6f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055edf3d6ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9934804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f99348050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f99348050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055edf3d6ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c (327 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti4_lane_zt_u16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8i16(i32 0, %0, i32 1) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8i16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti4_lane_zt_f16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8f16(i32 0, %0, i32 1) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8f16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti4_lane_zt_bf16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8bf16(i32 0, %0, i32 1) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8bf16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti4_lane_zt_s16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8i16(i32 0, %0, i32 1) # | ret { , , , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti4_lane_zt_u32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4i32(i32 0, %0, i32 1) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4i32(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti4_lane_zt_s32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4i32(i32 0, %0, i32 1) # | ret { , , , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti4_lane_zt_f32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4f32(i32 0, %0, i32 1) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4f32(i32 immarg, , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000560d1203857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560d12035515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560d12038cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6ec1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6ec178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6ec1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6ec171b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560d11fce24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560d11fce096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560d11fb2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560d11c62176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560d11c61e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6ec171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6ec171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6ec171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560d11c61d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c (328 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x2_za32_s8_s8( %zn, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zm = alloca { , }, align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zm.coerce1, 1 # | store { , } %1, ptr %zm, align 16 # | %zm1 = load { , }, ptr %zm, align 16 # | store %zn, ptr %zn.addr, align 16 # | store { , } %zm1, ptr %zm.addr, align 16 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load { , }, ptr %zm.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.smop4a.wide.1x2.nxv16i8(i32 1, %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smop4a.wide.1x2.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_1x2_za32_s8_s8( %zn, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zm = alloca { , }, align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zm.coerce1, 1 # | store { , } %1, ptr %zm, align 16 # | %zm1 = load { , }, ptr %zm, align 16 # | store %zn, ptr %zn.addr, align 16 # | store { , } %zm1, ptr %zm.addr, align 16 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load { , }, ptr %zm.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.smop4s.wide.1x2.nxv16i8(i32 1, %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smop4s.wide.1x2.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x2_za32_u8_u8( %zn, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zm = alloca { , }, align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zm.coerce1, 1 # | store { , } %1, ptr %zm, align 16 # | %zm1 = load { , }, ptr %zm, align 16 # | store %zn, ptr %zn.addr, align 16 # | store { , } %zm1, ptr %zm.addr, align 16 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load { , }, ptr %zm.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.umop4a.wide.1x2.nxv16i8(i32 1, %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umop4a.wide.1x2.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_1x2_za32_u8_u8( %zn, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zm = alloca { , }, align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zm.coerce1, 1 # | store { , } %1, ptr %zm, align 16 # | %zm1 = load { , }, ptr %zm, align 16 # | store %zn, ptr %zn.addr, align 16 # | store { , } %zm1, ptr %zm.addr, align 16 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load { , }, ptr %zm.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.umop4s.wide.1x2.nxv16i8(i32 1, %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umop4s.wide.1x2.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x2_za32_s8_u8( %zn, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zm = alloca { , }, align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zm.coerce1, 1 # | store { , } %1, ptr %zm, align 16 # | %zm1 = load { , }, ptr %zm, align 16 # | store %zn, ptr %zn.addr, align 16 # | store { , } %zm1, ptr %zm.addr, align 16 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load { , }, ptr %zm.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.sumop4a.wide.1x2.nxv16i8(i32 1, %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.sumop4a.wide.1x2.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_1x2_za32_s8_u8( %zn, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zm = alloca { , }, align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zm.coerce1, 1 # | store { , } %1, ptr %zm, align 16 # | %zm1 = load { , }, ptr %zm, align 16 # | store %zn, ptr %zn.addr, align 16 # | store { , } %zm1, ptr %zm.addr, align 16 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load { , }, ptr %zm.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.sumop4s.wide.1x2.nxv16i8(i32 1, %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.sumop4s.wide.1x2.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x2_za32_u8_s8( %zn, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zm = alloca { , }, align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zm.coerce1, 1 # | store { , } %1, ptr %zm, align 16 # | %zm1 = load { < # | ... # `---data was truncated (10240/50724) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000564a0840857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564a08405515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564a08408cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fda71c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fda71ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fda71c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fda71c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564a0839e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564a0839e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564a08382f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564a08032176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564a08031e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fda71c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fda71c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fda71c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564a08031d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c (329 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv32i16.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willr # | ... # `---data was truncated (10240/205805) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b3f581d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b3f581a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b3f581dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fde30933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fde3098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fde30933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fde3091b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b3f57b324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b3f57b3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b3f5797f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b3f5447176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b3f5446e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fde3091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fde3091d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fde3091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b3f5446d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c (330 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmple_s8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmpge.nxv16i8( %0, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpge.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmple_s16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmpge.nxv8i16( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpge.nxv8i16(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmple_s32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmpge.nxv4i32( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpge.nxv4i32(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmple_s64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.cmpge.nxv2i64( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpge.nxv2i64(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmple_u8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmphs.nxv16i8( %0, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphs.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmple_u16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmphs.nxv8i16( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphs.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmple_u32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmphs.nxv4i32( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphs.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmple_u64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, # | ... # `---data was truncated (10240/41923) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000563a30d8357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563a30d80515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563a30d83cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9ce7d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9ce7d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9ce7d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9ce7d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563a30d1924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563a30d19096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563a30cfdf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563a309ad176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563a309ace93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9ce7d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9ce7d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9ce7d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563a309acd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c (331 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1w_s64( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv2i32.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv2i32.p0(, , ptr captures(none)) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1w_u64( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv2i32.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1w_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = getelementptr , ptr %1, i64 %2 # | %6 = trunc %3 to # | call void @llvm.aarch64.sve.st1.nxv2i32.p0( %6, %4, ptr %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1w_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = getelementptr , ptr %1, i64 %2 # | %6 = trunc %3 to # | call void @llvm.aarch64.sve.st1.nxv2i32.p0( %6, %4, ptr %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1w_scatter_u64base_s64( %pg, %bases, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = trunc %2 to # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i32.nxv2i64( %3, %4, %1, i64 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i32.nxv2i64(, , , i64) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1w_scatter_u64base_u64( %pg, %bases, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = trunc %2 to # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i32.nxv2i64( %3, %4, %1, i64 0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1w_scatter_s64offset_s64( %pg, ptr noundef %base, %offsets, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = load , ptr %data.addr, align 16 # | %4 = trunc %3 to # | %5 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.st1.scatter.nxv2i32.p0( %4, %5, ptr %1, %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.aarch64.sve.st1.scatter.nxv2i32.p0(, , ptr, ) #4 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1w_scatter_s64offset_u64( %pg, ptr noundef %base, %offsets, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = load , ptr %data.addr, align 16 # | %4 = trunc %3 to # | %5 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.st1.scatter.nxv2i32.p0( %4, %5, ptr %1, %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1w_scatter_u64offset_s64( %pg, ptr noundef %base, %offsets, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c (332 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_i8mf8x5_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c (333 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclasta_s8( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.clasta.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clasta.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclasta_s16( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.clasta.nxv8i16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clasta.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclasta_s32( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.clasta.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clasta.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclasta_s64( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.clasta.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clasta.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclasta_u8( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.clasta.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclasta_u16( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.clasta.nxv8i16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclasta_u32( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.clasta.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclasta_u64( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.clasta.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclasta_f16( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.clasta.nxv8f16(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c (334 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_s8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv16i8( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.reverse.nxv16i8() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv8i16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.reverse.nxv8i16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv4i32( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.reverse.nxv4i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv2i64( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.reverse.nxv2i64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_u8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv16i8( %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv8i16( %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv4i32( %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv2i64( %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_f16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv8f16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.reverse.nxv8f16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_f32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv4f32( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.reverse.nxv4f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_f64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv2f64( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.reverse.nxv2f64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_b8( %op) #0 { # | entry: # | %op.addr = alloca , align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %op.addr, align 2 # | %1 = call @llvm.vector.reverse.nxv16i1( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.reverse.nxv16i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_b16( %op) #0 { # | entry: # | %op.addr = alloca , align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %op.addr, align 2 # | %1 = call @llvm.aarch64.sve.rev.b16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.rev.b16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_b32( %op) #0 { # | entry: # | %op.addr = alloca , align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %op.addr, align 2 # | %1 = call @llvm.aarch64.sve.rev.b32( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.rev.b32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_b64( %op) #0 { # | entry: # | %op.addr = alloca , align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %op.addr, align 2 # | %1 = call @llvm.aarch64.sve.rev.b64( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.rev.b64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_bf16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv8bf16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.reverse.nxv8bf16() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055bbca12157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bbca11e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bbca121cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7697049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f76970a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7697049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7697031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bbca0b724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bbca0b7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bbca09bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bbc9d4b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bbc9d4ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7697032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f76970330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f76970330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bbc9d4ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c (335 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561e5edb657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561e5edb3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561e5edb6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0f08649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0f086a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0f08649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0f08631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561e5ed4c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561e5ed4c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561e5ed30f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561e5e9e0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561e5e9dfe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0f08632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0f086330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0f086330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561e5e9dfd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c (336 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf8_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c (337 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_s32_x2( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sdot.x2.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdot.x2.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_u32_x2( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.udot.x2.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.udot.x2.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_f32_x2( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fdot.x2.nxv4f32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fdot.x2.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_s32_x2( %op1, %op2, i16 noundef %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca i16, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store i16 %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load i16, ptr %op3.addr, align 2 # | %.splatinsert = insertelement poison, i16 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.sdot.x2.nxv4i32( %0, %1, %.splat) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_u32_x2( %op1, %op2, i16 noundef %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca i16, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store i16 %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load i16, ptr %op3.addr, align 2 # | %.splatinsert = insertelement poison, i16 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.udot.x2.nxv4i32( %0, %1, %.splat) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_f32_x2( %op1, %op2, half noundef %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca half, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store half %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load half, ptr %op3.addr, align 2 # | %.splatinsert = insertelement poison, half %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.fdot.x2.nxv4f32( %0, %1, %.splat) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_lane_s32_x2( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sdot.lane.x2.nxv4i32( %0, %1, %2, i32 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdot.lane.x2.nxv4i32(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_lane_u32_x2( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.udot.lane.x2.nxv4i32( %0, %1, %2, i32 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.udot.lane.x2.nxv4i32(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_lane_f32_x2( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fdot.lane.x2.nxv4f32( %0, %1, %2, i32 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fdot.lane.x2.nxv4f32(, , , i32 immarg) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync no # | ... # `---data was truncated (10240/10512) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055fee0a8357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fee0a80515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fee0a83cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2601249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f26012a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2601249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2601231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fee0a1924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fee0a19096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fee09fdf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fee06ad176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fee06ace93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2601232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f26012330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f26012330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fee06acd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c (338 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.neg.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.neg.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.neg.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.neg.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.neg.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.neg.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.neg.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.neg.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s8_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.neg.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.neg.nxv8i16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.neg.nxv4i32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.neg.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s8_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.neg.nxv16i8( undef, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.neg.nxv8i16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 # | ... # `---data was truncated (10240/20016) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055ae0a6d957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ae0a6d6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ae0a6d9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8646a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8646aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8646a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8646a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ae0a66f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ae0a66f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ae0a653f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ae0a303176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ae0a302e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8646a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8646a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8646a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ae0a302d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon-vget-hilo.c (339 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon-vget-hilo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vget_high_s8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vget_high_s16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> # | store <4 x i16> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vget_high_s32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <2 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | %1 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %2 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <4 x i32> %1, <4 x i32> %2, <2 x i32> # | store <2 x i32> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vget_high_s64(<2 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <1 x i64>, align 8 # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %2 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> # | store <1 x i64> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vget_high_u8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vget_high_u16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> # | store <4 x i16> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vget_high_u32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <2 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | %1 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %2 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <4 x i32> %1, <4 x i32> %2, <2 x i32> # | store <2 x i32> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vget_high_u64(<2 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <1 x i64>, align 8 # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %2 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> # | store <1 x i64> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vget_high_p64(<2 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <1 x i64>, align 8 # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %2 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> # | store <1 x i64> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vget_high_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <4 x half>, align 8 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x half>, ptr %__p0.addr.i, align 16 # | %2 = load <8 x half>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <8 x half> %1, <8 x half> %2, <4 x i32> # | store <4 x half> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vget_high_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <2 x float>, align 8 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %2 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <4 x float> %1, <4 x float> %2, <2 x i32> # | store <2 x float> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vget_high_p8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vget_high_p16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> # | store <4 x i16> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vget_high_f64(<2 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <1 x double>, align 8 # | %a.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x double>, ptr %__p0.addr.i, align 16 # | %2 = load <2 x double>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <2 x double> %1, <2 x double> %2, <1 x i32> # | store <1 x double> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <1 x double>, ptr %__ret.i, align 8 # | ret <1 x double> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vget_low_s8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = allo # | ... # `---data was truncated (10240/20383) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a6fb54457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a6fb541515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a6fb544cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9dd7a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9dd7aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9dd7a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9dd7a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a6fb4da24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a6fb4da096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a6fb4bef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a6fb16e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a6fb16de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9dd7a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9dd7a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9dd7a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a6fb16dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/thinlto_backend_local_name_conflict.ll (340 of 27911) ******************** TEST 'Clang :: CodeGen/thinlto_backend_local_name_conflict.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 8 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -module-hash /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend_local_name_conflict.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend_local_name_conflict.ll.tmp.bc # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -module-hash /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend_local_name_conflict.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend_local_name_conflict.ll.tmp.bc # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -module-hash /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend_local_name_conflict.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend_local_name_conflict.ll.tmp.bc # | #0 0x000055b4d386e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b4d386b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b4d386ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f57c7133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f57c718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f57c7133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f57c711b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b4d380424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b4d3804096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b4d37e8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b4d3498176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b4d3497e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f57c711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f57c711d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f57c711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b4d3497d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c (341 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretu # | ... # `---data was truncated (10240/113047) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ad64cf957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ad64cf6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ad64cf9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3078333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f307838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3078333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f307831b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ad64c8f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ad64c8f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ad64c73f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ad64923176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ad64922e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f307831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f307831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f307831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ad64922d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c (342 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16mf4_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m4_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m8_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f32mf2_f64m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f32m1_f64m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca # | ... # `---data was truncated (10240/60342) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555d7adcf57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555d7adcc515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555d7adcfcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6621f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6621f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6621f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6621f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555d7ad6524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555d7ad65096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555d7ad49f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555d7a9f9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555d7a9f8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6621f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6621f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6621f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555d7a9f8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c (343 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecd_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdecd.n32(i32 %0, i32 31, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqdecd.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecd_n_s32_1(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdecd.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecd_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqdecd.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqdecd.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecd_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqdecd.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqdecd.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecd_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqdecd.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uqdecd.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecd_pat_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdecd.n32(i32 %0, i32 4, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecd_pat_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqdecd.n64(i64 %0, i32 5, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecd_pat_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqdecd.n32(i32 %0, i32 6, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecd_pat_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqdecd.n64(i64 %0, i32 7, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdecd_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqdecd.nxv2i64( %0, i32 31, i32 16) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqdecd.nxv2i64(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdecd_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqdecd.nxv2i64( %0, i32 31, i32 1) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqdecd.nxv2i64(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdecd_pat_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqdecd.nxv2i64( %0, i32 8, i32 16) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdecd_pat_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqdecd.nxv2i64( %0, i32 9, i32 1) # | ret %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000555a5fdd357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555a5fdd0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555a5fdd3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0099d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0099d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0099d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0099ced507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555a5fd6924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555a5fd69096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555a5fd4df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555a5f9fd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555a5f9fce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0099ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0099cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0099cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555a5f9fcd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/bf16-lane-intrinsics.c (344 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/bf16-lane-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vcopy_lane_bf16_v1(<4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x bfloat>, align 8 # | %b.addr = alloca <4 x bfloat>, align 8 # | %__ret_322 = alloca <4 x bfloat>, align 8 # | %__s0_322 = alloca <4 x bfloat>, align 8 # | %__s2_322 = alloca <4 x bfloat>, align 8 # | %__ret = alloca <4 x bfloat>, align 8 # | %__s0 = alloca bfloat, align 2 # | %__ret1 = alloca bfloat, align 2 # | %__s02 = alloca <4 x bfloat>, align 8 # | %ref.tmp = alloca bfloat, align 2 # | %tmp = alloca bfloat, align 2 # | %__s1 = alloca <4 x bfloat>, align 8 # | %ref.tmp3 = alloca <4 x bfloat>, align 8 # | %tmp4 = alloca <4 x bfloat>, align 8 # | %tmp5 = alloca <4 x bfloat>, align 8 # | store <4 x bfloat> %a, ptr %a.addr, align 8 # | store <4 x bfloat> %b, ptr %b.addr, align 8 # | %0 = load <4 x bfloat>, ptr %a.addr, align 8 # | store <4 x bfloat> %0, ptr %__s0_322, align 8 # | %1 = load <4 x bfloat>, ptr %b.addr, align 8 # | store <4 x bfloat> %1, ptr %__s2_322, align 8 # | %2 = load <4 x bfloat>, ptr %__s2_322, align 8 # | store <4 x bfloat> %2, ptr %__s02, align 8 # | %3 = load <4 x bfloat>, ptr %__s02, align 8 # | %vget_lane = extractelement <4 x bfloat> %3, i32 3 # | store bfloat %vget_lane, ptr %ref.tmp, align 2 # | %4 = load bfloat, ptr %ref.tmp, align 2 # | store bfloat %4, ptr %__ret1, align 2 # | %5 = load bfloat, ptr %__ret1, align 2 # | store bfloat %5, ptr %tmp, align 2 # | %6 = load bfloat, ptr %tmp, align 2 # | store bfloat %6, ptr %__s0, align 2 # | %7 = load <4 x bfloat>, ptr %__s0_322, align 8 # | store <4 x bfloat> %7, ptr %__s1, align 8 # | %8 = load bfloat, ptr %__s0, align 2 # | %9 = load <4 x bfloat>, ptr %__s1, align 8 # | %vset_lane = insertelement <4 x bfloat> %9, bfloat %8, i32 1 # | store <4 x bfloat> %vset_lane, ptr %ref.tmp3, align 8 # | %10 = load <4 x bfloat>, ptr %ref.tmp3, align 8 # | store <4 x bfloat> %10, ptr %__ret, align 8 # | %11 = load <4 x bfloat>, ptr %__ret, align 8 # | store <4 x bfloat> %11, ptr %tmp4, align 8 # | %12 = load <4 x bfloat>, ptr %tmp4, align 8 # | store <4 x bfloat> %12, ptr %__ret_322, align 8 # | %13 = load <4 x bfloat>, ptr %__ret_322, align 8 # | store <4 x bfloat> %13, ptr %tmp5, align 8 # | %14 = load <4 x bfloat>, ptr %tmp5, align 8 # | ret <4 x bfloat> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vcopy_lane_bf16_v2(<4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x bfloat>, align 8 # | %b.addr = alloca <4 x bfloat>, align 8 # | %__ret_322 = alloca <4 x bfloat>, align 8 # | %__s0_322 = alloca <4 x bfloat>, align 8 # | %__s2_322 = alloca <4 x bfloat>, align 8 # | %__ret = alloca <4 x bfloat>, align 8 # | %__s0 = alloca bfloat, align 2 # | %__ret1 = alloca bfloat, align 2 # | %__s02 = alloca <4 x bfloat>, align 8 # | %ref.tmp = alloca bfloat, align 2 # | %tmp = alloca bfloat, align 2 # | %__s1 = alloca <4 x bfloat>, align 8 # | %ref.tmp3 = alloca <4 x bfloat>, align 8 # | %tmp4 = alloca <4 x bfloat>, align 8 # | %tmp5 = alloca <4 x bfloat>, align 8 # | store <4 x bfloat> %a, ptr %a.addr, align 8 # | store <4 x bfloat> %b, ptr %b.addr, align 8 # | %0 = load <4 x bfloat>, ptr %a.addr, align 8 # | store <4 x bfloat> %0, ptr %__s0_322, align 8 # | %1 = load <4 x bfloat>, ptr %b.addr, align 8 # | store <4 x bfloat> %1, ptr %__s2_322, align 8 # | %2 = load <4 x bfloat>, ptr %__s2_322, align 8 # | store <4 x bfloat> %2, ptr %__s02, align 8 # | %3 = load <4 x bfloat>, ptr %__s02, align 8 # | %vget_lane = extractelement <4 x bfloat> %3, i32 0 # | store bfloat %vget_lane, ptr %ref.tmp, align 2 # | %4 = load bfloat, ptr %ref.tmp, align 2 # | store bfloat %4, ptr %__ret1, align 2 # | %5 = load bfloat, ptr %__ret1, align 2 # | store bfloat %5, ptr %tmp, align 2 # | %6 = load bfloat, ptr %tmp, align 2 # | store bfloat %6, ptr %__s0, align 2 # | %7 = load <4 x bfloat>, ptr %__s0_322, align 8 # | store <4 x bfloat> %7, ptr %__s1, align 8 # | %8 = load bfloat, ptr %__s0, align 2 # | %9 = load <4 x bfloat>, ptr %__s1, align 8 # | %vset_lane = insertelement <4 x bfloat> %9, bfloat %8, i32 2 # | store <4 x bfloat> %vset_lane, ptr %ref.tmp3, align 8 # | %10 = load <4 x bfloat>, ptr %ref.tmp3, align 8 # | store <4 x bfloat> %10, ptr %__ret, align 8 # | %11 = load <4 x bfloat>, ptr %__ret, align 8 # | store <4 x bfloat> %11, ptr %tmp4, align 8 # | %12 = load <4 x bfloat>, ptr %tmp4, align 8 # | store <4 x bfloat> %12, ptr %__ret_322, align 8 # | %13 = load <4 x bfloat>, ptr %__ret_322, align 8 # | store <4 x bfloat> %13, ptr %tmp5, align 8 # | %14 = load <4 x bfloat>, ptr %tmp5, align 8 # | ret <4 x bfloat> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcopyq_lane_bf16_v1(<8 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x bfloat>, align 16 # | %b.addr = alloca <4 x bfloat>, align 8 # | %__ret_298 = alloca <8 x bfloat>, align 16 # | %__s0_298 = alloca <8 x bfloat>, align 16 # | %__s2_298 = alloca <4 x bfloat>, align 8 # | %__ret = alloca <8 x bfloat>, align 16 # | %__s0 = alloca bfloat, align 2 # | %__ret1 = alloca bfloat, align 2 # | %__s02 = alloca <4 x bfloat>, align 8 # | %ref.tmp = alloca bfloat, align 2 # | %tmp = alloca bfloat, align 2 # | %__s1 = alloca <8 x bfloat>, align 16 # | %ref.tmp3 = alloca <8 x bfloat>, align 16 # | %tmp4 = alloca <8 x bfloat>, align 16 # | %tmp5 = alloca <8 x bfloat>, align 16 # | store <8 x bfloat> %a, ptr %a.addr, align 16 # | store <4 x bfloat> %b, ptr %b.addr, align 8 # | %0 = load <8 x bfloat>, ptr %a.addr, align 16 # | store <8 x bfloat> %0, ptr %__s0_298, align 16 # | %1 = load <4 x bfloat>, ptr %b.addr, align 8 # | store <4 x bfloat> %1, ptr %__s2_298, align 8 # | %2 = load <4 x bfloat>, ptr %__s2_298, align 8 # | store <4 x bfloat> %2, ptr %__s02, align 8 # | %3 = load <4 x bfloat>, ptr %__s02, align 8 # | %vget_lane = extractelement <4 x bfloat> %3, i32 2 # | store bfloat %vget_lane, ptr %ref.tmp, align 2 # | %4 = load bfloat, ptr %ref.tmp, align 2 # | store bfloat %4, ptr %__ret1, align 2 # | %5 = load bfloat, ptr %__ret1, align 2 # | store bfloat %5, ptr %tmp, align 2 # | %6 = load bfloat, ptr %tmp, align 2 # | store bfloat %6, ptr %__s0, align 2 # | %7 = load <8 x bfloat>, ptr %__s0_298, align 16 # | store <8 x bfloat> %7, ptr %__s1, align 16 # | %8 = load bfloat, ptr %__s0, align 2 # | %9 = load <8 x bfloat>, ptr %__s1, align 16 # | %vset_lane = insertelement <8 x bfloat> %9, bfloat %8, i32 0 # | store <8 x bfloat> %vset_lane, ptr %ref.tmp3, align 16 # | %10 = load <8 x bfloat>, ptr %ref.tmp3, align 16 # | store <8 x bfloat> %10, ptr %__ret, align 16 # | %11 = load <8 x bfloat>, ptr %__ret, align 16 # | store <8 x bfloat> %11, ptr %tmp4, align 16 # | %12 = load <8 x bfloat>, ptr %tmp4, align 16 # | store <8 x bfloat> %12, ptr %__ret_298, align 16 # | %13 = load <8 x bfloat>, ptr %__ret_298, align 16 # | store <8 x bfloat> %13, ptr %tmp5, align 16 # | %14 = load <8 x bfloat>, ptr %tmp5, align 16 # | ret <8 x bfloat> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcopyq_lane_bf16_v2(<8 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x bfloat>, align 16 # | %b.addr = alloca <4 x bfloat>, align 8 # | %__ret_298 = alloca <8 x bfloat>, align 16 # | %__s0_298 = alloca <8 x bfloat>, align 16 # | %__s2_298 = alloca <4 x bfloat>, align 8 # | %__ret = alloca <8 x bfloat>, align 16 # | %__s0 = alloca bfloat, align 2 # | %__ret1 = alloca bfloat, align 2 # | %__s02 = alloca <4 x bfloat>, align 8 # | %ref.tmp = alloca bfloat, align 2 # | %tmp = alloca bfloat, align 2 # | %__s1 = alloca <8 x bfloat>, align 16 # | %ref.tmp3 = alloca <8 x bfloat>, align 16 # | %tmp4 = alloca <8 x bfloat>, align 16 # | %tmp5 = alloca <8 x bfloat>, align 16 # | store <8 x bfloat> %a, ptr %a.addr, align 16 # | store <4 x bfloat> %b, ptr %b.addr, align 8 # | %0 = load <8 x bfloat>, ptr %a.addr, align 16 # | store <8 x bfloat> %0, ptr %__s0_298, align 16 # | %1 = load <4 x bfloat>, ptr %b.addr, align 8 # | store <4 x bfloat> %1, ptr %__s2_298, align 8 # | %2 = load <4 x bfloat>, ptr %__s2_298, align 8 # | store <4 x bfloat> %2, ptr %__s02, align 8 # | %3 = load <4 x bfloat>, ptr %__s02, align 8 # | %vget_lane = extractelement <4 x bfloat> %3, i32 0 # | store bfloat %vget_lane, ptr %ref.tmp, align 2 # | %4 = load bfloat, ptr %ref.tmp, align 2 # | store bfloat %4, ptr %__ret1, align 2 # | %5 = load bfloat, ptr %__ret1, align 2 # | store bfloat %5, ptr %tmp, align 2 # | %6 = load bfloat, ptr %tmp, align 2 # | store bfloat %6, ptr %__s0, align 2 # | %7 = load <8 x bfloat>, ptr %__s0_298, align 16 # | store <8 x bfloat> %7, ptr %__s1, align 16 # | %8 = load bfloat, ptr %__s0, align 2 # | %9 = load <8 x bfloat>, ptr %__s1, align 16 # | %vset_lane = insertelement <8 x bfloat> %9, bfloat %8, i32 6 # | store <8 x bfloat> %vset_lane, ptr %ref.tmp3, align 16 # | %10 = load <8 x bfloat>, ptr %ref.tmp3, align 16 # | store <8 x bfloat> %10, ptr %__ret, align 16 # | %11 = load <8 x bfloat>, ptr %__ret, align 16 # | store <8 x bfloat> %11, ptr %tmp4, align 16 # | %12 = load <8 x bfloat>, ptr %tmp4, align 16 # | store <8 x bfloat> %12, ptr %__ret_298, align 16 # | %13 = load <8 x bfloat>, ptr %__ret_298, align 16 # | store <8 x bfloat> %13, ptr %tmp5, align 16 # | %14 = load <8 x bfloat>, ptr %tmp5, align 16 # | ret <8 x bfloat> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vcopy_laneq_bf16_v1(<4 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x bfloat>, align 8 # | %b.addr = alloca <8 x bfloat>, align 16 # | %__ret_374 = alloca <4 x bfloat>, align 8 # | %__s0_374 = alloca <4 x bfloat>, align 8 # | %__s2_374 = alloca <8 x bfloat>, align 16 # | %__ret = alloca <4 x bfloat>, align 8 # | %__s0 = alloca bfloat, align 2 # | %__ret1 = alloca bfloat, align 2 # | %__s02 = alloca <8 x bfloat>, align 16 # | %ref.tmp = alloca bfloat, align 2 # | %tmp = alloca bfloat, align 2 # | %__s1 = alloca <4 x bfloat>, align 8 # | %ref.tmp3 = alloca <4 x bfloat>, align 8 # | %tmp4 = alloca <4 x bfloat>, align 8 # | %tmp5 = alloca <4 x bfloat>, align 8 # | store <4 x bfloat> %a, ptr %a.addr, align 8 # | store <8 x bfloat> %b, ptr %b.add # | ... # `---data was truncated (10240/18871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563cdfbb757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563cdfbb4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563cdfbb7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdd9c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdd9c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdd9c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdd9c71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563cdfb4d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563cdfb4d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563cdfb31f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563cdf7e1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563cdf7e0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fdd9c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdd9c71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdd9c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563cdf7e0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c (345 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16mf4( %op1, %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %index.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16mf4( %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv1f16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv1f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16mf2( %op1, %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %index.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16mf2( %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv2f16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv2f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m1( %op1, %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %index.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16m1( %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv4f16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv4f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m2( %op1, %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %index.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16m2( %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv8f16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv8f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m4( %op1, %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %index.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16m4( %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv16f16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willre # | ... # `---data was truncated (10240/273697) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005610091b057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005610091ad515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005610091b0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2ceff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2ceff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2ceff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2ceff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056100914624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561009146096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056100912af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561008dda176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561008dd9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2ceff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2ceff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2ceff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561008dd9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c (346 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf8_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m8_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i16mf4_i32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i16mf2_i32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv2i32.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv2i32.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i16m1_i32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, ali # | ... # `---data was truncated (10240/43507) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f4f9ed357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f4f9ed0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f4f9ed3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f47aef05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f47aef5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f47aef05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f47aeeed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f4f9e6924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f4f9e69096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f4f9e4df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f4f9afd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f4f9afce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f47aeeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f47aeeef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f47aeeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f4f9afcd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c (347 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_bf16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fminnm.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fminnm.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_bf16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fminnm.nxv8bf16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_bf16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fminnm.u.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fminnm.u.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_bf16_n_m( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fminnm.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_bf16_n_z( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fminnm.nxv8bf16( %3, %4, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_bf16_n_x( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fminnm.u.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005572e253757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005572e2534515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005572e2537cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5e21d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5e21d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5e21d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5e21d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005572e24cd24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005572e24cd096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005572e24b1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005572e2161176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005572e2160e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5e21d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5e21d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5e21d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005572e2160d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c (348 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_b8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.zip1.nxv16i1( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_b16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.zip1.b16( %0, %1) # | ret %2 # | ... # `---data was truncated (10240/13404) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005639a6ba257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005639a6b9f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005639a6ba2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9542649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f95426a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9542649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9542631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005639a6b3824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005639a6b38096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005639a6b1cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005639a67cc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005639a67cbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9542632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f95426330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f95426330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005639a67cbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c (349 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | # | ... # `---data was truncated (10240/222475) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560566b2657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560566b23515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560566b26cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9f9ba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9f9baa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9f9ba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9f9ba31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560566abc24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560566abc096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560566aa0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560566750176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056056674fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9f9ba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9f9ba330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9f9ba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056056674fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c (350 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align # | ... # `---data was truncated (10240/52607) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005584dc8f657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005584dc8f3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005584dc8f6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f891fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f891fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f891fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f891fb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005584dc88c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005584dc88c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005584dc870f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005584dc520176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005584dc51fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f891fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f891fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f891fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005584dc51fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c (351 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f16f16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f16f16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_cvtl_f32_x2( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sve.fcvtl.widen.x2.nxv4f32( %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fcvtl.widen.x2.nxv4f32() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme-f16f16" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000563e843d757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563e843d4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563e843d7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f15b7c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f15b7ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f15b7c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f15b7c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563e8436d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563e8436d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563e84351f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563e84001176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563e84000e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f15b7c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f15b7c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f15b7c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563e84000d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c (352 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/82983) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557dfb2e157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557dfb2de515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557dfb2e1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6ba1b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6ba1b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6ba1b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6ba1b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557dfb27724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557dfb277096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557dfb25bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557dfaf0b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557dfaf0ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6ba1b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6ba1b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6ba1b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557dfaf0ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c (353 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m8_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32m2_tu( %maskedoff, ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c (354 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti2_lane_zt_u8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 0, %0, i32 7) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti2_lane_zt_s8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 0, %0, i32 7) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti2_lane_zt_mf8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 0, %0, i32 7) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti2_lane_zt_u16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8i16(i32 0, %0, i32 7) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8i16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti2_lane_zt_s16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8i16(i32 0, %0, i32 7) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti2_lane_zt_f16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8f16(i32 0, %0, i32 7) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8f16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti2_lane_zt_bf16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8bf16(i32 0, %0, i32 7) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8bf16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti2_lane_zt_u32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4i32(i32 0, %0, i32 7) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4i32(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti2_lane_zt_s32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4i32(i32 0, %0, i32 7) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti2_lane_zt_f32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4f32(i32 0, %0, i32 7) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4f32(i32 immarg, , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000558f0d3d357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558f0d3d0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558f0d3d3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007facd3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007facd338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007facd3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007facd331b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558f0d36924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558f0d369096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558f0d34df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558f0cffd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558f0cffce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007facd331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007facd331d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007facd331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558f0cffcd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c (355 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_s8( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sclamp.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sclamp.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_s16( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sclamp.nxv8i16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sclamp.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_s32( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sclamp.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sclamp.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_s64( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sclamp.nxv2i64( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sclamp.nxv2i64(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005642d04e657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005642d04e3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005642d04e6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f11bde49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f11bdea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f11bde49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f11bde31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005642d047c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005642d047c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005642d0460f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005642d0110176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005642d010fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f11bde32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f11bde330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f11bde330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005642d010fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c (356 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_s8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.cnt.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cnt.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_s16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.cnt.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cnt.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.cnt.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cnt.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.cnt.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cnt.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_u8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.cnt.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_u16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.cnt.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_u32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.cnt.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.cnt.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.cnt.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cnt.nxv8f16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.cnt.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cnt.nxv4f32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.cnt.nxv2f64( zeroi # | ... # `---data was truncated (10240/32102) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055a78f7cf57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a78f7cc515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a78f7cfcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feb29133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feb2918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feb29133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feb2911b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a78f76524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a78f765096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a78f749f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a78f3f9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a78f3f8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007feb2911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feb2911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feb2911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a78f3f8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c (357 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv16i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv32i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv64i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16mf4_tu( %maskedoff, %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i16, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv1i16.i16.i64( %0, %1, i16 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16mf2_tu( %maskedoff, %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i16, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = c # | ... # `---data was truncated (10240/207083) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005573ca20957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005573ca206515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005573ca209cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7301f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7301f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7301f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7301f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005573ca19f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005573ca19f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005573ca183f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005573c9e33176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005573c9e32e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7301f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7301f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7301f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005573c9e32d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c (358 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_s8_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = select %0, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mls.nxv16i8( %0, %4, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mls.nxv16i8(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_s16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mls.nxv8i16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mls.nxv8i16(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_s32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mls.nxv4i32( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mls.nxv4i32(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_s64_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mls.nxv2i64( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mls.nxv2i64(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_u8_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = select %0, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mls.nxv16i8( %0, %4, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_u16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mls.nxv8i16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_u32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mls.nxv4i32( %4, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c (359 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16mf4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16mf2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m1_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m8_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f32mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f32m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff # | ... # `---data was truncated (10240/44185) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005567eff0a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005567eff07515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005567eff0acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f50a8449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f50a84a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f50a8449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f50a8431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005567efea024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005567efea0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005567efe84f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005567efb34176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005567efb33e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f50a8432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f50a84330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f50a84330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005567efb33d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c (360 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 31) # | ret i64 %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.cntb(i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_1() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_2() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_3() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 3) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_4() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 4) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_5() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 5) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_6() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 6) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_7() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_8() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 8) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_9() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 9) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_10() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 10) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_11() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 11) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_12() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 12) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_13() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 13) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_14() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 29) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_15() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 30) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_16() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 31) # | ret i64 %0 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x000055658e8cc57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055658e8c9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055658e8cccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f935a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f935a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f935a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f935a91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055658e86224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055658e862096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055658e846f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055658e4f6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055658e4f5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f935a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f935a91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f935a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055658e4f5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c (361 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16mf4_tu( %maskedoff, %op1, %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %index.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16mf4_tu( %maskedoff, %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %index.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv1f16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv1f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16mf2_tu( %maskedoff, %op1, %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %index.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16mf2_tu( %maskedoff, %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %index.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv2f16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv2f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m1_tu( %maskedoff, %op1, %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %index.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16m1_tu( %maskedoff, %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %index.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv4f16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv4f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m2_tu( %maskedoff, %op1, %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %index.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16m2_tu( %maskedoff, %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %index.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv8f16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv8f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m4_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-vls-subscript-ops.c (362 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-subscript-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local i16 @subscript_int16( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca i64, align 8 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <32 x i16> %0, i64 %1 # | ret i16 %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local i16 @subscript_uint16( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca i64, align 8 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <32 x i16> %0, i64 %1 # | ret i16 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local i32 @subscript_int32( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i32>, align 16 # | %b.addr = alloca i64, align 8 # | %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %a.coerce, i64 0) # | store <16 x i32> %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <16 x i32>, ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <16 x i32> %0, i64 %1 # | ret i32 %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local i32 @subscript_uint32( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i32>, align 16 # | %b.addr = alloca i64, align 8 # | %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %a.coerce, i64 0) # | store <16 x i32> %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <16 x i32>, ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <16 x i32> %0, i64 %1 # | ret i32 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local i64 @subscript_int64( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i64>, align 16 # | %b.addr = alloca i64, align 8 # | %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64( %a.coerce, i64 0) # | store <8 x i64> %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <8 x i64>, ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <8 x i64> %0, i64 %1 # | ret i64 %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local i64 @subscript_uint64( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i64>, align 16 # | %b.addr = alloca i64, align 8 # | %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64( %a.coerce, i64 0) # | store <8 x i64> %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <8 x i64>, ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <8 x i64> %0, i64 %1 # | ret i64 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local half @subscript_float16( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <32 x half>, align 16 # | %b.addr = alloca i64, align 8 # | %a = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16( %a.coerce, i64 0) # | store <32 x half> %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <32 x half>, ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <32 x half> %0, i64 %1 # | ret half %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x half> @llvm.vector.extract.v32f16.nxv8f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local float @subscript_float32( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x float>, align 16 # | %b.addr = alloca i64, align 8 # | %a = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32( %a.coerce, i64 0) # | store <16 x float> %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <16 x float>, ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <16 x float> %0, i64 %1 # | ret float %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x float> @llvm.vector.extract.v16f32.nxv4f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local double @subscript_float64( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x double>, align 16 # | %b.addr = alloca i64, align 8 # | %a = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64( %a.coerce, i64 0) # | store <8 x double> %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <8 x double>, ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <8 x double> %0, i64 %1 # | ret double %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x double> @llvm.vector.extract.v8f64.nxv2f64(, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,4) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x0000562e96fb157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562e96fae515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562e96fb1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa5a1d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa5a1d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa5a1d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa5a1ced507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562e96f4724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562e96f47096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562e96f2bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562e96bdb176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562e96bdae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa5a1ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa5a1cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa5a1cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562e96bdad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c (363 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32m2x4_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c (364 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmopa_za16_mf8_m( %pn, %pm, %zn, %zm, i64 noundef %fpmr) #0 { # | entry: # | %pn.addr = alloca , align 2 # | %pm.addr = alloca , align 2 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | store %pn, ptr %pn.addr, align 2 # | store %pm, ptr %pm.addr, align 2 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load , ptr %pn.addr, align 2 # | %1 = load , ptr %pm.addr, align 2 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load , ptr %zm.addr, align 16 # | %4 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %4) # | call void @llvm.aarch64.sme.fp8.fmopa.za16(i32 1, %0, %1, %2, %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmopa.za16(i32 immarg, , , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmopa_za32_mf8_m( %pn, %pm, %zn, %zm, i64 noundef %fpmr) #0 { # | entry: # | %pn.addr = alloca , align 2 # | %pm.addr = alloca , align 2 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | store %pn, ptr %pn.addr, align 2 # | store %pm, ptr %pm.addr, align 2 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load , ptr %pn.addr, align 2 # | %1 = load , ptr %pm.addr, align 2 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load , ptr %zm.addr, align 16 # | %4 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %4) # | call void @llvm.aarch64.sme.fp8.fmopa.za32(i32 3, %0, %1, %2, %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmopa.za32(i32 immarg, , , , ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme-f8f16,+sme-f8f32" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005622b5df457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005622b5df1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005622b5df4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7f8e81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7f8e8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7f8e81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7f8e803507 abort ./stdlib/abort.c:85:3 # | #7 0x00005622b5d8a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005622b5d8a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005622b5d6ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005622b5a1e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005622b5a1de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7f8e804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7f8e8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7f8e8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005622b5a1dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c (365 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/97913) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562457bde57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562457bdb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562457bdecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff759249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff7592a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff759249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff759231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562457b7424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562457b74096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562457b58f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562457808176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562457807e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff759232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff7592330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff7592330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562457807d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c (366 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svfirstp_b8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call i64 @llvm.aarch64.sve.firstp.nxv16i1( %0, %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.firstp.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svfirstp_b16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call i64 @llvm.aarch64.sve.firstp.nxv8i1( %2, %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.firstp.nxv8i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svfirstp_b32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call i64 @llvm.aarch64.sve.firstp.nxv4i1( %2, %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.firstp.nxv4i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svfirstp_b64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call i64 @llvm.aarch64.sve.firstp.nxv2i1( %2, %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.firstp.nxv2i1(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2p2" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000561cb1e7557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561cb1e72515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561cb1e75cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f92c6105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f92c615c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f92c6105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f92c60ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561cb1e0b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561cb1e0b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561cb1deff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561cb1a9f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561cb1a9ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f92c60eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f92c60ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f92c60ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561cb1a9ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon/widen.c (367 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon/widen.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c --check-prefixes=LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vmovl_s8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vmovl.i = sext <8 x i8> %1 to <8 x i16> # | store <8 x i16> %vmovl.i, ptr %ref.tmp.i, align 16 # | %2 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %2, ptr %__ret.i, align 16 # | %3 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vmovl_s16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x i16> # | %vmovl.i = sext <4 x i16> %2 to <4 x i32> # | store <4 x i32> %vmovl.i, ptr %ref.tmp.i, align 16 # | %3 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %3, ptr %__ret.i, align 16 # | %4 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vmovl_s32(<2 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i64>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <2 x i32> # | %vmovl.i = sext <2 x i32> %2 to <2 x i64> # | store <2 x i64> %vmovl.i, ptr %ref.tmp.i, align 16 # | %3 = load <2 x i64>, ptr %ref.tmp.i, align 16 # | store <2 x i64> %3, ptr %__ret.i, align 16 # | %4 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vmovl_u8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vmovl.i = zext <8 x i8> %1 to <8 x i16> # | store <8 x i16> %vmovl.i, ptr %ref.tmp.i, align 16 # | %2 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %2, ptr %__ret.i, align 16 # | %3 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vmovl_u16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x i16> # | %vmovl.i = zext <4 x i16> %2 to <4 x i32> # | store <4 x i32> %vmovl.i, ptr %ref.tmp.i, align 16 # | %3 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %3, ptr %__ret.i, align 16 # | %4 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vmovl_u32(<2 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i64>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <2 x i32> # | %vmovl.i = zext <2 x i32> %2 to <2 x i64> # | store <2 x i64> %vmovl.i, ptr %ref.tmp.i, align 16 # | %3 = load <2 x i64>, ptr %ref.tmp.i, align 16 # | store <2 x i64> %3, ptr %__ret.i, align 16 # | %4 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vmovl_high_s8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i1 = alloca <8 x i8>, align 8 # | %__p0_561.addr.i = alloca <16 x i8>, align 16 # | %__ret_561.i = alloca <8 x i16>, align 16 # | %__a1_561.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %__s0.i = alloca <8 x i8>, align 8 # | %ref.tmp1.i = alloca <16 x i8>, align 16 # | %tmp.i = alloca <8 x i16>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0_561.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0_561.addr.i, align 16 # | store <16 x i8> %1, ptr %__p0.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %2, <16 x i8> %3, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i1, align 8 # | %4 = load <8 x i8>, ptr %__ret.i1, align 8 # | store <8 x i8> %4, ptr %__a1_561.i, align 8 # | %5 = load <8 x i8>, ptr %__a1_561.i, align 8 # | store <8 x i8> %5, ptr %__s0.i, align 8 # | %6 = load <8 x i8>, ptr %__s0.i, align 8 # | %7 = sext <8 x i8> %6 to <8 x i16> # | store <8 x i16> %7, ptr %ref.tmp1.i, align 16 # | %8 = load <8 x i16>, ptr %ref.tmp1.i, align 16 # | store <8 x i16> %8, ptr %__ret.i, align 16 # | %9 = load <8 x i16>, ptr %__ret.i, align 16 # | store <8 x i16> %9, ptr %tmp.i, align 16 # | %10 = load <8 x i16>, ptr %tmp.i, align 16 # | store <8 x i16> %10, ptr %ref.tmp.i, align 16 # | %11 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %11, ptr %__ret_561.i, align 16 # | %12 = load <8 x i16>, ptr %__ret_561.i, align 16 # | ret <8 x i16> %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vmovl_high_s16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i1 = alloca <4 x i16>, align 8 # | %__p0_567.addr.i = alloca <8 x i16>, align 16 # | %__ret_567.i = alloca <4 x i32>, align 16 # | %__a1_567.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %__s0.i = alloca <4 x i16>, align 8 # | %ref.tmp1.i = alloca <16 x i8>, align 16 # | %tmp.i = alloca <4 x i32>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0_567.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0_567.addr.i, align 16 # | store <8 x i16> %1, ptr %__p0.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %3 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <8 x i16> %2, <8 x i16> %3, <4 x i32> # | store <4 x i16> %shuffle.i, ptr %__ret.i1, align 8 # | %4 = load <4 x i16>, ptr %__ret.i1, align 8 # | store <4 x i16> %4, ptr %__a1_567.i, align 8 # | %5 = load <4 x i16>, ptr %__a1_567.i, align 8 # | store <4 x i16> %5, ptr %__s0.i, align 8 # | %6 = load <8 x i8>, ptr %__s0.i, align 8 # | %7 = bitcast <8 x i8> %6 to <4 x i16> # | %8 = sext <4 x i16> %7 to <4 x i32> # | store <4 x i32> %8, ptr %ref.tmp1.i, align 16 # | %9 = load <4 x i32>, ptr %ref.tmp1.i, align 16 # | store <4 x i32> %9, ptr %__ret.i, align 16 # | %10 = load <4 x i32>, ptr %__ret.i, align 16 # | store <4 x i32> %10, ptr %tmp.i, align 16 # | %11 = load <4 x i32>, ptr %tmp.i, align 16 # | store <4 x i32> %11, ptr %ref.tmp.i, align 16 # | %12 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %12, ptr %__ret_567.i, align 16 # | %13 = load <4 x i32>, ptr %__ret_567.i, align 16 # | ret <4 x i32> %13 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vmovl_high_s32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i1 = alloca <2 x i32>, align 8 # | %__p0_564.addr.i = alloca <4 x i32>, align 16 # | %__ret_564.i = alloca <2 x i64>, align 16 # | %__a1_564.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %__s0.i = alloca <2 x i32>, align 8 # | %ref.tmp1.i = alloca <16 x i8>, align 16 # | %tmp.i = alloca <2 x i64>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0_564.addr.i, align 16 # | %1 = load <4 x i32>, ptr %__p0_564.addr.i, align 16 # | store <4 x i32> %1, ptr %__p0.addr.i, align 16 # | %2 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %3 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <4 x i32> %2, <4 x i32> %3, <2 x i32> # | store <2 x i32> %shuffle.i, ptr %__ret.i1, align 8 # | %4 = load <2 x i32>, ptr %__ret.i1, align 8 # | store <2 x i32> %4, ptr %__a1_564.i, align 8 # | %5 = load <2 x i32>, ptr %__a1_564.i, align 8 # | store <2 x i32> %5, ptr %__s0.i, align 8 # | %6 = load <8 x i8>, ptr %__s0.i, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x i32> # | %8 = sext <2 x i32> %7 to <2 x i64> # | store <2 x i64> %8, ptr %ref.tmp1.i, align 16 # | %9 = load <2 x i64>, ptr %ref.tmp1.i, align 16 # | store <2 x i64> %9, ptr %__ret.i, align 16 # | %10 = load <2 x i64>, ptr %__ret.i, align 16 # | store <2 x i64> %10, ptr %tmp.i, align 16 # | %11 = load <2 x i64>, ptr %tmp.i, align 16 # | store <2 x i64> %11, ptr %ref.tmp.i, align 16 # | %12 = load <2 # | ... # `---data was truncated (10240/16529) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055fa1dce457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fa1dce1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fa1dce4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1738f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1738f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1738f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1738f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fa1dc7a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fa1dc7a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fa1dc5ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fa1d90e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fa1d90de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1738f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1738f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1738f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fa1d90dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c --check-prefixes=LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c --check-prefixes=LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c (368 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svset4_s8( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3, %x) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %4 = load { , , , }, ptr %tuple.addr, align 16 # | %5 = load , ptr %x.addr, align 16 # | %6 = insertvalue { , , , } %4, %5, 1 # | ret { , , , } %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svset4_s16( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3, %x) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %4 = load { , , , }, ptr %tuple.addr, align 16 # | %5 = load , ptr %x.addr, align 16 # | %6 = insertvalue { , , , } %4, %5, 3 # | ret { , , , } %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svset4_s32( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3, %x) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %4 = load { , , , }, ptr %tuple.addr, align 16 # | %5 = load , ptr %x.addr, align 16 # | %6 = insertvalue { , , , } %4, %5, 1 # | ret { , , , } %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svset4_s64( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3, %x) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %4 = load { , , , }, ptr %tuple.addr, align 16 # | %5 = load , ptr %x.addr, align 16 # | %6 = insertvalue { , , , } %4, %5, 1 # | ret { , , , } %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svset4_u8( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3, %x) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %4 = load { , , , }, ptr %tuple.addr, align 16 # | %5 = load , ptr %x.addr, align 16 # | ... # `---data was truncated (10240/34217) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056438b43e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056438b43b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056438b43ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa32ba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa32baa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa32ba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa32ba31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056438b3d424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056438b3d4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056438b3b8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056438b068176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056438b067e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa32ba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa32ba330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa32ba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056438b067d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c (369 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmul_single_f16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fmul.single.x2.nxv8f16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fmul.single.x2.nxv8f16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svmul_single_f16_x4( %zdn.coerce0, %zdn.coerce1, %zdn.coerce2, %zdn.coerce3, %zm) #0 { # | entry: # | %zdn = alloca { , , , }, align 16 # | %zdn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zdn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zdn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zdn.coerce3, 3 # | store { , , , } %3, ptr %zdn, align 16 # | %zdn1 = load { , , , }, ptr %zdn, align 16 # | store { , , , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %4 = load { , , , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = load , ptr %zm.addr, align 16 # | %10 = call { , , , } @llvm.aarch64.sve.fmul.single.x4.nxv8f16( %5, %6, %7, %8, %9) # | ret { , , , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.fmul.single.x4.nxv8f16(, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmul_f16_x2( %zdn.coerce0, %zdn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | %10 = call { , } @llvm.aarch64.sve.fmul.x2.nxv8f16( %5, %6, %8, %9) # | ret { , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fmul.x2.nxv8f16(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svmul_f16_x4( %zdn.coerce0, %zdn.coerce1, %zdn.coerce2, %zdn.coerce3, %zm.coerce0, %zm.coerce1, %zm.coerce2, %zm.coerce3) #0 { # | entry: # | %zdn = alloca { , , , }, align 16 # | %zm = alloca { , , , }, align 16 # | %zdn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zdn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zdn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zdn.coerce3, 3 # | store { , , , } %3, ptr %zdn, align 16 # | %zdn1 = load { , , , }, ptr %zdn, align 16 # | %4 = insertvalue { , , , } poison, %zm.coerce0, 0 # | %5 = insertvalue { , , , } %4, %zm.coerce1, 1 # | %6 = insertvalue { , , , } %5, %zm.coerce2, 2 # | %7 = insertvalue { , , , } %6, %zm.coerce3, 3 # | store { , , , } %7, ptr %zm, align 16 # | %zm2 = load { , , , }, ptr %zm, align 16 # | store { , , , } %zdn1, ptr %zdn.addr, align 16 # | store { , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c (370 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m4_tu( %maske # | ... # `---data was truncated (10240/157777) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d0f9cb357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d0f9cb0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d0f9cb3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6fa6d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6fa6d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6fa6d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6fa6d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d0f9c4924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d0f9c49096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d0f9c2df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d0f98dd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d0f98dce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6fa6d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6fa6d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6fa6d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d0f98dcd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c (371 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulh_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.smulh.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smulh.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulh_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.smulh.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smulh.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulh_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.smulh.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smulh.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulh_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.smulh.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smulh.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulh_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.umulh.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.umulh.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulh_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.umulh.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.umulh.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulh_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.umulh.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.umulh.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulh_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/orn.c (372 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve/orn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svorn_b_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.orn.z.nxv16i1( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.orn.z.nxv16i1(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x0000559bec4fa57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559bec4f7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559bec4facbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f56f021bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f56f02725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f56f021ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f56f0203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559bec49024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559bec490096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559bec474f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559bec124176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559bec123e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f56f0204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f56f02050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f56f02050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559bec123d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c (373 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory # | ... # `---data was truncated (10240/69669) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555f18b8d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555f18b8a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555f18b8dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd5dad05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd5dad5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd5dad05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd5daced507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555f18b2324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555f18b23096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555f18b07f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555f187b7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555f187b6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd5daceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd5dacef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd5dacef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555f187b6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-vector-shift-ops.c (374 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-shift-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @lshift_i8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shl = shl %0, %1 # | ret %shl # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @rshift_i8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shr = ashr %0, %1 # | ret %shr # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @lshift_u8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shl = shl %0, %1 # | ret %shl # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @rshift_u8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shr = lshr %0, %1 # | ret %shr # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @lshift_i16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shl = shl %0, %1 # | ret %shl # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @rshift_i16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shr = ashr %0, %1 # | ret %shr # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @lshift_u16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shl = shl %0, %1 # | ret %shl # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @rshift_u16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shr = lshr %0, %1 # | ret %shr # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @lshift_i32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shl = shl %0, %1 # | ret %shl # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @rshift_i32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shr = ashr %0, %1 # | ret %shr # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @lshift_u32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shl = shl %0, %1 # | ret %shl # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @rshift_u32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shr = lshr %0, %1 # | ret %shr # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @lshift_i64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shl = shl %0, %1 # | ret %shl # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @rshift_i64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shr = ashr %0, %1 # | ret %shr # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @lshift_u64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shl = shl %0, %1 # | ret %shl # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @rshift_u64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shr = lshr %0, %1 # | ret %shr # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @lshift_i8_rsplat( %a, i8 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i8, align 1 # | store %a, ptr %a.addr, align 16 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load , ptr %a.addr, align 16 # | %1 = load i8, ptr %b.addr, align 1 # | %splat.splatinsert = insertelement poison, i8 %1, i64 0 # | %splat.splat = shufflevector %splat.splatinsert, poison, zeroinitializer # | %shl = shl %0, %splat.splat # | ret %shl # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @lshift_i8_lsplat( %a, i8 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i8, align 1 # | store %a, ptr %a.addr, align 16 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load i8, ptr %b.addr, align 1 # | %splat.splatinsert = insertelement poison, i8 %0, i64 0 # | %splat.splat # | ... # `---data was truncated (10240/32491) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x00005571a54e957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005571a54e6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005571a54e9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f580a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f580a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f580a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f580a51b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005571a547f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005571a547f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005571a5463f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005571a5113176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005571a5112e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f580a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f580a51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f580a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005571a5112d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c (375 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_s16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.revb.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.revb.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.revb.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.revb.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.revb.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.revb.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_u16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.revb.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_u32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.revb.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.revb.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_s16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.revb.nxv8i16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.revb.nxv4i32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_s64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.revb.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_u16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.revb.nxv8i16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_u32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | # | ... # `---data was truncated (10240/16804) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055a2bce2957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a2bce26515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a2bce29cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f710d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f710d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f710d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f710d831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a2bcdbf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a2bcdbf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a2bcda3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a2bca53176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a2bca52e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f710d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f710d8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f710d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a2bca52d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c (376 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntp_b8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call i64 @llvm.aarch64.sve.cntp.nxv16i1( %0, %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.cntp.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntp_b16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call i64 @llvm.aarch64.sve.cntp.nxv8i1( %2, %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.cntp.nxv8i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntp_b32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call i64 @llvm.aarch64.sve.cntp.nxv4i1( %2, %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.cntp.nxv4i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntp_b64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call i64 @llvm.aarch64.sve.cntp.nxv2i1( %2, %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.cntp.nxv2i1(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000563632d5457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563632d51515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563632d54cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2162705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f216275c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2162705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f21626ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563632cea24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563632cea096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563632ccef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056363297e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056363297de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f21626eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f21626ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f21626ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056363297dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c (377 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdivr_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sdivr.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdivr.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdivr_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sdivr.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdivr.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdivr_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.udivr.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.udivr.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdivr_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.udivr.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.udivr.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdivr_s32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.sdivr.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdivr_s64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.sdivr.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdivr_u32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.udivr.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdivr_u64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.udivr.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdivr_s32_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c (378 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_s8() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_s16() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_s32() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_s64() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_u8() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_u16() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_u32() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_u64() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_f16() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_f32() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_f64() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_mf8() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_bf16() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | !llvm.errno.tbaa = !{!4} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # | !4 = !{!5, !6, i64 0} # | !5 = !{!"__libc_errno", !6, i64 0} # | !6 = !{!"int", !7, i64 0} # | !7 = !{!"omnipotent char", !8, i64 0} # | !8 = !{!"Simple C/C++ TBAA"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055788a18757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055788a184515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055788a187cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feae9649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feae96a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feae9649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feae9631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055788a11d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055788a11d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055788a101f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557889db1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557889db0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007feae9632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feae96330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feae96330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557889db0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c (379 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_i32mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_i32m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_u32mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_u32m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_i32mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_i32m1x7_m( %mask, ptr noundef % # | ... # `---data was truncated (10240/14001) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005579a06ad57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005579a06aa515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005579a06adcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdbd0449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdbd04a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdbd0449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdbd0431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005579a064324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005579a0643096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005579a0627f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005579a02d7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005579a02d6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fdbd0432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdbd04330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdbd04330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005579a02d6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon-tbl.c (380 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon-tbl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | %struct.int8x8x2_t = type { [2 x <8 x i8>] } # | %struct.int8x16x2_t = type { [2 x <16 x i8>] } # | %struct.int8x8x3_t = type { [3 x <8 x i8>] } # | %struct.int8x16x3_t = type { [3 x <16 x i8>] } # | %struct.int8x8x4_t = type { [4 x <8 x i8>] } # | %struct.int8x16x4_t = type { [4 x <16 x i8>] } # | %struct.uint8x8x2_t = type { [2 x <8 x i8>] } # | %struct.uint8x16x2_t = type { [2 x <16 x i8>] } # | %struct.uint8x8x3_t = type { [3 x <8 x i8>] } # | %struct.uint8x16x3_t = type { [3 x <16 x i8>] } # | %struct.uint8x8x4_t = type { [4 x <8 x i8>] } # | %struct.uint8x16x4_t = type { [4 x <16 x i8>] } # | %struct.poly8x8x2_t = type { [2 x <8 x i8>] } # | %struct.poly8x16x2_t = type { [2 x <16 x i8>] } # | %struct.poly8x8x3_t = type { [3 x <8 x i8>] } # | %struct.poly8x16x3_t = type { [3 x <16 x i8>] } # | %struct.poly8x8x4_t = type { [4 x <8 x i8>] } # | %struct.poly8x16x4_t = type { [4 x <16 x i8>] } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vtbl1_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vtbl1.i = shufflevector <8 x i8> %2, <8 x i8> zeroinitializer, <16 x i32> # | %vtbl11.i = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %vtbl1.i, <8 x i8> %3) # | store <8 x i8> %vtbl11.i, ptr %ref.tmp.i, align 8 # | %4 = load <8 x i8>, ptr %ref.tmp.i, align 8 # | store <8 x i8> %4, ptr %__ret.i, align 8 # | %5 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vqtbl1_s8(<16 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 16 # | %b.addr = alloca <8 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 16 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vtbl1.i = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %2, <8 x i8> %3) # | store <8 x i8> %vtbl1.i, ptr %ref.tmp.i, align 8 # | %4 = load <8 x i8>, ptr %ref.tmp.i, align 8 # | store <8 x i8> %4, ptr %__ret.i, align 8 # | %5 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vtbl2_s8([2 x <8 x i8>] alignstack(8) %a.coerce, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.i = alloca %struct.int8x8x2_t, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a = alloca %struct.int8x8x2_t, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %coerce.dive = getelementptr inbounds nuw %struct.int8x8x2_t, ptr %a, i32 0, i32 0 # | store [2 x <8 x i8>] %a.coerce, ptr %coerce.dive, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %b.addr, align 8 # | %coerce.dive1 = getelementptr inbounds nuw %struct.int8x8x2_t, ptr %a, i32 0, i32 0 # | %1 = load [2 x <8 x i8>], ptr %coerce.dive1, align 8 # | store [2 x <8 x i8>] %1, ptr %__p0.i, align 8 # | store <8 x i8> %0, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.i, align 8 # | %arrayidx2.i = getelementptr inbounds [2 x <8 x i8>], ptr %__p0.i, i64 0, i64 1 # | %3 = load <8 x i8>, ptr %arrayidx2.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vtbl1.i = shufflevector <8 x i8> %2, <8 x i8> %3, <16 x i32> # | %vtbl13.i = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %vtbl1.i, <8 x i8> %4) # | store <8 x i8> %vtbl13.i, ptr %ref.tmp.i, align 8 # | %5 = load <8 x i8>, ptr %ref.tmp.i, align 8 # | store <8 x i8> %5, ptr %__ret.i, align 8 # | %6 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vqtbl2_s8([2 x <16 x i8>] alignstack(16) %a.coerce, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.i = alloca %struct.int8x16x2_t, align 16 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a = alloca %struct.int8x16x2_t, align 16 # | %b.addr = alloca <8 x i8>, align 8 # | %coerce.dive = getelementptr inbounds nuw %struct.int8x16x2_t, ptr %a, i32 0, i32 0 # | store [2 x <16 x i8>] %a.coerce, ptr %coerce.dive, align 16 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %b.addr, align 8 # | %coerce.dive1 = getelementptr inbounds nuw %struct.int8x16x2_t, ptr %a, i32 0, i32 0 # | %1 = load [2 x <16 x i8>], ptr %coerce.dive1, align 16 # | store [2 x <16 x i8>] %1, ptr %__p0.i, align 16 # | store <8 x i8> %0, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.i, align 16 # | %arrayidx2.i = getelementptr inbounds [2 x <16 x i8>], ptr %__p0.i, i64 0, i64 1 # | %3 = load <16 x i8>, ptr %arrayidx2.i, align 16 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vtbl2.i = call <8 x i8> @llvm.aarch64.neon.tbl2.v8i8(<16 x i8> %2, <16 x i8> %3, <8 x i8> %4) # | store <8 x i8> %vtbl2.i, ptr %ref.tmp.i, align 8 # | %5 = load <8 x i8>, ptr %ref.tmp.i, align 8 # | store <8 x i8> %5, ptr %__ret.i, align 8 # | %6 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vtbl3_s8([3 x <8 x i8>] alignstack(8) %a.coerce, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.i = alloca %struct.int8x8x3_t, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a = alloca %struct.int8x8x3_t, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %coerce.dive = getelementptr inbounds nuw %struct.int8x8x3_t, ptr %a, i32 0, i32 0 # | store [3 x <8 x i8>] %a.coerce, ptr %coerce.dive, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %b.addr, align 8 # | %coerce.dive1 = getelementptr inbounds nuw %struct.int8x8x3_t, ptr %a, i32 0, i32 0 # | %1 = load [3 x <8 x i8>], ptr %coerce.dive1, align 8 # | store [3 x <8 x i8>] %1, ptr %__p0.i, align 8 # | store <8 x i8> %0, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.i, align 8 # | %arrayidx2.i = getelementptr inbounds [3 x <8 x i8>], ptr %__p0.i, i64 0, i64 1 # | %3 = load <8 x i8>, ptr %arrayidx2.i, align 8 # | %arrayidx4.i = getelementptr inbounds [3 x <8 x i8>], ptr %__p0.i, i64 0, i64 2 # | %4 = load <8 x i8>, ptr %arrayidx4.i, align 8 # | %5 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vtbl2.i = shufflevector <8 x i8> %2, <8 x i8> %3, <16 x i32> # | %vtbl25.i = shufflevector <8 x i8> %4, <8 x i8> zeroinitializer, <16 x i32> # | %vtbl26.i = call <8 x i8> @llvm.aarch64.neon.tbl2.v8i8(<16 x i8> %vtbl2.i, <16 x i8> %vtbl25.i, <8 x i8> %5) # | store <8 x i8> %vtbl26.i, ptr %ref.tmp.i, align 8 # | %6 = load <8 x i8>, ptr %ref.tmp.i, align 8 # | store <8 x i8> %6, ptr %__ret.i, align 8 # | %7 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vqtbl3_s8([3 x <16 x i8>] alignstack(16) %a.coerce, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.i = alloca %struct.int8x16x3_t, align 16 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a = alloca %struct.int8x16x3_t, align 16 # | %b.addr = alloca <8 x i8>, align 8 # | %coerce.dive = getelementptr inbounds nuw %struct.int8x16x3_t, ptr %a, i32 0, i32 0 # | store [3 x <16 x i8>] %a.coerce, ptr %coerce.dive, align 16 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %b.addr, align 8 # | %coerce.dive1 = getelementptr inbounds nuw %struct.int8x16x3_t, ptr %a, i32 0, i32 0 # | %1 = load [3 x <16 x i8>], ptr %coerce.dive1, align 16 # | store [3 x <16 x i8>] %1, ptr %__p0.i, align 16 # | store <8 x i8> %0, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.i, align 16 # | %arrayidx2.i = getelementptr inbounds [3 x <16 x i8>], ptr %__p0.i, i64 0, i64 1 # | %3 = load <16 x i8>, ptr %arrayidx2.i, align 16 # | %arrayidx4.i = getelementptr inbounds [3 x <16 x i8>], ptr %__p0.i, i64 0, i64 2 # | %4 = load <16 x i8>, ptr %arrayidx4.i, align 16 # | %5 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vtbl3.i = call <8 x i8> @llvm.aarch64.neon.tbl3.v8i8(<16 x i8> %2, <16 x i8> %3, <16 x i8> %4, <8 x i8> %5) # | store <8 x i8> %vtbl3.i, ptr %ref.tmp.i, align 8 # | %6 = load <8 x i8>, ptr %ref.tmp.i, align 8 # | store <8 x i8> %6, ptr %__ret.i, align 8 # | %7 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vtbl4_s8([4 x <8 x i8>] alignstack(8) %a.coerce, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.i = alloca %struct.int8x8x4_t, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a = alloca %struct.int8x8x4_t, align 8 # | %b.a # | ... # `---data was truncated (10240/125901) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557e1f2a557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557e1f2a2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557e1f2a5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f29d4133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f29d418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f29d4133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f29d411b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557e1f23b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557e1f23b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557e1f21ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557e1eecf176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557e1eecee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f29d411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f29d411d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f29d411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557e1eeced81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon/getset.c (381 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon/getset.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c --check-prefixes=ALL,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local i8 @test_vget_lane_u8(<8 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %__ret = alloca i8, align 1 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | %vget_lane = extractelement <8 x i8> %1, i32 7 # | store i8 %vget_lane, ptr %ref.tmp, align 1 # | %2 = load i8, ptr %ref.tmp, align 1 # | store i8 %2, ptr %__ret, align 1 # | %3 = load i8, ptr %__ret, align 1 # | store i8 %3, ptr %tmp, align 1 # | %4 = load i8, ptr %tmp, align 1 # | ret i8 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vget_lane_u16(<4 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i16>, align 8 # | %__ret = alloca i16, align 2 # | %__s0 = alloca <4 x i16>, align 8 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__s0, align 8 # | %1 = load <4 x i16>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x i16> %1, i32 3 # | store i16 %vget_lane, ptr %ref.tmp, align 2 # | %2 = load i16, ptr %ref.tmp, align 2 # | store i16 %2, ptr %__ret, align 2 # | %3 = load i16, ptr %__ret, align 2 # | store i16 %3, ptr %tmp, align 2 # | %4 = load i16, ptr %tmp, align 2 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_vget_lane_u32(<2 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i32>, align 8 # | %__ret = alloca i32, align 4 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__s0, align 8 # | %1 = load <2 x i32>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x i32> %1, i32 1 # | store i32 %vget_lane, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i8 @test_vget_lane_s8(<8 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %__ret = alloca i8, align 1 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | %vget_lane = extractelement <8 x i8> %1, i32 7 # | store i8 %vget_lane, ptr %ref.tmp, align 1 # | %2 = load i8, ptr %ref.tmp, align 1 # | store i8 %2, ptr %__ret, align 1 # | %3 = load i8, ptr %__ret, align 1 # | store i8 %3, ptr %tmp, align 1 # | %4 = load i8, ptr %tmp, align 1 # | ret i8 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vget_lane_s16(<4 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i16>, align 8 # | %__ret = alloca i16, align 2 # | %__s0 = alloca <4 x i16>, align 8 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__s0, align 8 # | %1 = load <4 x i16>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x i16> %1, i32 3 # | store i16 %vget_lane, ptr %ref.tmp, align 2 # | %2 = load i16, ptr %ref.tmp, align 2 # | store i16 %2, ptr %__ret, align 2 # | %3 = load i16, ptr %__ret, align 2 # | store i16 %3, ptr %tmp, align 2 # | %4 = load i16, ptr %tmp, align 2 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_vget_lane_s32(<2 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i32>, align 8 # | %__ret = alloca i32, align 4 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__s0, align 8 # | %1 = load <2 x i32>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x i32> %1, i32 1 # | store i32 %vget_lane, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i8 @test_vget_lane_p8(<8 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %__ret = alloca i8, align 1 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | %vget_lane = extractelement <8 x i8> %1, i32 7 # | store i8 %vget_lane, ptr %ref.tmp, align 1 # | %2 = load i8, ptr %ref.tmp, align 1 # | store i8 %2, ptr %__ret, align 1 # | %3 = load i8, ptr %__ret, align 1 # | store i8 %3, ptr %tmp, align 1 # | %4 = load i8, ptr %tmp, align 1 # | ret i8 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vget_lane_p16(<4 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i16>, align 8 # | %__ret = alloca i16, align 2 # | %__s0 = alloca <4 x i16>, align 8 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__s0, align 8 # | %1 = load <4 x i16>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x i16> %1, i32 3 # | store i16 %vget_lane, ptr %ref.tmp, align 2 # | %2 = load i16, ptr %ref.tmp, align 2 # | store i16 %2, ptr %__ret, align 2 # | %3 = load i16, ptr %__ret, align 2 # | store i16 %3, ptr %tmp, align 2 # | %4 = load i16, ptr %tmp, align 2 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i8> @test_vget_lane_mf8(<8 x i8> %a) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <1 x i8>, align 1 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <1 x i8>, align 1 # | %tmp = alloca <1 x i8>, align 1 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | %vget_lane = extractelement <8 x i8> %1, i32 7 # | store i8 %vget_lane, ptr %ref.tmp, align 1 # | %2 = load <1 x i8>, ptr %ref.tmp, align 1 # | store <1 x i8> %2, ptr %__ret, align 1 # | %3 = load <1 x i8>, ptr %__ret, align 1 # | store <1 x i8> %3, ptr %tmp, align 1 # | %4 = load <1 x i8>, ptr %tmp, align 1 # | ret <1 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vget_lane_f16(<4 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x half>, align 8 # | %__ret_847 = alloca half, align 2 # | %__s0_847 = alloca <4 x half>, align 8 # | %ref.tmp = alloca i16, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca <4 x i16>, align 8 # | %ref.tmp1 = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | %tmp2 = alloca half, align 2 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__s0_847, align 8 # | %1 = load <4 x i16>, ptr %__s0_847, align 8 # | store <4 x i16> %1, ptr %__s0, align 8 # | %2 = load <4 x i16>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x i16> %2, i32 1 # | store i16 %vget_lane, ptr %ref.tmp1, align 2 # | %3 = load i16, ptr %ref.tmp1, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | store i16 %5, ptr %ref.tmp, align 2 # | %6 = load half, ptr %ref.tmp, align 2 # | store half %6, ptr %__ret_847, align 2 # | %7 = load half, ptr %__ret_847, align 2 # | store half %7, ptr %tmp2, align 2 # | %8 = load half, ptr %tmp2, align 2 # | %conv = fpext half %8 to float # | ret float %conv # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vget_lane_f32(<2 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x float>, align 8 # | %__ret = alloca float, align 4 # | %__s0 = alloca <2 x float>, align 8 # | %ref.tmp = alloca float, align 4 # | %tmp = alloca float, align 4 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__s0, align 8 # | %1 = load <2 x float>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x float> %1, i32 1 # | store float %vget_lane, ptr %ref.tmp, align 4 # | %2 = load float, ptr %ref.tmp, align 4 # | store float %2, ptr %__ret, align 4 # | %3 = load float, ptr %__ret, align 4 # | store float %3, ptr %tmp, align 4 # | %4 = load float, ptr %tmp, align 4 # | ret float %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_vget_lane_f64(<1 x double> noundef %a) #0 { # | entry: # | %a.addr = alloca <1 x double>, align 8 # | %__ret = alloca double, align 8 # | %__s0 = alloca <1 x double>, align 8 # | %ref.tmp = alloca double, align 8 # | %tmp = alloca double, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__s0, align 8 # | %1 = load <1 x double>, ptr %__s0, align 8 # | %vget_lane = extractelement <1 x double> %1, i32 0 # | store double %vget_lane, ptr %ref.tmp, align 8 # | %2 = load double, ptr %ref.tmp, align 8 # | store double %2, ptr %__ret, align 8 # | %3 = load double, ptr %__ret, align 8 # | store double %3, ptr %tmp, align 8 # | %4 = load double, ptr %tmp, align 8 # | ret double %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i8 @test_vgetq_lane_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 16 # | %__ret = alloca i8, align 1 # | %__s0 = alloca <16 x i8>, align 16 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__s0, align # | ... # `---data was truncated (10240/76998) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055866076557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558660762515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558660765cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9344533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f934458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9344533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f934451b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005586606fb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005586606fb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005586606dff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055866038f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055866038ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f934451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f934451d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f934451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055866038ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c --check-prefixes=ALL,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c --check-prefixes=ALL,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c (382 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfdot_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfdot( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfdot(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfdot_lane_0_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfdot.lane.v2( %0, %1, %2, i32 0) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfdot.lane.v2(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfdot_lane_3_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfdot.lane.v2( %0, %1, %2, i32 3) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfdot_n_f32( %x, %y, bfloat noundef %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca bfloat, align 2 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store bfloat %z, ptr %z.addr, align 2 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load bfloat, ptr %z.addr, align 2 # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.bfdot( %0, %1, %.splat) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055d5aba9457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d5aba91515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d5aba94cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efc8d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efc8d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efc8d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efc8d51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d5aba2a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d5aba2a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d5aba0ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d5ab6be176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d5ab6bde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efc8d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efc8d51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efc8d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d5ab6bdd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c (383 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +lut -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +lut -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | %struct.mfloat8x8x2_t = type { [2 x <8 x i8>] } # | %struct.mfloat8x8x3_t = type { [3 x <8 x i8>] } # | %struct.mfloat8x8x4_t = type { [4 x <8 x i8>] } # | %struct.mfloat8x16x2_t = type { [2 x <16 x i8>] } # | %struct.mfloat8x16x3_t = type { [3 x <16 x i8>] } # | %struct.mfloat8x16x4_t = type { [4 x <16 x i8>] } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vcreate_mf8(i64 noundef %a) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__promote = alloca i64, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | store i64 %0, ptr %__promote, align 8 # | %1 = load <8 x i8>, ptr %__promote, align 8 # | store <8 x i8> %1, ptr %__ret, align 8 # | %2 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %2, ptr %tmp, align 8 # | %3 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vdup_n_mf8(<1 x i8> %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i8>, align 1 # | %__ret.i = alloca <8 x i8>, align 8 # | %.compoundliteral.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x i8>, align 1 # | store <1 x i8> %a, ptr %a.addr, align 1 # | %0 = load <1 x i8>, ptr %a.addr, align 1 # | store <1 x i8> %0, ptr %__p0.addr.i, align 1 # | %1 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext.i = shufflevector <1 x i8> %1, <1 x i8> poison, <8 x i32> # | %vecinit.i = shufflevector <8 x i8> %vext.i, <8 x i8> poison, <8 x i32> # | %2 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext1.i = shufflevector <1 x i8> %2, <1 x i8> poison, <8 x i32> # | %vecinit2.i = shufflevector <8 x i8> %vecinit.i, <8 x i8> %vext1.i, <8 x i32> # | %3 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext3.i = shufflevector <1 x i8> %3, <1 x i8> poison, <8 x i32> # | %vecinit4.i = shufflevector <8 x i8> %vecinit2.i, <8 x i8> %vext3.i, <8 x i32> # | %4 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext5.i = shufflevector <1 x i8> %4, <1 x i8> poison, <8 x i32> # | %vecinit6.i = shufflevector <8 x i8> %vecinit4.i, <8 x i8> %vext5.i, <8 x i32> # | %5 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext7.i = shufflevector <1 x i8> %5, <1 x i8> poison, <8 x i32> # | %vecinit8.i = shufflevector <8 x i8> %vecinit6.i, <8 x i8> %vext7.i, <8 x i32> # | %6 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext9.i = shufflevector <1 x i8> %6, <1 x i8> poison, <8 x i32> # | %vecinit10.i = shufflevector <8 x i8> %vecinit8.i, <8 x i8> %vext9.i, <8 x i32> # | %7 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext11.i = shufflevector <1 x i8> %7, <1 x i8> poison, <8 x i32> # | %vecinit12.i = shufflevector <8 x i8> %vecinit10.i, <8 x i8> %vext11.i, <8 x i32> # | %8 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext13.i = shufflevector <1 x i8> %8, <1 x i8> poison, <8 x i32> # | %vecinit14.i = shufflevector <8 x i8> %vecinit12.i, <8 x i8> %vext13.i, <8 x i32> # | store <8 x i8> %vecinit14.i, ptr %.compoundliteral.i, align 8 # | %9 = load <8 x i8>, ptr %.compoundliteral.i, align 8 # | store <8 x i8> %9, ptr %__ret.i, align 8 # | %10 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vdupq_n_mf8(<1 x i8> %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i8>, align 1 # | %__ret.i = alloca <16 x i8>, align 16 # | %.compoundliteral.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <1 x i8>, align 1 # | store <1 x i8> %a, ptr %a.addr, align 1 # | %0 = load <1 x i8>, ptr %a.addr, align 1 # | store <1 x i8> %0, ptr %__p0.addr.i, align 1 # | %1 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext.i = shufflevector <1 x i8> %1, <1 x i8> poison, <16 x i32> # | %vecinit.i = shufflevector <16 x i8> %vext.i, <16 x i8> poison, <16 x i32> # | %2 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext1.i = shufflevector <1 x i8> %2, <1 x i8> poison, <16 x i32> # | %vecinit2.i = shufflevector <16 x i8> %vecinit.i, <16 x i8> %vext1.i, <16 x i32> # | %3 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext3.i = shufflevector <1 x i8> %3, <1 x i8> poison, <16 x i32> # | %vecinit4.i = shufflevector <16 x i8> %vecinit2.i, <16 x i8> %vext3.i, <16 x i32> # | %4 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext5.i = shufflevector <1 x i8> %4, <1 x i8> poison, <16 x i32> # | %vecinit6.i = shufflevector <16 x i8> %vecinit4.i, <16 x i8> %vext5.i, <16 x i32> # | %5 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext7.i = shufflevector <1 x i8> %5, <1 x i8> poison, <16 x i32> # | %vecinit8.i = shufflevector <16 x i8> %vecinit6.i, <16 x i8> %vext7.i, <16 x i32> # | %6 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext9.i = shufflevector <1 x i8> %6, <1 x i8> poison, <16 x i32> # | %vecinit10.i = shufflevector <16 x i8> %vecinit8.i, <16 x i8> %vext9.i, <16 x i32> # | %7 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext11.i = shufflevector <1 x i8> %7, <1 x i8> poison, <16 x i32> # | %vecinit12.i = shufflevector <16 x i8> %vecinit10.i, <16 x i8> %vext11.i, <16 x i32> # | %8 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext13.i = shufflevector <1 x i8> %8, <1 x i8> poison, <16 x i32> # | %vecinit14.i = shufflevector <16 x i8> %vecinit12.i, <16 x i8> %vext13.i, <16 x i32> # | %9 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext15.i = shufflevector <1 x i8> %9, <1 x i8> poison, <16 x i32> # | %vecinit16.i = shufflevector <16 x i8> %vecinit14.i, <16 x i8> %vext15.i, <16 x i32> ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c (384 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_i8mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef # | ... # `---data was truncated (10240/69988) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ec6555757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ec65554515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ec65557cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1aa321bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1aa32725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1aa321ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1aa3203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ec654ed24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ec654ed096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ec654d1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ec65181176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ec65180e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1aa3204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1aa32050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1aa32050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ec65180d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c (385 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562de922257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562de921f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562de9222cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8c18e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8c18ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8c18e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8c18e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562de91b824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562de91b8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562de919cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562de8e4c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562de8e4be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8c18e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8c18e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8c18e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562de8e4bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/arm_neon_intrinsics.c (386 of 27911) ******************** TEST 'Clang :: CodeGen/arm_neon_intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7s-apple-darwin -target-abi apcs-gnu -target-cpu swift -target-feature +fullfp16 -ffreestanding -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7s-apple-darwin -target-abi apcs-gnu -target-cpu swift -target-feature +fullfp16 -ffreestanding -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c" # | target datalayout = "e-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" # | target triple = "thumbv7s-apple-darwin" # | # | %struct.uint8x16x2_t = type { [2 x <16 x i8>] } # | %struct.uint16x8x2_t = type { [2 x <8 x i16>] } # | %struct.uint32x4x2_t = type { [2 x <4 x i32>] } # | %struct.int8x16x2_t = type { [2 x <16 x i8>] } # | %struct.int16x8x2_t = type { [2 x <8 x i16>] } # | %struct.int32x4x2_t = type { [2 x <4 x i32>] } # | %struct.float16x8x2_t = type { [2 x <8 x half>] } # | %struct.float32x4x2_t = type { [2 x <4 x float>] } # | %struct.poly8x16x2_t = type { [2 x <16 x i8>] } # | %struct.poly16x8x2_t = type { [2 x <8 x i16>] } # | %struct.uint8x8x2_t = type { [2 x <8 x i8>] } # | %struct.uint16x4x2_t = type { [2 x <4 x i16>] } # | %struct.uint32x2x2_t = type { [2 x <2 x i32>] } # | %struct.uint64x1x2_t = type { [2 x <1 x i64>] } # | %struct.int8x8x2_t = type { [2 x <8 x i8>] } # | %struct.int16x4x2_t = type { [2 x <4 x i16>] } # | %struct.int32x2x2_t = type { [2 x <2 x i32>] } # | %struct.int64x1x2_t = type { [2 x <1 x i64>] } # | %struct.float16x4x2_t = type { [2 x <4 x half>] } # | %struct.float32x2x2_t = type { [2 x <2 x float>] } # | %struct.poly8x8x2_t = type { [2 x <8 x i8>] } # | %struct.poly16x4x2_t = type { [2 x <4 x i16>] } # | %struct.uint8x16x3_t = type { [3 x <16 x i8>] } # | %struct.uint16x8x3_t = type { [3 x <8 x i16>] } # | %struct.uint32x4x3_t = type { [3 x <4 x i32>] } # | %struct.int8x16x3_t = type { [3 x <16 x i8>] } # | %struct.int16x8x3_t = type { [3 x <8 x i16>] } # | %struct.int32x4x3_t = type { [3 x <4 x i32>] } # | %struct.float16x8x3_t = type { [3 x <8 x half>] } # | %struct.float32x4x3_t = type { [3 x <4 x float>] } # | %struct.poly8x16x3_t = type { [3 x <16 x i8>] } # | %struct.poly16x8x3_t = type { [3 x <8 x i16>] } # | %struct.uint8x8x3_t = type { [3 x <8 x i8>] } # | %struct.uint16x4x3_t = type { [3 x <4 x i16>] } # | %struct.uint32x2x3_t = type { [3 x <2 x i32>] } # | %struct.uint64x1x3_t = type { [3 x <1 x i64>] } # | %struct.int8x8x3_t = type { [3 x <8 x i8>] } # | %struct.int16x4x3_t = type { [3 x <4 x i16>] } # | %struct.int32x2x3_t = type { [3 x <2 x i32>] } # | %struct.int64x1x3_t = type { [3 x <1 x i64>] } # | %struct.float16x4x3_t = type { [3 x <4 x half>] } # | %struct.float32x2x3_t = type { [3 x <2 x float>] } # | %struct.poly8x8x3_t = type { [3 x <8 x i8>] } # | %struct.poly16x4x3_t = type { [3 x <4 x i16>] } # | %struct.uint8x16x4_t = type { [4 x <16 x i8>] } # | %struct.uint16x8x4_t = type { [4 x <8 x i16>] } # | %struct.uint32x4x4_t = type { [4 x <4 x i32>] } # | %struct.int8x16x4_t = type { [4 x <16 x i8>] } # | %struct.int16x8x4_t = type { [4 x <8 x i16>] } # | %struct.int32x4x4_t = type { [4 x <4 x i32>] } # | %struct.float16x8x4_t = type { [4 x <8 x half>] } # | %struct.float32x4x4_t = type { [4 x <4 x float>] } # | %struct.poly8x16x4_t = type { [4 x <16 x i8>] } # | %struct.poly16x8x4_t = type { [4 x <8 x i16>] } # | %struct.uint8x8x4_t = type { [4 x <8 x i8>] } # | %struct.uint16x4x4_t = type { [4 x <4 x i16>] } # | %struct.uint32x2x4_t = type { [4 x <2 x i32>] } # | %struct.uint64x1x4_t = type { [4 x <1 x i64>] } # | %struct.int8x8x4_t = type { [4 x <8 x i8>] } # | %struct.int16x4x4_t = type { [4 x <4 x i16>] } # | %struct.int32x2x4_t = type { [4 x <2 x i32>] } # | %struct.int64x1x4_t = type { [4 x <1 x i64>] } # | %struct.float16x4x4_t = type { [4 x <4 x half>] } # | %struct.float32x2x4_t = type { [4 x <2 x float>] } # | %struct.poly8x8x4_t = type { [4 x <8 x i8>] } # | %struct.poly16x4x4_t = type { [4 x <4 x i16>] } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @test_vaba_s8(<8 x i8> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i1 = alloca <8 x i8>, align 8 # | %__p1.addr.i2 = alloca <8 x i8>, align 8 # | %__ret.i3 = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %c.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | store <8 x i8> %c, ptr %c.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | %2 = load <8 x i8>, ptr %c.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | store <8 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | store <8 x i8> %4, ptr %__p0.addr.i1, align 8 # | store <8 x i8> %5, ptr %__p1.addr.i2, align 8 # | %6 = load <8 x i8>, ptr %__p0.addr.i1, align 8 # | %7 = load <8 x i8>, ptr %__p1.addr.i2, align 8 # | %vabd_v.i = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %6, <8 x i8> %7) # | store <8 x i8> %vabd_v.i, ptr %ref.tmp.i, align 8 # | %8 = load <8 x i8>, ptr %ref.tmp.i, align 8 # | store <8 x i8> %8, ptr %__ret.i3, align 8 # | %9 = load <8 x i8>, ptr %__ret.i3, align 8 # | %add.i = add <8 x i8> %3, %9 # | store <8 x i8> %add.i, ptr %__ret.i, align 8 # | %10 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define <4 x i16> @test_vaba_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %c) #0 { # | entry: # | %__p0.addr.i1 = alloca <4 x i16>, align 8 # | %__p1.addr.i2 = alloca <4 x i16>, align 8 # | %__ret.i3 = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__p2.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | %c.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | store <4 x i16> %c, ptr %c.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | %2 = load <4 x i16>, ptr %c.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | store <4 x i16> %2, ptr %__p2.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %4 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %5 = load <4 x i16>, ptr %__p2.addr.i, align 8 # | store <4 x i16> %4, ptr %__p0.addr.i1, align 8 # | store <4 x i16> %5, ptr %__p1.addr.i2, align 8 # | %6 = load <8 x i8>, ptr %__p0.addr.i1, align 8 # | %7 = load <8 x i8>, ptr %__p1.addr.i2, align 8 # | %vabd_v.i = bitcast <8 x i8> %6 to <4 x i16> # | %vabd_v1.i = bitcast <8 x i8> %7 to <4 x i16> # | %vabd_v2.i = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> %vabd_v.i, <4 x i16> %vabd_v1.i) # | %vabd_v3.i = bitcast <4 x i16> %vabd_v2.i to <8 x i8> # | store <8 x i8> %vabd_v3.i, ptr %ref.tmp.i, align 8 # | %8 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %8, ptr %__ret.i3, align 8 # | %9 = load <4 x i16>, ptr %__ret.i3, align 8 # | %add.i = add <4 x i16> %3, %9 # | store <4 x i16> %add.i, ptr %__ret.i, align 8 # | %10 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define <2 x i32> @test_vaba_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <2 x i32> noundef %c) #0 { # | entry: # | %__p0.addr.i1 = alloca <2 x i32>, align 8 # | %__p1.addr.i2 = alloca <2 x i32>, align 8 # | %__ret.i3 = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__p2.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <2 x i32>, align 8 # | %c.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <2 x i32> %b, ptr %b.addr, align 8 # | store <2 x i32> %c, ptr %c.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | %1 = load <2 x i32>, ptr %b.addr, align 8 # | %2 = load <2 x i32>, ptr %c.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | store <2 x i32> %2, ptr %__p2.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %4 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %5 = load <2 x i32>, ptr %__p2.addr.i, align 8 # | store <2 x i32> %4, ptr %__p0.addr.i1, align 8 # | store <2 x i32> %5, ptr %__p1.addr.i2, align 8 # | %6 = load <8 x i8>, ptr %__p0.addr.i1, align 8 # | %7 = load <8 x i8>, ptr %__p1.addr.i2, align 8 # | %vabd_v.i = bitcast <8 x i8> %6 to <2 x i32> # | %vabd_v1.i = bitcast <8 x i8> %7 to <2 x i32> # | %vabd_v2.i = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %vabd_v.i, <2 x i32> %vabd_v1.i) # | %vabd_v3.i = bitcast <2 x i32> %vabd_v2.i to <8 x i8> # | store <8 x i8> %vabd_v3.i, ptr %ref.tmp.i, align 8 # | %8 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %8, ptr %__ret.i3, align 8 # | %9 = load <2 x i32>, ptr %__ret.i3, align 8 # | %add.i = add <2 x i32> %3, %9 # | store <2 x i32> %add.i, ptr %__ret.i, align 8 # | %10 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @test_vaba_u8(<8 x i8> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i1 = alloca <8 x i8>, align 8 # | %__p1.addr.i2 = alloca <8 x i8>, align 8 # | %__ret.i3 = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %c.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | store <8 x i8> %c, ptr %c.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | %2 = load <8 x i8>, ptr %c.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | store <8 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | store <8 x i8> %4, pt # | ... # `---data was truncated (10240/2159854) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055d58794157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d58793e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d587941cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa6a6049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa6a60a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa6a6049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa6a6031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d5878d724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d5878d7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d5878bbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d58756b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d58756ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa6a6032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa6a60330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa6a60330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d58756ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/arm-bf16-reinterpret-intrinsics.c (387 of 27911) ******************** TEST 'Clang :: CodeGen/arm-bf16-reinterpret-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-arm-none-eabi -target-feature +neon -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-arm-none-eabi -target-feature +neon -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8.2a-arm-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_s8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_s16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_s32(<2 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_u8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_u16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_u32(<2 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_p8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_p16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_u64(<1 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_s64(<1 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_s8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 8 # | %__ret.i = alloca <8 x bfloat>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | store <16 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8 # | store <8 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 8 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_s16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 8 # | %__ret.i = alloca <8 x bfloat>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | store <8 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8 # | store <8 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 8 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_s32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 8 # | %__ret.i = alloca <8 x bfloat>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | store <4 x i32> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8 # | store <8 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 8 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <8 x bfloat>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8 # | store <8 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 8 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_u8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 8 # | %__ret.i = alloca <8 x bfloat>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | store <16 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8 # | store <8 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 8 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_u16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 8 # | %__ret.i = alloca <8 x bfloat>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | store <8 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8 # | store <8 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 8 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_u32(<4 x i32> nou # | ... # `---data was truncated (10240/28396) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine # | #0 0x0000560d494ef57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560d494ec515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560d494efcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f70f5e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f70f5ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f70f5e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f70f5e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560d4948524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560d49485096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560d49469f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560d49119176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560d49118e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f70f5e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f70f5e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f70f5e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560d49118d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c (388 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_bf16( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fclamp.nxv8bf16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fclamp.nxv8bf16(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16b16,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000564acefbe57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564acefbb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564acefbecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f22cde1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f22cde725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f22cde1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f22cde03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564acef5424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564acef54096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564acef38f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564acebe8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564acebe7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f22cde04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f22cde050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f22cde050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564acebe7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c (389 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vx_u16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wv_u16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wx_u16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.w.nxv1i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vx_u16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wv_u16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wx_u16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.w.nxv2i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vx_u16m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c (390 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_i8mf8x8_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp (391 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @in_zt0() #0 { # | entry: # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @out_zt0() #1 { # | entry: # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @inout_zt0() #2 { # | entry: # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @preserves_zt0() #3 { # | entry: # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @new_zt0() #4 { # | entry: # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @in_za_zt0() #5 { # | entry: # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @out_za_zt0() #6 { # | entry: # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @inout_za_zt0() #7 { # | entry: # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @preserves_za_zt0() #8 { # | entry: # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @new_za_zt0() #9 { # | entry: # | ret void # | } # | # | attributes #0 = { mustprogress noinline nounwind "aarch64_in_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { mustprogress noinline nounwind "aarch64_out_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #2 = { mustprogress noinline nounwind "aarch64_inout_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #3 = { mustprogress noinline nounwind "aarch64_preserves_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #4 = { mustprogress noinline nounwind "aarch64_new_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #5 = { mustprogress noinline nounwind "aarch64_in_za" "aarch64_in_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #6 = { mustprogress noinline nounwind "aarch64_out_za" "aarch64_out_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #7 = { mustprogress noinline nounwind "aarch64_inout_za" "aarch64_inout_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #8 = { mustprogress noinline nounwind "aarch64_preserves_za" "aarch64_preserves_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #9 = { mustprogress noinline nounwind "aarch64_new_za" "aarch64_new_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557f565e857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557f565e5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557f565e8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f211c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f211c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f211c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f211c631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557f5657e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557f5657e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557f56562f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557f56212176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557f56211e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f211c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f211c6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f211c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557f56211d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline # | #0 0x0000555b6ea1457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555b6ea11515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555b6ea14cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7ee2133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7ee218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7ee2133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7ee211b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555b6e9aa24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555b6e9aa096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555b6e98ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555b6e63e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555b6e63de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7ee211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7ee211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7ee211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555b6e63dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/fp8-extract.c (392 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-extract.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_var(<16 x i8> %v, i32 noundef %i) #0 { # | entry: # | %v.addr = alloca <16 x i8>, align 16 # | %i.addr = alloca i32, align 4 # | store <16 x i8> %v, ptr %v.addr, align 16 # | store i32 %i, ptr %i.addr, align 4 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | %1 = load i32, ptr %i.addr, align 4 # | %vecext = extractelement <16 x i8> %0, i32 %1 # | %mfp8ext = insertelement <1 x i8> poison, i8 %vecext, i64 0 # | call void @g(<1 x i8> %mfp8ext) # | ret void # | } # | # | declare void @g(<1 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_cst(<16 x i8> %v) #0 { # | entry: # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | %vecext = extractelement <16 x i8> %0, i32 3 # | %mfp8ext = insertelement <1 x i8> poison, i8 %vecext, i64 0 # | call void @g(<1 x i8> %mfp8ext) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine # | #0 0x000056209a1c757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056209a1c4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056209a1c7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f25d5f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f25d5f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f25d5f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f25d5f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056209a15d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056209a15d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056209a141f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562099df1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562099df0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f25d5f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f25d5f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f25d5f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562099df0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/len.c (393 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve/len.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_u8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 16 # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.vscale.i64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_s8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 16 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 8 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 8 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_f16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 8 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_bf16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 8 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 4 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 4 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_f32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 4 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 2 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 2 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_f64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 2 # | ret i64 %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x000055dd2228e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055dd2228b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055dd2228ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f420fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f420fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f420fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f420fc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dd2222424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055dd22224096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055dd22208f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055dd21eb8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055dd21eb7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f420fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f420fc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f420fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dd21eb7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c (394 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_bf16_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fmls.nxv8bf16( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmls.nxv8bf16(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_bf16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fmls.nxv8bf16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_bf16_x( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fmls.u.nxv8bf16( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmls.u.nxv8bf16(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_n_bf16_m( %pg, %op1, %op2, bfloat noundef %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store bfloat %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load bfloat, ptr %op3.addr, align 2 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %3, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmls.nxv8bf16( %4, %1, %2, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_n_bf16_z( %pg, %op1, %op2, bfloat noundef %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store bfloat %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load bfloat, ptr %op3.addr, align 2 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %3, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fmls.nxv8bf16( %4, %5, %2, %.splat) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_n_bf16_x( %pg, %op1, %op2, bfloat noundef %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store bfloat %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load bfloat, ptr %op3.addr, align 2 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %3, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmls.u.nxv8bf16( %4, %1, %2, %.splat) # | ret %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005603b3c7b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005603b3c78515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005603b3c7bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3cd5849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3cd58a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3cd5849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3cd5831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005603b3c1124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005603b3c11096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005603b3bf5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005603b38a5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005603b38a4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3cd5832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3cd58330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3cd58330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005603b38a4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c (395 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16mf4_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv1f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16mf2_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv2f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m1_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv4f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv4f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m2_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv8f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv8f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m4_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv16f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv16f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m8_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv32f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv32f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32mf2_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv1f32.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32m1_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv2f32.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32m2_tu( %maskedoff, %src, i64 noundef %offset # | ... # `---data was truncated (10240/287213) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fb46c6357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fb46c60515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fb46c63cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4ff1049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4ff10a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4ff1049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4ff1031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fb46bf924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fb46bf9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fb46bddf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fb4688d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fb4688ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4ff1032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4ff10330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4ff10330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fb4688cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c (396 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv32i8.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x # | ... # `---data was truncated (10240/164783) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560a8312e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560a8312b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560a8312ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8ced533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8ced58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8ced533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8ced51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560a830c424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560a830c4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560a830a8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560a82d58176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560a82d57e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8ced51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8ced51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8ced51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560a82d57d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c (397 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_bf16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmin.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmin.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_bf16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmin.nxv8bf16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_bf16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmin.u.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmin.u.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_bf16_n_m( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fmin.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_bf16_n_z( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmin.nxv8bf16( %3, %4, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_bf16_n_x( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fmin.u.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055eeb345d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055eeb345a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055eeb345dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd173933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd17398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd173933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd17391b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eeb33f324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055eeb33f3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055eeb33d7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055eeb3087176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055eeb3086e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd17391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd17391d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd17391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eeb3086d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c (398 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2_s8( %pg, ptr noundef %base, %data.coerce0, %data.coerce1) #0 { # | entry: # | %data = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %data.coerce0, 0 # | %1 = insertvalue { , } %0, %data.coerce1, 1 # | store { , } %1, ptr %data, align 16 # | %data1 = load { , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %data1, ptr %data.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %data.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | call void @llvm.aarch64.sve.st2.nxv16i8.p0( %5, %6, %2, ptr %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st2.nxv16i8.p0(, , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2_s16( %pg, ptr noundef %base, %data.coerce0, %data.coerce1) #0 { # | entry: # | %data = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %data.coerce0, 0 # | %1 = insertvalue { , } %0, %data.coerce1, 1 # | store { , } %1, ptr %data, align 16 # | %data1 = load { , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %data1, ptr %data.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %data.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %2) # | call void @llvm.aarch64.sve.st2.nxv8i16.p0( %5, %6, %7, ptr %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st2.nxv8i16.p0(, , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2_s32( %pg, ptr noundef %base, %data.coerce0, %data.coerce1) #0 { # | entry: # | %data = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %data.coerce0, 0 # | %1 = insertvalue { , } %0, %data.coerce1, 1 # | store { , } %1, ptr %data, align 16 # | %data1 = load { , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %data1, ptr %data.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %data.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %2) # | call void @llvm.aarch64.sve.st2.nxv4i32.p0( %5, %6, %7, ptr %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st2.nxv4i32.p0(, , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2_s64( %pg, ptr noundef %base, %data.coerce0, %data.coerce1) #0 { # | entry: # | %data = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %data.coerce0, 0 # | %1 = insertvalue { , } %0, %data.coerce1, 1 # | store { , } %1, ptr %data, align 16 # | %data1 = load { , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %data1, ptr %data.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %data.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %2) # | call void @llvm.aarch64.sve.st2.nxv2i64.p0( %5, %6, %7, ptr %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st2.nxv2i64.p0(, , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2_u8( %pg, ptr noundef %base, %data.coerce0, %data.coerce1) #0 { # | entry: # | %data = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %data.coerce0, 0 # | %1 = insertvalue { , } %0, %data.coerce1, 1 # | store { , } %1, ptr %data, align 16 # | %data1 = load { , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %data1, ptr %data.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %data.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | call void @llvm.aarch64.sve.st2.nxv16i8.p0( %5, %6, %2, ptr %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2_u16( %pg, ptr noundef %base, %data.coerce0, %data.coerce1) #0 { # | entry: # | %data = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %data.coerce0, 0 # | %1 = insertvalue { , } %0, %data.coerce1, 1 # | store { , } %1, ptr %data, align 16 # | %data1 = load { , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } # | ... # `---data was truncated (10240/45653) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005620b4b5a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005620b4b57515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005620b4b5acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2f04849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2f048a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2f04849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2f04831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005620b4af024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005620b4af0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005620b4ad4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005620b4784176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005620b4783e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2f04832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2f048330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2f048330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005620b4783d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c (399 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svcreate3_s8( %x0, %x1, %x2) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = insertvalue { , , } poison, %0, 0 # | %4 = insertvalue { , , } %3, %1, 1 # | %5 = insertvalue { , , } %4, %2, 2 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svcreate3_s16( %x0, %x1, %x2) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = insertvalue { , , } poison, %0, 0 # | %4 = insertvalue { , , } %3, %1, 1 # | %5 = insertvalue { , , } %4, %2, 2 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svcreate3_s32( %x0, %x1, %x2) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = insertvalue { , , } poison, %0, 0 # | %4 = insertvalue { , , } %3, %1, 1 # | %5 = insertvalue { , , } %4, %2, 2 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svcreate3_s64( %x0, %x1, %x2) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = insertvalue { , , } poison, %0, 0 # | %4 = insertvalue { , , } %3, %1, 1 # | %5 = insertvalue { , , } %4, %2, 2 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svcreate3_u8( %x0, %x1, %x2) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = insertvalue { , , } poison, %0, 0 # | %4 = insertvalue { , , } %3, %1, 1 # | %5 = insertvalue { , , } %4, %2, 2 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svcreate3_u16( %x0, %x1, %x2) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = insertvalue { , , } poison, %0, 0 # | %4 = insertvalue { , , } %3, %1, 1 # | %5 = insertvalue { , , } %4, %2, 2 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svcreate3_u32( %x0, %x1, %x2) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = insertvalue { , , } poison, %0, 0 # | %4 = insertvalue { , , } %3, %1, 1 # | %5 = insertvalue { , , } %4, %2, 2 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svcreate3_u64( %x0, %x1, %x2) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = insertvalue { , , } poison, %0, 0 # | %4 = insertvalue { , , } %3, %1, 1 # | %5 = insertvalue { , , } %4, %2, 2 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svcreate3_f16( %x0, %x1, %x2) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = insertvalue { , , } poison, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c (400 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svclamp_single_s8_x2( %op1.coerce0, %op1.coerce1, %op2, %op3) #0 { # | entry: # | %op1 = alloca { , }, align 16 # | %op1.addr = alloca { , }, align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %op1.coerce0, 0 # | %1 = insertvalue { , } %0, %op1.coerce1, 1 # | store { , } %1, ptr %op1, align 16 # | %op11 = load { , }, ptr %op1, align 16 # | store { , } %op11, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %2 = load { , }, ptr %op1.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %op2.addr, align 16 # | %6 = load , ptr %op3.addr, align 16 # | %7 = call { , } @llvm.aarch64.sve.sclamp.single.x2.nxv16i8( %3, %4, %5, %6) # | ret { , } %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sclamp.single.x2.nxv16i8(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svclamp_single_s16_x2( %op1.coerce0, %op1.coerce1, %op2, %op3) #0 { # | entry: # | %op1 = alloca { , }, align 16 # | %op1.addr = alloca { , }, align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %op1.coerce0, 0 # | %1 = insertvalue { , } %0, %op1.coerce1, 1 # | store { , } %1, ptr %op1, align 16 # | %op11 = load { , }, ptr %op1, align 16 # | store { , } %op11, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %2 = load { , }, ptr %op1.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %op2.addr, align 16 # | %6 = load , ptr %op3.addr, align 16 # | %7 = call { , } @llvm.aarch64.sve.sclamp.single.x2.nxv8i16( %3, %4, %5, %6) # | ret { , } %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sclamp.single.x2.nxv8i16(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svclamp_single_s32_x2( %op1.coerce0, %op1.coerce1, %op2, %op3) #0 { # | entry: # | %op1 = alloca { , }, align 16 # | %op1.addr = alloca { , }, align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %op1.coerce0, 0 # | %1 = insertvalue { , } %0, %op1.coerce1, 1 # | store { , } %1, ptr %op1, align 16 # | %op11 = load { , }, ptr %op1, align 16 # | store { , } %op11, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %2 = load { , }, ptr %op1.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %op2.addr, align 16 # | %6 = load , ptr %op3.addr, align 16 # | %7 = call { , } @llvm.aarch64.sve.sclamp.single.x2.nxv4i32( %3, %4, %5, %6) # | ret { , } %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sclamp.single.x2.nxv4i32(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svclamp_single_s64_x2( %op1.coerce0, %op1.coerce1, %op2, %op3) #0 { # | entry: # | %op1 = alloca { , }, align 16 # | %op1.addr = alloca { , }, align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %op1.coerce0, 0 # | %1 = insertvalue { , } %0, %op1.coerce1, 1 # | store { , } %1, ptr %op1, align 16 # | %op11 = load { , }, ptr %op1, align 16 # | store { , } %op11, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %2 = load { , }, ptr %op1.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %op2.addr, align 16 # | %6 = load , ptr %op3.addr, align 16 # | %7 = call { , } @llvm.aarch64.sve.sclamp.single.x2.nxv2i64( %3, %4, %5, %6) # | ret { , } %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sclamp.single.x2.nxv2i64(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svclamp_single_s8_x4( %op1.coerce0, %op1.coerce1, %op1.coerce2, %op1.coerce3, %op2, %op3) #0 { # | entry: # | %op1 = alloca { , , , }, align 16 # | %op1.addr = alloca { , , , }, align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %op1.coerce0, 0 # | %1 = insertvalue { , , , } %0, %op1.coerce1, 1 # | %2 = insertvalue { , , , } %1, %op1.coerce2, 2 # | %3 = insertvalue { , , , } %2, %op1.coerce3, 3 # | store { , , , } %3, ptr %op1, align 16 # | %op11 = load { , , , }, ptr %op1, align 16 # | store { , , , } %op11, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %4 = load { , , , }, ptr %op1.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c (401 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpge_s8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmpge.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpge.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpge_s16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmpge.nxv8i16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpge.nxv8i16(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpge_s32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmpge.nxv4i32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpge.nxv4i32(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpge_s64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.cmpge.nxv2i64( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpge.nxv2i64(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpge_u8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmphs.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphs.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpge_u16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmphs.nxv8i16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphs.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpge_u32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmphs.nxv4i32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphs.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpge_u64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, # | ... # `---data was truncated (10240/41923) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055fd16fb057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fd16fad515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fd16fb0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8e1c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8e1c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8e1c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8e1c031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fd16f4624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fd16f46096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fd16f2af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fd16bda176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fd16bd9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8e1c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8e1c0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8e1c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fd16bd9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c (402 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf4_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf2_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m1_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m2_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m4_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv16bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m8_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv32bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv32bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vle.mask.nxv1bf16.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vle.mask.nxv2bf16.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vle.mask.nxv4bf16.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m2_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl. # | ... # `---data was truncated (10240/24951) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562cf268857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562cf2685515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562cf2688cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa733705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa73375c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa733705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa7336ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562cf261e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562cf261e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562cf2602f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562cf22b2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562cf22b1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa7336eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa7336ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa7336ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562cf22b1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c (403 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpa_f16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.fexpa.x.nxv8f16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fexpa.x.nxv8f16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpa_f32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.fexpa.x.nxv4f32( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fexpa.x.nxv4f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpa_f64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.fexpa.x.nxv2f64( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fexpa.x.nxv2f64() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055b4193eb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b4193e8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b4193ebcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbc66c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbc66ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbc66c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbc66c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b41938124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b419381096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b419365f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b419015176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b419014e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbc66c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbc66c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbc66c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b419014d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c (404 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c (405 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svvdot_lane_za32_bf16_vg1x2(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.fvdot.lane.za32.vg1x2.nxv8bf16(i32 %2, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fvdot.lane.za32.vg1x2.nxv8bf16(i32, , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svvdot_lane_za32_f16_vg1x2(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.fvdot.lane.za32.vg1x2.nxv8f16(i32 %2, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fvdot.lane.za32.vg1x2.nxv8f16(i32, , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svvdot_lane_za32_s16_vg1x2(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.svdot.lane.za32.vg1x2.nxv8i16(i32 %2, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.svdot.lane.za32.vg1x2.nxv8i16(i32, , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svvdot_lane_za32_u16_vg1x2(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.uvdot.lane.za32.vg1x2.nxv8i16(i32 %2, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.uvdot.lane.za32.vg1x2.nxv8i16(i32, , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svvdot_lane_za32_s8_vg1x4(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , , , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , , , } %5, 0 # | %7 = extractvalue { , , , } %5, 1 # | %8 = extractvalue { , , , } %5, 2 # | %9 = extractvalue { , , , } %5, 3 # | %10 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.svdot.lane.za32.vg1x4.nxv16i8(i32 %4, %6, %7, %8, %9, %10, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.svdot.lane.za32.vg1x4.nxv16i8(i32, , , , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | ... # `---data was truncated (10240/24605) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055d6a889857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d6a8895515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d6a8898cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8fbd733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8fbd78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8fbd733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8fbd71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d6a882e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d6a882e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d6a8812f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d6a84c2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d6a84c1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8fbd71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8fbd71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8fbd71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d6a84c1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c (406 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64( %1, ptr %2, %3, %0, i64 %4, i # | ... # `---data was truncated (10240/25624) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561a30aea57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561a30ae7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561a30aeacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd7c0533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd7c058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd7c0533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd7c051b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561a30a8024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561a30a80096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561a30a64f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561a30714176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561a30713e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd7c051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd7c051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd7c051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561a30713d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c (407 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintp_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frintp.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintp.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintp_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frintp.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintp.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintp_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frintp.nxv2f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintp.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintp_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.frintp.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintp_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.frintp.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintp_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.frintp.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintp_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frintp.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintp_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frintp.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintp_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frintp.nxv2f64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000556c1250557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556c12502515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556c12505cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa21f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa21f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa21f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa21f31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556c1249b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556c1249b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556c1247ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556c1212f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556c1212ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa21f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa21f31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa21f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556c1212ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c (408 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svsub_write_single2_s32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv4i32(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv4i32(i32, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svsub_write_single2_u32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv4i32(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svsub_write_single2_s64(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv2i64(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv2i64(i32, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svsub_write_single2_u64(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv2i64(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svsub_write_single4_s32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , , , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , , , } %5, 0 # | %7 = extractvalue { , , , } %5, 1 # | %8 = extractvalue { , , , } %5, 2 # | %9 = extractvalue { , , , } %5, 3 # | %10 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.sub.write.single.za.vg1x4.nxv4i32(i32 %4, %6, %7, %8, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.sub.write.single.za.vg1x4.nxv4i32(i32, , , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svsub_write_single4_u32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/maxv.c (409 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve/maxv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svmaxv_s8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.smaxv.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i8 @llvm.aarch64.sve.smaxv.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svmaxv_s16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.smaxv.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.aarch64.sve.smaxv.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svmaxv_s32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.smaxv.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.smaxv.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svmaxv_s64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.smaxv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.smaxv.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svmaxv_u8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.umaxv.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i8 @llvm.aarch64.sve.umaxv.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svmaxv_u16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.umaxv.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.aarch64.sve.umaxv.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svmaxv_u32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.umaxv.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.umaxv.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svmaxv_u64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.umaxv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.umaxv.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local half @test_svmaxv_f16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call half @llvm.aarch64.sve.fmaxv.nxv8f16( %2, %1) # | ret half %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.aarch64.sve.fmaxv.nxv8f16(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local float @test_svmaxv_f32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call float @llvm.aarch64.sve.fmaxv.nxv4f32( %2, %1) # | ret float %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.aarch64.sve.fmaxv.nxv4f32(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local double @test_svmaxv_f64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call double @llvm.aarch64.sve.fmaxv.nxv2f64( %2, %1) # | ret double %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.aarch64.sve.fmaxv.nxv2f64(, ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attribute # | ... # `---data was truncated (10240/10818) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x000055a85cc4657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a85cc43515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a85cc46cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f751b849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f751b8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f751b849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f751b831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a85cbdc24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a85cbdc096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a85cbc0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a85c870176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a85c86fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f751b832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f751b8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f751b8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a85c86fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c (410 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_i16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | # | ... # `---data was truncated (10240/100521) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005566672ad57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005566672aa515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005566672adcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f82ae333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f82ae38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f82ae333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f82ae31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055666724324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556667243096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556667227f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556666ed7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556666ed6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f82ae31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f82ae31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f82ae31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556666ed6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c (411 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_mf8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ldff1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv16i8.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_s8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ldff1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv8i16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv4i32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv2i64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_u8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ldff1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_f16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv8f16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv8f16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_f32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4f32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv4f32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_f64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2f64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv2f64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_vnum_mf8( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | # | ... # `---data was truncated (10240/64727) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055cfd78cb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cfd78c8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cfd78cbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5def649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5def6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5def649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5def631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cfd786124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cfd7861096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cfd7845f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cfd74f5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cfd74f4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5def632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5def6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5def6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cfd74f4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c (412 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv64i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv64i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv32i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv32i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv16i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv16i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv8i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv8i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv4i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv4i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv2i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv2i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv1i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv1i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsif.mask.nxv64i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsif.mask.nxv32i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsif.mask.nxv16i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsif.mask.nxv8i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b16_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsif.mask.nxv4i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree no # | ... # `---data was truncated (10240/13023) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055607e0ba57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055607e0b7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055607e0bacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd2d5333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd2d538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd2d5333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd2d531b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055607e05024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055607e050096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055607e034f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055607dce4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055607dce3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd2d531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd2d531d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd2d531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055607dce3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c (413 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextb_s16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.sxtb.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sxtb.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextb_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.sxtb.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sxtb.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextb_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.sxtb.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sxtb.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextb_u16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.uxtb.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uxtb.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextb_u32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.uxtb.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uxtb.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextb_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.uxtb.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uxtb.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextb_s16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.sxtb.nxv8i16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextb_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.sxtb.nxv4i32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextb_s64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.sxtb.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextb_u16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.ad # | ... # `---data was truncated (10240/17434) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000561fae18c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561fae189515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561fae18ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9397f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9397f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9397f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9397f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561fae12224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561fae122096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561fae106f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561faddb6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561faddb5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9397f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9397f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9397f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561faddb5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c (414 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf4_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load , ptr %vs1.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 # | ... # `---data was truncated (10240/32709) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056111388157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056111387e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561113881cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3661b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3661b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3661b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3661b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056111381724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561113817096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005611137fbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005611134ab176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005611134aae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3661b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3661b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3661b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005611134aad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c (415 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_f64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_f64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_i64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_i64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_u64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_u64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_f64m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_f64m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs # | ... # `---data was truncated (10240/15978) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c3b57e157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c3b57de515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c3b57e1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd834049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd8340a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd834049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd834031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c3b577724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c3b5777096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c3b575bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c3b540b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c3b540ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd834032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd8340330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd8340330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c3b540ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c (416 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv32i8.nxv32i8.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c (417 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_i32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_i32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_u32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_u32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32mf2x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("ri # | ... # `---data was truncated (10240/32023) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560c1262d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560c1262a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560c1262dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6af2b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6af2b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6af2b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6af2b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560c125c324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560c125c3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560c125a7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560c12257176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560c12256e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6af2b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6af2b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6af2b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560c12256d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c (418 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 # | ... # `---data was truncated (10240/66565) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055728e85b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055728e858515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055728e85bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f218cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f218cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f218cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f218cc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055728e7f124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055728e7f1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055728e7d5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055728e485176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055728e484e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f218cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f218cc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f218cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055728e484d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c (419 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmla_f16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmla.nxv8f16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmla.nxv8f16(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmla_f32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmla.nxv4f32( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmla.nxv4f32(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmla_f64_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmla.nxv2f64( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmla.nxv2f64(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmla_f16_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fnmla.nxv8f16( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmla_f32_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = call @llvm.aarch64.sve.fnmla.nxv4f32( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmla_f64_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = call @llvm.aarch64.sve.fnmla.nxv2f64( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmla_f16_x( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fnmla.u.nxv8f16( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind w # | ... # `---data was truncated (10240/26173) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000558da2cc557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558da2cc2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558da2cc5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff564933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff56498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff564933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff56491b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558da2c5b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558da2c5b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558da2c3ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558da28ef176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558da28eee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff56491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff56491d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff56491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558da28eed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c (420 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32m2x3_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c (421 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32mf2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m1x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32mf2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m1x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_u32mf2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_u32m1x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_u32m2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_u32m4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32mf2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | # | ... # `---data was truncated (10240/23061) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c1c382557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c1c3822515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c1c3825cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f82bdd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f82bdd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f82bdd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f82bdd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c1c37bb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c1c37bb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c1c379ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c1c344f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c1c344ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f82bdd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f82bdd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f82bdd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c1c344ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c (422 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c (423 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i32.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv2i32.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i32.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv2i32.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv2i32.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_gather_u64base_s64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64( %2, %1, i64 0) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(, , i64) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_gather_u64base_u64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64( %2, %1, i64 0) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_gather_s64offset_s64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ld1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = sext %4 to # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(, ptr, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_gather_s64offset_u64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ld1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = sext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_gather_u64offset_s64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ld1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = sext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_gather_u64offset_u64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ld1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = sext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_gather_u64base_offset_s64( %pg, %bases, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon/store.c (424 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon/store.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c --check-prefixes=ALL,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | %struct.float64x1x2_t = type { [2 x <1 x double>] } # | %struct.float64x1x3_t = type { [3 x <1 x double>] } # | %struct.float64x1x4_t = type { [4 x <1 x double>] } # | %struct.mfloat8x8x2_t = type { [2 x <8 x i8>] } # | %struct.mfloat8x8x3_t = type { [3 x <8 x i8>] } # | %struct.mfloat8x8x4_t = type { [4 x <8 x i8>] } # | %struct.poly64x1x2_t = type { [2 x <1 x i64>] } # | %struct.poly64x1x3_t = type { [3 x <1 x i64>] } # | %struct.poly64x1x4_t = type { [4 x <1 x i64>] } # | %struct.float64x2x2_t = type { [2 x <2 x double>] } # | %struct.float64x2x3_t = type { [3 x <2 x double>] } # | %struct.float64x2x4_t = type { [4 x <2 x double>] } # | %struct.mfloat8x16x2_t = type { [2 x <16 x i8>] } # | %struct.mfloat8x16x3_t = type { [3 x <16 x i8>] } # | %struct.mfloat8x16x4_t = type { [4 x <16 x i8>] } # | %struct.poly64x2x2_t = type { [2 x <2 x i64>] } # | %struct.poly64x2x3_t = type { [3 x <2 x i64>] } # | %struct.poly64x2x4_t = type { [4 x <2 x i64>] } # | %struct.float16x4x2_t = type { [2 x <4 x half>] } # | %struct.float32x2x2_t = type { [2 x <2 x float>] } # | %struct.poly16x4x2_t = type { [2 x <4 x i16>] } # | %struct.poly8x8x2_t = type { [2 x <8 x i8>] } # | %struct.int16x4x2_t = type { [2 x <4 x i16>] } # | %struct.int32x2x2_t = type { [2 x <2 x i32>] } # | %struct.int64x1x2_t = type { [2 x <1 x i64>] } # | %struct.int8x8x2_t = type { [2 x <8 x i8>] } # | %struct.uint16x4x2_t = type { [2 x <4 x i16>] } # | %struct.uint32x2x2_t = type { [2 x <2 x i32>] } # | %struct.uint64x1x2_t = type { [2 x <1 x i64>] } # | %struct.uint8x8x2_t = type { [2 x <8 x i8>] } # | %struct.float16x4x3_t = type { [3 x <4 x half>] } # | %struct.float32x2x3_t = type { [3 x <2 x float>] } # | %struct.poly16x4x3_t = type { [3 x <4 x i16>] } # | %struct.poly8x8x3_t = type { [3 x <8 x i8>] } # | %struct.int16x4x3_t = type { [3 x <4 x i16>] } # | %struct.int32x2x3_t = type { [3 x <2 x i32>] } # | %struct.int64x1x3_t = type { [3 x <1 x i64>] } # | %struct.int8x8x3_t = type { [3 x <8 x i8>] } # | %struct.uint16x4x3_t = type { [3 x <4 x i16>] } # | %struct.uint32x2x3_t = type { [3 x <2 x i32>] } # | %struct.uint64x1x3_t = type { [3 x <1 x i64>] } # | %struct.uint8x8x3_t = type { [3 x <8 x i8>] } # | %struct.float16x4x4_t = type { [4 x <4 x half>] } # | %struct.float32x2x4_t = type { [4 x <2 x float>] } # | %struct.poly16x4x4_t = type { [4 x <4 x i16>] } # | %struct.poly8x8x4_t = type { [4 x <8 x i8>] } # | %struct.int16x4x4_t = type { [4 x <4 x i16>] } # | %struct.int32x2x4_t = type { [4 x <2 x i32>] } # | %struct.int64x1x4_t = type { [4 x <1 x i64>] } # | %struct.int8x8x4_t = type { [4 x <8 x i8>] } # | %struct.uint16x4x4_t = type { [4 x <4 x i16>] } # | %struct.uint32x2x4_t = type { [4 x <2 x i32>] } # | %struct.uint64x1x4_t = type { [4 x <1 x i64>] } # | %struct.uint8x8x4_t = type { [4 x <8 x i8>] } # | %struct.float16x8x2_t = type { [2 x <8 x half>] } # | %struct.float32x4x2_t = type { [2 x <4 x float>] } # | %struct.poly16x8x2_t = type { [2 x <8 x i16>] } # | %struct.poly8x16x2_t = type { [2 x <16 x i8>] } # | %struct.int16x8x2_t = type { [2 x <8 x i16>] } # | %struct.int32x4x2_t = type { [2 x <4 x i32>] } # | %struct.int64x2x2_t = type { [2 x <2 x i64>] } # | %struct.int8x16x2_t = type { [2 x <16 x i8>] } # | %struct.uint16x8x2_t = type { [2 x <8 x i16>] } # | %struct.uint32x4x2_t = type { [2 x <4 x i32>] } # | %struct.uint64x2x2_t = type { [2 x <2 x i64>] } # | %struct.uint8x16x2_t = type { [2 x <16 x i8>] } # | %struct.float16x8x3_t = type { [3 x <8 x half>] } # | %struct.float32x4x3_t = type { [3 x <4 x float>] } # | %struct.poly16x8x3_t = type { [3 x <8 x i16>] } # | %struct.poly8x16x3_t = type { [3 x <16 x i8>] } # | %struct.int16x8x3_t = type { [3 x <8 x i16>] } # | %struct.int32x4x3_t = type { [3 x <4 x i32>] } # | %struct.int64x2x3_t = type { [3 x <2 x i64>] } # | %struct.int8x16x3_t = type { [3 x <16 x i8>] } # | %struct.uint16x8x3_t = type { [3 x <8 x i16>] } # | %struct.uint32x4x3_t = type { [3 x <4 x i32>] } # | %struct.uint64x2x3_t = type { [3 x <2 x i64>] } # | %struct.uint8x16x3_t = type { [3 x <16 x i8>] } # | %struct.float16x8x4_t = type { [4 x <8 x half>] } # | %struct.float32x4x4_t = type { [4 x <4 x float>] } # | %struct.poly16x8x4_t = type { [4 x <8 x i16>] } # | %struct.poly8x16x4_t = type { [4 x <16 x i8>] } # | %struct.int16x8x4_t = type { [4 x <8 x i16>] } # | %struct.int32x4x4_t = type { [4 x <4 x i32>] } # | %struct.int64x2x4_t = type { [4 x <2 x i64>] } # | %struct.int8x16x4_t = type { [4 x <16 x i8>] } # | %struct.uint16x8x4_t = type { [4 x <8 x i16>] } # | %struct.uint32x4x4_t = type { [4 x <4 x i32>] } # | %struct.uint64x2x4_t = type { [4 x <2 x i64>] } # | %struct.uint8x16x4_t = type { [4 x <16 x i8>] } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_f16(ptr noundef %a, <4 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %__s1 = alloca <4 x half>, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | %0 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | %3 = bitcast <8 x i8> %2 to <4 x half> # | store <4 x half> %3, ptr %1, align 2 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_f32(ptr noundef %a, <2 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <2 x float>, align 8 # | %__s1 = alloca <2 x float>, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %b.addr, align 8 # | store <2 x float> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | %3 = bitcast <8 x i8> %2 to <2 x float> # | store <2 x float> %3, ptr %1, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_f64(ptr noundef %a, <1 x double> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <1 x double>, align 8 # | %__s1 = alloca <1 x double>, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store <1 x double> %b, ptr %b.addr, align 8 # | %0 = load <1 x double>, ptr %b.addr, align 8 # | store <1 x double> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | %3 = bitcast <8 x i8> %2 to <1 x double> # | store <1 x double> %3, ptr %1, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_mf8(ptr noundef %a, <8 x i8> %val) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %val.addr = alloca <8 x i8>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store <8 x i8> %val, ptr %val.addr, align 8 # | %0 = load <8 x i8>, ptr %val.addr, align 8 # | store <8 x i8> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | store <8 x i8> %2, ptr %1, align 1 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_p16(ptr noundef %a, <4 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | %__s1 = alloca <4 x i16>, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | %0 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | %3 = bitcast <8 x i8> %2 to <4 x i16> # | store <4 x i16> %3, ptr %1, align 2 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_p64(ptr noundef %ptr, <1 x i64> noundef %val) #0 { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %val.addr = alloca <1 x i64>, align 8 # | %__s1 = alloca <1 x i64>, align 8 # | store ptr %ptr, ptr %ptr.addr, align 8 # | store <1 x i64> %val, ptr %val.addr, align 8 # | %0 = load <1 x i64>, ptr %val.addr, align 8 # | store <1 x i64> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %ptr.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | %3 = bitcast <8 x i8> %2 to <1 x i64> # | store <1 x i64> %3, ptr %1, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_p8(ptr noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | store <8 x i8> %2, ptr %1, align 1 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1q_f16(ptr noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <8 x half>, align 16 # | %__s1 = alloca <8 x half>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 16 # | %0 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %0, ptr %__s1, align 16 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %__s1, align 16 # | %3 = bitcast <16 x i8> %2 to <8 x half> # | store <8 x half> %3, ptr %1, align 2 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1q_f32(ptr noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <4 x float>, align 16 # | %__s1 = alloca <4 x float>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %b.addr, align 16 # | store <4 x float> %0, ptr %__s1, align 16 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %__s1, align 16 # | %3 = bitcast <16 x i8> %2 to <4 x float> # | store <4 x float> %3, ptr %1, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1q_f64(ptr noundef %a, <2 x double> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <2 x double>, align 16 # | %__s1 = alloca <2 x double>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | store <2 x double> %b, ptr %b.addr, align 16 # | %0 = load <2 x double>, ptr %b.addr, align 16 # | store <2 x double> %0, ptr %__s1, align 16 # | %1 = load ptr, ptr # | ... # `---data was truncated (10240/446007) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine # | #0 0x000055e6a149957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e6a1496515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e6a1499cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdb9da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdb9daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdb9da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdb9da31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e6a142f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e6a142f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e6a1413f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e6a10c3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e6a10c2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fdb9da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdb9da330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdb9da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e6a10c2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c --check-prefixes=ALL,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c --check-prefixes=ALL,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c (425 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vx_i8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vx_i8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vx_i8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vx_i8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv32i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv32i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vx_i8m4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 # | ... # `---data was truncated (10240/66065) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556cecda357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556cecda0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556cecda3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0bd0049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0bd00a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0bd0049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0bd0031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556cecd3924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556cecd39096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556cecd1df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556cec9cd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556cec9cce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0bd0032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0bd00330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0bd00330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556cec9ccd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c (426 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv32bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf4_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.mask.nxv1bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf2_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.mask.nxv2bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.mask.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m1_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr # | ... # `---data was truncated (10240/15320) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563f766fd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563f766fa515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563f766fdcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc58b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc58b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc58b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc58b91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563f7669324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563f76693096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563f76677f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563f76327176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563f76326e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc58b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc58b91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc58b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563f76326d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c (427 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_s8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.rbit.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.rbit.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_s16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.rbit.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.rbit.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.rbit.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.rbit.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.rbit.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.rbit.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_u8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.rbit.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_u16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.rbit.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_u32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.rbit.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.rbit.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_s8_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.rbit.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_s16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.rbit.nxv8i16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c (428 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf8_tu( %maskedoff, %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv1i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf4_tu( %maskedoff, %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv2i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf2_tu( %maskedoff, %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv4i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8m1_tu( %maskedoff, %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(, , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c (429 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e30b1a557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e30b1a2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e30b1a5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0bbaf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0bbaf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0bbaf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0bbaf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e30b13b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e30b13b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e30b11ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e30adcf176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e30adcee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0bbaf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0bbaf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0bbaf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e30adced81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c (430 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16mf4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16mf2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv16f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv32f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv32f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_i16mf4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1i16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_i16mf2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2i16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c (431 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_i8mf8x5 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558cfc35457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558cfc351515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558cfc354cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9905d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9905d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9905d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9905d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558cfc2ea24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558cfc2ea096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558cfc2cef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558cfbf7e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558cfbf7de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9905d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9905d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9905d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558cfbf7dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c (432 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_s8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_u8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_f16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_f32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_f64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_s8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_u8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_f16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_f32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_f64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s32_s8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s32_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s32_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | ret # | ... # `---data was truncated (10240/58597) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055d83db4c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d83db49515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d83db4ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8fd3733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8fd378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8fd3733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8fd371b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d83dae224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d83dae2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d83dac6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d83d776176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d83d775e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8fd371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8fd371d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8fd371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d83d775d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c (433 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.cls.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cls.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.cls.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cls.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.cls.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cls.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.cls.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cls.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s8_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.cls.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.cls.nxv8i16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.cls.nxv4i32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.cls.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s8_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.cls.nxv16i8( undef, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.cls.nxv8i16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 # | ... # `---data was truncated (10240/11769) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005602d669357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005602d6690515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005602d6693cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6ac261bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6ac26725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6ac261ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6ac2603507 abort ./stdlib/abort.c:85:3 # | #7 0x00005602d662924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005602d6629096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005602d660df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005602d62bd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005602d62bce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6ac2604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6ac26050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6ac26050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005602d62bcd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c (434 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbrkpb_b_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.brkpb.z.nxv16i1( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.brkpb.z.nxv16i1(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000560c7f7da57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560c7f7d7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560c7f7dacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f350bb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f350bb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f350bb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f350baed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560c7f77024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560c7f770096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560c7f754f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560c7f404176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560c7f403e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f350baeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f350baef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f350baef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560c7f403d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c (435 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uwq_u32( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = call @llvm.aarch64.sve.ld1uwq.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv1i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1uwq.nxv4i32.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uwq_vnum_u32( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = getelementptr , ptr %1, i64 -8 # | %4 = call @llvm.aarch64.sve.ld1uwq.nxv4i32.p0( %2, ptr %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uwq_s32( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = call @llvm.aarch64.sve.ld1uwq.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uwq_vnum_s32( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = getelementptr , ptr %1, i64 7 # | %4 = call @llvm.aarch64.sve.ld1uwq.nxv4i32.p0( %2, ptr %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uwq_f32( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = call @llvm.aarch64.sve.ld1uwq.nxv4f32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1uwq.nxv4f32.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uwq_vnum_f32( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = getelementptr , ptr %1, i64 -8 # | %4 = call @llvm.aarch64.sve.ld1uwq.nxv4f32.p0( %2, ptr %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1udq_u64( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = call @llvm.aarch64.sve.ld1udq.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1udq.nxv2i64.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1udq_vnum_u64( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = getelementptr , ptr %1, i64 7 # | %4 = call @llvm.aarch64.sve.ld1udq.nxv2i64.p0( %2, ptr %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1udq_s64( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = call @llvm.aarch64.sve.ld1udq.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1udq_vnum_s64( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = getelementptr , ptr %1, i64 -8 # | %4 = call @llvm.aarch64.sve.ld1udq.nxv2i64.p0( %2, ptr %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1udq_f64( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = call @llvm.aarch64.sve.ld1udq.nxv2f64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1udq.nxv2f64.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1udq_vnum_f64( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = getelementptr , ptr %1, i64 7 # | %4 = call @llvm.aarch64.sve.ld1udq.nxv2f64.p0( %2, ptr %3) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !" # | ... # `---data was truncated (10240/10573) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055fa5227857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fa52275515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fa52278cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc42ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc42ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc42ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc42ed1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fa5220e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fa5220e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fa521f2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fa51ea2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fa51ea1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc42ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc42ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc42ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fa51ea1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_min.c (436 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_min.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.smin.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smin.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.smin.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smin.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.smin.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smin.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.smin.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smin.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.umin.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.umin.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.umin.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.umin.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.umin.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.umin.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c (437 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-tmop -target-feature +sme-f16f16 -target-feature +sme-f8f32 -target-feature +sme-b16b16 -target-feature +sme-f8f16 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-tmop -target-feature +sme-f16f16 -target-feature +sme-f8f32 -target-feature +sme-b16b16 -target-feature +sme-f8f16 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svtmopa_lane_za32_s8_s8( %zn.coerce0, %zn.coerce1, %zm, %zk) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %zk.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store %zk, ptr %zk.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = load , ptr %zk.addr, align 16 # | call void @llvm.aarch64.sme.stmopa.za32.nxv16i8(i32 1, %3, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.stmopa.za32.nxv16i8(i32 immarg, , , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svtmopa_lane_za32_u8_u8( %zn.coerce0, %zn.coerce1, %zm, %zk) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %zk.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store %zk, ptr %zk.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = load , ptr %zk.addr, align 16 # | call void @llvm.aarch64.sme.utmopa.za32.nxv16i8(i32 1, %3, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.utmopa.za32.nxv16i8(i32 immarg, , , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svtmopa_lane_za32_s8_u8( %zn.coerce0, %zn.coerce1, %zm, %zk) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %zk.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store %zk, ptr %zk.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = load , ptr %zk.addr, align 16 # | call void @llvm.aarch64.sme.sutmopa.za32.nxv16i8(i32 1, %3, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.sutmopa.za32.nxv16i8(i32 immarg, , , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svtmopa_lane_za32_u8_s8( %zn.coerce0, %zn.coerce1, %zm, %zk) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %zk.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store %zk, ptr %zk.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = load , ptr %zk.addr, align 16 # | call void @llvm.aarch64.sme.ustmopa.za32.nxv16i8(i32 1, %3, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.ustmopa.za32.nxv16i8(i32 immarg, , , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svtmopa_lane_za32_s16_s16( %zn.coerce0, %zn.coerce1, %zm, %zk) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %zk.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store %zk, ptr %zk.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = load , ptr %zk.addr, align 16 # | call void @llvm.aarch64.sme.stmopa.za32.nxv8i16(i32 1, %3, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.stmopa.za32.nxv8i16(i32 immarg, , , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svtmopa_lane_za32_u16_u16( %zn.coerce0, %zn.coerce1, %zm, %zk) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %zk.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store %zk, ptr %zk.addr, align 16 # | %2 = load { ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c (438 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmlalb_f16_mf8( %zda, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fmlalb.nxv8f16( %0, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fmlalb.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmlalb_n_f16_mf8( %zda, %zn, <1 x i8> %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca <1 x i8>, align 1 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store <1 x i8> %zm, ptr %zm.addr, align 1 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load <1 x i8>, ptr %zm.addr, align 1 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = extractelement <1 x i8> %2, i64 0 # | %.splatinsert = insertelement poison, i8 %4, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %5 = call @llvm.aarch64.sve.fp8.fmlalb.nxv8f16( %0, %1, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmlalt_f16_mf8( %zda, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fmlalt.nxv8f16( %0, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fmlalt.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmlalt_n_f16_mf8( %zda, %zn, <1 x i8> %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca <1 x i8>, align 1 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store <1 x i8> %zm, ptr %zm.addr, align 1 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load <1 x i8>, ptr %zm.addr, align 1 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = extractelement <1 x i8> %2, i64 0 # | %.splatinsert = insertelement poison, i8 %4, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %5 = call @llvm.aarch64.sve.fp8.fmlalt.nxv8f16( %0, %1, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmlalb_lane_f16_mf8( %zda, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fmlalb.lane.nxv8f16( %0, %1, %2, i32 7) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fmlalb.lane.nxv8f16(, , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmlalt_lane_f16_mf8( %zda, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fmlalt.lane.nxv8f16( %0, %1, %2, i32 7) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fmlalt.lane.nxv8f16(, , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmlallbb_f32_mf8( %zda, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fmlallbb.nxv4f32( %0, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fmlallbb.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmlallbb_n_f32_mf8( %zda, %zn, <1 x i8> %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca <1 x i8>, align 1 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store <1 x i8> %zm, ptr %zm.addr, align 1 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load <1 x i8>, ptr %zm.addr, align 1 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = extractelement <1 x i8> %2, i64 0 # | %.splat # | ... # `---data was truncated (10240/24132) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005580517a857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005580517a5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005580517a8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f97d1133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f97d118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f97d1133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f97d111b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055805173e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055805173e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558051722f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005580513d2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005580513d1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f97d111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f97d111d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f97d111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005580513d1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c (439 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmax_single_s8_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.smax.single.x2.nxv16i8( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.smax.single.x2.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmax_single_s16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.smax.single.x2.nxv8i16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.smax.single.x2.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmax_single_s32_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.smax.single.x2.nxv4i32( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.smax.single.x2.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmax_single_s64_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.smax.single.x2.nxv2i64( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.smax.single.x2.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmax_single_u8_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.umax.single.x2.nxv16i8( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.umax.single.x2.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmax_single_u16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.umax.single.x2.nxv8i16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.umax.single.x # | ... # `---data was truncated (10240/142195) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055774c73d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055774c73a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055774c73dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7f56705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7f5675c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7f56705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7f566ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055774c6d324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055774c6d3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055774c6b7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055774c367176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055774c366e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7f566eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7f566ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7f566ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055774c366d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c (440 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv16i8.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv16i8.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf8_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.mask.nxv1i8.nxv1f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.mask.nxv1i8.nxv1f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf8_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, ali # | ... # `---data was truncated (10240/69542) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555b3ba2257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555b3ba1f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555b3ba22cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fac69f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fac69f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fac69f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fac69f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555b3b9b824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555b3b9b8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555b3b99cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555b3b64c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555b3b64be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fac69f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fac69f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fac69f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555b3b64bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-vector-compare-ops.c (441 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-compare-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_bool( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 2 # | %b.addr = alloca , align 2 # | store %a, ptr %a.addr, align 2 # | store %b, ptr %b.addr, align 2 # | %0 = load , ptr %a.addr, align 2 # | %1 = load , ptr %b.addr, align 2 # | %cmp = icmp eq %0, %1 # | ret %cmp # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_i8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp eq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_i16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp eq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_i32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp eq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_i64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp eq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_u8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp eq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_u16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp eq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_u32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp eq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_u64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp eq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_f16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = fcmp oeq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_f32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = fcmp oeq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_f64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = fcmp oeq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @neq_bool( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 2 # | %b.addr = alloca , align 2 # | store %a, ptr %a.addr, align 2 # | store %b, ptr %b.addr, align 2 # | %0 = load , ptr %a.addr, align 2 # | %1 = load , ptr %b.addr, align 2 # | %cmp = icmp ne %0, %1 # | ret %cmp # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @neq_i8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp ne %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @neq_i16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp ne %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @neq_i32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp ne %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @neq_i64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | stor # | ... # `---data was truncated (10240/44453) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x00005555b95e257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005555b95df515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005555b95e2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f53d9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f53d9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f53d9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f53d9f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005555b957824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005555b9578096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005555b955cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005555b920c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005555b920be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f53d9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f53d9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f53d9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005555b920bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c (442 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sw_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i32.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv2i32.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sw_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i32.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sw_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv2i32.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sw_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv2i32.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sw_gather_u64base_s64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64( %2, %1, i64 0) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64(, , i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sw_gather_u64base_u64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64( %2, %1, i64 0) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sw_gather_s64offset_s64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = sext %4 to # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(, ptr, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sw_gather_s64offset_u64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = sext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sw_gather_u64offset_s64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = sext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sw_gather_u64offset_u64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = sext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff # | ... # `---data was truncated (10240/18920) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000558dc716257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558dc715f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558dc7162cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcee7c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcee7ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcee7c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcee7c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558dc70f824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558dc70f8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558dc70dcf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558dc6d8c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558dc6d8be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcee7c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcee7c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcee7c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558dc6d8bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c (443 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_s8() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_s16() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_s32() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_s64() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_u8() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_u16() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_u32() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_u64() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_f16() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_f32() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_f64() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_mf8() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_bf16() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | !llvm.errno.tbaa = !{!4} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # | !4 = !{!5, !6, i64 0} # | !5 = !{!"__libc_errno", !6, i64 0} # | !6 = !{!"int", !7, i64 0} # | !7 = !{!"omnipotent char", !8, i64 0} # | !8 = !{!"Simple C/C++ TBAA"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005626ed38b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005626ed388515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005626ed38bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcd03a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcd03aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcd03a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcd03a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005626ed32124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005626ed321096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005626ed305f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005626ecfb5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005626ecfb4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcd03a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcd03a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcd03a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005626ecfb4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c (444 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_f32mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_f32m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_f32m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_i32mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_i32m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_i32m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_u32mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_u32m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_u32m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_f32mf2x4_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | decl # | ... # `---data was truncated (10240/20497) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e01b2d557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e01b2d2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e01b2d5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7b82933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7b8298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7b82933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7b8291b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e01b26b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e01b26b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e01b24ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e01aeff176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e01aefee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7b8291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7b8291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7b8291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e01aefed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c (445 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbrka_b_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.brka.z.nxv16i1( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.brka.z.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbrka_b_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 2 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %inactive, ptr %inactive.addr, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %inactive.addr, align 2 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 2 # | %3 = call @llvm.aarch64.sve.brka.nxv16i1( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.brka.nxv16i1(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055f772ccf57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f772ccc515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f772ccfcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5266133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f526618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5266133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f526611b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f772c6524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f772c65096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f772c49f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f7728f9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f7728f8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f526611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f526611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f526611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f7728f8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-vector-subscript-ops.c (446 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-subscript-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @subscript_int16( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load , ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement %0, i64 %1 # | ret i16 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @subscript_uint16( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load , ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement %0, i64 %1 # | ret i16 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @subscript_int32( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load , ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement %0, i64 %1 # | ret i32 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @subscript_uint32( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load , ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement %0, i64 %1 # | ret i32 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @subscript_int64( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load , ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement %0, i64 %1 # | ret i64 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @subscript_uint64( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load , ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement %0, i64 %1 # | ret i64 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local half @subscript_float16( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load , ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement %0, i64 %1 # | ret half %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local float @subscript_float32( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load , ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement %0, i64 %1 # | ret float %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local double @subscript_float64( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load , ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement %0, i64 %1 # | ret double %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @subscript_write_float32( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %b.addr, align 8 # | %1 = load , ptr %a.addr, align 16 # | %vecins = insertelement %1, float 1.000000e+00, i64 %0 # | store %vecins, ptr %a.addr, align 16 # | %2 = load , ptr %a.addr, align 16 # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @subscript_read_write_float32( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %b.addr, align 8 # | %1 = load , ptr %a.addr, align 16 # | %vecext = extractelement %1, i64 %0 # | %add = fadd float %vecext, 1.000000e+00 # | %2 = load , ptr %a.addr, align 16 # | %vecins = insertelement %2, float %add, i64 %0 # | store %vecins, ptr %a.addr, align 16 # | %3 = load , ptr %a.addr, align 16 # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x00005627df3e757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005627df3e4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005627df3e7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6c52533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6c5258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6c52533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6c5251b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005627df37d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005627df37d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005627df361f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005627df011176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005627df010e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6c5251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6c5251d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6c5251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005627df010d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c (447 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_f32mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_f32m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_i32mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_i32m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_u32mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_u32m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_f32mf2x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_f32m1x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_i32mf2x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_i32m1x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/14010) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dfd61fa57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055dfd61f7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055dfd61facbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7d16d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7d16d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7d16d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7d16d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dfd619024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055dfd6190096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055dfd6174f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055dfd5e24176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055dfd5e23e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7d16d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7d16d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7d16d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dfd5e23d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c (448 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_s8( %op1, i8 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i8, align 1 # | store %op1, ptr %op1.addr, align 16 # | store i8 %op2, ptr %op2.addr, align 1 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = call @llvm.aarch64.sve.insr.nxv16i8( %0, i8 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.insr.nxv16i8(, i8) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_s16( %op1, i16 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i16, align 2 # | store %op1, ptr %op1.addr, align 16 # | store i16 %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i16, ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.insr.nxv8i16( %0, i16 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.insr.nxv8i16(, i16) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_s32( %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i32, align 4 # | store %op1, ptr %op1.addr, align 16 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.insr.nxv4i32( %0, i32 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.insr.nxv4i32(, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_s64( %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 16 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.insr.nxv2i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.insr.nxv2i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_u8( %op1, i8 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i8, align 1 # | store %op1, ptr %op1.addr, align 16 # | store i8 %op2, ptr %op2.addr, align 1 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = call @llvm.aarch64.sve.insr.nxv16i8( %0, i8 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_u16( %op1, i16 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i16, align 2 # | store %op1, ptr %op1.addr, align 16 # | store i16 %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i16, ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.insr.nxv8i16( %0, i16 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_u32( %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i32, align 4 # | store %op1, ptr %op1.addr, align 16 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.insr.nxv4i32( %0, i32 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_u64( %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 16 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.insr.nxv2i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_f16( %op1, half noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca half, align 2 # | store %op1, ptr %op1.addr, align 16 # | store half %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.insr.nxv8f16( %0, half %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.insr.nxv8f16(, half) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_f32( %op1, float noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca float, align 4 # | store %op1, ptr %op1.addr, align 16 # | store float %op2, ptr %op2.addr, align 4 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.insr.nxv4f32( %0, float %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.insr.nxv4f32(, float) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_f64( %op1, double noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca double, align 8 # | store %op1, ptr %op1.addr, align 16 # | store double %op2, ptr %op2.addr, align 8 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load double, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.insr.nxv2f64( %0, double %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.insr.nxv2f64(, double) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_bf16( %op1, bfloat noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.insr.nxv8bf16( %0, bfloat %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.insr.nxv8bf16(, bfloat) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000560bdb87957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560bdb876515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560bdb879cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6996d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6996d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6996d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6996ced507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560bdb80f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560bdb80f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560bdb7f3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560bdb4a3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560bdb4a2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6996ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6996cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6996cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560bdb4a2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c (449 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature +sme -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature +sme -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za8_s8_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare { , } @llvm.aarch64.sme.readz.horiz.x2.nxv16i8(i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za8_u8_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za8_mf8_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za16_s16_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv8i16(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare { , } @llvm.aarch64.sme.readz.horiz.x2.nxv8i16(i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za16_u16_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv8i16(i32 1, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za16_f16_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv8f16(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare { , } @llvm.aarch64.sme.readz.horiz.x2.nxv8f16(i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za16_bf16_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv8bf16(i32 1, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare { , } @llvm.aarch64.sme.readz.horiz.x2.nxv8bf16(i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za32_s32_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv4i32(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare { , } @llvm.aarch64.sme.readz.horiz.x2.nxv4i32(i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za32_u32_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv4i32(i32 2, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za32_f32_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv4f32(i32 3, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare { , } @llvm.aarch64.sme.readz.horiz.x2.nxv4f32(i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za64_s64_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv2i64(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare { , } @llvm.aarch64.sme.readz.horiz.x2.nxv2i64(i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za64_u64_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv2i64(i32 4, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za64_f64_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv2f64(i32 7, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare { , } @llvm.aarch64.sme.readz.horiz.x2.nxv2f64(i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_ver_za8_s8_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.vert.x2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare { , } @llvm.aarch64.sme.readz.vert.x2.nxv16i8(i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_ver_za8_u8_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.vert.x2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_ver_za8_mf8_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.vert.x2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_ver_za16_s16_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.vert.x2.nxv8i16(i32 0, i32 %0) # | ret { , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c (450 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m4_tu( %maske # | ... # `---data was truncated (10240/157777) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056537ce1b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056537ce18515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056537ce1bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd0ab533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd0ab58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd0ab533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd0ab51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056537cdb124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056537cdb1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056537cd95f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056537ca45176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056537ca44e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd0ab51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd0ab51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd0ab51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056537ca44d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c (451 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560e76c7657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560e76c73515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560e76c76cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f92f7849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f92f78a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f92f7849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f92f7831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560e76c0c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560e76c0c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560e76bf0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560e768a0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560e7689fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f92f7832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f92f78330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f92f78330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560e7689fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c (452 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m8_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32m2_tu( %maskedoff, ptr noundef % # | ... # `---data was truncated (10240/280171) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c4330fe57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c4330fb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c4330fecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f81a1933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f81a198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f81a1933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f81a191b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c43309424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c433094096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c433078f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c432d28176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c432d27e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f81a191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f81a191d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f81a191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c432d27d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c (453 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv2f32.i64( %0, % # | ... # `---data was truncated (10240/291999) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d12fb2857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d12fb25515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d12fb28cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f666b61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f666b6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f666b61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f666b603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d12fabe24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d12fabe096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d12faa2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d12f752176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d12f751e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f666b604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f666b6050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f666b6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d12f751d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c (454 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_b8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.trn2.nxv16i1( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_b16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.trn2.b16( %0, %1) # | ret %2 # | ... # `---data was truncated (10240/13404) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000561eb847757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561eb8474515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561eb8477cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe740249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe7402a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe740249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe740231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561eb840d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561eb840d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561eb83f1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561eb80a1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561eb80a0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe740232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe7402330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe7402330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561eb80a0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c (455 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_bf16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fsub.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fsub.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_bf16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fsub.nxv8bf16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_bf16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fsub.u.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fsub.u.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_bf16_n_m( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fsub.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_bf16_n_z( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fsub.nxv8bf16( %3, %4, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_bf16_n_x( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fsub.u.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000557052fbc57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557052fb9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557052fbccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f15e8649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f15e86a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f15e8649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f15e8631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557052f5224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557052f52096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557052f36f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557052be6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557052be5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f15e8632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f15e86330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f15e86330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557052be5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c (456 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.prf.nxv4i1.p0(, ptr, i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_1( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_2( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_3( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_4( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_5( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_6( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 8) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_7( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 9) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 10) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_9( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 11) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_10( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 12) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_11( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 13) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_vnum( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %3, ptr %4, i32 0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_gather_u32base( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prfw.gather.scalar.offset.nxv4i32( %2, %1, i64 0, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) # | declare void @llvm.aarch64.sve.prfw.gather.scalar.offset.nxv4i32(, , i64, i32 immarg) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_gather_u64base( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store # | ... # `---data was truncated (10240/17826) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000555d0c72b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555d0c728515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555d0c72bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa1bfb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa1bfb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa1bfb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa1bfb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555d0c6c124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555d0c6c1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555d0c6a5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555d0c355176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555d0c354e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa1bfb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa1bfb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa1bfb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555d0c354d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c (457 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_b( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 2 # | %x1.addr = alloca , align 2 # | store %x0, ptr %x0.addr, align 2 # | store %x1, ptr %x1.addr, align 2 # | %0 = load , ptr %x0.addr, align 2 # | %1 = load , ptr %x1.addr, align 2 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055a78ac6957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a78ac66515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a78ac69cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2bbe733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2bbe78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2bbe733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2bbe71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a78abff24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a78abff096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a78abe3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a78a893176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a78a892e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2bbe71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2bbe71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2bbe71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a78a892d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c (458 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmlslb( %zda, %zn, %zm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfmlslb( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfmlslb(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmlslb_lane( %zda, %zn, %zm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfmlslb.lane( %0, %1, %2, i32 7) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfmlslb.lane(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmlslt( %zda, %zn, %zm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfmlslt( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfmlslt(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmlslt_lane( %zda, %zn, %zm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfmlslt.lane( %0, %1, %2, i32 7) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfmlslt.lane(, , , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055994ceb057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055994cead515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055994ceb0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0d52e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0d52ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0d52e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0d52e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055994ce4624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055994ce46096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055994ce2af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055994cada176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055994cad9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0d52e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0d52e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0d52e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055994cad9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c (459 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv4i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind # | ... # `---data was truncated (10240/15211) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056010ccbb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056010ccb8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056010ccbbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6ce7f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6ce7f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6ce7f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6ce7f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056010cc5124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056010cc51096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056010cc35f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056010c8e5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056010c8e4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6ce7f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6ce7f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6ce7f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056010c8e4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c (460 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_s8( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_s16( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = extractvalue { , } %2, 1 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_s32( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_s64( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = extractvalue { , } %2, 1 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_u8( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_u16( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = extractvalue { , } %2, 1 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_u32( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_u64( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = extractvalue { , } %2, 1 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_f16( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_f32( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = extractvalue { , } %2, 1 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | d # | ... # `---data was truncated (10240/14679) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055f9b643257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f9b642f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f9b6432cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2d53533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2d5358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2d53533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2d5351b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f9b63c824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f9b63c8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f9b63acf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f9b605c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f9b605be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2d5351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2d5351d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2d5351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f9b605bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c (461 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svsel_s8_x4(target("aarch64.svcount") %pn, %zn1.coerce0, %zn1.coerce1, %zn1.coerce2, %zn1.coerce3, %zn2.coerce0, %zn2.coerce1, %zn2.coerce2, %zn2.coerce3) #0 { # | entry: # | %zn1 = alloca { , , , }, align 16 # | %zn2 = alloca { , , , }, align 16 # | %pn.addr = alloca target("aarch64.svcount"), align 2 # | %zn1.addr = alloca { , , , }, align 16 # | %zn2.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn1.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn1.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn1.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn1.coerce3, 3 # | store { , , , } %3, ptr %zn1, align 16 # | %zn11 = load { , , , }, ptr %zn1, align 16 # | %4 = insertvalue { , , , } poison, %zn2.coerce0, 0 # | %5 = insertvalue { , , , } %4, %zn2.coerce1, 1 # | %6 = insertvalue { , , , } %5, %zn2.coerce2, 2 # | %7 = insertvalue { , , , } %6, %zn2.coerce3, 3 # | store { , , , } %7, ptr %zn2, align 16 # | %zn22 = load { , , , }, ptr %zn2, align 16 # | store target("aarch64.svcount") %pn, ptr %pn.addr, align 2 # | store { , , , } %zn11, ptr %zn1.addr, align 16 # | store { , , , } %zn22, ptr %zn2.addr, align 16 # | %8 = load target("aarch64.svcount"), ptr %pn.addr, align 2 # | %9 = load { , , , }, ptr %zn1.addr, align 16 # | %10 = extractvalue { , , , } %9, 0 # | %11 = extractvalue { , , , } %9, 1 # | %12 = extractvalue { , , , } %9, 2 # | %13 = extractvalue { , , , } %9, 3 # | %14 = load { , , , }, ptr %zn2.addr, align 16 # | %15 = extractvalue { , , , } %14, 0 # | %16 = extractvalue { , , , } %14, 1 # | %17 = extractvalue { , , , } %14, 2 # | %18 = extractvalue { , , , } %14, 3 # | %19 = call { , , , } @llvm.aarch64.sve.sel.x4.nxv16i8(target("aarch64.svcount") %8, %10, %11, %12, %13, %15, %16, %17, %18) # | ret { , , , } %19 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.sel.x4.nxv16i8(target("aarch64.svcount"), , , , , , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svsel_u8_x4(target("aarch64.svcount") %pn, %zn1.coerce0, %zn1.coerce1, %zn1.coerce2, %zn1.coerce3, %zn2.coerce0, %zn2.coerce1, %zn2.coerce2, %zn2.coerce3, ptr nofreeobj noundef align 16 dead_on_return %0, ptr nofreeobj noundef align 16 dead_on_return %1) #0 { # | entry: # | %zn1 = alloca { , , , }, align 16 # | %zn2 = alloca { , , , }, align 16 # | %pn.addr = alloca target("aarch64.svcount"), align 2 # | %zn1.addr = alloca { , , , }, align 16 # | %zn2.addr = alloca { , , , }, align 16 # | %zn3.addr = alloca { , , , }, align 16 # | %zn4.addr = alloca { , , , }, align 16 # | %2 = insertvalue { , , , } poison, %zn1.coerce0, 0 # | %3 = insertvalue { , , , } %2, %zn1.coerce1, 1 # | %4 = insertvalue { , , , } %3, %zn1.coerce2, 2 # | %5 = insertvalue { , , , } %4, %zn1.coerce3, 3 # | store { , , , } %5, ptr %zn1, align 16 # | %zn11 = load { , , , }, ptr %zn1, align 16 # | %6 = insertvalue { , , , } poison, %zn2.coerce0, 0 # | %7 = insertvalue { , , , } %6, %zn2.coerce1, 1 # | %8 = insertvalue { , , , } %7, %zn2.coerce2, 2 # | %9 = insertvalue { , , , } %8, %zn2.coerce3, 3 # | store { , , , } %9, ptr %zn2, align 16 # | %zn22 = load { , , , }, ptr %zn2, align 16 # | %zn3 = load { , , , }, ptr %0, align 16 # | %zn4 = load { , , , }, ptr %1, align 16 # | store target("aarch64.svcount") %pn, ptr %pn.addr, align 2 # | store { , , , } %zn11, ptr %zn1.addr, align 16 # | store { , , , } %zn22, ptr %zn2.addr, align 16 # | store { , , , } %zn3, ptr %zn3.addr, align 16 # | store { , , , } %zn4, ptr %zn4.addr, align 16 # | %10 = load target("aarch64.svcount"), ptr %pn.addr, align 2 # | %11 = load { , , , }, ptr %zn1.addr, align 16 # | %12 = extractvalue { , , , } %11, 0 # | %13 = extractvalue { , , , } %11, 1 # | %14 = extractvalue { , , , } %11, 2 # | %15 = extractvalue { , , , } %11, 3 # | %16 = load { , , , }, ptr %zn2.addr, align 16 # | %17 = extractvalue { , , , } %16, 0 # | %18 = extractvalue { , , , } %16, 1 # | %19 = extractvalue { , , , } %16, 2 # | %20 = extractvalue { , , , } %16, 3 # | %21 = call { , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vrhaddq.c (462 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vrhaddq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrhaddq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vrhadd.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vrhadd.v16i8(<16 x i8>, <16 x i8>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrhaddq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vrhadd.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vrhadd.v8i16(<8 x i16>, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrhaddq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vrhadd.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vrhadd.v4i32(<4 x i32>, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrhaddq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.rhadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.rhadd.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrhaddq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.rhadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.rhadd.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrhaddq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.rhadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.rhadd.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrhaddq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.rhadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrhaddq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.rhadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrhaddq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.rhadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056512876b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000565128768515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056512876bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9c39905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9c3995c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9c39905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9c398ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056512870124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000565128701096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005651286e5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000565128395176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000565128394e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9c398eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9c398ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9c398ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565128394d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-vector-bitwise-ops.c (463 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-bitwise-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @and_bool( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 2 # | %b.addr = alloca , align 2 # | store %a, ptr %a.addr, align 2 # | store %b, ptr %b.addr, align 2 # | %0 = load , ptr %a.addr, align 2 # | %1 = load , ptr %b.addr, align 2 # | %and = and %0, %1 # | ret %and # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @and_i8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %and = and %0, %1 # | ret %and # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @and_i16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %and = and %0, %1 # | ret %and # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @and_i32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %and = and %0, %1 # | ret %and # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @and_i64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %and = and %0, %1 # | ret %and # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @and_u8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %and = and %0, %1 # | ret %and # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @and_u16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %and = and %0, %1 # | ret %and # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @and_u32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %and = and %0, %1 # | ret %and # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @and_u64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %and = and %0, %1 # | ret %and # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @or_bool( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 2 # | %b.addr = alloca , align 2 # | store %a, ptr %a.addr, align 2 # | store %b, ptr %b.addr, align 2 # | %0 = load , ptr %a.addr, align 2 # | %1 = load , ptr %b.addr, align 2 # | %or = or %0, %1 # | ret %or # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @or_i8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %or = or %0, %1 # | ret %or # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @or_i16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %or = or %0, %1 # | ret %or # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @or_i32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %or = or %0, %1 # | ret %or # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @or_i64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %or = or %0, %1 # | ret %or # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @or_u8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %or = or %0, %1 # | ret %or # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @or_u16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %or = or %0, %1 # | ret %or # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @or_u32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %or = or %0, %1 # | ret %or # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @or_u64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %or = or %0, %1 # | ret %or # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @xor_bool( %a, %b) #0 { # | entry: # | %a.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c (464 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbfmlalt_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfmlalt( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfmlalt(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmlalt_lane_0_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfmlalt.lane.v2( %0, %1, %2, i32 0) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfmlalt.lane.v2(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmlalt_lane_7_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfmlalt.lane.v2( %0, %1, %2, i32 7) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmlalt_n_f32( %x, %y, bfloat noundef %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca bfloat, align 2 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store bfloat %z, ptr %z.addr, align 2 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load bfloat, ptr %z.addr, align 2 # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.bfmlalt( %0, %1, %.splat) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055755b2e057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055755b2dd515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055755b2e0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faccb849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faccb8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faccb849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faccb831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055755b27624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055755b276096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055755b25af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055755af0a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055755af09e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007faccb832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faccb8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faccb8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055755af09d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/poly64.c (465 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/poly64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -flax-vector-conversions=none -ffp-contract=fast -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -flax-vector-conversions=none -ffp-contract=fast -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vceq_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %ref.tmp.i = alloca <1 x i64>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | %1 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <1 x i64>, ptr %__p0.addr.i, align 8 # | %3 = load <1 x i64>, ptr %__p1.addr.i, align 8 # | %cmp.i = icmp eq <1 x i64> %2, %3 # | %sext.i = sext <1 x i1> %cmp.i to <1 x i64> # | store <1 x i64> %sext.i, ptr %ref.tmp.i, align 8 # | %4 = load <1 x i64>, ptr %ref.tmp.i, align 8 # | store <1 x i64> %4, ptr %__ret.i, align 8 # | %5 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vceqq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__p1.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %ref.tmp.i = alloca <2 x i64>, align 16 # | %a.addr = alloca <2 x i64>, align 16 # | %b.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | store <2 x i64> %1, ptr %__p1.addr.i, align 16 # | %2 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %3 = load <2 x i64>, ptr %__p1.addr.i, align 16 # | %cmp.i = icmp eq <2 x i64> %2, %3 # | %sext.i = sext <2 x i1> %cmp.i to <2 x i64> # | store <2 x i64> %sext.i, ptr %ref.tmp.i, align 16 # | %4 = load <2 x i64>, ptr %ref.tmp.i, align 16 # | store <2 x i64> %4, ptr %__ret.i, align 16 # | %5 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vtst_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | %1 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %4 = bitcast <8 x i8> %2 to <1 x i64> # | %5 = bitcast <8 x i8> %3 to <1 x i64> # | %6 = and <1 x i64> %4, %5 # | %7 = icmp ne <1 x i64> %6, zeroinitializer # | %vtst.i = sext <1 x i1> %7 to <1 x i64> # | store <1 x i64> %vtst.i, ptr %ref.tmp.i, align 8 # | %8 = load <1 x i64>, ptr %ref.tmp.i, align 8 # | store <1 x i64> %8, ptr %__ret.i, align 8 # | %9 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vtstq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__p1.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x i64>, align 16 # | %b.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | store <2 x i64> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %4 = bitcast <16 x i8> %2 to <2 x i64> # | %5 = bitcast <16 x i8> %3 to <2 x i64> # | %6 = and <2 x i64> %4, %5 # | %7 = icmp ne <2 x i64> %6, zeroinitializer # | %vtst.i = sext <2 x i1> %7 to <2 x i64> # | store <2 x i64> %vtst.i, ptr %ref.tmp.i, align 16 # | %8 = load <2 x i64>, ptr %ref.tmp.i, align 16 # | store <2 x i64> %8, ptr %__ret.i, align 16 # | %9 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vcopy_lane_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca <1 x i64>, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | %__ret_913 = alloca <1 x i64>, align 8 # | %__s0_913 = alloca <1 x i64>, align 8 # | %__s2_913 = alloca <1 x i64>, align 8 # | %__ret = alloca <1 x i64>, align 8 # | %__s0 = alloca i64, align 8 # | %__ret1 = alloca i64, align 8 # | %__s02 = alloca <1 x i64>, align 8 # | %ref.tmp = alloca i64, align 8 # | %tmp = alloca i64, align 8 # | %__s1 = alloca <1 x i64>, align 8 # | %ref.tmp3 = alloca <1 x i64>, align 8 # | %tmp4 = alloca <1 x i64>, align 8 # | %tmp5 = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | store <1 x i64> %0, ptr %__s0_913, align 8 # | %1 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %1, ptr %__s2_913, align 8 # | %2 = load <1 x i64>, ptr %__s2_913, align 8 # | store <1 x i64> %2, ptr %__s02, align 8 # | %3 = load <1 x i64>, ptr %__s02, align 8 # | %vget_lane = extractelement <1 x i64> %3, i32 0 # | store i64 %vget_lane, ptr %ref.tmp, align 8 # | %4 = load i64, ptr %ref.tmp, align 8 # | store i64 %4, ptr %__ret1, align 8 # | %5 = load i64, ptr %__ret1, align 8 # | store i64 %5, ptr %tmp, align 8 # | %6 = load i64, ptr %tmp, align 8 # | store i64 %6, ptr %__s0, align 8 # | %7 = load <1 x i64>, ptr %__s0_913, align 8 # | store <1 x i64> %7, ptr %__s1, align 8 # | %8 = load i64, ptr %__s0, align 8 # | %9 = load <1 x i64>, ptr %__s1, align 8 # | %vset_lane = insertelement <1 x i64> %9, i64 %8, i32 0 # | store <1 x i64> %vset_lane, ptr %ref.tmp3, align 8 # | %10 = load <1 x i64>, ptr %ref.tmp3, align 8 # | store <1 x i64> %10, ptr %__ret, align 8 # | %11 = load <1 x i64>, ptr %__ret, align 8 # | store <1 x i64> %11, ptr %tmp4, align 8 # | %12 = load <1 x i64>, ptr %tmp4, align 8 # | store <1 x i64> %12, ptr %__ret_913, align 8 # | %13 = load <1 x i64>, ptr %__ret_913, align 8 # | store <1 x i64> %13, ptr %tmp5, align 8 # | %14 = load <1 x i64>, ptr %tmp5, align 8 # | ret <1 x i64> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vcopyq_lane_p64(<2 x i64> noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 16 # | %b.addr = alloca <1 x i64>, align 8 # | %__ret_909 = alloca <2 x i64>, align 16 # | %__s0_909 = alloca <2 x i64>, align 16 # | %__s2_909 = alloca <1 x i64>, align 8 # | %__ret = alloca <2 x i64>, align 16 # | %__s0 = alloca i64, align 8 # | %__ret1 = alloca i64, align 8 # | %__s02 = alloca <1 x i64>, align 8 # | %ref.tmp = alloca i64, align 8 # | %tmp = alloca i64, align 8 # | %__s1 = alloca <2 x i64>, align 16 # | %ref.tmp3 = alloca <2 x i64>, align 16 # | %tmp4 = alloca <2 x i64>, align 16 # | %tmp5 = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__s0_909, align 16 # | %1 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %1, ptr %__s2_909, align 8 # | %2 = load <1 x i64>, ptr %__s2_909, align 8 # | store <1 x i64> %2, ptr %__s02, align 8 # | %3 = load <1 x i64>, ptr %__s02, align 8 # | %vget_lane = extractelement <1 x i64> %3, i32 0 # | store i64 %vget_lane, ptr %ref.tmp, align 8 # | %4 = load i64, ptr %ref.tmp, align 8 # | store i64 %4, ptr %__ret1, align 8 # | %5 = load i64, ptr %__ret1, align 8 # | store i64 %5, ptr %tmp, align 8 # | %6 = load i64, ptr %tmp, align 8 # | store i64 %6, ptr %__s0, align 8 # | %7 = load <2 x i64>, ptr %__s0_909, align 16 # | store <2 x i64> %7, ptr %__s1, align 16 # | %8 = load i64, ptr %__s0, align 8 # | %9 = load <2 x i64>, ptr %__s1, align 16 # | %vset_lane = insertelement <2 x i64> %9, i64 %8, i32 1 # | store <2 x i64> %vset_lane, ptr %ref.tmp3, align 16 # | %10 = load <2 x i64>, ptr %ref.tmp3, align 16 # | store <2 x i64> %10, ptr %__ret, align 16 # | %11 = load <2 x i64>, ptr %__ret, align 16 # | store <2 x i64> %11, ptr %tmp4, align 16 # | %12 = load <2 x i64>, ptr %tmp4, align 16 # | store <2 x i64> %12, ptr %__ret_909, align 16 # | %13 = load <2 x i64>, ptr %__ret_909, align 16 # | store <2 x i64> %13, ptr %tmp5, align 16 # | %14 = load <2 x i64>, ptr %tmp5, align 16 # | ret <2 x i64> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vcopyq_laneq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 16 # | %b.addr = alloca <2 x i64>, align 16 # | %__ret_915 = alloca <2 x i64>, align 16 # | %__s0_915 = alloca <2 x i64>, align 16 # | %__s2_915 = alloca <2 x i64>, align 16 # | %__ret = alloca <2 x i64>, align 16 # | %__s0 = alloca i64, align 8 # | %__ret1 = alloca i64, align 8 # | %__s02 = alloca <2 x i64>, align 16 # | %ref.tmp = alloca i64, align 8 # | %tmp = alloca i64, align 8 # | %__s1 = alloca <2 x i64>, align 16 # | %ref.tmp3 = alloca <2 x i64>, align 16 # | %tmp4 = alloca <2 x i64>, align 16 # | %tmp5 = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__s0_915, align 16 # | %1 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %1, ptr %__s2_915, align 16 # | %2 = load <2 x i64>, ptr %__s2_915, align 16 # | store <2 x i64> %2, ptr %__s02, align 16 # | %3 = load <2 x i64>, ptr %__s02, align 16 # | %vgetq_lane = extractelement <2 x i64> %3, i32 1 # | store i64 %vgetq_lane, ptr %ref.tmp, align 8 # | %4 = load i64, ptr %ref.tmp, align 8 # | store i64 %4, ptr %__ret1, align 8 # | %5 = # | ... # `---data was truncated (10240/22456) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055636a8c457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055636a8c1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055636a8c4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7397049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f73970a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7397049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7397031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055636a85a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055636a85a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055636a83ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055636a4ee176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055636a4ede93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7397032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f73970330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f73970330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055636a4edd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c (466 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +f64mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +f64mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_mf8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ld1ro.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1ro.nxv16i8.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_s8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ld1ro.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1ro.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1ro.nxv8i16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1ro.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1ro.nxv4i32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1ro.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1ro.nxv2i64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_u8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ld1ro.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1ro.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1ro.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1ro.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_f16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1ro.nxv8f16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1ro.nxv8f16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_f32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1ro.nxv4f32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1ro.nxv4f32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_f64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1ro.nxv2f64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1ro.nxv2f64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_bf16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr # | ... # `---data was truncated (10240/11274) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055b7f988a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b7f9887515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b7f988acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb107c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb107ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb107c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb107c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b7f982024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b7f9820096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b7f9804f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b7f94b4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b7f94b3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb107c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb107c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb107c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b7f94b3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c (467 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c (468 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test # | ... # `---data was truncated (10240/156773) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561688ebe57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561688ebb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561688ebecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f43cdb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f43cdb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f43cdb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f43cdb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561688e5424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561688e54096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561688e38f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561688ae8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561688ae7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f43cdb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f43cdb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f43cdb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561688ae7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c (469 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i6 # | ... # `---data was truncated (10240/47604) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562ac281f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562ac281c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562ac281fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8180c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8180c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8180c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8180c03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562ac27b524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562ac27b5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562ac2799f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562ac2449176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562ac2448e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8180c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8180c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8180c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562ac2448d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c (470 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/48305) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bd8e72157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bd8e71e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bd8e721cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3a3aa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3a3aaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3a3aa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3a3aa31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bd8e6b724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bd8e6b7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bd8e69bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bd8e34b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bd8e34ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3a3aa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3a3aa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3a3aa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bd8e34ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c (471 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv4i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv2i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv4i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv2i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv4i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv2i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_gather_u32base_s32( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32( %2, %1, i64 0) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32(, , i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_gather_u64base_s64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64( %2, %1, i64 0) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64(, , i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_gather_u32base_u32( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, # | ... # `---data was truncated (10240/37388) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055a9c7c7657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a9c7c73515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a9c7c76cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f036d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f036d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f036d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f036d631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a9c7c0c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a9c7c0c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a9c7bf0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a9c78a0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a9c789fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f036d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f036d6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f036d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a9c789fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c (472 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmopa_s16( %pn, %pm, %zn, %zm) #0 { # | entry: # | %pn.addr = alloca , align 2 # | %pm.addr = alloca , align 2 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %pn, ptr %pn.addr, align 2 # | store %pm, ptr %pm.addr, align 2 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %pn.addr, align 2 # | %1 = load , ptr %pm.addr, align 2 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load , ptr %zm.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | call void @llvm.aarch64.sme.smopa.za32.nxv8i16(i32 3, %4, %5, %2, %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smopa.za32.nxv8i16(i32 immarg, , , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmopa_u16( %pn, %pm, %zn, %zm) #0 { # | entry: # | %pn.addr = alloca , align 2 # | %pm.addr = alloca , align 2 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %pn, ptr %pn.addr, align 2 # | store %pm, ptr %pm.addr, align 2 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %pn.addr, align 2 # | %1 = load , ptr %pm.addr, align 2 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load , ptr %zm.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | call void @llvm.aarch64.sme.umopa.za32.nxv8i16(i32 3, %4, %5, %2, %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umopa.za32.nxv8i16(i32 immarg, , , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmops_s16( %pn, %pm, %zn, %zm) #0 { # | entry: # | %pn.addr = alloca , align 2 # | %pm.addr = alloca , align 2 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %pn, ptr %pn.addr, align 2 # | store %pm, ptr %pm.addr, align 2 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %pn.addr, align 2 # | %1 = load , ptr %pm.addr, align 2 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load , ptr %zm.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | call void @llvm.aarch64.sme.smops.za32.nxv8i16(i32 3, %4, %5, %2, %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smops.za32.nxv8i16(i32 immarg, , , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmops_u16( %pn, %pm, %zn, %zm) #0 { # | entry: # | %pn.addr = alloca , align 2 # | %pm.addr = alloca , align 2 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %pn, ptr %pn.addr, align 2 # | store %pm, ptr %pm.addr, align 2 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %pn.addr, align 2 # | %1 = load , ptr %pm.addr, align 2 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load , ptr %zm.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | call void @llvm.aarch64.sme.umops.za32.nxv8i16(i32 3, %4, %5, %2, %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umops.za32.nxv8i16(i32 immarg, , , , ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005596b68b157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005596b68ae515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005596b68b1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f434e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f434e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f434e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f434e831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005596b684724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005596b6847096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005596b682bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005596b64db176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005596b64dae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f434e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f434e8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f434e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005596b64dad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c (473 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmplt_s8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmpgt.nxv16i8( %0, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpgt.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmplt_s16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmpgt.nxv8i16( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpgt.nxv8i16(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmplt_s32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmpgt.nxv4i32( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpgt.nxv4i32(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmplt_s64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.cmpgt.nxv2i64( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpgt.nxv2i64(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmplt_u8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmphi.nxv16i8( %0, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphi.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmplt_u16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmphi.nxv8i16( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphi.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmplt_u32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmphi.nxv4i32( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphi.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmplt_u64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, # | ... # `---data was truncated (10240/41923) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005623b9d7757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005623b9d74515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005623b9d77cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efd00f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efd00f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efd00f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efd00f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005623b9d0d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005623b9d0d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005623b9cf1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005623b99a1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005623b99a0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efd00f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efd00f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efd00f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005623b99a0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c (474 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c (475 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vmlalb(<8 x half> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__p3.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <8 x half>, align 16 # | %vd.addr = alloca <8 x half>, align 16 # | %vn.addr = alloca <16 x i8>, align 16 # | %vm.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <8 x half> %vd, ptr %vd.addr, align 16 # | store <16 x i8> %vn, ptr %vn.addr, align 16 # | store <16 x i8> %vm, ptr %vm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <8 x half>, ptr %vd.addr, align 16 # | %1 = load <16 x i8>, ptr %vn.addr, align 16 # | %2 = load <16 x i8>, ptr %vm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | store i64 %3, ptr %__p3.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %6 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %7 = load i64, ptr %__p3.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %vmlal.i = bitcast <16 x i8> %4 to <8 x half> # | %vmlal1.i = call <8 x half> @llvm.aarch64.neon.fp8.fmlalb.v8f16(<8 x half> %vmlal.i, <16 x i8> %5, <16 x i8> %6) # | store <8 x half> %vmlal1.i, ptr %ref.tmp.i, align 16 # | %8 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %8, ptr %__ret.i, align 16 # | %9 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vmlalt(<8 x half> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__p3.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <8 x half>, align 16 # | %vd.addr = alloca <8 x half>, align 16 # | %vn.addr = alloca <16 x i8>, align 16 # | %vm.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <8 x half> %vd, ptr %vd.addr, align 16 # | store <16 x i8> %vn, ptr %vn.addr, align 16 # | store <16 x i8> %vm, ptr %vm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <8 x half>, ptr %vd.addr, align 16 # | %1 = load <16 x i8>, ptr %vn.addr, align 16 # | %2 = load <16 x i8>, ptr %vm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | store i64 %3, ptr %__p3.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %6 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %7 = load i64, ptr %__p3.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %vmlal.i = bitcast <16 x i8> %4 to <8 x half> # | %vmlal1.i = call <8 x half> @llvm.aarch64.neon.fp8.fmlalt.v8f16(<8 x half> %vmlal.i, <16 x i8> %5, <16 x i8> %6) # | store <8 x half> %vmlal1.i, ptr %ref.tmp.i, align 16 # | %8 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %8, ptr %__ret.i, align 16 # | %9 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vmlallbb(<4 x float> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__p3.addr.i = alloca i64, align 8 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <4 x float>, align 16 # | %vd.addr = alloca <4 x float>, align 16 # | %vn.addr = alloca <16 x i8>, align 16 # | %vm.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <4 x float> %vd, ptr %vd.addr, align 16 # | store <16 x i8> %vn, ptr %vn.addr, align 16 # | store <16 x i8> %vm, ptr %vm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <4 x float>, ptr %vd.addr, align 16 # | %1 = load <16 x i8>, ptr %vn.addr, align 16 # | %2 = load <16 x i8>, ptr %vm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | store i64 %3, ptr %__p3.addr.i, align 8 # | %4 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %6 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %7 = load i64, ptr %__p3.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %vmlall.i = call <4 x float> @llvm.aarch64.neon.fp8.fmlallbb.v4f32(<4 x float> %4, <16 x i8> %5, <16 x i8> %6) # | store <4 x float> %vmlall.i, ptr %ref.tmp.i, align 16 # | %8 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %8, ptr %__ret.i, align 16 # | %9 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vmlallbt(<4 x float> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__p3.addr.i = alloca i64, align 8 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <4 x float>, align 16 # | %vd.addr = alloca <4 x float>, align 16 # | %vn.addr = alloca <16 x i8>, align 16 # | %vm.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <4 x float> %vd, ptr %vd.addr, align 16 # | store <16 x i8> %vn, ptr %vn.addr, align 16 # | store <16 x i8> %vm, ptr %vm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <4 x float>, ptr %vd.addr, align 16 # | %1 = load <16 x i8>, ptr %vn.addr, align 16 # | %2 = load <16 x i8>, ptr %vm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | store i64 %3, ptr %__p3.addr.i, align 8 # | %4 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %6 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %7 = load i64, ptr %__p3.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %vmlall.i = call <4 x float> @llvm.aarch64.neon.fp8.fmlallbt.v4f32(<4 x float> %4, <16 x i8> %5, <16 x i8> %6) # | store <4 x float> %vmlall.i, ptr %ref.tmp.i, align 16 # | %8 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %8, ptr %__ret.i, align 16 # | %9 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vmlalltb(<4 x float> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__p3.addr.i = alloca i64, align 8 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <4 x float>, align 16 # | %vd.addr = alloca <4 x float>, align 16 # | %vn.addr = alloca <16 x i8>, align 16 # | %vm.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <4 x float> %vd, ptr %vd.addr, align 16 # | store <16 x i8> %vn, ptr %vn.addr, align 16 # | store <16 x i8> %vm, ptr %vm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <4 x float>, ptr %vd.addr, align 16 # | %1 = load <16 x i8>, ptr %vn.addr, align 16 # | %2 = load <16 x i8>, ptr %vm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | store i64 %3, ptr %__p3.addr.i, align 8 # | %4 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %6 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %7 = load i64, ptr %__p3.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %vmlall.i = call <4 x float> @llvm.aarch64.neon.fp8.fmlalltb.v4f32(<4 x float> %4, <16 x i8> %5, <16 x i8> %6) # | store <4 x float> %vmlall.i, ptr %ref.tmp.i, align 16 # | %8 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %8, ptr %__ret.i, align 16 # | %9 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vmlalltt(<4 x float> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__p3.addr.i = alloca i64, align 8 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <4 x float>, align 16 # | %vd.addr = alloca <4 x float>, align 16 # | %vn.addr = alloca <16 x i8>, align 16 # | %vm.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <4 x float> %vd, ptr %vd.addr, align 16 # | store <16 x i8> %vn, ptr %vn.addr, align 16 # | store <16 x i8> %vm, ptr %vm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <4 x float>, ptr %vd.addr, align 16 # | %1 = load <16 x i8>, ptr %vn.addr, align 16 # | %2 = load <16 x i8>, ptr %vm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | store i64 %3, ptr %__p3.addr.i, align 8 # | %4 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %6 # | ... # `---data was truncated (10240/35980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa # | #0 0x0000560c4370057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560c436fd515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560c43700cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0b85849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0b858a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0b85849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0b85831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560c4369624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560c43696096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560c4367af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560c4332a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560c43329e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0b85832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0b858330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0b858330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560c43329d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c (476 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056012ab9c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056012ab99515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056012ab9ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff450333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff45038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff450333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff45031b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056012ab3224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056012ab32096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056012ab16f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056012a7c6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056012a7c5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff45031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff45031d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff45031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056012a7c5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c (477 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv8f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv16f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv32f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff. # | ... # `---data was truncated (10240/128424) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a0d402b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a0d4028515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a0d402bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7431733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f743178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7431733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f743171b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a0d3fc124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a0d3fc1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a0d3fa5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a0d3c55176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a0d3c54e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f743171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f743171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f743171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a0d3c54d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_not.c (478 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_not.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_s8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.not.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.not.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_s16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.not.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.not.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.not.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.not.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.not.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.not.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_u8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.not.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_u16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.not.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_u32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.not.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.not.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_s8_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.not.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_s16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.not.nxv8i16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c (479 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c (480 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8m4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca # | ... # `---data was truncated (10240/98343) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b5bf78957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b5bf786515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b5bf789cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7d36049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7d360a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7d36049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7d36031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b5bf71f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b5bf71f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b5bf703f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b5bf3b3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b5bf3b2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7d36032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7d360330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7d360330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b5bf3b2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c (481 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf8( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, a # | ... # `---data was truncated (10240/207757) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556a7cb7857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556a7cb75515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556a7cb78cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f08c0933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f08c098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f08c0933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f08c091b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556a7cb0e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556a7cb0e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556a7caf2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556a7c7a2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556a7c7a1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f08c091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f08c091d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f08c091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556a7c7a1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c (482 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_qcvtn_s16_s32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.sqcvtn.x2.nxv4i32( %3, %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.sqcvtn.x2.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_qcvtn_u16_u32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.uqcvtn.x2.nxv4i32( %3, %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.uqcvtn.x2.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_qcvtn_u16_s32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.sqcvtun.x2.nxv4i32( %3, %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.sqcvtun.x2.nxv4i32(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055748966257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055748965f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557489662cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4460133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f446018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4460133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f446011b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005574895f824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005574895f8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005574895dcf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055748928c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055748928be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f446011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f446011d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f446011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055748928bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c (483 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_bf16mf4_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_bf16mf4_f32mf2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_bf16mf4_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_bf16_f32mf2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_bf16mf2_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_bf16mf2_f32m1_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_bf16mf2_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_bf16_f32m1_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c (484 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f5579e357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f5579e0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f5579e3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f77d2449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f77d24a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f77d2449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f77d2431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f55797924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f557979096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f55795df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f55760d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f55760ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f77d2432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f77d24330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f77d24330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f55760cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c (485 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_mf8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ld1rq.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1rq.nxv16i8.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_s8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ld1rq.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1rq.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1rq.nxv8i16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1rq.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1rq.nxv4i32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1rq.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1rq.nxv2i64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_u8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ld1rq.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1rq.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1rq.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1rq.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_f16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1rq.nxv8f16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1rq.nxv8f16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_f32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1rq.nxv4f32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1rq.nxv4f32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_f64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1rq.nxv2f64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1rq.nxv2f64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_bf16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr # | ... # `---data was truncated (10240/11267) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005599bd95557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005599bd952515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005599bd955cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feb6b705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feb6b75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feb6b705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feb6b6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005599bd8eb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005599bd8eb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005599bd8cff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005599bd57f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005599bd57ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007feb6b6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feb6b6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feb6b6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005599bd57ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c (486 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32mf2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m1( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m4( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m8( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32mf2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m1_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Functio # | ... # `---data was truncated (10240/13657) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a2943ca57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a2943c7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a2943cacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc82ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc82ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc82ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc82ed1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a29436024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a294360096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a294344f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a293ff4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a293ff3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc82ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc82ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc82ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a293ff3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c (487 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmul_single_bf16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fmul.single.x2.nxv8bf16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fmul.single.x2.nxv8bf16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svmul_single_bf16_x4( %zdn.coerce0, %zdn.coerce1, %zdn.coerce2, %zdn.coerce3, %zm) #0 { # | entry: # | %zdn = alloca { , , , }, align 16 # | %zdn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zdn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zdn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zdn.coerce3, 3 # | store { , , , } %3, ptr %zdn, align 16 # | %zdn1 = load { , , , }, ptr %zdn, align 16 # | store { , , , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %4 = load { , , , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = load , ptr %zm.addr, align 16 # | %10 = call { , , , } @llvm.aarch64.sve.fmul.single.x4.nxv8bf16( %5, %6, %7, %8, %9) # | ret { , , , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.fmul.single.x4.nxv8bf16(, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmul_bf16_x2( %zdn.coerce0, %zdn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | %10 = call { , } @llvm.aarch64.sve.fmul.x2.nxv8bf16( %5, %6, %8, %9) # | ret { , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fmul.x2.nxv8bf16(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svmul_bf16_x4( %zdn.coerce0, %zdn.coerce1, %zdn.coerce2, %zdn.coerce3, %zm.coerce0, %zm.coerce1, %zm.coerce2, %zm.coerce3) #0 { # | entry: # | %zdn = alloca { , , , }, align 16 # | %zm = alloca { , , , }, align 16 # | %zdn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zdn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zdn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zdn.coerce3, 3 # | store { , , , } %3, ptr %zdn, align 16 # | %zdn1 = load { , , , }, ptr %zdn, align 16 # | %4 = insertvalue { , , , } poison, %zm.coerce0, 0 # | %5 = insertvalue { , , , } %4, %zm.coerce1, 1 # | %6 = insertvalue { , , , } %5, %zm.coerce2, 2 # | %7 = insertvalue { ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c (488 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16mf4_tu( %maskedoff, %op1, %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %index.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16mf4_tu( %maskedoff, %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %index.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv1f16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv1f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16mf2_tu( %maskedoff, %op1, %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %index.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16mf2_tu( %maskedoff, %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %index.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv2f16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv2f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m1_tu( %maskedoff, %op1, %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %index.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16m1_tu( %maskedoff, %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %index.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv4f16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv4f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m2_tu( %maskedoff, %op1, %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %index.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16m2_tu( %maskedoff, %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %index.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv8f16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv8f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m4_tu( %ma # | ... # `---data was truncated (10240/619127) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559dfe82657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559dfe823515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559dfe826cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcd9f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcd9f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcd9f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcd9f11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559dfe7bc24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559dfe7bc096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559dfe7a0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559dfe450176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559dfe44fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcd9f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcd9f11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcd9f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559dfe44fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c (489 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.7a -target-feature +f16mm -target-feature +f16f32mm -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.7a -target-feature +f16mm -target-feature +f16f32mm -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local <8 x half> @test_vmmlaq_f16(<8 x half> noundef %acc, <8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %acc.addr = alloca <8 x half>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | store <8 x half> %acc, ptr %acc.addr, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | %0 = load <8 x half>, ptr %acc.addr, align 16 # | %1 = load <8 x half>, ptr %a.addr, align 16 # | %2 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %fmmla.i = bitcast <16 x i8> %3 to <8 x half> # | %fmmla1.i = bitcast <16 x i8> %4 to <8 x half> # | %fmmla2.i = bitcast <16 x i8> %5 to <8 x half> # | %fmmla3.i = call <8 x half> @llvm.aarch64.neon.fmmla.v8f16.v8f16(<8 x half> %fmmla.i, <8 x half> %fmmla1.i, <8 x half> %fmmla2.i) # | store <8 x half> %fmmla3.i, ptr %ref.tmp.i, align 16 # | %6 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %6, ptr %__ret.i, align 16 # | %7 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %7 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local <4 x float> @test_vmmlaq_f32_f16(<4 x float> noundef %acc, <8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %acc.addr = alloca <4 x float>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | store <4 x float> %acc, ptr %acc.addr, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %acc.addr, align 16 # | %1 = load <8 x half>, ptr %a.addr, align 16 # | %2 = load <8 x half>, ptr %b.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %fmmla.i = bitcast <16 x i8> %3 to <4 x float> # | %fmmla1.i = bitcast <16 x i8> %4 to <8 x half> # | %fmmla2.i = bitcast <16 x i8> %5 to <8 x half> # | %fmmla3.i = call <4 x float> @llvm.aarch64.neon.fmmla.v4f32.v8f16(<4 x float> %fmmla.i, <8 x half> %fmmla1.i, <8 x half> %fmmla2.i) # | store <4 x float> %fmmla3.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %6, ptr %__ret.i, align 16 # | %7 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.aarch64.neon.fmmla.v8f16.v8f16(<8 x half>, <8 x half>, <8 x half>) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.aarch64.neon.fmmla.v4f32.v8f16(<4 x float>, <8 x half>, <8 x half>) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+bti,+ccidx,+cmpbr,+complxnum,+cpa,+crc,+cssc,+dit,+dotprod,+f16f32dot,+f16f32mm,+f16mm,+faminmax,+flagm,+fp-armv8,+fprcvt,+fullfp16,+hbc,+hinte,+i8mm,+jsconv,+lse,+lsui,+lut,+mec,+mops,+neon,+occmo,+pauth,+predres,+ras,+rasv2,+rcpc,+rdm,+rme,+sb,+spe-eef,+specres2,+ssbs,+sve,+sve2,+sve2p1,+sve2p3,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v8.9a,+v8a,+v9.1a,+v9.2a,+v9.3a,+v9.4a,+v9.5a,+v9.6a,+v9.7a,+v9a,+wfxt" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055b0a279057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b0a278d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b0a2790cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc942049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc9420a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc942049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc942031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b0a272624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b0a2726096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b0a270af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b0a23ba176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b0a23b9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc942032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc9420330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc9420330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b0a23b9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c (490 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f32.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f32.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16f32.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f32.p0.nxv16i32.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c (491 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf8( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv1i8.nxv1i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf8( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv1i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf4( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv2i8.nxv2i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf4( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv2i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf2( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv4i8.nxv4i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf2( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv4i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8m1( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv8i8.nxv8i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8m1( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv8i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv8i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8m2( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , a # | ... # `---data was truncated (10240/98149) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055aafa33057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055aafa32d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055aafa330cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa7db133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa7db18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa7db133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa7db11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aafa2c624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055aafa2c6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055aafa2aaf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055aaf9f5a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055aaf9f59e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa7db11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa7db11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa7db11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aaf9f59d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c (492 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_f16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fscale.nxv8f16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fscale.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_f32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fscale.nxv4f32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fscale.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_f64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fscale.nxv2f64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fscale.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_f16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fscale.nxv8f16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_f32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.fscale.nxv4f32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_f64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.fscale.nxv2f64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_f16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fscale.nxv8f16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_f32_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.fscale.nxv4f32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_f64_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbo # | ... # `---data was truncated (10240/21216) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000564f7a4e357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564f7a4e0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564f7a4e3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f437db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f437db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f437db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f437db1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564f7a47924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564f7a479096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564f7a45df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564f7a10d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564f7a10ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f437db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f437db1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f437db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564f7a10cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c (493 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv16i8.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv16i8.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf8_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.mask.nxv1i8.nxv1f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.mask.nxv1i8.nxv1f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf8_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | s # | ... # `---data was truncated (10240/69534) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d285c8357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d285c80515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d285c83cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3865d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3865d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3865d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3865d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d285c1924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d285c19096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d285bfdf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d2858ad176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d2858ace93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3865d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3865d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3865d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d2858acd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c (494 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, ali # | ... # `---data was truncated (10240/223367) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cd13d9457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cd13d91515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cd13d94cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0501649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f05016a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0501649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0501631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cd13d2a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cd13d2a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cd13d0ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cd139be176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cd139bde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0501632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f05016330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f05016330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cd139bdd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c (495 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +f8f16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +f8f16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_f16mf8( %acc, %a, %b, i64 noundef %fpmr) #0 { # | entry: # | %acc.addr = alloca , align 16 # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | store %acc, ptr %acc.addr, align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load , ptr %acc.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %2 = load , ptr %b.addr, align 16 # | %3 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fmmla.nxv8f16( %0, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fmmla.nxv8f16(, , ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f8f16mm,+sve,+sve2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000557d47d3657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557d47d33515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557d47d36cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa42f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa42f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa42f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa42f11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557d47ccc24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557d47ccc096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557d47cb0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557d47960176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557d4795fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa42f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa42f11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa42f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557d4795fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c (496 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32mf2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m1( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m4( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llv # | ... # `---data was truncated (10240/51751) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e9f9b9557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e9f9b92515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e9f9b95cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f19be61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f19be6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f19be61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f19be603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e9f9b2b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e9f9b2b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e9f9b0ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e9f97bf176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e9f97bee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f19be604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f19be6050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f19be6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e9f97bed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c (497 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmmla_f64( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmmla.nxv2f64.nxv2f64( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmmla.nxv2f64.nxv2f64(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000564f2ae5b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564f2ae58515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564f2ae5bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6ddbf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6ddbf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6ddbf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6ddbf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564f2adf124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564f2adf1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564f2add5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564f2aa85176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564f2aa84e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6ddbf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6ddbf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6ddbf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564f2aa84d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c (498 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretur # | ... # `---data was truncated (10240/69677) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c04bf8a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c04bf87515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c04bf8acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa9d121bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa9d12725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa9d121ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa9d1203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c04bf2024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c04bf20096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c04bf04f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c04bbb4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c04bbb3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa9d1204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa9d12050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa9d12050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c04bbb3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c (499 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpx_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frecpx.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frecpx.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpx_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frecpx.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frecpx.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpx_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frecpx.nxv2f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frecpx.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpx_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.frecpx.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpx_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.frecpx.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpx_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.frecpx.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpx_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frecpx.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpx_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frecpx.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpx_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frecpx.nxv2f64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005555641d057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005555641cd515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005555641d0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6281649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f62816a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6281649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6281631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055556416624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555564166096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055556414af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555563dfa176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555563df9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6281632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f62816330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f62816330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555563df9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon/load.c (500 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon/load.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c --check-prefixes=ALL,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | %struct.float16x8x2_t = type { [2 x <8 x half>] } # | %struct.float32x4x2_t = type { [2 x <4 x float>] } # | %struct.float64x2x2_t = type { [2 x <2 x double>] } # | %struct.mfloat8x16x2_t = type { [2 x <16 x i8>] } # | %struct.poly16x8x2_t = type { [2 x <8 x i16>] } # | %struct.poly64x2x2_t = type { [2 x <2 x i64>] } # | %struct.poly8x16x2_t = type { [2 x <16 x i8>] } # | %struct.int16x8x2_t = type { [2 x <8 x i16>] } # | %struct.int32x4x2_t = type { [2 x <4 x i32>] } # | %struct.int64x2x2_t = type { [2 x <2 x i64>] } # | %struct.int8x16x2_t = type { [2 x <16 x i8>] } # | %struct.uint16x8x2_t = type { [2 x <8 x i16>] } # | %struct.uint32x4x2_t = type { [2 x <4 x i32>] } # | %struct.uint64x2x2_t = type { [2 x <2 x i64>] } # | %struct.uint8x16x2_t = type { [2 x <16 x i8>] } # | %struct.float16x4x2_t = type { [2 x <4 x half>] } # | %struct.float32x2x2_t = type { [2 x <2 x float>] } # | %struct.float64x1x2_t = type { [2 x <1 x double>] } # | %struct.mfloat8x8x2_t = type { [2 x <8 x i8>] } # | %struct.poly16x4x2_t = type { [2 x <4 x i16>] } # | %struct.poly64x1x2_t = type { [2 x <1 x i64>] } # | %struct.poly8x8x2_t = type { [2 x <8 x i8>] } # | %struct.int16x4x2_t = type { [2 x <4 x i16>] } # | %struct.int32x2x2_t = type { [2 x <2 x i32>] } # | %struct.int64x1x2_t = type { [2 x <1 x i64>] } # | %struct.int8x8x2_t = type { [2 x <8 x i8>] } # | %struct.uint16x4x2_t = type { [2 x <4 x i16>] } # | %struct.uint32x2x2_t = type { [2 x <2 x i32>] } # | %struct.uint64x1x2_t = type { [2 x <1 x i64>] } # | %struct.uint8x8x2_t = type { [2 x <8 x i8>] } # | %struct.float16x8x3_t = type { [3 x <8 x half>] } # | %struct.float32x4x3_t = type { [3 x <4 x float>] } # | %struct.float64x2x3_t = type { [3 x <2 x double>] } # | %struct.mfloat8x16x3_t = type { [3 x <16 x i8>] } # | %struct.poly16x8x3_t = type { [3 x <8 x i16>] } # | %struct.poly64x2x3_t = type { [3 x <2 x i64>] } # | %struct.poly8x16x3_t = type { [3 x <16 x i8>] } # | %struct.int16x8x3_t = type { [3 x <8 x i16>] } # | %struct.int32x4x3_t = type { [3 x <4 x i32>] } # | %struct.int64x2x3_t = type { [3 x <2 x i64>] } # | %struct.int8x16x3_t = type { [3 x <16 x i8>] } # | %struct.uint16x8x3_t = type { [3 x <8 x i16>] } # | %struct.uint32x4x3_t = type { [3 x <4 x i32>] } # | %struct.uint64x2x3_t = type { [3 x <2 x i64>] } # | %struct.uint8x16x3_t = type { [3 x <16 x i8>] } # | %struct.float16x4x3_t = type { [3 x <4 x half>] } # | %struct.float32x2x3_t = type { [3 x <2 x float>] } # | %struct.float64x1x3_t = type { [3 x <1 x double>] } # | %struct.mfloat8x8x3_t = type { [3 x <8 x i8>] } # | %struct.poly16x4x3_t = type { [3 x <4 x i16>] } # | %struct.poly64x1x3_t = type { [3 x <1 x i64>] } # | %struct.poly8x8x3_t = type { [3 x <8 x i8>] } # | %struct.int16x4x3_t = type { [3 x <4 x i16>] } # | %struct.int32x2x3_t = type { [3 x <2 x i32>] } # | %struct.int64x1x3_t = type { [3 x <1 x i64>] } # | %struct.int8x8x3_t = type { [3 x <8 x i8>] } # | %struct.uint16x4x3_t = type { [3 x <4 x i16>] } # | %struct.uint32x2x3_t = type { [3 x <2 x i32>] } # | %struct.uint64x1x3_t = type { [3 x <1 x i64>] } # | %struct.uint8x8x3_t = type { [3 x <8 x i8>] } # | %struct.float16x8x4_t = type { [4 x <8 x half>] } # | %struct.float32x4x4_t = type { [4 x <4 x float>] } # | %struct.float64x2x4_t = type { [4 x <2 x double>] } # | %struct.mfloat8x16x4_t = type { [4 x <16 x i8>] } # | %struct.poly16x8x4_t = type { [4 x <8 x i16>] } # | %struct.poly64x2x4_t = type { [4 x <2 x i64>] } # | %struct.poly8x16x4_t = type { [4 x <16 x i8>] } # | %struct.int16x8x4_t = type { [4 x <8 x i16>] } # | %struct.int32x4x4_t = type { [4 x <4 x i32>] } # | %struct.int64x2x4_t = type { [4 x <2 x i64>] } # | %struct.int8x16x4_t = type { [4 x <16 x i8>] } # | %struct.uint16x8x4_t = type { [4 x <8 x i16>] } # | %struct.uint32x4x4_t = type { [4 x <4 x i32>] } # | %struct.uint64x2x4_t = type { [4 x <2 x i64>] } # | %struct.uint8x16x4_t = type { [4 x <16 x i8>] } # | %struct.float16x4x4_t = type { [4 x <4 x half>] } # | %struct.float32x2x4_t = type { [4 x <2 x float>] } # | %struct.float64x1x4_t = type { [4 x <1 x double>] } # | %struct.mfloat8x8x4_t = type { [4 x <8 x i8>] } # | %struct.poly16x4x4_t = type { [4 x <4 x i16>] } # | %struct.poly64x1x4_t = type { [4 x <1 x i64>] } # | %struct.poly8x8x4_t = type { [4 x <8 x i8>] } # | %struct.int16x4x4_t = type { [4 x <4 x i16>] } # | %struct.int32x2x4_t = type { [4 x <2 x i32>] } # | %struct.int64x1x4_t = type { [4 x <1 x i64>] } # | %struct.int8x8x4_t = type { [4 x <8 x i8>] } # | %struct.uint16x4x4_t = type { [4 x <4 x i16>] } # | %struct.uint32x2x4_t = type { [4 x <2 x i32>] } # | %struct.uint64x1x4_t = type { [4 x <1 x i64>] } # | %struct.uint8x8x4_t = type { [4 x <8 x i8>] } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vld1q_f16(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %__ret = alloca <8 x half>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x half>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %0, align 2 # | store <8 x half> %1, ptr %ref.tmp, align 16 # | %2 = load <8 x half>, ptr %ref.tmp, align 16 # | store <8 x half> %2, ptr %__ret, align 16 # | %3 = load <8 x half>, ptr %__ret, align 16 # | store <8 x half> %3, ptr %tmp, align 16 # | %4 = load <8 x half>, ptr %tmp, align 16 # | ret <8 x half> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vld1q_f32(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %__ret = alloca <4 x float>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <4 x float>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %0, align 4 # | store <4 x float> %1, ptr %ref.tmp, align 16 # | %2 = load <4 x float>, ptr %ref.tmp, align 16 # | store <4 x float> %2, ptr %__ret, align 16 # | %3 = load <4 x float>, ptr %__ret, align 16 # | store <4 x float> %3, ptr %tmp, align 16 # | %4 = load <4 x float>, ptr %tmp, align 16 # | ret <4 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vld1q_f64(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %__ret = alloca <2 x double>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <2 x double>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %1 = load <2 x double>, ptr %0, align 8 # | store <2 x double> %1, ptr %ref.tmp, align 16 # | %2 = load <2 x double>, ptr %ref.tmp, align 16 # | store <2 x double> %2, ptr %__ret, align 16 # | %3 = load <2 x double>, ptr %__ret, align 16 # | store <2 x double> %3, ptr %tmp, align 16 # | %4 = load <2 x double>, ptr %tmp, align 16 # | ret <2 x double> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vld1q_mf8(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %__ret = alloca <16 x i8>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <16 x i8>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %0, align 1 # | store <16 x i8> %1, ptr %ref.tmp, align 16 # | %2 = load <16 x i8>, ptr %ref.tmp, align 16 # | store <16 x i8> %2, ptr %__ret, align 16 # | %3 = load <16 x i8>, ptr %__ret, align 16 # | store <16 x i8> %3, ptr %tmp, align 16 # | %4 = load <16 x i8>, ptr %tmp, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vld1q_p16(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %__ret = alloca <8 x i16>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x i16>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %0, align 2 # | store <8 x i16> %1, ptr %ref.tmp, align 16 # | %2 = load <8 x i16>, ptr %ref.tmp, align 16 # | store <8 x i16> %2, ptr %__ret, align 16 # | %3 = load <8 x i16>, ptr %__ret, align 16 # | store <8 x i16> %3, ptr %tmp, align 16 # | %4 = load <8 x i16>, ptr %tmp, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vld1q_p64(ptr noundef %ptr) #0 { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %__ret = alloca <2 x i64>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <2 x i64>, align 16 # | store ptr %ptr, ptr %ptr.addr, align 8 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load <2 x i64>, ptr %0, align 8 # | store <2 x i64> %1, ptr %ref.tmp, align 16 # | %2 = load <2 x i64>, ptr %ref.tmp, align 16 # | store <2 x i64> %2, ptr %__ret, align 16 # | %3 = load <2 x i64>, ptr %__ret, align 16 # | store <2 x i64> %3, ptr %tmp, align 16 # | %4 = load <2 x i64>, ptr %tmp, align 16 # | ret <2 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vld1q_p8(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %__ret = alloca <16 x i8>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <16 x i8>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %0, align 1 # | store <16 x i8> %1, ptr %ref.tmp, align 16 # | %2 = load <16 x i8>, ptr %ref.tmp, align 16 # | store <16 x i8> %2, ptr %__ret, align 16 # | %3 = load <16 x i8>, ptr %__ret, align 16 # | store <16 x i8> %3, ptr %tmp, align 16 # | %4 = load <16 x i8>, ptr %tmp, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vld1q_s16(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %__ret = alloca <8 x i16>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x i16>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %0, align 2 # | store <8 x i16> %1, ptr %ref.tmp, align 16 # | %2 = load <8 x i16>, ptr %ref.tmp, align 16 # | store <8 x i16> %2, ptr %__ret, align 16 # | %3 = load <8 x i16>, ptr %__ret, align 16 # | store <8 x i16> %3, ptr %tmp, align 16 # | %4 = load <8 x i16>, ptr %tmp, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vld1q_s32(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %__ret = alloca <4 x i32>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <4 x i32>, align 16 # | store ptr %a # | ... # `---data was truncated (10240/415795) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine # | #0 0x000055b81eaa557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b81eaa2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b81eaa5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1b39133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1b3918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1b39133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1b3911b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b81ea3b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b81ea3b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b81ea1ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b81e6cf176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b81e6cee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1b3911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1b3911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1b3911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b81e6ced81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c --check-prefixes=ALL,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c --check-prefixes=ALL,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c (501 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test # | ... # `---data was truncated (10240/94993) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055affac6657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055affac63515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055affac66cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc10a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc10a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc10a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc10a11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055affabfc24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055affabfc096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055affabe0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055affa890176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055affa88fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc10a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc10a11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc10a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055affa88fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c (502 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf8_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/bf16-reinterpret-intrinsics.c (503 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/bf16-reinterpret-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_s8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_s16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_s32(<2 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_u8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_u16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_u32(<2 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_p8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_p16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_u64(<1 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_s64(<1 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_s8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16 # | store <8 x bfloat> %1, ptr %__ret.i, align 16 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_s16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16 # | store <8 x bfloat> %1, ptr %__ret.i, align 16 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_s32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16 # | store <8 x bfloat> %1, ptr %__ret.i, align 16 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16 # | store <8 x bfloat> %1, ptr %__ret.i, align 16 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_u8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16 # | store <8 x bfloat> %1, ptr %__ret.i, align 16 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_u16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16 # | store <8 x bfloat> %1, ptr %__ret.i, align 16 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_u32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load # | ... # `---data was truncated (10240/31171) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x00005572572bf57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005572572bc515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005572572bfcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0e98c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0e98ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0e98c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0e98c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055725725524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557257255096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557257239f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557256ee9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557256ee8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0e98c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0e98c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0e98c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557256ee8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c (504 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_2x2_za32_s8_s8( %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | call void @llvm.aarch64.sme.smop4a.wide.2x2.nxv16i8(i32 1, %5, %6, %8, %9) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smop4a.wide.2x2.nxv16i8(i32 immarg, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_2x2_za32_s8_s8( %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | call void @llvm.aarch64.sme.smop4s.wide.2x2.nxv16i8(i32 1, %5, %6, %8, %9) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smop4s.wide.2x2.nxv16i8(i32 immarg, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_2x2_za32_u8_u8( %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | call void @llvm.aarch64.sme.umop4a.wide.2x2.nxv16i8(i32 1, %5, %6, %8, %9) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umop4a.wide.2x2.nxv16i8(i32 immarg, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_2x2_za32_u8_u8( %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | call void @llvm.aarch64.sme.umop4s.wide.2x2.nxv16i8(i32 1, %5, %6, %8, %9) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umop4s.wide.2x2.nxv16i8(i32 immarg, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_2x2_za32_s8_u8( %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | % # | ... # `---data was truncated (10240/74176) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005560e77bd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005560e77ba515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005560e77bdcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0591533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f059158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0591533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f059151b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005560e775324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005560e7753096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005560e7737f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005560e73e7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005560e73e6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f059151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f059151d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f059151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005560e73e6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c (505 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_i8mf8x6 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b38b2e057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b38b2dd515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b38b2e0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5dcd61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5dcd6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5dcd61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5dcd603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b38b27624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b38b276096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b38b25af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b38af0a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b38af09e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5dcd604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5dcd6050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5dcd6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b38af09d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c (506 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv16i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv32i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv32i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv64i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv64i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, ali # | ... # `---data was truncated (10240/63510) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564fae6b457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564fae6b1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564fae6b4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7148849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f71488a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7148849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7148831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564fae64a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564fae64a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564fae62ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564fae2de176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564fae2dde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7148832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f71488330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f71488330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564fae2ddd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c (507 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svvdot_lane_za16_mf8_vg1x2(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zm, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice, ptr %slice.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %2 = load i32, ptr %slice.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | %7 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | call void @llvm.aarch64.sme.fp8.fvdot.lane.za16.vg1x2(i32 %2, %4, %5, %6, i32 7) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fvdot.lane.za16.vg1x2(i32, , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svvdotb_lane_za32_mf8_vg1x4(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zm, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice, ptr %slice.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %2 = load i32, ptr %slice.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | %7 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | call void @llvm.aarch64.sme.fp8.fvdotb.lane.za32.vg1x4(i32 %2, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fvdotb.lane.za32.vg1x4(i32, , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svvdott_lane_za32_mf8_vg1x4(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zm, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice, ptr %slice.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %2 = load i32, ptr %slice.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | %7 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | call void @llvm.aarch64.sme.fp8.fvdott.lane.za32.vg1x4(i32 %2, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fvdott.lane.za32.vg1x4(i32, , , , i32 immarg) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme-f8f16,+sme-f8f32" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim # | #0 0x000055ff7c91757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ff7c914515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ff7c917cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f67d9305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f67d935c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f67d9305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f67d92ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ff7c8ad24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ff7c8ad096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ff7c891f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ff7c541176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ff7c540e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f67d92eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f67d92ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f67d92ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ff7c540d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c (508 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_u32mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 nounde # | ... # `---data was truncated (10240/31748) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556d815fe57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556d815fb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556d815fecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f234f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f234f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f234f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f234f71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556d8159424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556d81594096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556d81578f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556d81228176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556d81227e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f234f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f234f71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f234f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556d81227d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c (509 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_ver_za8_u8_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.read.ver.vg2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read) # | declare { , } @llvm.aarch64.sme.read.ver.vg2.nxv16i8(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_ver_za8_s8_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.read.ver.vg2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_ver_za8_mf8_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.read.ver.vg2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_hor_za8_u8_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.read.hor.vg2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read) # | declare { , } @llvm.aarch64.sme.read.hor.vg2.nxv16i8(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_hor_za8_s8_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.read.hor.vg2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_hor_za8_mf8_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.read.hor.vg2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svread_hor_za8_u8_vg4(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , , , } @llvm.aarch64.sme.read.hor.vg4.nxv16i8(i32 0, i32 %0) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read) # | declare { , , , } @llvm.aarch64.sme.read.hor.vg4.nxv16i8(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svread_hor_za8_s8_vg4(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , , , } @llvm.aarch64.sme.read.hor.vg4.nxv16i8(i32 0, i32 %0) # | ret { , , , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svread_hor_za8_mf8_vg4(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , , , } @llvm.aarch64.sme.read.hor.vg4.nxv16i8(i32 0, i32 %0) # | ret { , , , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svread_ver_za8_u8_vg4(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , , , } @llvm.aarch64.sme.read.ver.vg4.nxv16i8(i32 0, i32 %0) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read) # | declare { , , , } @llvm.aarch64.sme.read.ver.vg4.nxv16i8(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svread_ver_za8_s8_vg4(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , , , } @llvm.aarch64.sme.read.ver.vg4.nxv16i8(i32 0, i32 %0) # | ret { , , , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svread_ver_za8_mf8_vg4(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , , , } @llvm.aarch64.sme.read.ver.vg4.nxv16i8(i32 0, i32 %0) # | ret { , , , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_hor_za16_u16_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.read.hor.vg2.nxv8i16(i32 1, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read) # | declare { , } @llvm.aarch64.sme.read.hor.vg2.nxv8i16(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_hor_za16_bf16_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.read.hor.vg2.nxv8bf16(i32 1, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read) # | declare { , } @llvm.aarch64.sme.read.hor.vg2.nxv8bf16(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_hor_za16_f16_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.read.hor.vg2.nxv8f16(i32 1, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read) # | declare { , } @llvm.aarch64.sme.read.hor.vg2.nxv8f16(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_hor_za16_s16_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.read.hor.vg2.nxv8i16(i32 1, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_ver_za16_u16_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c (510 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla2_f16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.fmlal.vg2x2.nxv8f16(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fmlal.vg2x2.nxv8f16(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla2_bf16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.fmlal.vg2x2.nxv8bf16(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fmlal.vg2x2.nxv8bf16(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla2_u16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.umlal.vg2x2.nxv8i16(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umlal.vg2x2.nxv8i16(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla2_s16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.smlal.vg2x2.nxv8i16(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smlal.vg2x2.nxv8i16(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla4 # | ... # `---data was truncated (10240/73614) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005579fb72257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005579fb71f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005579fb722cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb701849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb7018a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb701849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb701831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005579fb6b824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005579fb6b8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005579fb69cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005579fb34c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005579fb34be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb701832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb7018330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb7018330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005579fb34bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c (511 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintm_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frintm.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintm.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintm_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frintm.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintm.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintm_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frintm.nxv2f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintm.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintm_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.frintm.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintm_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.frintm.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintm_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.frintm.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintm_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frintm.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintm_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frintm.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintm_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frintm.nxv2f64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000564e69f3457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564e69f31515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564e69f34cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f43caa1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f43caa725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f43caa1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f43caa03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564e69eca24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564e69eca096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564e69eaef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564e69b5e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564e69b5de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f43caa04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f43caa050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f43caa050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564e69b5dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c (512 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005627af74c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005627af749515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005627af74ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f205241bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f20524725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f205241ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2052403507 abort ./stdlib/abort.c:85:3 # | #7 0x00005627af6e224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005627af6e2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005627af6c6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005627af376176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005627af375e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2052404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f20524050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f20524050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005627af375d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c (513 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacgt_f16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.facgt.nxv8f16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facgt.nxv8f16(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacgt_f32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.facgt.nxv4f32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facgt.nxv4f32(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacgt_f64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.facgt.nxv2f64( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facgt.nxv2f64(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacgt_n_f32( %pg, %op1, float noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca float, align 4 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store float %op2, ptr %op2.addr, align 4 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %.splatinsert = insertelement poison, float %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.facgt.nxv4f32( %3, %1, %.splat) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacgt_n_f64( %pg, %op1, double noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca double, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store double %op2, ptr %op2.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load double, ptr %op2.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %.splatinsert = insertelement poison, double %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.facgt.nxv2f64( %3, %1, %.splat) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055cfc559957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cfc5596515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cfc5599cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe69c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe69c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe69c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe69c11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cfc552f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cfc552f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cfc5513f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cfc51c3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cfc51c2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe69c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe69c11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe69c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cfc51c2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c (514 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c -check-prefix=RV64ZKNH # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @sha512sig0(i64 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i64, align 8 # | %rs1.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | store i64 %0, ptr %__x.addr.i, align 8 # | %1 = load i64, ptr %__x.addr.i, align 8 # | %2 = call i64 @llvm.riscv.sha512sig0(i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @sha512sig1(i64 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i64, align 8 # | %rs1.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | store i64 %0, ptr %__x.addr.i, align 8 # | %1 = load i64, ptr %__x.addr.i, align 8 # | %2 = call i64 @llvm.riscv.sha512sig1(i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @sha512sum0(i64 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i64, align 8 # | %rs1.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | store i64 %0, ptr %__x.addr.i, align 8 # | %1 = load i64, ptr %__x.addr.i, align 8 # | %2 = call i64 @llvm.riscv.sha512sum0(i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @sha512sum1(i64 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i64, align 8 # | %rs1.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | store i64 %0, ptr %__x.addr.i, align 8 # | %1 = load i64, ptr %__x.addr.i, align 8 # | %2 = call i64 @llvm.riscv.sha512sum1(i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @sha256sig0(i32 noundef signext %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.sha256sig0(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @sha256sig1(i32 noundef signext %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.sha256sig1(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @sha256sum0(i32 noundef signext %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.sha256sum0(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @sha256sum1(i32 noundef signext %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.sha256sum1(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.sha512sig0(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.sha512sig1(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.sha512sum0(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.sha512sum1(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha256sig0(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha256sig1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha256sum0(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha256sum1(i32) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zknh" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zknh1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555b9ba9557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555b9ba92515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555b9ba95cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa3cbf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa3cbf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa3cbf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa3cbf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555b9ba2b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555b9ba2b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555b9ba0ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555b9b6bf176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555b9b6bee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa3cbf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa3cbf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa3cbf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555b9b6bed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c -check-prefix=RV64ZKNH # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c -check-prefix=RV64ZKNH # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c (515 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i32.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv2i32.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i32.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv2i32.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv2i32.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_gather_u64base_s64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64( %2, %1, i64 0) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(, , i64) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_gather_u64base_u64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64( %2, %1, i64 0) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_gather_s64offset_s64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ld1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = zext %4 to # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(, ptr, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_gather_s64offset_u64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ld1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = zext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_gather_u64offset_s64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ld1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = zext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_gather_u64offset_u64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ld1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = zext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_gather_u64base_offset_s64( %pg, %bases, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c (516 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_f16mf4x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_f16mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_f16m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_i16mf4x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_i16mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_i16m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_u16mf4x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_u16mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_u16m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_f16mf4x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.ri # | ... # `---data was truncated (10240/20449) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f87f0af57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f87f0ac515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f87f0afcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc954333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc95438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc954333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc95431b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f87f04524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f87f045096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f87f029f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f87ecd9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f87ecd8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc95431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc95431d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc95431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f87ecd8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c (517 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 31) # | ret i64 %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.cnth(i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_1() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_2() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_3() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 3) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_4() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 4) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_5() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 5) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_6() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 6) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_7() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_8() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 8) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_9() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 9) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_10() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 10) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_11() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 11) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_12() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 12) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_13() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 13) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_14() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 29) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_15() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 30) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_16() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 31) # | ret i64 %0 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x0000563a5a64757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563a5a644515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563a5a647cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0a64f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0a64f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0a64f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0a64f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563a5a5dd24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563a5a5dd096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563a5a5c1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563a5a271176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563a5a270e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0a64f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0a64f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0a64f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563a5a270d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c (518 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m1x2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m2x2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m4x2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005616fdf1157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005616fdf0e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005616fdf11cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb4fcf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb4fcf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb4fcf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb4fcf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005616fdea724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005616fdea7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005616fde8bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005616fdb3b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005616fdb3ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb4fcf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb4fcf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb4fcf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005616fdb3ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c (519 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/80500) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557a5f9a357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557a5f9a0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557a5f9a3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc79fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc79faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc79fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc79fa31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557a5f93924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557a5f939096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557a5f91df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557a5f5cd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557a5f5cce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc79fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc79fa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc79fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557a5f5ccd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c (520 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.abs.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.abs.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.abs.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.abs.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.abs.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.abs.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.abs.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.abs.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s8_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.abs.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.abs.nxv8i16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.abs.nxv4i32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.abs.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s8_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.abs.nxv16i8( undef, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.abs.nxv8i16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 # | ... # `---data was truncated (10240/20016) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005570aae1157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005570aae0e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005570aae11cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0efff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0efff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0efff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0efff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005570aada724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005570aada7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005570aad8bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005570aaa3b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005570aaa3ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0efff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0efff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0efff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005570aaa3ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c (521 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s8_z( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = select %0, %1, zeroinitializer # | %3 = call @llvm.aarch64.sve.asrd.nxv16i8( %0, %2, i32 1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.asrd.nxv16i8(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s8_z_1( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = select %0, %1, zeroinitializer # | %3 = call @llvm.aarch64.sve.asrd.nxv16i8( %0, %2, i32 8) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s16_z( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = select %2, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.asrd.nxv8i16( %2, %3, i32 1) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.asrd.nxv8i16(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s16_z_1( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = select %2, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.asrd.nxv8i16( %2, %3, i32 16) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s32_z( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = select %2, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.asrd.nxv4i32( %2, %3, i32 1) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.asrd.nxv4i32(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s32_z_1( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = select %2, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.asrd.nxv4i32( %2, %3, i32 32) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s64_z( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = select %2, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.asrd.nxv2i64( %2, %3, i32 1) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.asrd.nxv2i64(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s64_z_1( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = select %2, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.asrd.nxv2i64( %2, %3, i32 64) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s8_m( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = call @llvm.aarch64.sve.asrd.nxv16i8( %0, %1, i32 1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s16_m( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.asrd.nxv8i16( %2, %1, i32 1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s32_m( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.asrd.nxv4i32( %2, # | ... # `---data was truncated (10240/14353) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055dbcc0e157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055dbcc0de515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055dbcc0e1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f84eed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f84eed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f84eed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f84eed1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dbcc07724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055dbcc077096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055dbcc05bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055dbcbd0b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055dbcbd0ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f84eed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f84eed1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f84eed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dbcbd0ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c (522 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @ll # | ... # `---data was truncated (10240/47728) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b2bc22457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b2bc221515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b2bc224cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff08e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff08e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff08e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff08e91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b2bc1ba24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b2bc1ba096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b2bc19ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b2bbe4e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b2bbe4de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff08e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff08e91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff08e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b2bbe4dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c (523 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_b8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.trn1.nxv16i1( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_b16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.trn1.b16( %0, %1) # | ret %2 # | ... # `---data was truncated (10240/13404) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000560e81d9557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560e81d92515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560e81d95cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbc8c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbc8c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbc8c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbc8c31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560e81d2b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560e81d2b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560e81d0ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560e819bf176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560e819bee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbc8c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbc8c31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbc8c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560e819bed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c (524 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_u8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { targe # | ... # `---data was truncated (10240/68233) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055977e59d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055977e59a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055977e59dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3b60f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3b60f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3b60f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3b60f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055977e53324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055977e533096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055977e517f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055977e1c7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055977e1c6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3b60f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3b60f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3b60f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055977e1c6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c (525 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_i8mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef # | ... # `---data was truncated (10240/69988) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559372a8457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559372a81515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559372a84cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4cf8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4cf898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4cf8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4cf891b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559372a1a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559372a1a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005593729fef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005593726ae176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005593726ade93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4cf891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4cf891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4cf891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005593726add81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c (526 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1q.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1q.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1q.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1q.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1q.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1q.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1q.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_bf16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1q.nxv8bf16(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005570d983757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005570d9834515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005570d9837cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f24a9733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f24a978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f24a9733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f24a971b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005570d97cd24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005570d97cd096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005570d97b1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005570d9461176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005570d9460e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f24a971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f24a971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f24a971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005570d9460d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c (527 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svqdmulh_single_s8_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv16i8( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svqdmulh_single_s16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv8i16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svqdmulh_single_s32_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv4i32( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svqdmulh_single_s64_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv2i64( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svqdmulh_single_s8_x4( %zdn.coerce0, %zdn.coerce1, %zdn.coerce2, %zdn.coerce3, %zm) #0 { # | entry: # | %zdn = alloca { , , , }, align 16 # | %zdn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zdn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zdn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zdn.coerce3, 3 # | store { , , , } %3, ptr %zdn, align 16 # | %zdn1 = load { , , , }, ptr %zdn, align 16 # | store { , , , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %4 = load { , , , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = load , ptr %zm.addr, align 16 # | %10 = call { , , , } @llvm.aarch64.sve.sqdmulh.single.vgx4.nxv16i8( %5, %6, %7, %8, %9) # | ret { , , , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.sqdmulh.single.vgx4.nxv16i8(, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svqdmulh_single_s16_x4( %zdn.coerce0, %zdn.coerce1, %zdn.coerce2, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/f16f32dot-intrinsics.c (528 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/f16f32dot-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +f16f32dot -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +f16f32dot -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vdot_f32_f16(<2 x float> noundef %r, <4 x half> noundef %a, <4 x half> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x float>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | store <2 x float> %r, ptr %r.addr, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %r.addr, align 8 # | %1 = load <4 x half>, ptr %a.addr, align 8 # | %2 = load <4 x half>, ptr %b.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vdot.i = bitcast <8 x i8> %3 to <2 x float> # | %vdot1.i = bitcast <8 x i8> %4 to <4 x half> # | %vdot2.i = bitcast <8 x i8> %5 to <4 x half> # | %vdot3.i = call <2 x float> @llvm.aarch64.neon.fdot.v2f32.v4f16(<2 x float> %vdot.i, <4 x half> %vdot1.i, <4 x half> %vdot2.i) # | store <2 x float> %vdot3.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %6, ptr %__ret.i, align 8 # | %7 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vdotq_f32_f16(<4 x float> noundef %r, <8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %r.addr = alloca <4 x float>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | store <4 x float> %r, ptr %r.addr, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %r.addr, align 16 # | %1 = load <8 x half>, ptr %a.addr, align 16 # | %2 = load <8 x half>, ptr %b.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vdot.i = bitcast <16 x i8> %3 to <4 x float> # | %vdot1.i = bitcast <16 x i8> %4 to <8 x half> # | %vdot2.i = bitcast <16 x i8> %5 to <8 x half> # | %vdot3.i = call <4 x float> @llvm.aarch64.neon.fdot.v4f32.v8f16(<4 x float> %vdot.i, <8 x half> %vdot1.i, <8 x half> %vdot2.i) # | store <4 x float> %vdot3.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %6, ptr %__ret.i, align 16 # | %7 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vdot_lane_f32_f16(<2 x float> noundef %r, <4 x half> noundef %a, <4 x half> noundef %b) #0 { # | entry: # | %r.addr = alloca <2 x float>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %__ret = alloca <2 x float>, align 8 # | %__s0 = alloca <2 x float>, align 8 # | %__s1 = alloca <4 x half>, align 8 # | %__s2 = alloca <4 x half>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x float>, align 8 # | store <2 x float> %r, ptr %r.addr, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %r.addr, align 8 # | store <2 x float> %0, ptr %__s0, align 8 # | %1 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %1, ptr %__s1, align 8 # | %2 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %2, ptr %__s2, align 8 # | %3 = load <8 x i8>, ptr %__s0, align 8 # | %4 = load <8 x i8>, ptr %__s1, align 8 # | %5 = load <8 x i8>, ptr %__s2, align 8 # | %6 = bitcast <8 x i8> %5 to <4 x half> # | %lane = shufflevector <4 x half> %6, <4 x half> %6, <4 x i32> zeroinitializer # | %vdot = bitcast <8 x i8> %3 to <2 x float> # | %vdot1 = bitcast <8 x i8> %4 to <4 x half> # | %vdot2 = call <2 x float> @llvm.aarch64.neon.fdot.v2f32.v4f16(<2 x float> %vdot, <4 x half> %vdot1, <4 x half> %lane) # | store <2 x float> %vdot2, ptr %ref.tmp, align 8 # | %7 = load <2 x float>, ptr %ref.tmp, align 8 # | store <2 x float> %7, ptr %__ret, align 8 # | %8 = load <2 x float>, ptr %__ret, align 8 # | store <2 x float> %8, ptr %tmp, align 8 # | %9 = load <2 x float>, ptr %tmp, align 8 # | ret <2 x float> %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x float> @llvm.aarch64.neon.fdot.v2f32.v4f16(<2 x float>, <4 x half>, <4 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vdot_laneq_f32_f16(<2 x float> noundef %r, <4 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %r.addr = alloca <2 x float>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <8 x half>, align 16 # | %__ret = alloca <2 x float>, align 8 # | %__s0 = alloca <2 x float>, align 8 # | %__s1 = alloca <4 x half>, align 8 # | %__s2 = alloca <8 x half>, align 16 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x float>, align 8 # | store <2 x float> %r, ptr %r.addr, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 16 # | %0 = load <2 x float>, ptr %r.addr, align 8 # | store <2 x float> %0, ptr %__s0, align 8 # | %1 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %1, ptr %__s1, align 8 # | %2 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %2, ptr %__s2, align 16 # | %3 = load <8 x i8>, ptr %__s0, align 8 # | %4 = load <8 x i8>, ptr %__s1, align 8 # | %5 = load <16 x i8>, ptr %__s2, align 16 # | %6 = bitcast <16 x i8> %5 to <8 x half> # | %lane = shufflevector <8 x half> %6, <8 x half> %6, <4 x i32> # | %vdot = bitcast <8 x i8> %3 to <2 x float> # | %vdot1 = bitcast <8 x i8> %4 to <4 x half> # | %vdot2 = call <2 x float> @llvm.aarch64.neon.fdot.v2f32.v4f16(<2 x float> %vdot, <4 x half> %vdot1, <4 x half> %lane) # | store <2 x float> %vdot2, ptr %ref.tmp, align 8 # | %7 = load <2 x float>, ptr %ref.tmp, align 8 # | store <2 x float> %7, ptr %__ret, align 8 # | %8 = load <2 x float>, ptr %__ret, align 8 # | store <2 x float> %8, ptr %tmp, align 8 # | %9 = load <2 x float>, ptr %tmp, align 8 # | ret <2 x float> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vdotq_lane_f32_f16(<4 x float> noundef %r, <8 x half> noundef %a, <4 x half> noundef %b) #0 { # | entry: # | %r.addr = alloca <4 x float>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <4 x half>, align 8 # | %__ret = alloca <4 x float>, align 16 # | %__s0 = alloca <4 x float>, align 16 # | %__s1 = alloca <8 x half>, align 16 # | %__s2 = alloca <4 x half>, align 8 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <4 x float>, align 16 # | store <4 x float> %r, ptr %r.addr, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <4 x half> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %r.addr, align 16 # | store <4 x float> %0, ptr %__s0, align 16 # | %1 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %1, ptr %__s1, align 16 # | %2 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %2, ptr %__s2, align 8 # | %3 = load <16 x i8>, ptr %__s0, align 16 # | %4 = load <16 x i8>, ptr %__s1, align 16 # | %5 = load <8 x i8>, ptr %__s2, align 8 # | %6 = bitcast <8 x i8> %5 to <4 x half> # | %lane = shufflevector <4 x half> %6, <4 x half> %6, <8 x i32> zeroinitializer # | %vdot = bitcast <16 x i8> %3 to <4 x float> # | %vdot1 = bitcast <16 x i8> %4 to <8 x half> # | %vdot2 = call <4 x float> @llvm.aarch64.neon.fdot.v4f32.v8f16(<4 x float> %vdot, <8 x half> %vdot1, <8 x half> %lane) # | store <4 x float> %vdot2, ptr %ref.tmp, align 16 # | %7 = load <4 x float>, ptr %ref.tmp, align 16 # | store <4 x float> %7, ptr %__ret, align 16 # | %8 = load <4 x float>, ptr %__ret, align 16 # | store <4 x float> %8, ptr %tmp, align 16 # | %9 = load <4 x float>, ptr %tmp, align 16 # | ret <4 x float> %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.aarch64.neon.fdot.v4f32.v8f16(<4 x float>, <8 x half>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vdotq_laneq_f32_f16(<4 x float> noundef %r, <8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %r.addr = alloca <4 x float>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %__ret = alloca <4 x float>, align 16 # | %__s0 = alloca <4 x float>, align 16 # | %__s1 = alloca <8 x half>, align 16 # | %__s2 = alloca <8 x half>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <4 x float>, align 16 # | store <4 x float> %r, ptr %r.addr, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %r.addr, align 16 # | store <4 x float> %0, ptr %__s0, align 16 # | %1 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %1, ptr %__s1, align 16 # | %2 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %2, ptr %__s2, align 16 # | %3 = load <16 x i8>, ptr %__s0, align 16 # | %4 = load <16 x i8>, ptr %__s1, align 16 # | %5 = load <16 x i8>, ptr %__s2, align 16 # | %6 = bitcast <16 x i8> %5 to <8 x half> # | %lane = shufflevector <8 x half> %6, <8 x half> %6, <8 x i32> # | %vdot = bitcast <16 x i8> %3 to <4 x float> # | %vdot1 = bitcast <16 x i8> %4 to <8 x half> # | %vdot2 = call <4 x float> @llvm.aa # | ... # `---data was truncated (10240/11256) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine # | #0 0x0000562bad28057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562bad27d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562bad280cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8383e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8383ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8383e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8383e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562bad21624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562bad216096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562bad1faf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562baceaa176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562bacea9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8383e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8383e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8383e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562bacea9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c (529 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svusdot_s32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.usdot.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.usdot.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svusdot_n_s32( %x, %y, i8 noundef %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca i8, align 1 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store i8 %z, ptr %z.addr, align 1 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load i8, ptr %z.addr, align 1 # | %.splatinsert = insertelement poison, i8 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.usdot.nxv4i32( %0, %1, %.splat) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svusdot_lane_s32_0( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.usdot.lane.nxv4i32( %0, %1, %2, i32 0) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.usdot.lane.nxv4i32(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svusdot_lane_s32_1( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.usdot.lane.nxv4i32( %0, %1, %2, i32 1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svusdot_lane_s32_2( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.usdot.lane.nxv4i32( %0, %1, %2, i32 2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svusdot_lane_s32_3( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.usdot.lane.nxv4i32( %0, %1, %2, i32 3) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+i8mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056359787457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563597871515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563597874cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f31c4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f31c478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f31c4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f31c471b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056359780a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056359780a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005635977eef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056359749e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056359749de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f31c471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f31c471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f31c471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056359749dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c (530 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i32.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv2i32.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv4i32.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv8i32.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv16i32.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i64.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv2i64.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv4i64.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv8i64.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv1i32.nxv1i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv1i32.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv2i32.nxv2i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv2i32.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv4i32.nxv4i8.i64(< # | ... # `---data was truncated (10240/17495) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005648f475b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005648f4758515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005648f475bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5c3d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5c3d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5c3d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5c3d71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005648f46f124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005648f46f1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005648f46d5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005648f4385176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005648f4384e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5c3d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5c3d71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5c3d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005648f4384d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c (531 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_bf16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmaxnm.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmaxnm.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_bf16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmaxnm.nxv8bf16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_bf16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmaxnm.u.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmaxnm.u.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_bf16_n_m( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fmaxnm.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_bf16_n_z( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmaxnm.nxv8bf16( %3, %4, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_bf16_n_x( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fmaxnm.u.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055cf36db157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cf36dae515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cf36db1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb5e3933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb5e398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb5e3933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb5e391b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cf36d4724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cf36d47096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cf36d2bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cf369db176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cf369dae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb5e391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb5e391d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb5e391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cf369dad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c (532 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16mf4_f8e4m3mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16mf4_f8e4m3mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16mf2_f8e4m3mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16mf2_f8e4m3mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m1_f8e4m3mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m1_f8e4m3mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m2_f8e4m3m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m2_f8e4m3m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m4_f8e4m3m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m4_f8e4m3m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m8_f8e4m3m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv32i8.nxv32bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv32i8.nxv32bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m8_f8e4m3m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load < # | ... # `---data was truncated (10240/84810) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ffeed6857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ffeed65515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ffeed68cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1d81933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1d8198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1d81933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1d8191b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ffeecfe24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ffeecfe096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ffeece2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ffee992176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ffee991e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1d8191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1d8191d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1d8191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ffee991d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c (533 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv1i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv2i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv4i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv8i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv16i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv32i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv64i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv1i16.i16.i64( %0, %1, i16 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv2i16.i16.i64( %0, %1, i16 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv4i16.i16.i64( %0, %1, i16 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i16.i16.i6 # | ... # `---data was truncated (10240/182165) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e40065b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e400658515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e40065bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7136a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7136a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7136a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7136a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e4005f124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e4005f1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e4005d5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e400285176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e400284e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7136a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7136a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7136a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e400284d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c (534 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c (535 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_i8mf4x5(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055feb4e2c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055feb4e29515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055feb4e2ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f39c741bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f39c74725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f39c741ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f39c7403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055feb4dc224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055feb4dc2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055feb4da6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055feb4a56176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055feb4a55e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f39c7404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f39c74050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f39c74050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055feb4a55d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c (536 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | s # | ... # `---data was truncated (10240/223359) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f1ba2af57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f1ba2ac515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f1ba2afcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7b3041bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7b304725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7b3041ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7b30403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f1ba24524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f1ba245096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f1ba229f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f1b9ed9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f1b9ed8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7b30404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7b304050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7b304050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f1b9ed8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c (537 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 # | ... # `---data was truncated (10240/66565) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005585e13e957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005585e13e6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005585e13e9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9a3bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9a3bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9a3bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9a3bf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005585e137f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005585e137f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005585e1363f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005585e1013176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005585e1012e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9a3bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9a3bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9a3bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005585e1012d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c (538 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m4_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon/fused-multiply-constrained.c (539 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon/fused-multiply-constrained.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -ffp-exception-behavior=strict -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c --check-prefixes=ALL,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -ffp-exception-behavior=strict -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <1 x double> @test_vfma_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <1 x double>, align 8 # | %__p1.addr.i = alloca <1 x double>, align 8 # | %__p2.addr.i = alloca <1 x double>, align 8 # | %__ret.i = alloca <1 x double>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x double>, align 8 # | %b.addr = alloca <1 x double>, align 8 # | %c.addr = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | store <1 x double> %b, ptr %b.addr, align 8 # | store <1 x double> %c, ptr %c.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | %1 = load <1 x double>, ptr %b.addr, align 8 # | %2 = load <1 x double>, ptr %c.addr, align 8 # | store <1 x double> %0, ptr %__p0.addr.i, align 8 # | store <1 x double> %1, ptr %__p1.addr.i, align 8 # | store <1 x double> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %6 = bitcast <8 x i8> %3 to <1 x double> # | %7 = bitcast <8 x i8> %4 to <1 x double> # | %8 = bitcast <8 x i8> %5 to <1 x double> # | %9 = call <1 x double> @llvm.experimental.constrained.fma.v1f64(<1 x double> %7, <1 x double> %8, <1 x double> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store <1 x double> %9, ptr %ref.tmp.i, align 8 # | %10 = load <1 x double>, ptr %ref.tmp.i, align 8 # | store <1 x double> %10, ptr %__ret.i, align 8 # | %11 = load <1 x double>, ptr %__ret.i, align 8 # | ret <1 x double> %11 # | } # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <1 x double> @test_vfma_laneq_f64(<1 x double> noundef %a, <1 x double> noundef %b, <2 x double> noundef %v) #0 { # | entry: # | %a.addr = alloca <1 x double>, align 8 # | %b.addr = alloca <1 x double>, align 8 # | %v.addr = alloca <2 x double>, align 16 # | %__ret = alloca <1 x double>, align 8 # | %__s0 = alloca <1 x double>, align 8 # | %__s1 = alloca <1 x double>, align 8 # | %__s2 = alloca <2 x double>, align 16 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | store <1 x double> %b, ptr %b.addr, align 8 # | store <2 x double> %v, ptr %v.addr, align 16 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__s0, align 8 # | %1 = load <1 x double>, ptr %b.addr, align 8 # | store <1 x double> %1, ptr %__s1, align 8 # | %2 = load <2 x double>, ptr %v.addr, align 16 # | store <2 x double> %2, ptr %__s2, align 16 # | %3 = load <8 x i8>, ptr %__s0, align 8 # | %4 = load <8 x i8>, ptr %__s1, align 8 # | %5 = load <16 x i8>, ptr %__s2, align 16 # | %6 = bitcast <8 x i8> %3 to double # | %7 = bitcast <8 x i8> %4 to double # | %8 = bitcast <16 x i8> %5 to <2 x double> # | %extract = extractelement <2 x double> %8, i32 0 # | %9 = call double @llvm.experimental.constrained.fma.f64(double %7, double %extract, double %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | %10 = bitcast double %9 to <1 x double> # | store <1 x double> %10, ptr %ref.tmp, align 8 # | %11 = load <1 x double>, ptr %ref.tmp, align 8 # | store <1 x double> %11, ptr %__ret, align 8 # | %12 = load <1 x double>, ptr %__ret, align 8 # | store <1 x double> %12, ptr %tmp, align 8 # | %13 = load <1 x double>, ptr %tmp, align 8 # | ret <1 x double> %13 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare double @llvm.experimental.constrained.fma.f64(double, double, double, metadata, metadata) #1 # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <2 x double> @test_vfmaq_laneq_f64(<2 x double> noundef %a, <2 x double> noundef %b, <2 x double> noundef %v) #0 { # | entry: # | %a.addr = alloca <2 x double>, align 16 # | %b.addr = alloca <2 x double>, align 16 # | %v.addr = alloca <2 x double>, align 16 # | %__ret = alloca <2 x double>, align 16 # | %__s0 = alloca <2 x double>, align 16 # | %__s1 = alloca <2 x double>, align 16 # | %__s2 = alloca <2 x double>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | store <2 x double> %b, ptr %b.addr, align 16 # | store <2 x double> %v, ptr %v.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | store <2 x double> %0, ptr %__s0, align 16 # | %1 = load <2 x double>, ptr %b.addr, align 16 # | store <2 x double> %1, ptr %__s1, align 16 # | %2 = load <2 x double>, ptr %v.addr, align 16 # | store <2 x double> %2, ptr %__s2, align 16 # | %3 = load <16 x i8>, ptr %__s0, align 16 # | %4 = load <16 x i8>, ptr %__s1, align 16 # | %5 = load <16 x i8>, ptr %__s2, align 16 # | %6 = bitcast <16 x i8> %3 to <2 x double> # | %7 = bitcast <16 x i8> %4 to <2 x double> # | %8 = bitcast <16 x i8> %5 to <2 x double> # | %lane = shufflevector <2 x double> %8, <2 x double> %8, <2 x i32> # | %9 = call <2 x double> @llvm.experimental.constrained.fma.v2f64(<2 x double> %lane, <2 x double> %7, <2 x double> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store <2 x double> %9, ptr %ref.tmp, align 16 # | %10 = load <2 x double>, ptr %ref.tmp, align 16 # | store <2 x double> %10, ptr %__ret, align 16 # | %11 = load <2 x double>, ptr %__ret, align 16 # | store <2 x double> %11, ptr %tmp, align 16 # | %12 = load <2 x double>, ptr %tmp, align 16 # | ret <2 x double> %12 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare <2 x double> @llvm.experimental.constrained.fma.v2f64(<2 x double>, <2 x double>, <2 x double>, metadata, metadata) #1 # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local float @test_vfmas_lane_f32(float noundef %a, float noundef %b, <2 x float> noundef %c) #0 { # | entry: # | %a.addr = alloca float, align 4 # | %b.addr = alloca float, align 4 # | %c.addr = alloca <2 x float>, align 8 # | %__ret = alloca float, align 4 # | %__s0 = alloca float, align 4 # | %__s1 = alloca float, align 4 # | %__s2 = alloca <2 x float>, align 8 # | %ref.tmp = alloca float, align 4 # | %tmp = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | store float %b, ptr %b.addr, align 4 # | store <2 x float> %c, ptr %c.addr, align 8 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__s0, align 4 # | %1 = load float, ptr %b.addr, align 4 # | store float %1, ptr %__s1, align 4 # | %2 = load <2 x float>, ptr %c.addr, align 8 # | store <2 x float> %2, ptr %__s2, align 8 # | %3 = load float, ptr %__s0, align 4 # | %4 = load float, ptr %__s1, align 4 # | %5 = load <2 x float>, ptr %__s2, align 8 # | %extract = extractelement <2 x float> %5, i32 1 # | %6 = call float @llvm.experimental.constrained.fma.f32(float %4, float %extract, float %3, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store float %6, ptr %ref.tmp, align 4 # | %7 = load float, ptr %ref.tmp, align 4 # | store float %7, ptr %__ret, align 4 # | %8 = load float, ptr %__ret, align 4 # | store float %8, ptr %tmp, align 4 # | %9 = load float, ptr %tmp, align 4 # | ret float %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare float @llvm.experimental.constrained.fma.f32(float, float, float, metadata, metadata) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare <1 x double> @llvm.experimental.constrained.fma.v1f64(<1 x double>, <1 x double>, <1 x double>, metadata, metadata) #1 # | # | attributes #0 = { noinline nounwind strictfp "stack-protector-buffer-size"="8" "target-features"="+neon" } # | attributes #1 = { nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) } # | attributes #2 = { strictfp } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055770657757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557706574515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557706577cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5da1b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5da1b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5da1b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5da1b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055770650d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055770650d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005577064f1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005577061a1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005577061a0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5da1b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5da1b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5da1b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005577061a0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c --check-prefixes=ALL,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c --check-prefixes=ALL,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c (540 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svrshl_single_s8_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.srshl.single.x2.nxv16i8( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.srshl.single.x2.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svrshl_single_s16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.srshl.single.x2.nxv8i16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.srshl.single.x2.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svrshl_single_s32_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.srshl.single.x2.nxv4i32( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.srshl.single.x2.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svrshl_single_s64_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.srshl.single.x2.nxv2i64( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.srshl.single.x2.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svrshl_single_u8_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.urshl.single.x2.nxv16i8( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.urshl.single.x2.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svrshl_single_u16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.urshl.single.x2.nxv8i16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , # | ... # `---data was truncated (10240/93119) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055aeb18fd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055aeb18fa515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055aeb18fdcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9d8d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9d8d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9d8d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9d8d51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aeb189324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055aeb1893096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055aeb1877f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055aeb1527176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055aeb1526e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9d8d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9d8d51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9d8d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aeb1526d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c (541 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %sr # | ... # `---data was truncated (10240/288111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056542d26457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056542d261515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056542d264cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fddc8b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fddc8b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fddc8b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fddc8b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056542d1fa24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056542d1fa096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056542d1def49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056542ce8e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056542ce8de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fddc8b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fddc8b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fddc8b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056542ce8dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c (542 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_i8mf8x7_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c (543 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_i8mf4x5(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561a157e657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561a157e3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561a157e6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6a70133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6a7018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6a70133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6a7011b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561a1577c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561a1577c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561a15760f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561a15410176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561a1540fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6a7011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6a7011d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6a7011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561a1540fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c (544 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005592ccc5d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005592ccc5a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005592ccc5dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa74ad05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa74ad5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa74ad05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa74aced507 abort ./stdlib/abort.c:85:3 # | #7 0x00005592ccbf324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005592ccbf3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005592ccbd7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005592cc887176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005592cc886e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa74aceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa74acef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa74acef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005592cc886d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon-misc.c (545 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon-misc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vcgez_s8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = icmp sge <8 x i8> %1, zeroinitializer # | %vcgez.i = sext <8 x i1> %2 to <8 x i8> # | store <8 x i8> %vcgez.i, ptr %ref.tmp.i, align 8 # | %3 = load <8 x i8>, ptr %ref.tmp.i, align 8 # | store <8 x i8> %3, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vcgez_s16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x i16> # | %3 = icmp sge <4 x i16> %2, zeroinitializer # | %vcgez.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vcgez.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vcgez_s32(<2 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <2 x i32> # | %3 = icmp sge <2 x i32> %2, zeroinitializer # | %vcgez.i = sext <2 x i1> %3 to <2 x i32> # | store <2 x i32> %vcgez.i, ptr %ref.tmp.i, align 8 # | %4 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %4, ptr %__ret.i, align 8 # | %5 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vcgez_s64(<1 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <1 x i64> # | %3 = icmp sge <1 x i64> %2, zeroinitializer # | %vcgez.i = sext <1 x i1> %3 to <1 x i64> # | store <1 x i64> %vcgez.i, ptr %ref.tmp.i, align 8 # | %4 = load <1 x i64>, ptr %ref.tmp.i, align 8 # | store <1 x i64> %4, ptr %__ret.i, align 8 # | %5 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vcgezq_s8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = icmp sge <16 x i8> %1, zeroinitializer # | %vcgez.i = sext <16 x i1> %2 to <16 x i8> # | store <16 x i8> %vcgez.i, ptr %ref.tmp.i, align 16 # | %3 = load <16 x i8>, ptr %ref.tmp.i, align 16 # | store <16 x i8> %3, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcgezq_s16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x i16> # | %3 = icmp sge <8 x i16> %2, zeroinitializer # | %vcgez.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vcgez.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vcgezq_s32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <4 x i32> # | %3 = icmp sge <4 x i32> %2, zeroinitializer # | %vcgez.i = sext <4 x i1> %3 to <4 x i32> # | store <4 x i32> %vcgez.i, ptr %ref.tmp.i, align 16 # | %4 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %4, ptr %__ret.i, align 16 # | %5 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vcgezq_s64(<2 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <2 x i64> # | %3 = icmp sge <2 x i64> %2, zeroinitializer # | %vcgez.i = sext <2 x i1> %3 to <2 x i64> # | store <2 x i64> %vcgez.i, ptr %ref.tmp.i, align 16 # | %4 = load <2 x i64>, ptr %ref.tmp.i, align 16 # | store <2 x i64> %4, ptr %__ret.i, align 16 # | %5 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vcgez_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <2 x float> # | %3 = fcmp oge <2 x float> %2, zeroinitializer # | %vcgez.i = sext <2 x i1> %3 to <2 x i32> # | store <2 x i32> %vcgez.i, ptr %ref.tmp.i, align 8 # | %4 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %4, ptr %__ret.i, align 8 # | %5 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vcgez_f64(<1 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x double>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <1 x double> # | %3 = fcmp oge <1 x double> %2, zeroinitializer # | %vcgez.i = sext <1 x i1> %3 to <1 x i64> # | store <1 x i64> %vcgez.i, ptr %ref.tmp.i, align 8 # | %4 = load <1 x i64>, ptr %ref.tmp.i, align 8 # | store <1 x i64> %4, ptr %__ret.i, align 8 # | %5 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vcgezq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <4 x float> # | %3 = fcmp oge <4 x float> %2, zeroinitializer # | %vcgez.i = sext <4 x i1> %3 to <4 x i32> # | store <4 x i32> %vcgez.i, ptr %ref.tmp.i, align 16 # | %4 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %4, ptr %__ret.i, align 16 # | %5 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vcgezq_f64(<2 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <2 x double> # | %3 = fcmp oge <2 x double> %2, zeroinitializer # | %vcgez.i = sext <2 x i1> %3 to <2 x i64> # | store <2 x i64> %vcgez.i, ptr %ref.tmp.i, align 16 # | %4 = load <2 x i64>, ptr %ref.tmp.i, align 16 # | store <2 x i64> %4, ptr %__ret.i, align 16 # | %5 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vclez_s8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, ali # | ... # `---data was truncated (10240/217310) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055c46998157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c46997e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c469981cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd84d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd84d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd84d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd84d51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c46991724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c469917096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c4698fbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c4695ab176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c4695aae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd84d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd84d51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd84d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c4695aad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c (546 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_multi_za32_vg1x2_f16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.fdot.za32.vg1x2.nxv8f16(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fdot.za32.vg1x2.nxv8f16(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_multi_za32_vg1x4_f16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm.coerce0, %zm.coerce1, %zm.coerce2, %zm.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zm = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | %4 = insertvalue { , , , } poison, %zm.coerce0, 0 # | %5 = insertvalue { , , , } %4, %zm.coerce1, 1 # | %6 = insertvalue { , , , } %5, %zm.coerce2, 2 # | %7 = insertvalue { , , , } %6, %zm.coerce3, 3 # | store { , , , } %7, ptr %zm, align 16 # | %zm2 = load { , , , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store { , , , } %zm2, ptr %zm.addr, align 16 # | %8 = load i32, ptr %slice_base.addr, align 4 # | %9 = load { , , , }, ptr %zn.addr, align 16 # | %10 = extractvalue { , , , } %9, 0 # | %11 = extractvalue { , , , } %9, 1 # | %12 = extractvalue { , , , } %9, 2 # | %13 = extractvalue { , , , } %9, 3 # | %14 = load { , , , }, ptr %zm.addr, align 16 # | %15 = extractvalue { , , , } %14, 0 # | %16 = extractvalue { , , , } %14, 1 # | %17 = extractvalue { , , , } %14, 2 # | %18 = extractvalue { , , , } %14, 3 # | call void @llvm.aarch64.sme.fdot.za32.vg1x4.nxv8f16(i32 %8, %10, %11, %12, %13, %15, %16, %17, %18) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fdot.za32.vg1x4.nxv8f16(i32, , , , , , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_single_za32_vg1x2_f16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.fdot.single.za32.vg1x2.nxv8f16(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fdot.single.za32.vg1x2.nxv8f16(i32, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_single_za32_vg1x4_f16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c (547 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sw_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i32.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv2i32.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sw_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i32.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sw_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv2i32.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sw_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv2i32.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055fc750f457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fc750f1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fc750f4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f567121bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f56712725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f567121ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5671203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fc7508a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fc7508a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fc7506ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fc74d1e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fc74d1de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5671204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f56712050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f56712050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fc74d1dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c (548 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcvt1_bf16_mf8_fpm(<8 x i8> %op, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %ref.tmp.i = alloca <8 x bfloat>, align 16 # | %op.addr = alloca <8 x i8>, align 8 # | %fpm.addr = alloca i64, align 8 # | store <8 x i8> %op, ptr %op.addr, align 8 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <8 x i8>, ptr %op.addr, align 8 # | %1 = load i64, ptr %fpm.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store i64 %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load i64, ptr %__p1.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %vbfcvt1.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl1.v8bf16.v8i8(<8 x i8> %2) # | store <8 x bfloat> %vbfcvt1.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x bfloat>, ptr %ref.tmp.i, align 16 # | store <8 x bfloat> %4, ptr %__ret.i, align 16 # | %5 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcvt1_low_bf16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %ref.tmp.i = alloca <8 x bfloat>, align 16 # | %op.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <16 x i8> %op, ptr %op.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <16 x i8>, ptr %op.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store i64 %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load i64, ptr %__p1.addr.i, align 8 # | %4 = call <8 x i8> @llvm.vector.extract.v8i8.v16i8(<16 x i8> %2, i64 0) # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %vbfcvt1.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl1.v8bf16.v8i8(<8 x i8> %4) # | store <8 x bfloat> %vbfcvt1.i, ptr %ref.tmp.i, align 16 # | %5 = load <8 x bfloat>, ptr %ref.tmp.i, align 16 # | store <8 x bfloat> %5, ptr %__ret.i, align 16 # | %6 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcvt2_bf16_mf8_fpm(<8 x i8> %op, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %ref.tmp.i = alloca <8 x bfloat>, align 16 # | %op.addr = alloca <8 x i8>, align 8 # | %fpm.addr = alloca i64, align 8 # | store <8 x i8> %op, ptr %op.addr, align 8 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <8 x i8>, ptr %op.addr, align 8 # | %1 = load i64, ptr %fpm.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store i64 %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load i64, ptr %__p1.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %vbfcvt2.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl2.v8bf16.v8i8(<8 x i8> %2) # | store <8 x bfloat> %vbfcvt2.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x bfloat>, ptr %ref.tmp.i, align 16 # | store <8 x bfloat> %4, ptr %__ret.i, align 16 # | %5 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcvt2_low_bf16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %ref.tmp.i = alloca <8 x bfloat>, align 16 # | %op.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <16 x i8> %op, ptr %op.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <16 x i8>, ptr %op.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store i64 %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load i64, ptr %__p1.addr.i, align 8 # | %4 = call <8 x i8> @llvm.vector.extract.v8i8.v16i8(<16 x i8> %2, i64 0) # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %vbfcvt2.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl2.v8bf16.v8i8(<8 x i8> %4) # | store <8 x bfloat> %vbfcvt2.i, ptr %ref.tmp.i, align 16 # | %5 = load <8 x bfloat>, ptr %ref.tmp.i, align 16 # | store <8 x bfloat> %5, ptr %__ret.i, align 16 # | %6 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcvt1_high_bf16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %ref.tmp.i = alloca <8 x bfloat>, align 16 # | %op.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <16 x i8> %op, ptr %op.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <16 x i8>, ptr %op.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store i64 %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load i64, ptr %__p1.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %vbfcvt1.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl1.v8bf16.v16i8(<16 x i8> %2) # | store <8 x bfloat> %vbfcvt1.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x bfloat>, ptr %ref.tmp.i, align 16 # | store <8 x bfloat> %4, ptr %__ret.i, align 16 # | %5 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcvt2_high_bf16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %ref.tmp.i = alloca <8 x bfloat>, align 16 # | %op.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <16 x i8> %op, ptr %op.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <16 x i8>, ptr %op.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store i64 %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load i64, ptr %__p1.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %vbfcvt2.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl2.v8bf16.v16i8(<16 x i8> %2) # | store <8 x bfloat> %vbfcvt2.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x bfloat>, ptr %ref.tmp.i, align 16 # | store <8 x bfloat> %4, ptr %__ret.i, align 16 # | %5 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vcvt1_f16_mf8_fpm(<8 x i8> %op, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <8 x half>, align 16 # | %op.addr = alloca <8 x i8>, align 8 # | %fpm.addr = alloca i64, align 8 # | store <8 x i8> %op, ptr %op.addr, align 8 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <8 x i8>, ptr %op.addr, align 8 # | %1 = load i64, ptr %fpm.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store i64 %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load i64, ptr %__p1.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %vbfcvt1.i = call <8 x half> @llvm.aarch64.neon.fp8.cvtl1.v8f16.v8i8(<8 x i8> %2) # | store <8 x half> %vbfcvt1.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %4, ptr %__ret.i, align 16 # | %5 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vcvt1_low_f16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <8 x half>, align 16 # | %op.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <16 x i8> %op, ptr %op.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <16 x i8>, ptr %op.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store i64 %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load i64, ptr %__p1.addr.i, align 8 # | %4 = call <8 x i8> @llvm.vector.extract.v8i8.v16i8(<16 x i8> %2, i64 0) # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %vbfcvt1.i = call <8 x half> @llvm.aarch64.neon.fp8.cvtl1.v8f16.v8i8(<8 x i8> %4) # | store <8 x half> %vbfcvt1.i, ptr %ref.tmp.i, align 16 # | %5 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %5, ptr %__ret.i, align 16 # | %6 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vcvt2_f16_mf8_fpm(<8 x i8> %op, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <8 x half>, align 16 # | %op.addr = alloca <8 x i8>, align 8 # | %fpm.addr = alloca i64, align 8 # | store <8 x i8> %op, ptr %op.addr, align 8 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <8 x i8>, ptr %op.addr, align 8 # | %1 = load i64, ptr %fpm.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store i64 %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load i64, ptr %__p1.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %vbfcvt2.i = call <8 x half> @llvm.aarch64.neon.fp8.cvtl2.v8f16.v8i8(<8 x i8> %2) # | store <8 x half> %vbfcvt2.i, ptr %ref.tmp.i # | ... # `---data was truncated (10240/23350) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa # | #0 0x000056475d23b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056475d238515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056475d23bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3bec133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3bec18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3bec133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3bec11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056475d1d124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056475d1d1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056475d1b5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056475ce65176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056475ce64e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3bec11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3bec11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3bec11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056475ce64d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c (549 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m4_bf16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv8bf16.nxv8i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv8bf16.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c (550 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf8_b64( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf4_b32( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf2_b16( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8m1_b8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8m2_b4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv32i8.n # | ... # `---data was truncated (10240/95347) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056280163457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562801631515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562801634cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faec6e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faec6ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faec6e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faec6e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005628015ca24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005628015ca096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005628015aef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056280125e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056280125de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007faec6e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faec6e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faec6e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056280125dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c (551 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_i64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_u64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_f64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 5) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_i64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 5) %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_u64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple # | ... # `---data was truncated (10240/20903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bde77f357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bde77f0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bde77f3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7451933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f745198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7451933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f745191b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bde778924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bde7789096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bde776df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bde741d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bde741ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f745191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f745191d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f745191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bde741cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c (552 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32mf2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m1_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m4_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m8_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32mf2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m1_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Fu # | ... # `---data was truncated (10240/25086) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dda9acc57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055dda9ac9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055dda9acccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f74b6333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f74b638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f74b6333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f74b631b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dda9a6224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055dda9a62096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055dda9a46f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055dda96f6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055dda96f5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f74b631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f74b631d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f74b631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dda96f5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c (553 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local half @test_svadda_f16( %pg, half noundef %initial, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %initial.addr = alloca half, align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store half %initial, ptr %initial.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load half, ptr %initial.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call half @llvm.aarch64.sve.fadda.nxv8f16( %3, half %1, %2) # | ret half %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.aarch64.sve.fadda.nxv8f16(, half, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local float @test_svadda_f32( %pg, float noundef %initial, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %initial.addr = alloca float, align 4 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store float %initial, ptr %initial.addr, align 4 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load float, ptr %initial.addr, align 4 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call float @llvm.aarch64.sve.fadda.nxv4f32( %3, float %1, %2) # | ret float %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.aarch64.sve.fadda.nxv4f32(, float, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local double @test_svadda_f64( %pg, double noundef %initial, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %initial.addr = alloca double, align 8 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store double %initial, ptr %initial.addr, align 8 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load double, ptr %initial.addr, align 8 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call double @llvm.aarch64.sve.fadda.nxv2f64( %3, double %1, %2) # | ret double %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.aarch64.sve.fadda.nxv2f64(, double, ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000563455f1e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563455f1b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563455f1ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f150db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f150db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f150db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f150db1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563455eb424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563455eb4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563455e98f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563455b48176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563455b47e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f150db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f150db1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f150db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563455b47d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c (554 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_i8mf4x6(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005601659aa57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005601659a7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005601659aacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2d5ae1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2d5ae725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2d5ae1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2d5ae03507 abort ./stdlib/abort.c:85:3 # | #7 0x000056016594024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560165940096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560165924f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005601655d4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005601655d3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2d5ae04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2d5ae050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2d5ae050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005601655d3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c (555 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vaeskf1.nxv1i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv1i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vaeskf1.nxv2i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv2i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vaeskf1.nxv4i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv4i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vaeskf1.nxv8i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv8i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vaeskf1.nxv16i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv16i32.i64.i64(, , i64 immarg, i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e7da26257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e7da25f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e7da262cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f50d5e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f50d5ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f50d5e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f50d5e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e7da1f824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e7da1f8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e7da1dcf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e7d9e8c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e7d9e8be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f50d5e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f50d5e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f50d5e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e7d9e8bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c (556 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f32m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f64m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f64.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; F # | ... # `---data was truncated (10240/102296) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fabe24157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fabe23e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fabe241cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fba52449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fba524a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fba52449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fba52431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fabe1d724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fabe1d7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fabe1bbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fabde6b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fabde6ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fba52432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fba524330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fba524330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fabde6ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c (557 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_s_s_w4_i8m8_i8m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.s.s.i64.nxv64i8.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.s.s.i64.nxv64i8.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557e696e657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557e696e3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557e696e6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fad62133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fad6218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fad62133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fad6211b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557e6967c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557e6967c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557e69660f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557e69310176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557e6930fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fad6211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fad6211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fad6211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557e6930fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c (558 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_f32mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_f32m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_i32mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_i32m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_u32mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_u32m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_f32mf2x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_f32m1x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_i32mf2x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_i32m1x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry # | ... # `---data was truncated (10240/14002) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005608d004a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005608d0047515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005608d004acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8da0c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8da0c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8da0c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8da0c03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005608cffe024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005608cffe0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005608cffc4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005608cfc74176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005608cfc73e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8da0c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8da0c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8da0c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005608cfc73d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c (559 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16mf4_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16mf2_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m1_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv4f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv4f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m2_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv8f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv8f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m4_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv16f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv16f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m8_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv32f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv32f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32mf2_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1f32.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32m1_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2f32.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32m2_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | s # | ... # `---data was truncated (10240/280209) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e1debc257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e1debbf515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e1debc2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6adf533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6adf58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6adf533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6adf51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e1deb5824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e1deb58096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e1deb3cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e1de7ec176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e1de7ebe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6adf51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6adf51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6adf51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e1de7ebd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c (560 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_i8mf8x7 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055726358857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557263585515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557263588cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f41a1933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f41a198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f41a1933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f41a191b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055726351e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055726351e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557263502f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005572631b2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005572631b1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f41a191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f41a191d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f41a191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005572631b1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c (561 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_i8mf8x8 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005579393fa57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005579393f7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005579393facbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1dae133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1dae18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1dae133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1dae11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055793939024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557939390096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557939374f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557939024176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557939023e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1dae11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1dae11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1dae11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557939023d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c (562 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, pt # | ... # `---data was truncated (10240/66557) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cc114fe57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cc114fb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cc114fecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f64e1f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f64e1f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f64e1f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f64e1f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cc1149424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cc11494096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cc11478f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cc11128176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cc11127e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f64e1f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f64e1f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f64e1f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cc11127d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c (563 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svunpk_s16_x4( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , , , } @llvm.aarch64.sve.sunpk.x4.nxv8i16( %3, %4) # | ret { , , , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.sunpk.x4.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svunpk_u16_x4( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , , , } @llvm.aarch64.sve.uunpk.x4.nxv8i16( %3, %4) # | ret { , , , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.uunpk.x4.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svunpk_s32_x4( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , , , } @llvm.aarch64.sve.sunpk.x4.nxv4i32( %3, %4) # | ret { , , , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.sunpk.x4.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svunpk_u32_x4( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , , , } @llvm.aarch64.sve.uunpk.x4.nxv4i32( %3, %4) # | ret { , , , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.uunpk.x4.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svunpk_s64_x4( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , , , } @llvm.aarch64.sve.sunpk.x4.nxv2i64( %3, %4) # | ret { , , , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.sunpk.x4.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svunpk_u64_x4( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , , , } @llvm.aarch64.sve.uunpk.x4.nxv2i64( %3, %4) # | ret { , , , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.uunpk.x4.nxv2i64(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005622d354557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005622d3542515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005622d3545cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb619649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb6196a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb619649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb619631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005622d34db24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005622d34db096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005622d34bff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005622d316f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005622d316ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb619632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb6196330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb6196330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005622d316ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c (564 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_cvtn_f16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.fcvtn.x2.nxv4f32( %3, %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcvtn.x2.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_cvtn_bf16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.bfcvtn.x2( %3, %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfcvtn.x2(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_qcvtn_u8_u32_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call @llvm.aarch64.sve.uqcvtn.x4.nxv4i32( %5, %6, %7, %8) # | ret %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.uqcvtn.x4.nxv4i32(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_qcvtn_u16_u64_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call @llvm.aarch64.sve.uqcvtn.x4.nxv2i64( %5, %6, %7, %8) # | ret %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.uqcvtn.x4.nxv2i64(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_qcvtn_s8_s32_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call @llvm.aarch64.sve.sqcvtn.x4.nxv4i32( %5, %6, %7, %8) # | ret %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.sqcvtn.x4.nxv4i32(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_loc # | ... # `---data was truncated (10240/17734) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005555c5ac257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005555c5abf515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005555c5ac2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efddd733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efddd78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efddd733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efddd71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005555c5a5824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005555c5a58096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005555c5a3cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005555c56ec176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005555c56ebe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efddd71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efddd71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efddd71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005555c56ebd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c (565 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_f16mf4x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_f16mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_f16m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_i16mf4x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_i16mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_i16m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_u16mf4x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_u16mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_u16m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_f16mf4x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.ri # | ... # `---data was truncated (10240/20449) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b78028c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b780289515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b78028ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2ec9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2ec9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2ec9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2ec9b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b78022224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b780222096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b780206f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b77feb6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b77feb5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2ec9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2ec9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2ec9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b77feb5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/orv.c (566 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve/orv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svorv_s8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.orv.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i8 @llvm.aarch64.sve.orv.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svorv_s16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.orv.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.aarch64.sve.orv.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svorv_s32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.orv.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.orv.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svorv_s64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.orv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.orv.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svorv_u8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.orv.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svorv_u16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.orv.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svorv_u32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.orv.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svorv_u64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.orv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x0000558ba543f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558ba543c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558ba543fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3fb5f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3fb5f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3fb5f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3fb5f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558ba53d524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558ba53d5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558ba53b9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558ba5069176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558ba5068e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3fb5f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3fb5f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3fb5f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558ba5068d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c (567 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_b8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.uzp2.nxv16i1( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_b16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.uzp2.b16( %0, %1) # | ret %2 # | ... # `---data was truncated (10240/13404) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000558a9440c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558a94409515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558a9440ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0796b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0796b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0796b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0796b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558a943a224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558a943a2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558a94386f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558a94036176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558a94035e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0796b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0796b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0796b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558a94035d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c (568 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_i32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_i32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_u32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_u32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32mf2x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret ta # | ... # `---data was truncated (10240/32031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563242af657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563242af3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563242af6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f10f7933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f10f798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f10f7933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f10f791b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563242a8c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563242a8c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563242a70f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563242720176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056324271fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f10f791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f10f791d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f10f791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056324271fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon/fused-multiply.c (569 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon/fused-multiply.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c --check-prefixes=ALL,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vfma_f32(<2 x float> noundef %a, <2 x float> noundef %b, <2 x float> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__p2.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | %c.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | store <2 x float> %c, ptr %c.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | %2 = load <2 x float>, ptr %c.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | store <2 x float> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %6 = bitcast <8 x i8> %3 to <2 x float> # | %7 = bitcast <8 x i8> %4 to <2 x float> # | %8 = bitcast <8 x i8> %5 to <2 x float> # | %9 = call <2 x float> @llvm.fma.v2f32(<2 x float> %7, <2 x float> %8, <2 x float> %6) # | store <2 x float> %9, ptr %ref.tmp.i, align 8 # | %10 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %10, ptr %__ret.i, align 8 # | %11 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vfma_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <1 x double>, align 8 # | %__p1.addr.i = alloca <1 x double>, align 8 # | %__p2.addr.i = alloca <1 x double>, align 8 # | %__ret.i = alloca <1 x double>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x double>, align 8 # | %b.addr = alloca <1 x double>, align 8 # | %c.addr = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | store <1 x double> %b, ptr %b.addr, align 8 # | store <1 x double> %c, ptr %c.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | %1 = load <1 x double>, ptr %b.addr, align 8 # | %2 = load <1 x double>, ptr %c.addr, align 8 # | store <1 x double> %0, ptr %__p0.addr.i, align 8 # | store <1 x double> %1, ptr %__p1.addr.i, align 8 # | store <1 x double> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %6 = bitcast <8 x i8> %3 to <1 x double> # | %7 = bitcast <8 x i8> %4 to <1 x double> # | %8 = bitcast <8 x i8> %5 to <1 x double> # | %9 = call <1 x double> @llvm.fma.v1f64(<1 x double> %7, <1 x double> %8, <1 x double> %6) # | store <1 x double> %9, ptr %ref.tmp.i, align 8 # | %10 = load <1 x double>, ptr %ref.tmp.i, align 8 # | store <1 x double> %10, ptr %__ret.i, align 8 # | %11 = load <1 x double>, ptr %__ret.i, align 8 # | ret <1 x double> %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vfmaq_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <4 x float>, align 16 # | %__p2.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <4 x float>, align 16 # | %c.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <4 x float> %b, ptr %b.addr, align 16 # | store <4 x float> %c, ptr %c.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | %2 = load <4 x float>, ptr %c.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <4 x float> %1, ptr %__p1.addr.i, align 16 # | store <4 x float> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %6 = bitcast <16 x i8> %3 to <4 x float> # | %7 = bitcast <16 x i8> %4 to <4 x float> # | %8 = bitcast <16 x i8> %5 to <4 x float> # | %9 = call <4 x float> @llvm.fma.v4f32(<4 x float> %7, <4 x float> %8, <4 x float> %6) # | store <4 x float> %9, ptr %ref.tmp.i, align 16 # | %10 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %10, ptr %__ret.i, align 16 # | %11 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vfmaq_f64(<2 x double> noundef %a, <2 x double> noundef %b, <2 x double> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__p1.addr.i = alloca <2 x double>, align 16 # | %__p2.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | %b.addr = alloca <2 x double>, align 16 # | %c.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | store <2 x double> %b, ptr %b.addr, align 16 # | store <2 x double> %c, ptr %c.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | %1 = load <2 x double>, ptr %b.addr, align 16 # | %2 = load <2 x double>, ptr %c.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | store <2 x double> %1, ptr %__p1.addr.i, align 16 # | store <2 x double> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %6 = bitcast <16 x i8> %3 to <2 x double> # | %7 = bitcast <16 x i8> %4 to <2 x double> # | %8 = bitcast <16 x i8> %5 to <2 x double> # | %9 = call <2 x double> @llvm.fma.v2f64(<2 x double> %7, <2 x double> %8, <2 x double> %6) # | store <2 x double> %9, ptr %ref.tmp.i, align 16 # | %10 = load <2 x double>, ptr %ref.tmp.i, align 16 # | store <2 x double> %10, ptr %__ret.i, align 16 # | %11 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vfma_lane_f32(<2 x float> noundef %a, <2 x float> noundef %b, <2 x float> noundef %v) #0 { # | entry: # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | %v.addr = alloca <2 x float>, align 8 # | %__ret = alloca <2 x float>, align 8 # | %__s0 = alloca <2 x float>, align 8 # | %__s1 = alloca <2 x float>, align 8 # | %__s2 = alloca <2 x float>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | store <2 x float> %v, ptr %v.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__s0, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | store <2 x float> %1, ptr %__s1, align 8 # | %2 = load <2 x float>, ptr %v.addr, align 8 # | store <2 x float> %2, ptr %__s2, align 8 # | %3 = load <8 x i8>, ptr %__s0, align 8 # | %4 = load <8 x i8>, ptr %__s1, align 8 # | %5 = load <8 x i8>, ptr %__s2, align 8 # | %6 = bitcast <8 x i8> %5 to <2 x float> # | %lane = shufflevector <2 x float> %6, <2 x float> %6, <2 x i32> # | %fmla = bitcast <8 x i8> %4 to <2 x float> # | %fmla1 = bitcast <8 x i8> %3 to <2 x float> # | %fmla2 = call <2 x float> @llvm.fma.v2f32(<2 x float> %fmla, <2 x float> %lane, <2 x float> %fmla1) # | store <2 x float> %fmla2, ptr %ref.tmp, align 8 # | %7 = load <2 x float>, ptr %ref.tmp, align 8 # | store <2 x float> %7, ptr %__ret, align 8 # | %8 = load <2 x float>, ptr %__ret, align 8 # | store <2 x float> %8, ptr %tmp, align 8 # | %9 = load <2 x float>, ptr %tmp, align 8 # | ret <2 x float> %9 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vfma_lane_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %v) #0 { # | entry: # | %a.addr = alloca <1 x double>, align 8 # | %b.addr = alloca <1 x double>, align 8 # | %v.addr = alloca <1 x double>, align 8 # | %__ret = alloca <1 x double>, align 8 # | %__s0 = alloca <1 x double>, align 8 # | %__s1 = alloca <1 x double>, align 8 # | %__s2 = alloca <1 x double>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | store <1 x double> %b, ptr %b.addr, align 8 # | store <1 x double> %v, ptr %v.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__s0, align 8 # | %1 = load <1 x double>, ptr %b.addr, align 8 # | store <1 x double> %1, ptr %__s1, align 8 # | %2 = load <1 x double>, ptr %v.addr, align 8 # | store <1 x double> %2, ptr %__s2, align 8 # | %3 = load <8 x i8>, ptr %__s0, align 8 # | %4 = load <8 x i8>, ptr %__s1, align 8 # | %5 = load <8 x i8>, ptr %__s2, align 8 # | %6 = bitcast <8 x i8> %5 to <1 x double> # | %lane = shufflevector <1 x double> %6, <1 x double> %6, <1 x i32> zeroinitializer # | %fmla = bitcast <8 x i8> %4 to <1 x double> # | %fmla1 = bitcast <8 x i8> %3 to <1 x double> # | %fmla2 = call <1 x double> @llvm.fma.v1f64(<1 x double> %fmla, <1 x double> %lane, <1 x double> %fmla1) # | store <1 x double> %fmla2, ptr %ref.tmp, align 8 # | %7 = load <1 x double>, ptr %ref.tmp, align 8 # | store <1 x double> %7, ptr %__ret, align 8 # | %8 = load <1 x double>, ptr %__ret, align 8 # | store <1 x double> %8, ptr %tmp, align 8 # | %9 = load <1 x double>, ptr %tmp, align 8 # | ret <1 x double> %9 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <1 x double> @llvm.fma.v1f64(<1 x double>, <1 x double>, <1 x double>) #1 # | # | ; Functio # | ... # `---data was truncated (10240/80179) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055b78916f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b78916c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b78916fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f26c1b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f26c1b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f26c1b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f26c1b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b78910524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b789105096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b7890e9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b788d99176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b788d98e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f26c1b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f26c1b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f26c1b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b788d98d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c --check-prefixes=ALL,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c --check-prefixes=ALL,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c (570 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svset2_s8( %tuple.coerce0, %tuple.coerce1, %x) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = load , ptr %x.addr, align 16 # | %4 = insertvalue { , } %2, %3, 1 # | ret { , } %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svset2_s16( %tuple.coerce0, %tuple.coerce1, %x) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = load , ptr %x.addr, align 16 # | %4 = insertvalue { , } %2, %3, 0 # | ret { , } %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svset2_s32( %tuple.coerce0, %tuple.coerce1, %x) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = load , ptr %x.addr, align 16 # | %4 = insertvalue { , } %2, %3, 1 # | ret { , } %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svset2_s64( %tuple.coerce0, %tuple.coerce1, %x) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = load , ptr %x.addr, align 16 # | %4 = insertvalue { , } %2, %3, 0 # | ret { , } %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svset2_u8( %tuple.coerce0, %tuple.coerce1, %x) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = load , ptr %x.addr, align 16 # | %4 = insertvalue { , } %2, %3, 1 # | ret { , } %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svset2_u16( %tuple.coerce0, %tuple.coerce1, %x) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = load , ptr %x.addr, align 16 # | %4 = insertvalue { , } %2, %3, 0 # | ret { , } %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svset2_u32( %tuple.coerce0, %tuple.coerce1, %x) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = load , ptr %x.addr, align 16 # | %4 = insertvalue { , } %2, %3, 1 # | ret { , } %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svset2_u64( %tuple.coerce0, %tuple.coerce1, %x) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = load , ptr %x.addr, align 16 # | %4 = insertvalue { , } %2, %3, 0 # | ret { , } %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c (571 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vect # | ... # `---data was truncated (10240/108856) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561edd9db57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561edd9d8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561edd9dbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f37ac81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f37ac8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f37ac81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f37ac803507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561edd97124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561edd971096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561edd955f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561edd605176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561edd604e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f37ac804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f37ac8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f37ac8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561edd604d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c (572 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c86bd2457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c86bd21515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c86bd24cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f821e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f821e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f821e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f821e31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c86bcba24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c86bcba096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c86bc9ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c86b94e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c86b94de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f821e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f821e31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f821e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c86b94dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c (573 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f64m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f64.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f64.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f64m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f64.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f64.p0.nxv2i64.i64(, ptr # | ... # `---data was truncated (10240/91267) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e43c9cf57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e43c9cc515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e43c9cfcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f92f0133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f92f018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f92f0133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f92f011b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e43c96524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e43c965096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e43c949f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e43c5f9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e43c5f8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f92f011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f92f011d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f92f011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e43c5f8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c (574 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m4_tu( %maskedoff, ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c (575 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevw_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.revw.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.revw.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevw_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.revw.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevw_s64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.revw.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevw_u64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.revw.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevw_s64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.revw.nxv2i64( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevw_u64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.revw.nxv2i64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055e3ed6ce57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e3ed6cb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e3ed6cecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7763f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7763f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7763f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7763eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e3ed66424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e3ed664096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e3ed648f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e3ed2f8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e3ed2f7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7763eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7763eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7763eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e3ed2f7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c (576 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local target("aarch64.svcount") @test_svpfalse_c() #0 { # | entry: # | ret target("aarch64.svcount") zeroinitializer # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055cca057d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cca057a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cca057dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fac56105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fac5615c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fac56105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fac560ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cca051324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cca0513096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cca04f7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cca01a7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cca01a6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fac560eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fac560ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fac560ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cca01a6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c (577 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_f64m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_i64m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_u64m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005620c317157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005620c316e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005620c3171cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe91b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe91b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe91b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe91b631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005620c310724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005620c3107096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005620c30ebf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005620c2d9b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005620c2d9ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe91b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe91b6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe91b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005620c2d9ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c (578 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpeq_s8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmpeq.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpeq.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpeq_s16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmpeq.nxv8i16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpeq.nxv8i16(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpeq_s32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmpeq.nxv4i32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpeq.nxv4i32(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpeq_s64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.cmpeq.nxv2i64( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpeq.nxv2i64(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpeq_u8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmpeq.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpeq_u16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmpeq.nxv8i16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpeq_u32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmpeq.nxv4i32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpeq_u64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.cmpeq.nxv2i64( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_r # | ... # `---data was truncated (10240/34127) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005606ba29857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005606ba295515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005606ba298cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2a41d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2a41d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2a41d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2a41d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005606ba22e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005606ba22e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005606ba212f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005606b9ec2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005606b9ec1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2a41d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2a41d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2a41d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005606b9ec1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c (579 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m4( %vd, %v # | ... # `---data was truncated (10240/148843) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f19f3c157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f19f3be515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f19f3c1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff145649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff1456a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff145649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff145631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f19f35724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f19f357096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f19f33bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f19efeb176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f19efeae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff145632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff1456330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff1456330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f19efead81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c (580 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrshr_u16_u32_x4( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.uqrshr.x2.nxv4i32( %3, %4, i32 16) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.uqrshr.x2.nxv4i32(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrshr_s16_s32_x4( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.sqrshr.x2.nxv4i32( %3, %4, i32 16) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.sqrshr.x2.nxv4i32(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrshr_u8_u32_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call @llvm.aarch64.sve.uqrshr.x4.nxv4i32( %5, %6, %7, %8, i32 8) # | ret %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.uqrshr.x4.nxv4i32(, , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrshr_s8_s32_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call @llvm.aarch64.sve.sqrshr.x4.nxv4i32( %5, %6, %7, %8, i32 8) # | ret %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.sqrshr.x4.nxv4i32(, , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrshr_u16_u64_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call @llvm.aarch64.sve.uqrshr.x4.nxv2i64( %5, %6, %7, %8, i32 16) # | ret %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.uqrshr.x4.nxv2i64(, , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscal # | ... # `---data was truncated (10240/33461) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x000055d685ef157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d685eee515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d685ef1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5ba7f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5ba7f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5ba7f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5ba7eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d685e8724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d685e87096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d685e6bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d685b1b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d685b1ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5ba7eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5ba7eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5ba7eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d685b1ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c (581 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmsb_f16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmsb.nxv8f16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmsb.nxv8f16(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmsb_f32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmsb.nxv4f32( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmsb.nxv4f32(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmsb_f64_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmsb.nxv2f64( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmsb.nxv2f64(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmsb_f16_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fnmsb.nxv8f16( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmsb_f32_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = call @llvm.aarch64.sve.fnmsb.nxv4f32( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmsb_f64_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = call @llvm.aarch64.sve.fnmsb.nxv2f64( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmsb_f16_x( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fnmls.u.nxv8f16( %4, %3, %2, %1) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind w # | ... # `---data was truncated (10240/26173) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055b2141e257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b2141df515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b2141e2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd6a5c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd6a5ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd6a5c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd6a5c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b21417824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b214178096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b21415cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b213e0c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b213e0be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd6a5c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd6a5c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd6a5c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b213e0bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c (582 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svset4_b_0( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3, %x) #0 { # | entry: # | %tuple = alloca { , , , }, align 2 # | %tuple.addr = alloca { , , , }, align 2 # | %x.addr = alloca , align 2 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 2 # | %tuple1 = load { , , , }, ptr %tuple, align 2 # | store { , , , } %tuple1, ptr %tuple.addr, align 2 # | store %x, ptr %x.addr, align 2 # | %4 = load { , , , }, ptr %tuple.addr, align 2 # | %5 = load , ptr %x.addr, align 2 # | %6 = insertvalue { , , , } %4, %5, 0 # | ret { , , , } %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svset4_b_1( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3, %x) #0 { # | entry: # | %tuple = alloca { , , , }, align 2 # | %tuple.addr = alloca { , , , }, align 2 # | %x.addr = alloca , align 2 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 2 # | %tuple1 = load { , , , }, ptr %tuple, align 2 # | store { , , , } %tuple1, ptr %tuple.addr, align 2 # | store %x, ptr %x.addr, align 2 # | %4 = load { , , , }, ptr %tuple.addr, align 2 # | %5 = load , ptr %x.addr, align 2 # | %6 = insertvalue { , , , } %4, %5, 1 # | ret { , , , } %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svset4_b_3( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3, %x) #0 { # | entry: # | %tuple = alloca { , , , }, align 2 # | %tuple.addr = alloca { , , , }, align 2 # | %x.addr = alloca , align 2 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 2 # | %tuple1 = load { , , , }, ptr %tuple, align 2 # | store { , , , } %tuple1, ptr %tuple.addr, align 2 # | store %x, ptr %x.addr, align 2 # | %4 = load { , , , }, ptr %tuple.addr, align 2 # | %5 = load , ptr %x.addr, align 2 # | %6 = insertvalue { , , , } %4, %5, 3 # | ret { , , , } %6 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000558f2bb0557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558f2bb02515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558f2bb05cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6374d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6374d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6374d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6374d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558f2ba9b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558f2ba9b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558f2ba7ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558f2b72f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558f2b72ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6374d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6374d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6374d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558f2b72ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c (583 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.sqadd.x.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqadd.x.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.sqadd.x.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqadd.x.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.sqadd.x.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqadd.x.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.sqadd.x.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqadd.x.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uqadd.x.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqadd.x.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uqadd.x.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqadd.x.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uqadd.x.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqadd.x.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uqadd.x.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqadd.x.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_n_s8( %op1, i8 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i8, align 1 # | store %op1, ptr %op1.addr, align 16 # | store i8 %op2, ptr %op2.addr, align 1 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i8, ptr %op2.addr, align 1 # | %.splatinsert = insertelement poison, i8 %1, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %2 = call @llvm.aarch64.sve.sqadd.x.nxv16i8( %0, %.splat) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_n_s16( %op1, i16 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i16, align 2 # | store %op1, ptr %op1.addr, align 16 # | store i16 %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i16, ptr %op2.addr, align 2 # | %.splatinsert = insertelement poison, i16 %1, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %2 = call @llvm.aarch64.sve.sqadd.x.nxv8i16( %0, %.splat) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_n_s32( %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i32, align 4 # | store %op1, ptr %op1.addr, align 16 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i32, ptr %op2.addr, align 4 # | %.splatinsert = insertelement poison, i32 %1, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %2 = call @llvm.aarch64.sve.sqadd.x.nxv4i32( %0, %.splat) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_n_s64( %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 16 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i64, ptr %op2.addr, align 8 # | %.splatinsert = insertelement poison, i64 %1, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %2 = call @llvm.aarch64.sve.sqadd.x.nxv2i64( %0, %.splat) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_l # | ... # `---data was truncated (10240/13780) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000556c6099757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556c60994515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556c60997cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9fb281bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9fb28725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9fb281ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9fb2803507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556c6092d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556c6092d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556c60911f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556c605c1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556c605c0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9fb2804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9fb28050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9fb28050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556c605c0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c (584 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_lane_bf16_idx1( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.fmul.lane.nxv8bf16( %0, %1, i32 1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmul.lane.nxv8bf16(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_lane_bf16_idx3( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.fmul.lane.nxv8bf16( %0, %1, i32 3) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_lane_bf16_idx7( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.fmul.lane.nxv8bf16( %0, %1, i32 7) # | ret %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16b16,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005611fbd7657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005611fbd73515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005611fbd76cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4d93533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4d9358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4d93533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4d9351b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005611fbd0c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005611fbd0c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005611fbcf0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005611fb9a0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005611fb99fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4d9351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4d9351d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4d9351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005611fb99fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c (585 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.prf.nxv16i1.p0(, ptr, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_1( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_2( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_3( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_4( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_5( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_6( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 8) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_7( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 9) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 10) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_9( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 11) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_10( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 12) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_11( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 13) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_vnum( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = getelementptr , ptr %1, i64 %2 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %3, i32 0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_gather_u32base( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prfb.gather.scalar.offset.nxv4i32( %2, %1, i64 0, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) # | declare void @llvm.aarch64.sve.prfb.gather.scalar.offset.nxv4i32(, , i64, i32 immarg) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_gather_u64base( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prfb.gather.scalar.offset.nxv2i64( %2, %1, i64 0, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) # | declare void @llvm.aarch64.sve.prfb.gather.scalar.offset.nxv2i64(, , i64, i32 immarg) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_gather_s32offset( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, ali # | ... # `---data was truncated (10240/16554) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055f4a0cdc57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f4a0cd9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f4a0cdccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6dc0533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6dc058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6dc0533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6dc051b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f4a0c7224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f4a0c72096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f4a0c56f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f4a0906176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f4a0905e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6dc051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6dc051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6dc051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f4a0905d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c (586 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f32mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f32mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmmla_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmmla.nxv4f32.nxv4f32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmmla.nxv4f32.nxv4f32(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f32mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000562b21c4457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562b21c41515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562b21c44cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7be8d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7be8d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7be8d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7be8d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562b21bda24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562b21bda096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562b21bbef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562b2186e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562b2186de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7be8d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7be8d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7be8d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562b2186dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c (587 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m4( % # | ... # `---data was truncated (10240/149145) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005565ceaa457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005565ceaa1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005565ceaa4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6058933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f605898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6058933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f605891b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005565cea3a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005565cea3a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005565cea1ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005565ce6ce176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005565ce6cde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f605891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f605891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f605891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005565ce6cdd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c (588 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c (589 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_i32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_i32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_u32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_u32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32mf2x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple" # | ... # `---data was truncated (10240/35929) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cfb69e557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cfb69e2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cfb69e5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fafdb049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fafdb0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fafdb049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fafdb031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cfb697b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cfb697b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cfb695ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cfb660f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cfb660ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fafdb032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fafdb0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fafdb0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cfb660ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c (590 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nx # | ... # `---data was truncated (10240/25567) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c16cf6457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c16cf61515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c16cf64cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb1dff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb1dff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb1dff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb1dff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c16cefa24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c16cefa096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c16cedef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c16cb8e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c16cb8de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb1dff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb1dff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb1dff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c16cb8dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vbrsrq.c (591 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vbrsrq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbrsrq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call <4 x i32> @llvm.arm.mve.vbrsr.v4i32(<4 x i32> %0, i32 %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vbrsr.v4i32(<4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vbrsrq_n_f16(<8 x half> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca i32, align 4 # | store <8 x half> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call <8 x half> @llvm.arm.mve.vbrsr.v8f16(<8 x half> %0, i32 %1) # | ret <8 x half> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vbrsr.v8f16(<8 x half>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vbrsrq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %inactive.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = load i32, ptr %b.addr, align 4 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4) # | %6 = call <16 x i8> @llvm.arm.mve.vbrsr.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 %2, <16 x i1> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vbrsr.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vbrsrq_m_n_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %inactive.addr, align 8 # | %1 = load <4 x float>, ptr %a.addr, align 8 # | %2 = load i32, ptr %b.addr, align 4 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4) # | %6 = call <4 x float> @llvm.arm.mve.vbrsr.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 %2, <4 x i1> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.vbrsr.predicated.v4f32.v4i1(<4 x float>, <4 x float>, i32, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbrsrq_x_n_u16(<8 x i16> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vbrsr.predicated.v8i16.v8i1(<8 x i16> undef, <8 x i16> %0, i32 %1, <8 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vbrsr.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vbrsrq_x_n_f16(<8 x half> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x half> @llvm.arm.mve.vbrsr.predicated.v8f16.v8i1(<8 x half> undef, <8 x half> %0, i32 %1, <8 x i1> %4) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vbrsr.predicated.v8f16.v8i1(<8 x half>, <8 x half>, i32, <8 x i1>) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005585be5cc57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005585be5c9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005585be5cccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1483c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1483ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1483c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1483c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005585be56224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005585be562096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005585be546f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005585be1f6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005585be1f5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1483c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1483c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1483c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005585be1f5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c (592 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_i64m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_i64m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_u64m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_u64m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557f4a5ab57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557f4a5a8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557f4a5abcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3d2821bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3d282725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3d2821ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3d28203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557f4a54124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557f4a541096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557f4a525f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557f4a1d5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557f4a1d4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3d28204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3d282050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3d282050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557f4a1d4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c (593 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a88564d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a88564a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a88564dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2d8ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2d8caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2d8ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2d8ca31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a8855e324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a8855e3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a8855c7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a885277176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a885276e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2d8ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2d8ca330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2d8ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a885276d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/neon/bf16-getset.c (594 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon/bf16-getset.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c --check-prefixes=ALL,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local bfloat @test_vduph_lane_bf16(<4 x bfloat> noundef %v) #0 { # | entry: # | %v.addr = alloca <4 x bfloat>, align 8 # | %__ret = alloca bfloat, align 2 # | %__s0 = alloca <4 x bfloat>, align 8 # | %ref.tmp = alloca bfloat, align 2 # | %tmp = alloca bfloat, align 2 # | store <4 x bfloat> %v, ptr %v.addr, align 8 # | %0 = load <4 x bfloat>, ptr %v.addr, align 8 # | store <4 x bfloat> %0, ptr %__s0, align 8 # | %1 = load <4 x bfloat>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x bfloat> %1, i32 1 # | store bfloat %vget_lane, ptr %ref.tmp, align 2 # | %2 = load bfloat, ptr %ref.tmp, align 2 # | store bfloat %2, ptr %__ret, align 2 # | %3 = load bfloat, ptr %__ret, align 2 # | store bfloat %3, ptr %tmp, align 2 # | %4 = load bfloat, ptr %tmp, align 2 # | ret bfloat %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local bfloat @test_vduph_laneq_bf16(<8 x bfloat> noundef %v) #0 { # | entry: # | %v.addr = alloca <8 x bfloat>, align 16 # | %__ret = alloca bfloat, align 2 # | %__s0 = alloca <8 x bfloat>, align 16 # | %ref.tmp = alloca bfloat, align 2 # | %tmp = alloca bfloat, align 2 # | store <8 x bfloat> %v, ptr %v.addr, align 16 # | %0 = load <8 x bfloat>, ptr %v.addr, align 16 # | store <8 x bfloat> %0, ptr %__s0, align 16 # | %1 = load <8 x bfloat>, ptr %__s0, align 16 # | %vgetq_lane = extractelement <8 x bfloat> %1, i32 7 # | store bfloat %vgetq_lane, ptr %ref.tmp, align 2 # | %2 = load bfloat, ptr %ref.tmp, align 2 # | store bfloat %2, ptr %__ret, align 2 # | %3 = load bfloat, ptr %__ret, align 2 # | store bfloat %3, ptr %tmp, align 2 # | %4 = load bfloat, ptr %tmp, align 2 # | ret bfloat %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vdup_lane_bf16(<4 x bfloat> noundef %v) #0 { # | entry: # | %v.addr = alloca <4 x bfloat>, align 8 # | %__ret_48 = alloca <4 x bfloat>, align 8 # | %__s0_48 = alloca <4 x bfloat>, align 8 # | %__ret = alloca <4 x bfloat>, align 8 # | %__s0 = alloca <4 x bfloat>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x bfloat>, align 8 # | %tmp1 = alloca <4 x bfloat>, align 8 # | store <4 x bfloat> %v, ptr %v.addr, align 8 # | %0 = load <4 x bfloat>, ptr %v.addr, align 8 # | store <4 x bfloat> %0, ptr %__s0_48, align 8 # | %1 = load <4 x bfloat>, ptr %__s0_48, align 8 # | store <4 x bfloat> %1, ptr %__s0, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = bitcast <8 x i8> %2 to <4 x bfloat> # | %lane = shufflevector <4 x bfloat> %3, <4 x bfloat> %3, <4 x i32> # | store <4 x bfloat> %lane, ptr %ref.tmp, align 8 # | %4 = load <4 x bfloat>, ptr %ref.tmp, align 8 # | store <4 x bfloat> %4, ptr %__ret, align 8 # | %5 = load <4 x bfloat>, ptr %__ret, align 8 # | store <4 x bfloat> %5, ptr %tmp, align 8 # | %6 = load <4 x bfloat>, ptr %tmp, align 8 # | store <4 x bfloat> %6, ptr %__ret_48, align 8 # | %7 = load <4 x bfloat>, ptr %__ret_48, align 8 # | store <4 x bfloat> %7, ptr %tmp1, align 8 # | %8 = load <4 x bfloat>, ptr %tmp1, align 8 # | ret <4 x bfloat> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vdupq_lane_bf16(<4 x bfloat> noundef %v) #0 { # | entry: # | %v.addr = alloca <4 x bfloat>, align 8 # | %__ret_46 = alloca <8 x bfloat>, align 16 # | %__s0_46 = alloca <4 x bfloat>, align 8 # | %__ret = alloca <8 x bfloat>, align 16 # | %__s0 = alloca <4 x bfloat>, align 8 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x bfloat>, align 16 # | %tmp1 = alloca <8 x bfloat>, align 16 # | store <4 x bfloat> %v, ptr %v.addr, align 8 # | %0 = load <4 x bfloat>, ptr %v.addr, align 8 # | store <4 x bfloat> %0, ptr %__s0_46, align 8 # | %1 = load <4 x bfloat>, ptr %__s0_46, align 8 # | store <4 x bfloat> %1, ptr %__s0, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = bitcast <8 x i8> %2 to <4 x bfloat> # | %lane = shufflevector <4 x bfloat> %3, <4 x bfloat> %3, <8 x i32> # | store <8 x bfloat> %lane, ptr %ref.tmp, align 16 # | %4 = load <8 x bfloat>, ptr %ref.tmp, align 16 # | store <8 x bfloat> %4, ptr %__ret, align 16 # | %5 = load <8 x bfloat>, ptr %__ret, align 16 # | store <8 x bfloat> %5, ptr %tmp, align 16 # | %6 = load <8 x bfloat>, ptr %tmp, align 16 # | store <8 x bfloat> %6, ptr %__ret_46, align 16 # | %7 = load <8 x bfloat>, ptr %__ret_46, align 16 # | store <8 x bfloat> %7, ptr %tmp1, align 16 # | %8 = load <8 x bfloat>, ptr %tmp1, align 16 # | ret <8 x bfloat> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vdup_laneq_bf16(<8 x bfloat> noundef %v) #0 { # | entry: # | %v.addr = alloca <8 x bfloat>, align 16 # | %__ret_52 = alloca <4 x bfloat>, align 8 # | %__s0_52 = alloca <8 x bfloat>, align 16 # | %__ret = alloca <4 x bfloat>, align 8 # | %__s0 = alloca <8 x bfloat>, align 16 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x bfloat>, align 8 # | %tmp1 = alloca <4 x bfloat>, align 8 # | store <8 x bfloat> %v, ptr %v.addr, align 16 # | %0 = load <8 x bfloat>, ptr %v.addr, align 16 # | store <8 x bfloat> %0, ptr %__s0_52, align 16 # | %1 = load <8 x bfloat>, ptr %__s0_52, align 16 # | store <8 x bfloat> %1, ptr %__s0, align 16 # | %2 = load <16 x i8>, ptr %__s0, align 16 # | %3 = bitcast <16 x i8> %2 to <8 x bfloat> # | %lane = shufflevector <8 x bfloat> %3, <8 x bfloat> %3, <4 x i32> # | store <4 x bfloat> %lane, ptr %ref.tmp, align 8 # | %4 = load <4 x bfloat>, ptr %ref.tmp, align 8 # | store <4 x bfloat> %4, ptr %__ret, align 8 # | %5 = load <4 x bfloat>, ptr %__ret, align 8 # | store <4 x bfloat> %5, ptr %tmp, align 8 # | %6 = load <4 x bfloat>, ptr %tmp, align 8 # | store <4 x bfloat> %6, ptr %__ret_52, align 8 # | %7 = load <4 x bfloat>, ptr %__ret_52, align 8 # | store <4 x bfloat> %7, ptr %tmp1, align 8 # | %8 = load <4 x bfloat>, ptr %tmp1, align 8 # | ret <4 x bfloat> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vdupq_laneq_bf16(<8 x bfloat> noundef %v) #0 { # | entry: # | %v.addr = alloca <8 x bfloat>, align 16 # | %__ret_50 = alloca <8 x bfloat>, align 16 # | %__s0_50 = alloca <8 x bfloat>, align 16 # | %__ret = alloca <8 x bfloat>, align 16 # | %__s0 = alloca <8 x bfloat>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x bfloat>, align 16 # | %tmp1 = alloca <8 x bfloat>, align 16 # | store <8 x bfloat> %v, ptr %v.addr, align 16 # | %0 = load <8 x bfloat>, ptr %v.addr, align 16 # | store <8 x bfloat> %0, ptr %__s0_50, align 16 # | %1 = load <8 x bfloat>, ptr %__s0_50, align 16 # | store <8 x bfloat> %1, ptr %__s0, align 16 # | %2 = load <16 x i8>, ptr %__s0, align 16 # | %3 = bitcast <16 x i8> %2 to <8 x bfloat> # | %lane = shufflevector <8 x bfloat> %3, <8 x bfloat> %3, <8 x i32> # | store <8 x bfloat> %lane, ptr %ref.tmp, align 16 # | %4 = load <8 x bfloat>, ptr %ref.tmp, align 16 # | store <8 x bfloat> %4, ptr %__ret, align 16 # | %5 = load <8 x bfloat>, ptr %__ret, align 16 # | store <8 x bfloat> %5, ptr %tmp, align 16 # | %6 = load <8 x bfloat>, ptr %tmp, align 16 # | store <8 x bfloat> %6, ptr %__ret_50, align 16 # | %7 = load <8 x bfloat>, ptr %__ret_50, align 16 # | store <8 x bfloat> %7, ptr %tmp1, align 16 # | %8 = load <8 x bfloat>, ptr %tmp1, align 16 # | ret <8 x bfloat> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vdup_n_bf16(bfloat noundef %v) #0 { # | entry: # | %__p0.addr.i = alloca bfloat, align 2 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %.compoundliteral.i = alloca <4 x bfloat>, align 8 # | %v.addr = alloca bfloat, align 2 # | store bfloat %v, ptr %v.addr, align 2 # | %0 = load bfloat, ptr %v.addr, align 2 # | store bfloat %0, ptr %__p0.addr.i, align 2 # | %1 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit.i = insertelement <4 x bfloat> poison, bfloat %1, i32 0 # | %2 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit1.i = insertelement <4 x bfloat> %vecinit.i, bfloat %2, i32 1 # | %3 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit2.i = insertelement <4 x bfloat> %vecinit1.i, bfloat %3, i32 2 # | %4 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit3.i = insertelement <4 x bfloat> %vecinit2.i, bfloat %4, i32 3 # | store <4 x bfloat> %vecinit3.i, ptr %.compoundliteral.i, align 8 # | %5 = load <4 x bfloat>, ptr %.compoundliteral.i, align 8 # | store <4 x bfloat> %5, ptr %__ret.i, align 8 # | %6 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vdupq_n_bf16(bfloat noundef %v) #0 { # | entry: # | %__p0.addr.i = alloca bfloat, align 2 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %.compoundliteral.i = alloca <8 x bfloat>, align 16 # | %v.addr = alloca bfloat, align 2 # | store bfloat %v, ptr %v.addr, align 2 # | %0 = load bfloat, ptr %v.addr, align 2 # | store bfloat %0, ptr %__p0.addr.i, align 2 # | %1 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit.i = insertelement <8 x bfloat> poison, bfloat %1, i32 0 # | %2 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit1.i = insertelement <8 x bfloat> %vecinit.i, bfloat %2, i32 1 # | %3 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit2.i = insertelement <8 x bfloat> %vecinit1.i, bfloat %3, i32 2 # | %4 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit3.i = insertelement <8 x bfloat> %vecinit2.i, bfloat %4, i32 3 # | %5 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit4.i = insertelement <8 x bfloat> %vecinit3.i, bfloat %5, i32 4 # | %6 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit5.i = insertelement <8 x bfloat> %vecinit4.i, bfloat %6, i32 5 # | %7 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit6.i = insertelement <8 x bfloat> %vecinit5.i, bfloat %7, i32 6 # | %8 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit7.i = insertelement <8 x bfloat> %vecinit6.i, bfloat %8, i32 7 # | store <8 x bfloat> %vecinit7.i, ptr %.compoundliteral.i, align 16 # | %9 = load <8 x bfloat>, ptr %.compoundliteral.i, align 16 # | store <8 x bfloat> %9, ptr %__ret.i, align 16 # | %10 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %10 # | } # | # | ; Function Attrs: noinline noun # | ... # `---data was truncated (10240/13833) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000558a2954557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558a29542515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558a29545cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb59e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb59e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb59e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb59e71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558a294db24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558a294db096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558a294bff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558a2916f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558a2916ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb59e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb59e71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb59e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558a2916ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c --check-prefixes=ALL,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c --check-prefixes=ALL,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c (595 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svuzp_s8_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.uzp.x2.nxv16i8( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.uzp.x2.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svuzp_u8_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.uzp.x2.nxv16i8( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svuzp_mf8_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.uzp.x2.nxv16i8( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svuzp_s16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.uzp.x2.nxv8i16( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.uzp.x2.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svuzp_u16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.uzp.x2.nxv8i16( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svuzp_f16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.uzp.x2.nxv8f16( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.uzp.x2.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svuzp_bf16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.uzp.x2.nxv8bf16( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.uzp.x2.nxv8bf16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svuzp_s32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.c # | ... # `---data was truncated (10240/35785) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000562c9ee1257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562c9ee0f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562c9ee12cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4a1df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4a1df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4a1df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4a1df1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562c9eda824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562c9eda8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562c9ed8cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562c9ea3c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562c9ea3be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4a1df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4a1df1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4a1df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562c9ea3bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c (596 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svscale_single_bf16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fscale.single.x2.nxv8bf16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fscale.single.x2.nxv8bf16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svscale_single_bf16_x4( %zdn.coerce0, %zdn.coerce1, %zdn.coerce2, %zdn.coerce3, %zm) #0 { # | entry: # | %zdn = alloca { , , , }, align 16 # | %zdn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zdn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zdn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zdn.coerce3, 3 # | store { , , , } %3, ptr %zdn, align 16 # | %zdn1 = load { , , , }, ptr %zdn, align 16 # | store { , , , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %4 = load { , , , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = load , ptr %zm.addr, align 16 # | %10 = call { , , , } @llvm.aarch64.sve.fscale.single.x4.nxv8bf16( %5, %6, %7, %8, %9) # | ret { , , , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.fscale.single.x4.nxv8bf16(, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svscale_bf16_x2( %zdn.coerce0, %zdn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | %10 = call { , } @llvm.aarch64.sve.fscale.x2.nxv8bf16( %5, %6, %8, %9) # | ret { , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fscale.x2.nxv8bf16(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svscale_bf16_x4( %zdn.coerce0, %zdn.coerce1, %zdn.coerce2, %zdn.coerce3, %zm.coerce0, %zm.coerce1, %zm.coerce2, %zm.coerce3) #0 { # | entry: # | %zdn = alloca { , , , }, align 16 # | %zm = alloca { , , , }, align 16 # | %zdn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zdn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zdn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zdn.coerce3, 3 # | store { , , , } %3, ptr %zdn, align 16 # | %zdn1 = load { , , , }, ptr %zdn, align 16 # | %4 = insertvalue { , , , } poison, %zm.coerce0, 0 # | %5 = insertvalue { , , , } %4, %zm.coerce1, 1 # | %6 = insertvalue { , , , } %5, %zm.coerce2, 2 # | %7 = insertvalue { , , , } %6, %zm.coerce3, 3 # | store { , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c (597 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ta # | ... # `---data was truncated (10240/47488) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055af8490e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055af8490b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055af8490ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7293849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f72938a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7293849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7293831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055af848a424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055af848a4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055af84888f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055af84538176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055af84537e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7293832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f72938330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f72938330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055af84537d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c (598 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | # | ... # `---data was truncated (10240/135119) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560a1adb357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560a1adb0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560a1adb3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f09cef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f09cef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f09cef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f09cef1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560a1ad4924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560a1ad49096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560a1ad2df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560a1a9dd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560a1a9dce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f09cef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f09cef1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f09cef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560a1a9dcd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c (599 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_max.c (600 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_max.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.smax.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smax.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.smax.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smax.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.smax.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smax.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.smax.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smax.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.umax.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.umax.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.umax.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.umax.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.umax.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.umax.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c (601 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_x_f_v_i32mf2(< # | ... # `---data was truncated (10240/119297) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fc5334157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fc5333e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fc53341cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdd91049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdd910a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdd91049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdd91031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fc532d724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fc532d7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fc532bbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fc52f6b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fc52f6ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fdd91032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdd910330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdd910330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fc52f6ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c (602 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_s8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv16i8( %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.laneq.nxv16i8(, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_u8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv16i8( %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_s16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv8i16( %0, i32 1) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.laneq.nxv8i16(, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_u16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv8i16( %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_s32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv4i32( %0, i32 2) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.laneq.nxv4i32(, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_u32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv4i32( %0, i32 3) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_s64( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv2i64( %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.laneq.nxv2i64(, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_u64( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv2i64( %0, i32 1) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_f16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv8f16( %0, i32 4) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.laneq.nxv8f16(, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_f32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv4f32( %0, i32 1) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.laneq.nxv4f32(, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_f64( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv2f64( %0, i32 1) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.laneq.nxv2f64(, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_bf16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv8bf16( %0, i32 3) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.laneq.nxv8bf16(, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_mf8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv16i8( %0, i32 1) # | ret %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055a12c71957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a12c716515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a12c719cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1c5c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1c5c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1c5c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1c5c431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a12c6af24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a12c6af096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a12c693f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a12c343176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a12c342e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1c5c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1c5c4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1c5c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a12c342d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c (603 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintn_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frintn.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintn.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintn_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frintn.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintn.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintn_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frintn.nxv2f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintn.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintn_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.frintn.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintn_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.frintn.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintn_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.frintn.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintn_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frintn.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintn_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frintn.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintn_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frintn.nxv2f64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000556fb67de57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556fb67db515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556fb67decbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fad97f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fad97f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fad97f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fad97eed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556fb677424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556fb6774096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556fb6758f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556fb6408176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556fb6407e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fad97eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fad97eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fad97eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556fb6407d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-vls-shift-ops.c (604 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-shift-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @lshift_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <64 x i8>, align 16 # | %a.addr = alloca <64 x i8>, align 16 # | %b.addr = alloca <64 x i8>, align 16 # | %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %a.coerce, i64 0) # | %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %b.coerce, i64 0) # | store <64 x i8> %a, ptr %a.addr, align 16 # | store <64 x i8> %b, ptr %b.addr, align 16 # | %0 = load <64 x i8>, ptr %a.addr, align 16 # | %1 = load <64 x i8>, ptr %b.addr, align 16 # | %shl = shl <64 x i8> %0, %1 # | store <64 x i8> %shl, ptr %retval, align 16 # | %2 = load <64 x i8>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv16i8.v64i8( poison, <64 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16i8.v64i8(, <64 x i8>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @rshift_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <64 x i8>, align 16 # | %a.addr = alloca <64 x i8>, align 16 # | %b.addr = alloca <64 x i8>, align 16 # | %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %a.coerce, i64 0) # | %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %b.coerce, i64 0) # | store <64 x i8> %a, ptr %a.addr, align 16 # | store <64 x i8> %b, ptr %b.addr, align 16 # | %0 = load <64 x i8>, ptr %a.addr, align 16 # | %1 = load <64 x i8>, ptr %b.addr, align 16 # | %shr = ashr <64 x i8> %0, %1 # | store <64 x i8> %shr, ptr %retval, align 16 # | %2 = load <64 x i8>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv16i8.v64i8( poison, <64 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @lshift_u8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <64 x i8>, align 16 # | %a.addr = alloca <64 x i8>, align 16 # | %b.addr = alloca <64 x i8>, align 16 # | %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %a.coerce, i64 0) # | %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %b.coerce, i64 0) # | store <64 x i8> %a, ptr %a.addr, align 16 # | store <64 x i8> %b, ptr %b.addr, align 16 # | %0 = load <64 x i8>, ptr %a.addr, align 16 # | %1 = load <64 x i8>, ptr %b.addr, align 16 # | %shl = shl <64 x i8> %0, %1 # | store <64 x i8> %shl, ptr %retval, align 16 # | %2 = load <64 x i8>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv16i8.v64i8( poison, <64 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @rshift_u8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <64 x i8>, align 16 # | %a.addr = alloca <64 x i8>, align 16 # | %b.addr = alloca <64 x i8>, align 16 # | %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %a.coerce, i64 0) # | %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %b.coerce, i64 0) # | store <64 x i8> %a, ptr %a.addr, align 16 # | store <64 x i8> %b, ptr %b.addr, align 16 # | %0 = load <64 x i8>, ptr %a.addr, align 16 # | %1 = load <64 x i8>, ptr %b.addr, align 16 # | %shr = lshr <64 x i8> %0, %1 # | store <64 x i8> %shr, ptr %retval, align 16 # | %2 = load <64 x i8>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv16i8.v64i8( poison, <64 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @lshift_i16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i16>, align 16 # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca <32 x i16>, align 16 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %b.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store <32 x i16> %b, ptr %b.addr, align 16 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load <32 x i16>, ptr %b.addr, align 16 # | %shl = shl <32 x i16> %0, %1 # | store <32 x i16> %shl, ptr %retval, align 16 # | %2 = load <32 x i16>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv8i16.v32i16( poison, <32 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8i16.v32i16(, <32 x i16>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @rshift_i16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i16>, align 16 # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca <32 x i16>, align 16 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %b.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store <32 x i16> %b, ptr %b.addr, align 16 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load <32 x i16>, ptr %b.addr, align 16 # | %shr = ashr <32 x i16> %0, %1 # | store <32 x i16> %shr, ptr %retval, align 16 # | %2 = load <32 x i16>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv8i16.v32i16( poison, <32 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @lshift_u16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i16>, align 16 # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca <32 x i16>, align 16 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %b.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store <32 x i16> %b, ptr %b.addr, align 16 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load <32 x i16>, ptr %b.addr, align 16 # | %shl = shl <32 x i16> %0, %1 # | store <32 x i16> %shl, ptr %retval, align 16 # | %2 = load <32 x i16>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv8i16.v32i16( poison, <32 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @rshift_u16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i16>, align 16 # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca <32 x i16>, align 16 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %b.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store <32 x i16> %b, ptr %b.addr, align 16 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load <32 x i16>, ptr %b.addr, align 16 # | %shr = lshr <32 x i16> %0, %1 # | store <32 x i16> %shr, ptr %retval, align 16 # | %2 = load <32 x i16>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv8i16.v32i16( poison, <32 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @lshift_i32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i32>, align 16 # | %a.addr = alloca <16 x i32>, align 16 # | %b.addr = alloca <16 x i32>, align 16 # | %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %a.coerce, i64 0) # | %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %b.coerce, i64 0) # | store <16 x i32> %a, ptr %a.addr, align 16 # | store <16 x i32> %b, ptr %b.addr, align 16 # | %0 = load <16 x i32>, ptr %a.addr, align 16 # | %1 = load <16 x i32>, ptr %b.addr, align 16 # | %shl = shl <16 x i32> %0, %1 # | store <16 x i32> %shl, ptr %retval, align 16 # | %2 = load <16 x i32>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv4i32.v16i32( poison, <16 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4i32.v16i32(, <16 x i32>, i64 imma # | ... # `---data was truncated (10240/51475) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x000055d4475b357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d4475b0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d4475b3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efee1449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efee14a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efee1449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efee1431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d44754924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d447549096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d44752df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d4471dd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d4471dce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efee1432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efee14330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efee14330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d4471dcd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c (605 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_s8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ld1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv16i8.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv8i16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv4i32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv2i64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_u8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ld1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_f16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv8f16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv8f16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_f32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4f32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv4f32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_f64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2f64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv2f64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_mf8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ld1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_vnum_s8( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = # | ... # `---data was truncated (10240/63749) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x000055756f50457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055756f501515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055756f504cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0079f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0079f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0079f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0079f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055756f49a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055756f49a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055756f47ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055756f12e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055756f12de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0079f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0079f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0079f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055756f12dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c (606 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svlasta_s8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.lasta.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i8 @llvm.aarch64.sve.lasta.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svlasta_s16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.lasta.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.aarch64.sve.lasta.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svlasta_s32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.lasta.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.lasta.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlasta_s64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.lasta.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.lasta.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svlasta_u8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.lasta.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svlasta_u16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.lasta.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svlasta_u32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.lasta.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlasta_u64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.lasta.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local half @test_svlasta_f16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call half @llvm.aarch64.sve.lasta.nxv8f16( %2, %1) # | ret half %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare half @llvm.aarch64.sve.lasta.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local float @test_svlasta_f32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call float @llvm.aarch64.sve.lasta.nxv4f32( %2, %1) # | ret float %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare float @llvm.aarch64.sve.lasta.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local double @test_svlasta_f64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call double @llvm.aarch64.sve.lasta.nxv2f64( %2, %1) # | ret double %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare double @llvm.aarch64.sve.lasta.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local bfloat @test_svlasta_bf16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call bfloat @llvm.aarch64.sve.lasta.nxv8bf16( %2, %1) # | ret bfloat %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willretur # | ... # `---data was truncated (10240/10821) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005647545e657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005647545e3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005647545e6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7219333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f721938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7219333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f721931b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056475457c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056475457c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564754560f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564754210176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056475420fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f721931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f721931d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f721931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056475420fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve/nand.c (607 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve/nand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnand_b_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.nand.z.nxv16i1( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.nand.z.nxv16i1(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x00005625f6f4e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005625f6f4b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005625f6f4ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f64f3305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f64f335c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f64f3305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f64f32ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005625f6ee424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005625f6ee4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005625f6ec8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005625f6b78176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005625f6b77e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f64f32eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f64f32ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f64f32ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005625f6b77d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c (608 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesbfhcvt -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesbfhcvt -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_fcvt_s_bf16(bfloat noundef %bf) #0 { # | entry: # | %bf.addr.i = alloca bfloat, align 2 # | %bf.addr = alloca bfloat, align 2 # | store bfloat %bf, ptr %bf.addr, align 2 # | %0 = load bfloat, ptr %bf.addr, align 2 # | store bfloat %0, ptr %bf.addr.i, align 2 # | %1 = load bfloat, ptr %bf.addr.i, align 2 # | %2 = fpext bfloat %1 to float # | ret float %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local bfloat @test_fcvt_bf16_s(float noundef %sf) #0 { # | entry: # | %sf.addr.i = alloca float, align 4 # | %sf.addr = alloca float, align 4 # | store float %sf, ptr %sf.addr, align 4 # | %0 = load float, ptr %sf.addr, align 4 # | store float %0, ptr %sf.addr.i, align 4 # | %1 = load float, ptr %sf.addr.i, align 4 # | %2 = fptrunc float %1 to bfloat # | ret bfloat %2 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+f,+i,+xandesbfhcvt,+zicsr" } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_f2p2_zicsr2p0_xandesbfhcvt5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b84ae5557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b84ae52515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b84ae55cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff9b7f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff9b7f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff9b7f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff9b7f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b84adeb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b84adeb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b84adcff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b84aa7f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b84aa7ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff9b7f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff9b7f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff9b7f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b84aa7ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c (609 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvfwmaccqqq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvfwmaccqqq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005621cd77157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005621cd76e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005621cd771cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4033d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4033d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4033d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4033d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005621cd70724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005621cd707096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005621cd6ebf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005621cd39b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005621cd39ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4033d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4033d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4033d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005621cd39ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c (610 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_i64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_u64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_f64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_i64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_u64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_f64m1x7_tumu( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target(" # | ... # `---data was truncated (10240/18506) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cffbafa57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cffbaf7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cffbafacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbb9f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbb9f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbb9f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbb9f631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cffba9024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cffba90096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cffba74f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cffb724176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cffb723e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbb9f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbb9f6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbb9f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cffb723d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c (611 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_i8m1_i8m2( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv16i8.nxv8i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16i8.nxv8i8(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_i8m1_i8m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv32i8.nxv8i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32i8.nxv8i8(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_i8m2_i8m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv32i8.nxv16i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32i8.nxv16i8(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_i8m1_i8m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv64i8.nxv8i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv64i8.nxv8i8(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_i8m2_i8m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv64i8.nxv16i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv64i8.nxv16i8(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_i8m4_i8m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv64i8.nxv32i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv64i8.nxv32i8(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_u8m1_u8m2( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv16i8.nxv8i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_u8m1_u8m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv32i8.nxv8i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_u8m2_u8m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv32i8.nxv16i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_u8m1_u8m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv64i8.nxv8i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_u8m2_u8m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv64i8.nxv16i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_u8m4_u8m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, p # | ... # `---data was truncated (10240/54546) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055897a1af57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055897a1ac515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055897a1afcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa1f4d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa1f4d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa1f4d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa1f4d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055897a14524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055897a145096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055897a129f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558979dd9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558979dd8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa1f4d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa1f4d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa1f4d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558979dd8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_add.c (612 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_add.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.add.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.add.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.add.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.add.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.add.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.add.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.add.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.add.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.add.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.add.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.add.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.add.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_s8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, pt # | ... # `---data was truncated (10240/72449) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005577f599a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005577f5997515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005577f599acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9184105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f918415c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9184105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f91840ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005577f593024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005577f5930096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005577f5914f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005577f55c4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005577f55c3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f91840eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f91840ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f91840ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005577f55c3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c (613 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf8_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr % # | ... # `---data was truncated (10240/414517) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562ca3fee57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562ca3feb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562ca3feecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0185249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f01852a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0185249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0185231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562ca3f8424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562ca3f84096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562ca3f68f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562ca3c18176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562ca3c17e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0185232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f01852330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f01852330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562ca3c17d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c (614 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005591144ce57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005591144cb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005591144cecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f05e5533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f05e558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f05e5533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f05e551b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055911446424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559114464096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559114448f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005591140f8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005591140f7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f05e551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f05e551d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f05e551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005591140f7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c (615 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_i8mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/69980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005564f2d7e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005564f2d7b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005564f2d7ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2964a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2964aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2964a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2964a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005564f2d1424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005564f2d14096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005564f2cf8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005564f29a8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005564f29a7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2964a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2964a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2964a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005564f29a7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c (616 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svlastb_s8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.lastb.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i8 @llvm.aarch64.sve.lastb.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svlastb_s16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.lastb.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.aarch64.sve.lastb.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svlastb_s32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.lastb.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.lastb.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlastb_s64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.lastb.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.lastb.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svlastb_u8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.lastb.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svlastb_u16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.lastb.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svlastb_u32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.lastb.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlastb_u64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.lastb.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local half @test_svlastb_f16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call half @llvm.aarch64.sve.lastb.nxv8f16( %2, %1) # | ret half %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare half @llvm.aarch64.sve.lastb.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local float @test_svlastb_f32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call float @llvm.aarch64.sve.lastb.nxv4f32( %2, %1) # | ret float %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare float @llvm.aarch64.sve.lastb.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local double @test_svlastb_f64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call double @llvm.aarch64.sve.lastb.nxv2f64( %2, %1) # | ret double %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare double @llvm.aarch64.sve.lastb.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local bfloat @test_svlastb_bf16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call bfloat @llvm.aarch64.sve.lastb.nxv8bf16( %2, %1) # | ret bfloat %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willretur # | ... # `---data was truncated (10240/10821) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055fd6771457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fd67711515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fd67714cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc7e6c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc7e6c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc7e6c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc7e6c03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fd676aa24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fd676aa096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fd6768ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fd6733e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fd6733de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc7e6c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc7e6c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc7e6c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fd6733dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c (617 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2p2 -target-feature +f16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2p2 -target-feature +f16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_f16( %acc, %a, %b) #0 { # | entry: # | %acc.addr = alloca , align 16 # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %acc, ptr %acc.addr, align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %acc.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %2 = load , ptr %b.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmmla.nxv8f16.nxv8f16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmmla.nxv8f16.nxv8f16(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f16mm,+sve,+sve2p2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056174e9fa57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056174e9f7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056174e9facbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fac6c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fac6c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fac6c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fac6c11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056174e99024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056174e990096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056174e974f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056174e624176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056174e623e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fac6c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fac6c11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fac6c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056174e623d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c (618 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.a # | ... # `---data was truncated (10240/174713) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005616d9b2157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005616d9b1e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005616d9b21cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4ca1249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4ca12a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4ca1249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4ca1231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005616d9ab724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005616d9ab7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005616d9a9bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005616d974b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005616d974ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4ca1232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4ca12330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4ca12330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005616d974ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c (619 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecw_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdecw.n32(i32 %0, i32 31, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqdecw.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecw_n_s32_1(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdecw.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecw_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqdecw.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqdecw.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecw_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqdecw.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqdecw.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecw_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqdecw.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uqdecw.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecw_pat_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdecw.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecw_pat_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqdecw.n64(i64 %0, i32 0, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecw_pat_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqdecw.n32(i32 %0, i32 1, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecw_pat_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqdecw.n64(i64 %0, i32 2, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdecw_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqdecw.nxv4i32( %0, i32 31, i32 16) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqdecw.nxv4i32(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdecw_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqdecw.nxv4i32( %0, i32 31, i32 1) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqdecw.nxv4i32(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdecw_pat_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqdecw.nxv4i32( %0, i32 3, i32 16) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdecw_pat_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqdecw.nxv4i32( %0, i32 4, i32 1) # | ret %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055c5b938457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c5b9381515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c5b9384cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcb47849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcb478a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcb47849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcb47831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c5b931a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c5b931a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c5b92fef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c5b8fae176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c5b8fade93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcb47832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcb478330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcb478330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c5b8fadd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c (620 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f64m1x3(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c (621 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | # | ... # `---data was truncated (10240/116259) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560a73cdc57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560a73cd9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560a73cdccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4f3a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4f3a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4f3a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4f3a91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560a73c7224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560a73c72096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560a73c56f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560a73906176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560a73905e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4f3a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4f3a91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4f3a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560a73905d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c (622 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16mf4x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16mf2x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16mf4x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16mf2x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_u16mf4x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("ri # | ... # `---data was truncated (10240/13634) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005631a90ed57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005631a90ea515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005631a90edcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8374505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f837455c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8374505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f83744ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005631a908324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005631a9083096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005631a9067f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005631a8d17176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005631a8d16e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f83744eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f83744ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f83744ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005631a8d16d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c (623 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m2_f16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv8f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv8f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m4_f16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m8_f16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m4_f16m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m8_f16m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m8_f16m4( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv16f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv16f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m2_f32m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv2f32.nxv4f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f32.nxv4f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m4_f32m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv2f32.nxv8f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f32.nxv8f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m8_f32m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv2f32.nxv16f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f32.nxv16f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m4_f32m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv4f32.nxv8f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f32.nxv8f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m8_f32m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv4f32.nxv16f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f32.nxv16f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m8_f32m4( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv8f32.nxv16f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8f32.nxv16f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f64m2_f64m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 8 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = call @llvm.vector.extract.nxv1f64.nxv2f64( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f64.nxv2f64(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounw # | ... # `---data was truncated (10240/246606) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a0bb1c257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a0bb1bf515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a0bb1c2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f86fd049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f86fd0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f86fd049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f86fd031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a0bb15824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a0bb158096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a0bb13cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a0badec176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a0badebe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f86fd032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f86fd0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f86fd0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a0badebd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c (624 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32mf2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m1_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m4_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m8_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32mf2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m1_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) # | ... # `---data was truncated (10240/25094) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a73774a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a737747515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a73774acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fac6361bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fac636725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fac6361ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fac63603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a7376e024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a7376e0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a7376c4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a737374176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a737373e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fac63604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fac636050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fac636050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a737373d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c (625 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32mf2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m1_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m4_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64( # | ... # `---data was truncated (10240/179185) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005647d388557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005647d3882515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005647d3885cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f75da41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f75da4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f75da41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f75da403507 abort ./stdlib/abort.c:85:3 # | #7 0x00005647d381b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005647d381b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005647d37fff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005647d34af176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005647d34aee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f75da404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f75da4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f75da4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005647d34aed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c (626 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c (627 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svld4_s8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call { , , , } @llvm.aarch64.sve.ld4.sret.nxv16i8.p0( %0, ptr %1) # | ret { , , , } %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , , } @llvm.aarch64.sve.ld4.sret.nxv16i8.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svld4_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , , , } @llvm.aarch64.sve.ld4.sret.nxv8i16.p0( %2, ptr %1) # | ret { , , , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , , } @llvm.aarch64.sve.ld4.sret.nxv8i16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svld4_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , , , } @llvm.aarch64.sve.ld4.sret.nxv4i32.p0( %2, ptr %1) # | ret { , , , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , , } @llvm.aarch64.sve.ld4.sret.nxv4i32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svld4_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call { , , , } @llvm.aarch64.sve.ld4.sret.nxv2i64.p0( %2, ptr %1) # | ret { , , , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , , } @llvm.aarch64.sve.ld4.sret.nxv2i64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svld4_u8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call { , , , } @llvm.aarch64.sve.ld4.sret.nxv16i8.p0( %0, ptr %1) # | ret { , , , } %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svld4_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , , , } @llvm.aarch64.sve.ld4.sret.nxv8i16.p0( %2, ptr %1) # | ret { , , , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svld4_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , , , } @llvm.aarch64.sve.ld4.sret.nxv4i32.p0( %2, ptr %1) # | ret { , , , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svld4_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call { , , , } @llvm.aarch64.sve.ld4.sret.nxv2i64.p0( %2, ptr %1) # | ret { , , , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svld4_f16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , , , } @llvm.aarch64.sve.ld4.sret.nxv8f16.p0( %2, ptr %1) # | ret { , , , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , , } @llvm.aarch64.sve.ld4.sret.nxv8f16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svld4_f32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.fr # | ... # `---data was truncated (10240/27970) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055c7f091057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c7f090d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c7f0910cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007effbb733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007effbb78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007effbb733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007effbb71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c7f08a624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c7f08a6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c7f088af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c7f053a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c7f0539e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007effbb71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007effbb71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007effbb71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c7f0539d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c (628 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmad_s8_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = select %0, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mad.nxv16i8( %0, %4, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mad.nxv16i8(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmad_s16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mad.nxv8i16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mad.nxv8i16(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmad_s32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mad.nxv4i32( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mad.nxv4i32(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmad_s64_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mad.nxv2i64( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mad.nxv2i64(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmad_u8_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = select %0, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mad.nxv16i8( %0, %4, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmad_u16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mad.nxv8i16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmad_u32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mad.nxv4i32( %4, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c (629 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c (630 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svwrffr( %op) #0 { # | entry: # | %op.addr = alloca , align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %op.addr, align 2 # | call void @llvm.aarch64.sve.wrffr( %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.sve.wrffr() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000556c4e8bd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556c4e8ba515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556c4e8bdcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f67f3e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f67f3ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f67f3e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f67f3e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556c4e85324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556c4e853096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556c4e837f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556c4e4e7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556c4e4e6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f67f3e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f67f3e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f67f3e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556c4e4e6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve/dup.c (631 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve/dup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_s8(i8 noundef %op) #0 { # | entry: # | %op.addr = alloca i8, align 1 # | store i8 %op, ptr %op.addr, align 1 # | %0 = load i8, ptr %op.addr, align 1 # | %1 = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.x.nxv16i8(i8) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_s16(i16 noundef %op) #0 { # | entry: # | %op.addr = alloca i16, align 2 # | store i16 %op, ptr %op.addr, align 2 # | %0 = load i16, ptr %op.addr, align 2 # | %1 = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.x.nxv8i16(i16) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.x.nxv4i32(i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.x.nxv2i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_u8(i8 noundef %op) #0 { # | entry: # | %op.addr = alloca i8, align 1 # | store i8 %op, ptr %op.addr, align 1 # | %0 = load i8, ptr %op.addr, align 1 # | %1 = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_u16(i16 noundef %op) #0 { # | entry: # | %op.addr = alloca i16, align 2 # | store i16 %op, ptr %op.addr, align 2 # | %0 = load i16, ptr %op.addr, align 2 # | %1 = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_f16(half noundef %op) #0 { # | entry: # | %op.addr = alloca half, align 2 # | store half %op, ptr %op.addr, align 2 # | %0 = load half, ptr %op.addr, align 2 # | %1 = call @llvm.aarch64.sve.dup.x.nxv8f16(half %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.x.nxv8f16(half) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_f32(float noundef %op) #0 { # | entry: # | %op.addr = alloca float, align 4 # | store float %op, ptr %op.addr, align 4 # | %0 = load float, ptr %op.addr, align 4 # | %1 = call @llvm.aarch64.sve.dup.x.nxv4f32(float %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.x.nxv4f32(float) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_f64(double noundef %op) #0 { # | entry: # | %op.addr = alloca double, align 8 # | store double %op, ptr %op.addr, align 8 # | %0 = load double, ptr %op.addr, align 8 # | %1 = call @llvm.aarch64.sve.dup.x.nxv2f64(double %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.x.nxv2f64(double) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_b8(i1 noundef %op) #0 { # | entry: # | %op.addr = alloca i8, align 1 # | %storedv = zext i1 %op to i8 # | store i8 %storedv, ptr %op.addr, align 1 # | %0 = load i8, ptr %op.addr, align 1 # | %loadedv = icmp ne i8 %0, 0 # | %.splatinsert = insertelement poison, i1 %loadedv, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | ret %.splat # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_b16(i1 noundef %op) #0 { # | entry: # | %op.addr = alloca i8, align 1 # | %storedv = zext i1 %op to i8 # | store i8 %storedv, ptr %op.addr, align 1 # | %0 = load i8, ptr %op.addr, align 1 # | %loadedv = icmp ne i8 %0, 0 # | %.splatinsert = insertelement poison, i1 %loadedv, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %1 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %.splat) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_b32(i1 noundef %op) #0 { # | entry: # | %op.addr = alloca i8, align 1 # | %storedv = zext i1 %op to i8 # | store i8 %storedv, ptr %op.addr, align 1 # | %0 = load i8, ptr %op.addr, align 1 # | %loadedv = icmp ne i8 %0, 0 # | %.splatinsert = insertelement poison, i1 %loadedv, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %1 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %.splat) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_b64(i1 noundef %op) #0 { # | entry: # | %op.addr = alloca i8, align 1 # | %storedv = zext i1 %op to i8 # | store i8 %storedv, ptr %op.addr, align 1 # | %0 = load i8, ptr %op.addr, align 1 # | %loadedv = icmp ne i8 %0, 0 # | %.splatinsert = insertelement poison, i1 %loadedv, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %1 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %.splat) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_bf16(bfloat noundef %op) #0 { # | entry: # | %op.addr = alloca bfloat, align 2 # | store bfloat %op, ptr %op.addr, align 2 # | %0 = load bfloat, ptr %op.addr, align 2 # | %1 = call @llvm.aarch64.sve.dup.x.nxv8bf16(bfloat %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.x.nxv8bf16(bfloat) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_s8_z( %pg, i8 noundef %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca i8, align 1 # | store %pg, ptr %pg.addr, align 2 # | store i8 %op, ptr %op.addr, align 1 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load i8, ptr %op.addr, align 1 # | %2 = call @llvm.aarch64.sve.dup.nxv16i8( zeroinitializer, %0, i8 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.nxv16i8(, , i8) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_s16_z( %pg, i16 noundef %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca i16, align 2 # | store %pg, ptr %pg.addr, align 2 # | store i16 %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load i16, ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c (632 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32mf2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m1_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m4_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsa # | ... # `---data was truncated (10240/179511) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fe60b8d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fe60b8a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fe60b8dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6eff933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6eff98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6eff933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6eff91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fe60b2324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fe60b23096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fe60b07f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fe607b7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fe607b6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6eff91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6eff91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6eff91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fe607b6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c (633 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svzip_s8_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call { , , , } @llvm.aarch64.sve.zip.x4.nxv16i8( %5, %6, %7, %8) # | ret { , , , } %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.zip.x4.nxv16i8(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svzip_u8_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call { , , , } @llvm.aarch64.sve.zip.x4.nxv16i8( %5, %6, %7, %8) # | ret { , , , } %9 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svzip_mf8_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call { , , , } @llvm.aarch64.sve.zip.x4.nxv16i8( %5, %6, %7, %8) # | ret { , , , } %9 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svzip_s16_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call { , , , } @llvm.aarch64.sve.zip.x4.nxv8i16( %5, %6, %7, %8) # | ret { , , , } %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.zip.x4.nxv8i16(, , , ) #1 # | ... # `---data was truncated (10240/67329) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055cd44a6557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cd44a62515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cd44a65cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa75881bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa7588725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa75881ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa758803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cd449fb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cd449fb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cd449dff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cd4468f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cd4468ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa758804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa7588050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa7588050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cd4468ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c (634 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f32m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f64m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f64.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; F # | ... # `---data was truncated (10240/102296) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560561b7057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560561b6d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560561b70cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa745b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa745b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa745b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa745b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560561b0624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560561b06096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560561aeaf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056056179a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560561799e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa745b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa745b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa745b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560561799d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c (635 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svsel_s8_x2(target("aarch64.svcount") %pn, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %pn.addr = alloca target("aarch64.svcount"), align 2 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store target("aarch64.svcount") %pn, ptr %pn.addr, align 2 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load target("aarch64.svcount"), ptr %pn.addr, align 2 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | %11 = call { , } @llvm.aarch64.sve.sel.x2.nxv16i8(target("aarch64.svcount") %4, %6, %7, %9, %10) # | ret { , } %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sel.x2.nxv16i8(target("aarch64.svcount"), , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svsel_u8_x2(target("aarch64.svcount") %pn, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %pn.addr = alloca target("aarch64.svcount"), align 2 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store target("aarch64.svcount") %pn, ptr %pn.addr, align 2 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load target("aarch64.svcount"), ptr %pn.addr, align 2 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | %11 = call { , } @llvm.aarch64.sve.sel.x2.nxv16i8(target("aarch64.svcount") %4, %6, %7, %9, %10) # | ret { , } %11 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svsel_mf8_x2(target("aarch64.svcount") %pn, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %pn.addr = alloca target("aarch64.svcount"), align 2 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store target("aarch64.svcount") %pn, ptr %pn.addr, align 2 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load target("aarch64.svcount"), ptr %pn.addr, align 2 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | %11 = call { , } @llvm.aarch64.sve.sel.x2.nxv16i8(target("aarch64.svcount") %4, %6, %7, %9, %10) # | ret { , } %11 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svsel_s16_x2(target("aarch64.svcount") %pn, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %pn.addr = alloca target("aarch64.svcount"), align 2 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store target("aarch64.svcount") %pn, ptr %pn.addr, align 2 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load target("aarch64.svcount"), ptr %pn.addr, align 2 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | %11 = call { , } @llvm.aarch64.sve.sel.x2.nxv8i16(target("aarch64.svcount") %4, %6, %7, %9, %10) # | ret { , } %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sel.x2.nxv8i16(target("aarch64.svcount"), , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c (636 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv1i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv1i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv2i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv2i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv4i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv4i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv8i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv8i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv16i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv16i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function # | ... # `---data was truncated (10240/100281) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558894aca57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558894ac7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558894acacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc6e2049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc6e20a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc6e2049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc6e2031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558894a6024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558894a60096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558894a44f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005588946f4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005588946f3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc6e2032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc6e20330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc6e20330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005588946f3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c (637 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16m2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = allo # | ... # `---data was truncated (10240/153905) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563c3138157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563c3137e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563c31381cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff828533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff82858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff828533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff82851b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563c3131724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563c31317096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563c312fbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563c30fab176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563c30faae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff82851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff82851d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff82851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563c30faad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c (638 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32mf2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m1x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32mf2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m1x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_u32mf2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_u32m1x2_m( %mask, # | ... # `---data was truncated (10240/13544) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056398c72357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056398c720515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056398c723cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1425e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1425ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1425e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1425e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056398c6b924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056398c6b9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056398c69df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056398c34d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056398c34ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1425e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1425e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1425e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056398c34cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c (639 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv32bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv32bf16.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559fb7c5457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559fb7c51515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559fb7c54cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9149533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f914958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9149533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f914951b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559fb7bea24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559fb7bea096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559fb7bcef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559fb787e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559fb787de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f914951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f914951d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f914951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559fb787dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c (640 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofre # | ... # `---data was truncated (10240/183431) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562e22c2557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562e22c22515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562e22c25cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd49b41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd49b4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd49b41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd49b403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562e22bbb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562e22bbb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562e22b9ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562e2284f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562e2284ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd49b404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd49b4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd49b4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562e2284ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c (641 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/97647) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a8fc16457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a8fc161515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a8fc164cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3ccc649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3ccc6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3ccc649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3ccc631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a8fc0fa24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a8fc0fa096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a8fc0def49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a8fbd8e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a8fbd8de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3ccc632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3ccc6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3ccc6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a8fbd8dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c (642 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_f32mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_f32m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_i32mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_i32m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_u32mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_u32m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_f32mf2x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_f32m1x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_i32mf2x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_i32m1x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry # | ... # `---data was truncated (10240/14002) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564572dce57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564572dcb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564572dcecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa0b4705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa0b475c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa0b4705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa0b46ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564572d6424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564572d64096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564572d48f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005645729f8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005645729f7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa0b46eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa0b46ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa0b46ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005645729f7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve/nor.c (643 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve/nor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnor_b_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.nor.z.nxv16i1( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.nor.z.nxv16i1(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x0000557f0d15f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557f0d15c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557f0d15fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fecbeb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fecbeb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fecbeb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fecbeb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557f0d0f524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557f0d0f5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557f0d0d9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557f0cd89176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557f0cd88e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fecbeb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fecbeb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fecbeb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557f0cd88d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c (644 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv4i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv2i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv4i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv2i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv4i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv2i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_gather_u32base_s32( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32( %2, %1, i64 0) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32(, , i64) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_gather_u64base_s64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64( %2, %1, i64 0) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64(, , i64) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_gather_u32base_u32( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.a # | ... # `---data was truncated (10240/36974) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x000055bfb9cd257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bfb9ccf515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bfb9cd2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcbe2133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcbe218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcbe2133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcbe211b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bfb9c6824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bfb9c68096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bfb9c4cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bfb98fc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bfb98fbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcbe211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcbe211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcbe211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bfb98fbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c (645 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8mf8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8mf4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv32i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv64i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8mf8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8mf4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv32i8.p0.i64( %1, ptr %0, i64 %2) # | ret # | ... # `---data was truncated (10240/25287) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560fb6ff457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560fb6ff1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560fb6ff4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb9f7849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb9f78a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb9f7849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb9f7831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560fb6f8a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560fb6f8a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560fb6f6ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560fb6c1e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560fb6c1de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb9f7832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb9f78330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb9f78330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560fb6c1dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c (646 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005647906d457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005647906d1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005647906d4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7bf9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7bf9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7bf9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7bf9b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056479066a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056479066a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056479064ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005647902fe176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005647902fde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7bf9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7bf9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7bf9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005647902fdd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c (647 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u16_m( %zn, %pn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %pn.addr = alloca , align 2 # | store %zn, ptr %zn.addr, align 16 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %pn.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %3 = call @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv8i16( %0, %2, i32 1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv8i16(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_s16_m( %zn, %pn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %pn.addr = alloca , align 2 # | store %zn, ptr %zn.addr, align 16 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %pn.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %3 = call @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv8i16( %0, %2, i32 1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u32_m( %zn, %pn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %pn.addr = alloca , align 2 # | store %zn, ptr %zn.addr, align 16 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %pn.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %3 = call @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv4i32( %0, %2, i32 1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv4i32(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_s32_m( %zn, %pn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %pn.addr = alloca , align 2 # | store %zn, ptr %zn.addr, align 16 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %pn.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %3 = call @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv4i32( %0, %2, i32 3) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u64_m( %zn, %pn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %pn.addr = alloca , align 2 # | store %zn, ptr %zn.addr, align 16 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %pn.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %3 = call @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv2i64( %0, %2, i32 1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv2i64(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_s64_m( %zn, %pn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %pn.addr = alloca , align 2 # | store %zn, ptr %zn.addr, align 16 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %pn.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %3 = call @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv2i64( %0, %2, i32 7) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u8_z( %pn) #0 { # | entry: # | %pn.addr = alloca , align 2 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %pn.addr, align 2 # | %1 = call @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv16i8( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv16i8() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_s8_z( %pn) #0 { # | entry: # | %pn.addr = alloca , align 2 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %pn.addr, align 2 # | %1 = call @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv16i8( %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u16_z( %pn) #0 { # | entry: # | %pn.addr = alloca , align 2 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %pn.addr, align 2 # | %1 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %2 = call @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv8i16( %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv8i16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_s16_z( %pn) #0 { # | entry: # | %pn.addr = alloca , align 2 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %pn.addr, align 2 # | %1 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %2 = call @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv8i16( %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u32_z( %pn) #0 { # | entry: # | %pn.addr = alloca , align 2 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %pn.addr, align 2 # | %1 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %2 = call @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv4i32( %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv4i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_s32_z( %pn) #0 { # | entry: # | %pn.addr = alloca , align 2 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %pn.addr, align 2 # | %1 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %2 = call @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv4i32( %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u64_z( %pn) #0 { # | entry: # | %pn.addr = alloca , align 2 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %pn.addr, align 2 # | %1 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | ... # `---data was truncated (10240/11780) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000557b6566857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557b65665515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557b65668cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8f36705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8f3675c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8f36705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8f366ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557b655fe24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557b655fe096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557b655e2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557b65292176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557b65291e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8f366eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8f366ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8f366ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557b65291d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c (648 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b7c13b657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b7c13b3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b7c13b6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0584f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0584f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0584f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0584eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b7c134c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b7c134c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b7c1330f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b7c0fe0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b7c0fdfe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0584eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0584eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0584eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b7c0fdfd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c (649 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv16i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv32i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv64i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | # | ... # `---data was truncated (10240/54488) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564d2454957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564d24546515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564d24549cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3cb621bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3cb62725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3cb621ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3cb6203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564d244df24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564d244df096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564d244c3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564d24173176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564d24172e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3cb6204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3cb62050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3cb62050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564d24172d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c (650 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564a1477e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564a1477b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564a1477ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fac4da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fac4daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fac4da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fac4da31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564a1471424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564a14714096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564a146f8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564a143a8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564a143a7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fac4da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fac4da330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fac4da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564a143a7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c (651 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svadd_write_single2_s32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv4i32(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv4i32(i32, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svadd_write_single2_u32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv4i32(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svadd_write_single2_s64(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv2i64(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv2i64(i32, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svadd_write_single2_u64(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv2i64(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svadd_write_single4_s32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , , , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , , , } %5, 0 # | %7 = extractvalue { , , , } %5, 1 # | %8 = extractvalue { , , , } %5, 2 # | %9 = extractvalue { , , , } %5, 3 # | %10 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.add.write.single.za.vg1x4.nxv4i32(i32 %4, %6, %7, %8, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.add.write.single.za.vg1x4.nxv4i32(i32, , , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svadd_write_single4_u32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c (652 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_i64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_u64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_f64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_i64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_u64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_f64m1x5_tumu( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 0, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_i64m1x5_tumu( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c (653 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecb_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdecb.n32(i32 %0, i32 31, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqdecb.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecb_n_s32_1(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdecb.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecb_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqdecb.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqdecb.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecb_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqdecb.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqdecb.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecb_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqdecb.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uqdecb.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecb_pat_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdecb.n32(i32 %0, i32 0, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecb_pat_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqdecb.n64(i64 %0, i32 1, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecb_pat_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqdecb.n32(i32 %0, i32 2, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecb_pat_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqdecb.n64(i64 %0, i32 3, i32 1) # | ret i64 %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000559a18b7a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559a18b77515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559a18b7acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f123c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f123c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f123c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f123c231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559a18b1024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559a18b10096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559a18af4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559a187a4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559a187a3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f123c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f123c2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f123c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559a187a3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve/minnmv.c (654 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve/minnmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local half @test_svminnmv_f16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call half @llvm.aarch64.sve.fminnmv.nxv8f16( %2, %1) # | ret half %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.aarch64.sve.fminnmv.nxv8f16(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local float @test_svminnmv_f32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call float @llvm.aarch64.sve.fminnmv.nxv4f32( %2, %1) # | ret float %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.aarch64.sve.fminnmv.nxv4f32(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local double @test_svminnmv_f64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call double @llvm.aarch64.sve.fminnmv.nxv2f64( %2, %1) # | ret double %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.aarch64.sve.fminnmv.nxv2f64(, ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x000055ada616457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ada6161515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ada6164cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcc65533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcc6558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcc65533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcc6551b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ada60fa24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ada60fa096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ada60def49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ada5d8e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ada5d8de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcc6551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcc6551d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcc6551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ada5d8dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c (655 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564035b5b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564035b58515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564035b5bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7d67333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7d6738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7d67333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7d6731b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564035af124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564035af1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564035ad5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564035785176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564035784e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7d6731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7d6731d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7d6731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564035784d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c (656 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr # | ... # `---data was truncated (10240/20623) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fe943dd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fe943da515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fe943ddcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f132b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f132b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f132b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f132b71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fe9437324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fe94373096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fe94357f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fe94007176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fe94006e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f132b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f132b71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f132b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fe94006d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c (657 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf8x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_u8mf8x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, al # | ... # `---data was truncated (10240/72135) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055aa8e4e757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055aa8e4e4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055aa8e4e7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f26e2f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f26e2f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f26e2f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f26e2eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aa8e47d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055aa8e47d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055aa8e461f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055aa8e111176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055aa8e110e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f26e2eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f26e2eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f26e2eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aa8e110d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c (658 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c (659 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3e # | ... # `---data was truncated (10240/228857) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ef5752957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ef57526515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ef57529cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4daa449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4daa4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4daa449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4daa431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ef574bf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ef574bf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ef574a3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ef57153176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ef57152e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4daa432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4daa4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4daa4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ef57152d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c (660 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c (661 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=maytrap -DEXCEPT=1 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not=fpexcept.maytrap --implicit-check-not=' @llvm.fma.' # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=maytrap -DEXCEPT=1 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <4 x half> @test_vfma_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %6 = bitcast <8 x i8> %3 to <4 x half> # | %7 = bitcast <8 x i8> %4 to <4 x half> # | %8 = bitcast <8 x i8> %5 to <4 x half> # | %9 = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> %7, <4 x half> %8, <4 x half> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store <4 x half> %9, ptr %ref.tmp.i, align 8 # | %10 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %10, ptr %__ret.i, align 8 # | %11 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %11 # | } # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <8 x half> @test_vfmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store <8 x half> %c, ptr %c.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | %2 = load <8 x half>, ptr %c.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %6 = bitcast <16 x i8> %3 to <8 x half> # | %7 = bitcast <16 x i8> %4 to <8 x half> # | %8 = bitcast <16 x i8> %5 to <8 x half> # | %9 = call <8 x half> @llvm.experimental.constrained.fma.v8f16(<8 x half> %7, <8 x half> %8, <8 x half> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store <8 x half> %9, ptr %ref.tmp.i, align 16 # | %10 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %10, ptr %__ret.i, align 16 # | %11 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %11 # | } # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <4 x half> @test_vfma_lane_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | %__ret = alloca <4 x half>, align 8 # | %__s0 = alloca <4 x half>, align 8 # | %__s1 = alloca <4 x half>, align 8 # | %__s2 = alloca <4 x half>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__s0, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %1, ptr %__s1, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <4 x half> %2, ptr %__s2, align 8 # | %3 = load <8 x i8>, ptr %__s0, align 8 # | %4 = load <8 x i8>, ptr %__s1, align 8 # | %5 = load <8 x i8>, ptr %__s2, align 8 # | %6 = bitcast <8 x i8> %5 to <4 x half> # | %lane = shufflevector <4 x half> %6, <4 x half> %6, <4 x i32> # | %fmla = bitcast <8 x i8> %4 to <4 x half> # | %fmla1 = bitcast <8 x i8> %3 to <4 x half> # | %fmla2 = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> %fmla, <4 x half> %lane, <4 x half> %fmla1, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store <4 x half> %fmla2, ptr %ref.tmp, align 8 # | %7 = load <4 x half>, ptr %ref.tmp, align 8 # | store <4 x half> %7, ptr %__ret, align 8 # | %8 = load <4 x half>, ptr %__ret, align 8 # | store <4 x half> %8, ptr %tmp, align 8 # | %9 = load <4 x half>, ptr %tmp, align 8 # | ret <4 x half> %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half>, <4 x half>, <4 x half>, metadata, metadata) #1 # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <8 x half> @test_vfmaq_lane_f16(<8 x half> noundef %a, <8 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <4 x half>, align 8 # | %__ret = alloca <8 x half>, align 16 # | %__s0 = alloca <8 x half>, align 16 # | %__s1 = alloca <8 x half>, align 16 # | %__s2 = alloca <4 x half>, align 8 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__s0, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %1, ptr %__s1, align 16 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <4 x half> %2, ptr %__s2, align 8 # | %3 = load <16 x i8>, ptr %__s0, align 16 # | %4 = load <16 x i8>, ptr %__s1, align 16 # | %5 = load <8 x i8>, ptr %__s2, align 8 # | %6 = bitcast <8 x i8> %5 to <4 x half> # | %lane = shufflevector <4 x half> %6, <4 x half> %6, <8 x i32> # | %fmla = bitcast <16 x i8> %4 to <8 x half> # | %fmla1 = bitcast <16 x i8> %3 to <8 x half> # | %fmla2 = call <8 x half> @llvm.experimental.constrained.fma.v8f16(<8 x half> %fmla, <8 x half> %lane, <8 x half> %fmla1, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store <8 x half> %fmla2, ptr %ref.tmp, align 16 # | %7 = load <8 x half>, ptr %ref.tmp, align 16 # | store <8 x half> %7, ptr %__ret, align 16 # | %8 = load <8 x half>, ptr %__ret, align 16 # | store <8 x half> %8, ptr %tmp, align 16 # | %9 = load <8 x half>, ptr %tmp, align 16 # | ret <8 x half> %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare <8 x half> @llvm.experimental.constrained.fma.v8f16(<8 x half>, <8 x half>, <8 x half>, metadata, metadata) #1 # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <4 x half> @test_vfma_laneq_f16(<4 x half> noundef %a, <4 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <8 x half>, align 16 # | %__ret = alloca <4 x half>, align 8 # | %__s0 = alloca <4 x half>, align 8 # | %__s1 = alloca <4 x half>, align 8 # | %__s2 = alloca <8 x half>, align 16 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <8 x half> %c, ptr %c.addr, align 16 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__s0, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %1, ptr %__s1, align 8 # | %2 = load <8 x half>, ptr %c.addr, align 16 # | store <8 x half> %2, ptr %__s2, align 16 # | %3 = load <8 x i8>, ptr %__s0, align 8 # | %4 = load <8 x i8>, ptr %__s1, align 8 # | %5 = load <16 x i8>, ptr %__s2, align 16 # | %6 = bitcast <8 x i8> %3 to <4 x half> # | %7 = bitcast <8 x i8> %4 to <4 x half> # | %8 = bitcast <16 x i8> %5 to <8 x half> # | %lane = shufflevector <8 x half> %8, <8 x half> %8, <4 x i32> # | %9 = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> %lane, <4 x half> %7, <4 x half> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store <4 x half> %9, ptr %ref.tmp, align 8 # | %10 = load <4 x half>, ptr %ref.tmp, align 8 # | store <4 x half> %10, ptr %__ret, align 8 # | %11 = load <4 x half>, ptr %__ret, align 8 # | store <4 x half> %11, ptr %tmp, align 8 # | %12 = load <4 x half>, ptr %tmp, align 8 # | ret <4 x half> %12 # | } # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <8 x half> @test_vfmaq_laneq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <8 x half>, align 16 # | %__ret = alloca <8 x half>, align 16 # | %__s0 = alloca <8 x half>, align 16 # | %__s1 = alloca <8 x half>, align 16 # | %__s2 = alloca <8 x half>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store <8 x half> %c, ptr %c.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__s0, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %1, ptr %__s1, align 16 # | %2 = load <8 x half>, ptr %c.addr, align 16 # | store <8 x half> %2, ptr %__s2, align 16 # | %3 = load <16 x i8>, ptr %__s0, align 16 # | %4 = load <16 # | ... # `---data was truncated (10240/13273) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055d1a765157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d1a764e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d1a7651cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7332249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f73322a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7332249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7332231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d1a75e724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d1a75e7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d1a75cbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d1a727b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d1a727ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7332232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f73322330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f73322330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d1a727ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not=fpexcept.maytrap '--implicit-check-not= @llvm.fma.' # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not=fpexcept.maytrap --implicit-check-not= @llvm.fma. # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c (662 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f64m1x3(ptr noundef %base, %binde # | ... # `---data was truncated (10240/99754) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559790a3257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559790a2f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559790a32cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa7fa649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa7fa6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa7fa649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa7fa631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005597909c824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005597909c8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005597909acf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055979065c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055979065be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa7fa632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa7fa6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa7fa6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055979065bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c (663 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16mf4_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16mf4_f32mf2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16mf2_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16mf2_f32m1_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16m1_f32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16m1_f32m2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16m2_f32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16m2_f32m4_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: noca # | ... # `---data was truncated (10240/100960) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564bbd86257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564bbd85f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564bbd862cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff716449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff7164a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff716449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff716431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564bbd7f824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564bbd7f8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564bbd7dcf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564bbd48c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564bbd48be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff716432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff7164330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff7164330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564bbd48bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c (664 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf8_tu( %maskedoff, %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv1i8.nxv1i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv1i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf4_tu( %maskedoff, %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv2i8.nxv2i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv2i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf2_tu( %maskedoff, %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv4i8.nxv4i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv4i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8m1_tu( %maskedoff, %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv8i8.nxv8i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | ; Functi # | ... # `---data was truncated (10240/116949) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055906a24d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055906a24a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055906a24dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f843b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f843b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f843b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f843b031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055906a1e324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055906a1e3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055906a1c7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559069e77176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559069e76e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f843b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f843b0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f843b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559069e76d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c (665 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8mf8x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8mf4x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_u8mf8x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_u8mf4x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_u8mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_u8m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8mf8x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8mf4x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, pt # | ... # `---data was truncated (10240/18980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557c9b14d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557c9b14a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557c9b14dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7c96533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7c9658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7c96533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7c9651b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557c9b0e324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557c9b0e3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557c9b0c7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557c9ad77176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557c9ad76e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7c9651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7c9651d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7c9651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557c9ad76d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c (666 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sme2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sme2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svzero_za64_vg1x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | call void @llvm.aarch64.sme.zero.za64.vg1x2(i32 %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.zero.za64.vg1x2(i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svzero_za64_vg1x4(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | call void @llvm.aarch64.sme.zero.za64.vg1x4(i32 %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.zero.za64.vg1x4(i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svzero_za64_vg2x1(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | call void @llvm.aarch64.sme.zero.za64.vg2x1(i32 %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.zero.za64.vg2x1(i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svzero_za64_vg2x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | call void @llvm.aarch64.sme.zero.za64.vg2x2(i32 %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.zero.za64.vg2x2(i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svzero_za64_vg2x4(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | call void @llvm.aarch64.sme.zero.za64.vg2x4(i32 %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.zero.za64.vg2x4(i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svzero_za64_vg4x1(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | call void @llvm.aarch64.sme.zero.za64.vg4x1(i32 %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.zero.za64.vg4x1(i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svzero_za64_vg4x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | call void @llvm.aarch64.sme.zero.za64.vg4x2(i32 %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.zero.za64.vg4x2(i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svzero_za64_vg4x4(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | call void @llvm.aarch64.sme.zero.za64.vg4x4(i32 %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.zero.za64.vg4x4(i32) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sme2p1" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem1: write) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005639acd2157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005639acd1e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005639acd21cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9104d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9104d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9104d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9104d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005639accb724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005639accb7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005639acc9bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005639ac94b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005639ac94ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9104d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9104d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9104d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005639ac94ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/arm-mve-intrinsics/scalar-shifts.c (667 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/scalar-shifts.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_asrl(i64 noundef %value, i32 noundef %shift) #0 { # | entry: # | %value.addr = alloca i64, align 8 # | %shift.addr = alloca i32, align 4 # | store i64 %value, ptr %value.addr, align 8 # | store i32 %shift, ptr %shift.addr, align 4 # | %0 = load i64, ptr %value.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load i32, ptr %shift.addr, align 4 # | %5 = call { i32, i32 } @llvm.arm.mve.asrl(i32 %3, i32 %2, i32 %4) # | %6 = extractvalue { i32, i32 } %5, 1 # | %7 = zext i32 %6 to i64 # | %8 = shl i64 %7, 32 # | %9 = extractvalue { i32, i32 } %5, 0 # | %10 = zext i32 %9 to i64 # | %11 = or i64 %8, %10 # | ret i64 %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.mve.asrl(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_lsll(i64 noundef %value, i32 noundef %shift) #0 { # | entry: # | %value.addr = alloca i64, align 8 # | %shift.addr = alloca i32, align 4 # | store i64 %value, ptr %value.addr, align 8 # | store i32 %shift, ptr %shift.addr, align 4 # | %0 = load i64, ptr %value.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load i32, ptr %shift.addr, align 4 # | %5 = call { i32, i32 } @llvm.arm.mve.lsll(i32 %3, i32 %2, i32 %4) # | %6 = extractvalue { i32, i32 } %5, 1 # | %7 = zext i32 %6 to i64 # | %8 = shl i64 %7, 32 # | %9 = extractvalue { i32, i32 } %5, 0 # | %10 = zext i32 %9 to i64 # | %11 = or i64 %8, %10 # | ret i64 %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.mve.lsll(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_sqrshr(i32 noundef %value, i32 noundef %shift) #0 { # | entry: # | %value.addr = alloca i32, align 4 # | %shift.addr = alloca i32, align 4 # | store i32 %value, ptr %value.addr, align 4 # | store i32 %shift, ptr %shift.addr, align 4 # | %0 = load i32, ptr %value.addr, align 4 # | %1 = load i32, ptr %shift.addr, align 4 # | %2 = call i32 @llvm.arm.mve.sqrshr(i32 %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.sqrshr(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_sqrshrl(i64 noundef %value, i32 noundef %shift) #0 { # | entry: # | %value.addr = alloca i64, align 8 # | %shift.addr = alloca i32, align 4 # | store i64 %value, ptr %value.addr, align 8 # | store i32 %shift, ptr %shift.addr, align 4 # | %0 = load i64, ptr %value.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load i32, ptr %shift.addr, align 4 # | %5 = call { i32, i32 } @llvm.arm.mve.sqrshrl(i32 %3, i32 %2, i32 %4, i32 64) # | %6 = extractvalue { i32, i32 } %5, 1 # | %7 = zext i32 %6 to i64 # | %8 = shl i64 %7, 32 # | %9 = extractvalue { i32, i32 } %5, 0 # | %10 = zext i32 %9 to i64 # | %11 = or i64 %8, %10 # | ret i64 %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.mve.sqrshrl(i32, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_sqrshrl_sat48(i64 noundef %value, i32 noundef %shift) #0 { # | entry: # | %value.addr = alloca i64, align 8 # | %shift.addr = alloca i32, align 4 # | store i64 %value, ptr %value.addr, align 8 # | store i32 %shift, ptr %shift.addr, align 4 # | %0 = load i64, ptr %value.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load i32, ptr %shift.addr, align 4 # | %5 = call { i32, i32 } @llvm.arm.mve.sqrshrl(i32 %3, i32 %2, i32 %4, i32 48) # | %6 = extractvalue { i32, i32 } %5, 1 # | %7 = zext i32 %6 to i64 # | %8 = shl i64 %7, 32 # | %9 = extractvalue { i32, i32 } %5, 0 # | %10 = zext i32 %9 to i64 # | %11 = or i64 %8, %10 # | ret i64 %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_sqshl(i32 noundef %value) #0 { # | entry: # | %value.addr = alloca i32, align 4 # | store i32 %value, ptr %value.addr, align 4 # | %0 = load i32, ptr %value.addr, align 4 # | %1 = call i32 @llvm.arm.mve.sqshl(i32 %0, i32 2) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.sqshl(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_sqshll(i64 noundef %value) #0 { # | entry: # | %value.addr = alloca i64, align 8 # | store i64 %value, ptr %value.addr, align 8 # | %0 = load i64, ptr %value.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = call { i32, i32 } @llvm.arm.mve.sqshll(i32 %3, i32 %2, i32 17) # | %5 = extractvalue { i32, i32 } %4, 1 # | %6 = zext i32 %5 to i64 # | %7 = shl i64 %6, 32 # | %8 = extractvalue { i32, i32 } %4, 0 # | %9 = zext i32 %8 to i64 # | %10 = or i64 %7, %9 # | ret i64 %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.mve.sqshll(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_srshr(i32 noundef %value) #0 { # | entry: # | %value.addr = alloca i32, align 4 # | store i32 %value, ptr %value.addr, align 4 # | %0 = load i32, ptr %value.addr, align 4 # | %1 = call i32 @llvm.arm.mve.srshr(i32 %0, i32 6) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.srshr(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_srshrl(i64 noundef %value) #0 { # | entry: # | %value.addr = alloca i64, align 8 # | store i64 %value, ptr %value.addr, align 8 # | %0 = load i64, ptr %value.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = call { i32, i32 } @llvm.arm.mve.srshrl(i32 %3, i32 %2, i32 26) # | %5 = extractvalue { i32, i32 } %4, 1 # | %6 = zext i32 %5 to i64 # | %7 = shl i64 %6, 32 # | %8 = extractvalue { i32, i32 } %4, 0 # | %9 = zext i32 %8 to i64 # | %10 = or i64 %7, %9 # | ret i64 %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.mve.srshrl(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_uqrshl(i32 noundef %value, i32 noundef %shift) #0 { # | entry: # | %value.addr = alloca i32, align 4 # | %shift.addr = alloca i32, align 4 # | store i32 %value, ptr %value.addr, align 4 # | store i32 %shift, ptr %shift.addr, align 4 # | %0 = load i32, ptr %value.addr, align 4 # | %1 = load i32, ptr %shift.addr, align 4 # | %2 = call i32 @llvm.arm.mve.uqrshl(i32 %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.uqrshl(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_uqrshll(i64 noundef %value, i32 noundef %shift) #0 { # | entry: # | %value.addr = alloca i64, align 8 # | %shift.addr = alloca i32, align 4 # | store i64 %value, ptr %value.addr, align 8 # | store i32 %shift, ptr %shift.addr, align 4 # | %0 = load i64, ptr %value.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load i32, ptr %shift.addr, align 4 # | %5 = call { i32, i32 } @llvm.arm.mve.uqrshll(i32 %3, i32 %2, i32 %4, i32 64) # | %6 = extractvalue { i32, i32 } %5, 1 # | %7 = zext i32 %6 to i64 # | %8 = shl i64 %7, 32 # | %9 = extractvalue { i32, i32 } %5, 0 # | %10 = zext i32 %9 to i64 # | %11 = or i64 %8, %10 # | ret i64 %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.mve.uqrshll(i32, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_uqrshll_sat48(i64 noundef %value, i32 noundef %shift) #0 { # | entry: # | %value.addr = alloca i64, align 8 # | %shift.addr = alloca i32, align 4 # | store i64 %value, ptr %value.addr, align 8 # | store i32 %shift, ptr %shift.addr, align 4 # | %0 = load i64, ptr %value.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load i32, ptr %shift.addr, align 4 # | %5 = call { i32, i32 } @llvm.arm.mve.uqrshll(i32 %3, i32 %2, i32 %4, i32 48) # | %6 = extractvalue { i32, i32 } %5, 1 # | %7 = zext i32 %6 to i64 # | %8 = shl i64 %7, 32 # | %9 = extractvalue { i32, i32 } %5, 0 # | %10 = zext i32 %9 to i64 # | %11 = or i64 %8, %10 # | ret i64 %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_uqshl(i32 noundef %value) #0 { # | entry: # | %value.addr = alloca i32, align 4 # | store i32 %value, ptr %value.addr, align 4 # | %0 = load i32, ptr %value.addr, align 4 # | %1 = call i32 @llvm.arm.mve.uqshl(i32 %0, i32 21) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.uqshl(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_uqshll(i64 noundef %value) #0 { # | entry: # | %value.addr = alloca i64, align 8 # | store i64 %value, ptr %value.addr, align 8 # | %0 = load i64, ptr %value.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = call { i32, i32 } @llvm.arm.mve.uqshll(i32 %3, i32 %2, i32 16) # | %5 = extractvalue { i32, i32 } %4, 1 # | %6 = zext i32 %5 to i64 # | %7 = shl i64 %6, 32 # | %8 = extractvalue { i32, i32 } %4, 0 # | %9 = zext i32 %8 to i64 # | %10 = or i64 %7, %9 # | ret i64 %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.mve.uqshll(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_urshr(i32 noundef %value) #0 { # | entry: # | %value.addr = alloca i32, align 4 # | store i32 %value, ptr %value.addr, align 4 # | %0 = load i32, ptr %value.addr, align 4 # | %1 = call i32 @llvm.arm.mve.urshr(i32 %0, i32 22) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nos # | ... # `---data was truncated (10240/11578) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005591a713657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005591a7133515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005591a7136cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f09b0e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f09b0ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f09b0e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f09b0e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005591a70cc24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005591a70cc096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005591a70b0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005591a6d60176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005591a6d5fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f09b0e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f09b0e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f09b0e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005591a6d5fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c (668 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2q.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2q.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2q.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2q.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2q.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2q.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2q.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_bf16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2q.nxv8bf16(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000563453d1857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563453d15515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563453d18cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f78e0133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f78e018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f78e0133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f78e011b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563453cae24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563453cae096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563453c92f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563453942176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563453941e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f78e011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f78e011d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f78e011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563453941d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c (669 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv16i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c (670 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m4_tu( %maskedoff, %op1, # | ... # `---data was truncated (10240/157173) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d1d01b957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d1d01b6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d1d01b9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f108a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f108a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f108a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f108a831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d1d014f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d1d014f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d1d0133f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d1cfde3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d1cfde2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f108a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f108a8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f108a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d1cfde2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c (671 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv1i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv2i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv4i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv8i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv16i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv16i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vas # | ... # `---data was truncated (10240/99585) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056187fb9e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056187fb9b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056187fb9ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1b57305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1b5735c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1b57305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1b572ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056187fb3424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056187fb34096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056187fb18f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056187f7c8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056187f7c7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1b572eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1b572ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1b572ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056187f7c7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c (672 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_s8() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_s16() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_s32() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_s64() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_u8() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_u16() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_u32() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_u64() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_f16() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_f32() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_f64() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_mf8() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_bf16() #0 { # | entry: # | ret undef # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000558d371f057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558d371ed515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558d371f0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbeda21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbeda2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbeda21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbeda203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558d3718624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558d37186096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558d3716af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558d36e1a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558d36e19e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbeda204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbeda2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbeda2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558d36e19d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c (673 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv1i16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv2i16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv4i16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv8i16.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv16i16.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv32i16.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv1i32.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv2i32.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv4i32.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv8i32.nxv8i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallbac # | ... # `---data was truncated (10240/66028) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b0b036357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b0b0360515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b0b0363cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdc73133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdc7318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdc73133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdc7311b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b0b02f924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b0b02f9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b0b02ddf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b0aff8d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b0aff8ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fdc7311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdc7311d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdc7311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b0aff8cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c (674 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_s8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.ld2.sret.nxv16i8.p0( %0, ptr %1) # | ret { , } %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2.sret.nxv16i8.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2.sret.nxv8i16.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2.sret.nxv8i16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2.sret.nxv4i32.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2.sret.nxv4i32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2.sret.nxv2i64.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2.sret.nxv2i64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_u8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.ld2.sret.nxv16i8.p0( %0, ptr %1) # | ret { , } %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2.sret.nxv8i16.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2.sret.nxv4i32.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2.sret.nxv2i64.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_f16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2.sret.nxv8f16.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2.sret.nxv8f16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_f32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2.sret.nxv4f32.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2.sret.nxv4f32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_f64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2.sret.nxv2f64.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm # | ... # `---data was truncated (10240/24404) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005628af1da57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005628af1d7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005628af1dacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc49d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc49d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc49d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc49d231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005628af17024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005628af170096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005628af154f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005628aee04176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005628aee03e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc49d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc49d2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc49d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005628aee03d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c (675 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_i32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_i32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_u32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_u32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32mf2x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret ta # | ... # `---data was truncated (10240/32031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ee180dd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ee180da515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ee180ddcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f39f7f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f39f7f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f39f7f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f39f7eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ee1807324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ee18073096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ee18057f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ee17d07176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ee17d06e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f39f7eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f39f7eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f39f7eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ee17d06d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c (676 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32mf2x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_i32mf2x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_i32m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_u32mf2x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_u32m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ec7a25057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ec7a24d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ec7a250cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6721133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f672118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6721133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f672111b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ec7a1e624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ec7a1e6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ec7a1caf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ec79e7a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ec79e79e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f672111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f672111d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f672111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ec79e79d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c (677 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_i8mf8x8 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555ba319457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555ba3191515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555ba3194cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f26b1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f26b1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f26b1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f26b1d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555ba312a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555ba312a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555ba310ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555ba2dbe176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555ba2dbde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f26b1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f26b1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f26b1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555ba2dbdd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c (678 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %o # | ... # `---data was truncated (10240/223855) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005630e261357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005630e2610515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005630e2613cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0312049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f03120a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0312049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0312031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005630e25a924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005630e25a9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005630e258df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005630e223d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005630e223ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0312032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f03120330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f03120330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005630e223cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/neon-shifts.c (679 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon-shifts.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -ffp-contract=fast -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -ffp-contract=fast -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_shift_vshr(<8 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | %vshr_n = lshr <8 x i8> %1, splat (i8 5) # | store <8 x i8> %vshr_n, ptr %ref.tmp, align 8 # | %2 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %2, ptr %__ret, align 8 # | %3 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %3, ptr %tmp, align 8 # | %4 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_shift_vshr_smax(<8 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | %vshr_n = ashr <8 x i8> %1, splat (i8 7) # | store <8 x i8> %vshr_n, ptr %ref.tmp, align 8 # | %2 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %2, ptr %__ret, align 8 # | %3 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %3, ptr %tmp, align 8 # | %4 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_shift_vshr_umax(<8 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | store <8 x i8> zeroinitializer, ptr %ref.tmp, align 8 # | %2 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %2, ptr %__ret, align 8 # | %3 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %3, ptr %tmp, align 8 # | %4 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_shift_vsra(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = load <8 x i8>, ptr %__s1, align 8 # | %vsra_n = lshr <8 x i8> %3, splat (i8 5) # | %4 = add <8 x i8> %2, %vsra_n # | store <8 x i8> %4, ptr %ref.tmp, align 8 # | %5 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %5, ptr %__ret, align 8 # | %6 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %6, ptr %tmp, align 8 # | %7 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_shift_vsra_smax(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = load <8 x i8>, ptr %__s1, align 8 # | %vsra_n = ashr <8 x i8> %3, splat (i8 7) # | %4 = add <8 x i8> %2, %vsra_n # | store <8 x i8> %4, ptr %ref.tmp, align 8 # | %5 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %5, ptr %__ret, align 8 # | %6 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %6, ptr %tmp, align 8 # | %7 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_shift_vsra_umax(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = load <8 x i8>, ptr %__s1, align 8 # | %4 = add <8 x i8> %2, zeroinitializer # | store <8 x i8> %4, ptr %ref.tmp, align 8 # | %5 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %5, ptr %__ret, align 8 # | %6 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %6, ptr %tmp, align 8 # | %7 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %7 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055afe02fb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055afe02f8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055afe02fbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f37ea933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f37ea98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f37ea933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f37ea91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055afe029124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055afe0291096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055afe0275f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055afdff25176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055afdff24e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f37ea91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f37ea91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f37ea91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055afdff24d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c (680 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_e4m3_e5m2_w4_f8e4m3m8_f8e5m2m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.e4m3.e5m2.i64.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.e4m3.e5m2.i64.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005604338d457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005604338d1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005604338d4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fce60e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fce60ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fce60e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fce60e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056043386a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056043386a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056043384ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005604334fe176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005604334fde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fce60e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fce60e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fce60e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005604334fdd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c (681 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulx_f16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmulx.nxv8f16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmulx.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulx_f32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmulx.nxv4f32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmulx.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulx_f64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmulx.nxv2f64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmulx.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulx_f16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmulx.nxv8f16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulx_f32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.fmulx.nxv4f32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulx_f64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.fmulx.nxv2f64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulx_f16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmulx.u.nxv8f16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmulx.u.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulx_f32_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.fmulx.u.nxv4f32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmulx.u.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulx_f64_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c (682 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf4_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf2_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m1_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m2_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m4_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m8_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf4_u16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.mask.nxv1bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf2_u16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.mask.nxv2bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m1_u16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.mask.nxv4bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m2_u16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.mask.nxv8bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m4_u16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.mask.nxv16bf16.i64( poison, %1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c (683 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32mf2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m1_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m4_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m8_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32mf2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m1_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range # | ... # `---data was truncated (10240/24990) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005639144f957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005639144f6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005639144f9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fda43a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fda43aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fda43a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fda43a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056391448f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056391448f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563914473f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563914123176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563914122e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fda43a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fda43a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fda43a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563914122d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c (684 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16mf4_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16mf4_f32mf2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16mf2_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16mf2_f32m1_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16m1_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16m1_f32m2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16m2_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16m2_f32m4_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32. # | ... # `---data was truncated (10240/101394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005593125de57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005593125db515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005593125decbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd33d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd33d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd33d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd33d431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055931257424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559312574096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559312558f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559312208176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559312207e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd33d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd33d4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd33d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559312207d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c (685 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c (686 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3 # | ... # `---data was truncated (10240/64366) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e1b158457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e1b1581515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e1b1584cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0e3f449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0e3f4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0e3f449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0e3f431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e1b151a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e1b151a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e1b14fef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e1b11ae176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e1b11ade93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0e3f432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0e3f4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0e3f4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e1b11add81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c (687 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64( %0, %1, bf # | ... # `---data was truncated (10240/65202) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a9b200357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a9b2000515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a9b2003cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd191d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd191d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd191d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd191d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a9b1f9924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a9b1f99096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a9b1f7df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a9b1c2d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a9b1c2ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd191d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd191d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd191d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a9b1c2cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c (688 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c (689 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf4_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf2_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m1_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv4bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv4bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m2_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv8bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv8bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m4_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv16bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv16bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m8_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv32bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv32bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslideup.mask.nxv1bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.mask.nxv1bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslideup.mask.nxv2bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.mask.nxv2bf16.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve/rsqrts.c (690 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve/rsqrts.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrsqrts_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.frsqrts.x.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frsqrts.x.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrsqrts_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.frsqrts.x.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frsqrts.x.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrsqrts_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.frsqrts.x.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frsqrts.x.nxv2f64(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x0000559abe33f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559abe33c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559abe33fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4112305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f411235c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4112305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f41122ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559abe2d524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559abe2d5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559abe2b9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559abdf69176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559abdf68e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f41122eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f41122ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f41122ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559abdf68d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c (691 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define d # | ... # `---data was truncated (10240/12208) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056131443857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561314435515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561314438cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fea9a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fea9a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fea9a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fea9a31b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005613143ce24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005613143ce096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005613143b2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561314062176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561314061e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fea9a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fea9a31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fea9a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561314061d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c (692 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c (693 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf4x8_tumu( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 0, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", # | ... # `---data was truncated (10240/16800) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f663c0357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f663c00515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f663c03cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4f56733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4f5678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4f56733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4f5671b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f663b9924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f663b99096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f663b7df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f66382d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f66382ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4f5671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4f5671d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4f5671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f66382cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c (694 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f64m1x4(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c (695 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv32i8.nxv32i8.i64( %0, # | ... # `---data was truncated (10240/95081) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005607b9fff57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005607b9ffc515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005607b9fffcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f22ed249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f22ed2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f22ed249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f22ed231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005607b9f9524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005607b9f95096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005607b9f79f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005607b9c29176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005607b9c28e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f22ed232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f22ed2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f22ed2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005607b9c28d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c (696 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmmla_s32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.smmla.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smmla.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmmla_u32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.ummla.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.ummla.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svusmmla_s32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.usmmla.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.usmmla.nxv4i32(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+i8mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000558c9e86a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558c9e867515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558c9e86acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8f49049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8f490a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8f49049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8f49031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558c9e80024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558c9e800096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558c9e7e4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558c9e494176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558c9e493e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8f49032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8f490330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8f490330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558c9e493d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c (697 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055da9472757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055da94724515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055da94727cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fca41649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fca416a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fca41649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fca41631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055da946bd24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055da946bd096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055da946a1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055da94351176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055da94350e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fca41632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fca416330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fca416330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055da94350d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c (698 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m4( %vd, %vs1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c (699 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv1i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv2i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv4i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv8i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, al # | ... # `---data was truncated (10240/225213) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e9c585d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e9c585a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e9c585dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff846b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff846b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff846b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff846b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e9c57f324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e9c57f3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e9c57d7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e9c5487176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e9c5486e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff846b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff846b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff846b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e9c5486d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c (700 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_f16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fminnm.nxv8f16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fminnm.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_f32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fminnm.nxv4f32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fminnm.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_f64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fminnm.nxv2f64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fminnm.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_f16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fminnm.nxv8f16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_f32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.fminnm.nxv4f32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_f64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.fminnm.nxv2f64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_f16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fminnm.u.nxv8f16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fminnm.u.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_f32_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.fminnm.u.nxv4f32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fminnm.u.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_f64_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.ad # | ... # `---data was truncated (10240/22107) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000562022c6557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562022c62515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562022c65cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fed28105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fed2815c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fed28105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fed280ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562022bfb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562022bfb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562022bdff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056202288f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056202288ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fed280eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fed280ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fed280ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056202288ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c (701 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvv_se_u8mf8( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i8.nxv1i8.nxv1i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i8.nxv1i8.nxv1i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvv_se_u8mf4( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvv.se.i32.nxv2i8.nxv2i8.nxv2i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv2i8.nxv2i8.nxv2i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvv_se_u8mf2( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvv.se.i32.nxv4i8.nxv4i8.nxv4i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv4i8.nxv4i8.nxv4i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvv_se_u8m1( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvv.se.i32.nxv8i8.nxv8i8.nxv8i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv8i8.nxv8i8.nxv8i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvv_se_u8m2( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvv.se.i32.nxv16i8.nxv16i8.nxv16i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv16i8.nxv16i8.nxv16i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvv_se_u8m4( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvv.se.i32.nxv32i8.nxv32i8.nxv32i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv32i8.nxv32i8.nxv32i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvv_se_u8m8( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvv.se.i32.nxv64i8.nxv64i8.nxv64i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv64i8.nxv64i8.nxv64i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvv_se_u16mf4( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i16.nxv1i16.nxv1i16.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i16.nxv1i16.nxv1i16.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvv_se_u16mf2( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvv.se.i32.nxv2i16.nxv2i16.nxv # | ... # `---data was truncated (10240/255166) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555612e1357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555612e10515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555612e13cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5537a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5537aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5537a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5537a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555612da924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555612da9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555612d8df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555612a3d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555612a3ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5537a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5537a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5537a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555612a3cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c (702 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmad_f16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmad.nxv8f16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmad.nxv8f16(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmad_f32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmad.nxv4f32( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmad.nxv4f32(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmad_f64_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmad.nxv2f64( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmad.nxv2f64(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmad_f16_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fnmad.nxv8f16( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmad_f32_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = call @llvm.aarch64.sve.fnmad.nxv4f32( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmad_f64_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = call @llvm.aarch64.sve.fnmad.nxv2f64( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmad_f16_x( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fnmla.u.nxv8f16( %4, %3, %2, %1) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind w # | ... # `---data was truncated (10240/26173) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000557ddd40157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557ddd3fe515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557ddd401cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4ff9849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4ff98a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4ff9849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4ff9831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557ddd39724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557ddd397096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557ddd37bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557ddd02b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557ddd02ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4ff9832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4ff98330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4ff98330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557ddd02ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c (703 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_u8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tblq.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_u16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tblq.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_u32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tblq.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_u64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tblq.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_s8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_s16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_s32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_s64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_f16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tblq.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_f32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tblq.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_f64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tblq.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_bf16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tblq.nxv8bf16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_mf8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv16i8( %0, %1) # | ret %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "sta # | ... # `---data was truncated (10240/10820) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055698012357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556980120515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556980123cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f06f2d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f06f2d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f06f2d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f06f2d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005569800b924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005569800b9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055698009df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055697fd4d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055697fd4ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f06f2d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f06f2d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f06f2d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055697fd4cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGenCXX/inline-then-fold-variadics.cpp (704 of 27911) ******************** TEST 'Clang :: CodeGenCXX/inline-then-fold-variadics.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp -triple wasm32-unknown-unknown -Wno-varargs -O1 -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S --passes='module(expand-variadics,default)' --expand-variadics-override=optimize -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp -triple wasm32-unknown-unknown -Wno-varargs -O1 -emit-llvm -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp" # | target datalayout = "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-i128:128-n32:64-S128-ni:1:10:20" # | target triple = "wasm32-unknown-unknown" # | # | %struct.asc = type { i8, i16, i32, i32, float, double } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define noundef i32 @first_pair_i32(i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { # | entry: # | %call = tail call noundef i32 (...) @_ZL5firstIiiET_z(i32 noundef %x, i32 noundef %y) # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define internal noundef i32 @_ZL5firstIiiET_z(...) unnamed_addr #0 { # | entry: # | %va = alloca ptr, align 4 # | call void @llvm.lifetime.start.p0(ptr nonnull %va) #4 # | call void @llvm.va_start.p0(ptr nonnull %va) # | %argp.cur = load ptr, ptr %va, align 4 # | %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur, i32 4 # | store ptr %argp.next, ptr %va, align 4 # | %0 = load i32, ptr %argp.cur, align 4, !tbaa !6 # | call void @llvm.va_end.p0(ptr %va) # | call void @llvm.lifetime.end.p0(ptr nonnull %va) #4 # | ret i32 %0 # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define noundef i32 @second_pair_i32(i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { # | entry: # | %call = tail call noundef i32 (...) @_ZL6secondIiiET0_z(i32 noundef %x, i32 noundef %y) # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define internal noundef i32 @_ZL6secondIiiET0_z(...) unnamed_addr #0 { # | entry: # | %va = alloca ptr, align 4 # | call void @llvm.lifetime.start.p0(ptr nonnull %va) #4 # | call void @llvm.va_start.p0(ptr nonnull %va) # | %argp.cur = load ptr, ptr %va, align 4 # | %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur, i32 4 # | %argp.next2 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 8 # | store ptr %argp.next2, ptr %va, align 4 # | %0 = load i32, ptr %argp.next, align 4, !tbaa !6 # | call void @llvm.va_end.p0(ptr %va) # | call void @llvm.lifetime.end.p0(ptr nonnull %va) #4 # | ret i32 %0 # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define noundef double @first_pair_f64(double noundef %x, double noundef %y) local_unnamed_addr #0 { # | entry: # | %call = tail call noundef double (...) @_ZL5firstIddET_z(double noundef %x, double noundef %y) # | ret double %call # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define internal noundef double @_ZL5firstIddET_z(...) unnamed_addr #0 { # | entry: # | %va = alloca ptr, align 4 # | call void @llvm.lifetime.start.p0(ptr nonnull %va) #4 # | call void @llvm.va_start.p0(ptr nonnull %va) # | %argp.cur = load ptr, ptr %va, align 4 # | %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 7 # | %argp.cur.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8) # | %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 8 # | store ptr %argp.next, ptr %va, align 4 # | %1 = load double, ptr %argp.cur.aligned, align 8, !tbaa !7 # | call void @llvm.va_end.p0(ptr %va) # | call void @llvm.lifetime.end.p0(ptr nonnull %va) #4 # | ret double %1 # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define noundef double @second_pair_f64(double noundef %x, double noundef %y) local_unnamed_addr #0 { # | entry: # | %call = tail call noundef double (...) @_ZL6secondIddET0_z(double noundef %x, double noundef %y) # | ret double %call # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define internal noundef double @_ZL6secondIddET0_z(...) unnamed_addr #0 { # | entry: # | %va = alloca ptr, align 4 # | call void @llvm.lifetime.start.p0(ptr nonnull %va) #4 # | call void @llvm.va_start.p0(ptr nonnull %va) # | %argp.cur = load ptr, ptr %va, align 4 # | %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 7 # | %argp.cur.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8) # | %1 = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 8 # | %argp.next2 = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 16 # | store ptr %argp.next2, ptr %va, align 4 # | %2 = load double, ptr %1, align 8, !tbaa !7 # | call void @llvm.va_end.p0(ptr %va) # | call void @llvm.lifetime.end.p0(ptr nonnull %va) #4 # | ret double %2 # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define noundef i32 @first_i32_f64(i32 noundef %x, double noundef %y) local_unnamed_addr #0 { # | entry: # | %call = tail call noundef i32 (...) @_ZL5firstIidET_z(i32 noundef %x, double noundef %y) # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define internal noundef i32 @_ZL5firstIidET_z(...) unnamed_addr #0 { # | entry: # | %va = alloca ptr, align 4 # | call void @llvm.lifetime.start.p0(ptr nonnull %va) #4 # | call void @llvm.va_start.p0(ptr nonnull %va) # | %argp.cur = load ptr, ptr %va, align 4 # | %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur, i32 4 # | store ptr %argp.next, ptr %va, align 4 # | %0 = load i32, ptr %argp.cur, align 4, !tbaa !6 # | call void @llvm.va_end.p0(ptr %va) # | call void @llvm.lifetime.end.p0(ptr nonnull %va) #4 # | ret i32 %0 # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define noundef double @second_i32_f64(i32 noundef %x, double noundef %y) local_unnamed_addr #0 { # | entry: # | %call = tail call noundef double (...) @_ZL6secondIidET0_z(i32 noundef %x, double noundef %y) # | ret double %call # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define internal noundef double @_ZL6secondIidET0_z(...) unnamed_addr #0 { # | entry: # | %va = alloca ptr, align 4 # | call void @llvm.lifetime.start.p0(ptr nonnull %va) #4 # | call void @llvm.va_start.p0(ptr nonnull %va) # | %argp.cur = load ptr, ptr %va, align 4 # | %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 11 # | %argp.cur1.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8) # | %argp.next2 = getelementptr inbounds nuw i8, ptr %argp.cur1.aligned, i32 8 # | store ptr %argp.next2, ptr %va, align 4 # | %1 = load double, ptr %argp.cur1.aligned, align 8, !tbaa !7 # | call void @llvm.va_end.p0(ptr %va) # | call void @llvm.lifetime.end.p0(ptr nonnull %va) #4 # | ret double %1 # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define noundef double @first_f64_i32(double noundef %x, i32 noundef %y) local_unnamed_addr #0 { # | entry: # | %call = tail call noundef double (...) @_ZL5firstIdiET_z(double noundef %x, i32 noundef %y) # | ret double %call # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define internal noundef double @_ZL5firstIdiET_z(...) unnamed_addr #0 { # | entry: # | %va = alloca ptr, align 4 # | call void @llvm.lifetime.start.p0(ptr nonnull %va) #4 # | call void @llvm.va_start.p0(ptr nonnull %va) # | %argp.cur = load ptr, ptr %va, align 4 # | %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 7 # | %argp.cur.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8) # | %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 8 # | store ptr %argp.next, ptr %va, align 4 # | %1 = load double, ptr %argp.cur.aligned, align 8, !tbaa !7 # | call void @llvm.va_end.p0(ptr %va) # | call void @llvm.lifetime.end.p0(ptr nonnull %va) #4 # | ret double %1 # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define noundef i32 @second_f64_i32(double noundef %x, i32 noundef %y) local_unnamed_addr #0 { # | entry: # | %call = tail call noundef i32 (...) @_ZL6secondIdiET0_z(double noundef %x, i32 noundef %y) # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define internal noundef i32 @_ZL6secondIdiET0_z(...) unnamed_addr #0 { # | entry: # | %va = alloca ptr, align 4 # | call void @llvm.lifetime.start.p0(ptr nonnull %va) #4 # | call void @llvm.va_start.p0(ptr nonnull %va) # | %argp.cur = load ptr, ptr %va, align 4 # | %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 7 # | %argp.cur.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8) # | %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 8 # | %argp.next2 = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 12 # | store ptr %argp.next2, ptr %va, align 4 # | %1 = load i32, ptr %argp.next, align 8, !tbaa !6 # | call void @llvm.va_end.p0(ptr %va) # | call void @llvm.lifetime.end.p0(ptr nonnull %va) #4 # | ret i32 %1 # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define noundef i32 @first_i32_ulong2(i32 noundef %x, ptr nofree noundef readonly captures(none) %y) local_unnamed_addr #0 { # | entry: # | %0 = load <2 x i64>, ptr %y, align 16, !tbaa !9 # | %call = tail call noundef i32 (...) @_ZL5firstIiDv2_yET_z(i32 noundef %x, <2 x i64> noundef %0) # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define internal noundef i32 @_ZL5firstIiDv2_yET_z(...) unnamed_addr #0 { # | entry: # | %va = alloca ptr, align 4 # | call void @llvm.lifetime.start.p0(ptr nonnull %va) #4 # | call void @llvm.va_start.p0(ptr nonnull %va) # | %argp.cur = load ptr, ptr %va, align 4 # | %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur, i32 4 # | store ptr %argp.next, ptr %va, align 4 # | %0 = load i32, ptr %argp.cur, align 4, !tbaa !6 # | call void @llvm.va_end.p0(ptr %va) # | call void @llvm.lifetime.end.p0(ptr nonnull %va) #4 # | ret i32 %0 # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define void @second_i32_ulong2(i32 noundef %x, ptr nofree noundef readonly captures(none) %y, ptr nofree noundef writeonly captures(none) initializes((0, 16)) %r) local_unnamed_addr #0 { # | entry: # | %0 = load <2 x i64>, ptr %y, align 16, !tbaa !9 # | %call = tail call noundef <2 x i64> (...) @_ZL6secondIiDv2_yET0_z(i32 noundef %x, <2 x i64> noundef %0) # | store <2 x i64> %call, ptr %r, align 16, !tbaa !9 # | ret void # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define internal noundef <2 x i64> @_ZL6secondIiDv2_yET0_z(...) unnamed_addr #0 { # | entry: # | %va = alloca ptr, align 4 # | call void @llvm.lifetime.start.p0(ptr nonnull %va) #4 # | call void @llvm.va_start.p0(ptr n # | ... # `---data was truncated (10240/20646) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S '--passes=module(expand-variadics,default)' --expand-variadics-override=optimize -o - # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S --passes=module(expand-variadics,default) --expand-variadics-override=optimize -o - # | #0 0x000055c1f900857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c1f9005515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c1f9008cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe440533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe44058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe440533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe44051b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c1f8f9e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c1f8f9e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c1f8f82f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c1f8c32176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c1f8c31e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe44051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe44051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe44051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c1f8c31d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c (705 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_s8_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = select %0, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mla.nxv16i8( %0, %4, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mla.nxv16i8(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_s16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mla.nxv8i16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mla.nxv8i16(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_s32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mla.nxv4i32( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mla.nxv4i32(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_s64_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mla.nxv2i64( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mla.nxv2i64(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_u8_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = select %0, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mla.nxv16i8( %0, %4, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_u16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mla.nxv8i16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_u32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mla.nxv4i32( %4, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c (706 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_u64m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_u64m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_u64m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %ba # | ... # `---data was truncated (10240/24100) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560294a9957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560294a96515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560294a99cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6e9ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6e9ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6e9ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6e9ad1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560294a2f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560294a2f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560294a13f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005602946c3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005602946c2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6e9ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6e9ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6e9ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005602946c2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c (707 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget3_s8( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = extractvalue { , , } %3, 0 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget3_s16( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = extractvalue { , , } %3, 2 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget3_s32( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = extractvalue { , , } %3, 1 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget3_s64( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = extractvalue { , , } %3, 0 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget3_u8( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = extractvalue { , , } %3, 2 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget3_u16( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = extractvalue { , , } %3, 1 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget3_u32( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = extractvalue { , , } %3, 0 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget3_u64( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue # | ... # `---data was truncated (10240/21007) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055f30e9c757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f30e9c4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f30e9c7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f35ac649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f35ac6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f35ac649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f35ac631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f30e95d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f30e95d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f30e941f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f30e5f1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f30e5f0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f35ac632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f35ac6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f35ac6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f30e5f0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c (708 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare < # | ... # `---data was truncated (10240/112825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005561cc17057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005561cc16d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005561cc170cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f13ed049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f13ed0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f13ed049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f13ed031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005561cc10624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005561cc106096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005561cc0eaf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005561cbd9a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005561cbd99e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f13ed032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f13ed0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f13ed0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005561cbd99d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c (709 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c (710 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvtnt_bf16_f32_x( %even, %pg, %op) #0 { # | entry: # | %even.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %even, ptr %even.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %even.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.fcvtnt.bf16f32.v2( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcvtnt.bf16f32.v2(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvtnt_bf16_f32_m( %even, %pg, %op) #0 { # | entry: # | %even.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %even, ptr %even.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %even.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.fcvtnt.bf16f32.v2( %0, %3, %2) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055f3ec83857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f3ec835515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f3ec838cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5300c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5300ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5300c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5300c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f3ec7ce24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f3ec7ce096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f3ec7b2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f3ec462176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f3ec461e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5300c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5300c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5300c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f3ec461d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c (711 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16mf4( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16mf2( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m1( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m2( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m4( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m8( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32mf2( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32m1( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32m2( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32m4( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: Modules/pr93497.cppm (712 of 27911) ******************** TEST 'Clang :: Modules/pr93497.cppm' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 rm -rf /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp # executed command: rm -rf /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp # RUN: at line 2 mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp # executed command: mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp # RUN: at line 3 split-file /usr/local/google/home/thakis/src/llvm-project/clang/test/Modules/pr93497.cppm /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp # executed command: split-file /usr/local/google/home/thakis/src/llvm-project/clang/test/Modules/pr93497.cppm /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.cppm -emit-module-interface -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.pcm # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.cppm -emit-module-interface -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.pcm # RUN: at line 7 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp -fmodule-file=mod=/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.pcm -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=simplifycfg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp -fmodule-file=mod=/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.pcm -emit-llvm -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | %struct.Thing = type { i32 } # | %struct.C = type { i32 } # | %struct.NonConstexprDtor = type { i32 } # | # | $needed = comdat any # | # | @_ZNW3mod5Thing3OneE = external global %struct.Thing, align 4 # | @_ZW3mod13ConstantValue = available_externally constant %struct.C { i32 1 }, align 4 # | @_ZW3mod11ConstantPtr = external global ptr, align 8 # | @_ZW3mod16NonConstantValue = external global %struct.C, align 4 # | @_ZW3mod21NonConstexprDtorValue = external global %struct.NonConstexprDtor, align 4 # | @llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 65535, ptr @_GLOBAL__sub_I_use.cpp, ptr null }] # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z3usev() #0 { # | entry: # | %t1 = alloca %struct.Thing, align 4 # | call void @llvm.memcpy.p0.p0.i64(ptr align 4 %t1, ptr align 4 @_ZNW3mod5Thing3OneE, i64 4, i1 false) # | %raw = getelementptr inbounds nuw %struct.Thing, ptr %t1, i32 0, i32 0 # | %0 = load i32, ptr %raw, align 4 # | %call = call noundef i32 @_Z7consumei(i32 noundef %0) # | ret i32 %call # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.memcpy.p0.p0.i64(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i64, i1 immarg) #1 # | # | declare noundef i32 @_Z7consumei(i32 noundef) #2 # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z4use2v() #0 { # | entry: # | %agg.tmp = alloca %struct.C, align 4 # | call void @llvm.memcpy.p0.p0.i64(ptr align 4 %agg.tmp, ptr align 4 @_ZW3mod13ConstantValue, i64 4, i1 false) # | %coerce.dive = getelementptr inbounds nuw %struct.C, ptr %agg.tmp, i32 0, i32 0 # | %0 = load i32, ptr %coerce.dive, align 4 # | %call = call noundef i32 @_Z8consumeCW3mod1C(i32 %0) # | ret i32 %call # | } # | # | declare noundef i32 @_Z8consumeCW3mod1C(i32) #2 # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z4use3v() #0 { # | entry: # | %retval = alloca i32, align 4 # | %Ptr = alloca ptr, align 8 # | %agg.tmp = alloca %struct.C, align 4 # | %0 = load ptr, ptr @_ZW3mod11ConstantPtr, align 8 # | store ptr %0, ptr %Ptr, align 8 # | %1 = load ptr, ptr %Ptr, align 8 # | %value = getelementptr inbounds nuw %struct.C, ptr %1, i32 0, i32 0 # | %2 = load i32, ptr %value, align 4 # | %tobool = icmp ne i32 %2, 0 # | br i1 %tobool, label %if.then, label %if.end # | # | if.then: ; preds = %entry # | %3 = load ptr, ptr %Ptr, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 4 %agg.tmp, ptr align 4 %3, i64 4, i1 false) # | %coerce.dive = getelementptr inbounds nuw %struct.C, ptr %agg.tmp, i32 0, i32 0 # | %4 = load i32, ptr %coerce.dive, align 4 # | %call = call noundef i32 @_Z8consumeCW3mod1C(i32 %4) # | store i32 %call, ptr %retval, align 4 # | br label %return # | # | if.end: ; preds = %entry # | %call1 = call i32 @needed() # | store i32 %call1, ptr %retval, align 4 # | br label %return # | # | return: ; preds = %if.end, %if.then # | %5 = load i32, ptr %retval, align 4 # | ret i32 %5 # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define linkonce_odr i32 @needed() #0 comdat { # | entry: # | %call = call noundef i32 @_Z7consumei(i32 noundef 43) # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z4use4v() #0 { # | entry: # | %retval = alloca i32, align 4 # | %Ref = alloca %struct.C, align 4 # | %agg.tmp = alloca %struct.C, align 4 # | call void @llvm.memcpy.p0.p0.i64(ptr align 4 %Ref, ptr align 4 @_ZW3mod16NonConstantValue, i64 4, i1 false) # | %value = getelementptr inbounds nuw %struct.C, ptr %Ref, i32 0, i32 0 # | %0 = load i32, ptr %value, align 4 # | %tobool = icmp ne i32 %0, 0 # | br i1 %tobool, label %if.then, label %if.end # | # | if.then: ; preds = %entry # | call void @llvm.memcpy.p0.p0.i64(ptr align 4 %agg.tmp, ptr align 4 %Ref, i64 4, i1 false) # | %coerce.dive = getelementptr inbounds nuw %struct.C, ptr %agg.tmp, i32 0, i32 0 # | %1 = load i32, ptr %coerce.dive, align 4 # | %call = call noundef i32 @_Z8consumeCW3mod1C(i32 %1) # | store i32 %call, ptr %retval, align 4 # | br label %return # | # | if.end: ; preds = %entry # | %call1 = call i32 @needed() # | store i32 %call1, ptr %retval, align 4 # | br label %return # | # | return: ; preds = %if.end, %if.then # | %2 = load i32, ptr %retval, align 4 # | ret i32 %2 # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z4use5v() #0 { # | entry: # | %retval = alloca i32, align 4 # | %V = alloca %struct.NonConstexprDtor, align 4 # | %cleanup.dest.slot = alloca i32, align 4 # | call void @llvm.memcpy.p0.p0.i64(ptr align 4 %V, ptr align 4 @_ZW3mod21NonConstexprDtorValue, i64 4, i1 false) # | %raw = getelementptr inbounds nuw %struct.NonConstexprDtor, ptr %V, i32 0, i32 0 # | %0 = load i32, ptr %raw, align 4 # | %tobool = icmp ne i32 %0, 0 # | br i1 %tobool, label %if.then, label %if.end # | # | if.then: ; preds = %entry # | %raw1 = getelementptr inbounds nuw %struct.NonConstexprDtor, ptr %V, i32 0, i32 0 # | %1 = load i32, ptr %raw1, align 4 # | %call = call noundef i32 @_Z7consumei(i32 noundef %1) # | store i32 %call, ptr %retval, align 4 # | store i32 1, ptr %cleanup.dest.slot, align 4 # | br label %cleanup # | # | if.end: ; preds = %entry # | %call2 = call i32 @needed() # | store i32 %call2, ptr %retval, align 4 # | store i32 1, ptr %cleanup.dest.slot, align 4 # | br label %cleanup # | # | cleanup: ; preds = %if.end, %if.then # | call void @_ZNW3mod16NonConstexprDtorD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) %V) #5 # | %2 = load i32, ptr %retval, align 4 # | ret i32 %2 # | } # | # | ; Function Attrs: nounwind # | declare void @_ZNW3mod16NonConstexprDtorD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4)) unnamed_addr #3 # | # | declare void @_ZGIW3mod() # | # | ; Function Attrs: noinline nounwind # | define internal void @_GLOBAL__sub_I_use.cpp() #4 section ".text.startup" { # | entry: # | call void @_ZGIW3mod() # | ret void # | } # | # | attributes #0 = { mustprogress noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } # | attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | attributes #3 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | attributes #4 = { noinline nounwind "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | attributes #5 = { nounwind } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=simplifycfg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=simplifycfg # | #0 0x0000563d0d7c757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563d0d7c4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563d0d7c7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f89f4649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f89f46a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f89f4649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f89f4631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563d0d75d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563d0d75d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563d0d741f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563d0d3f1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563d0d3f0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f89f4632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f89f46330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f89f46330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563d0d3f0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c (713 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.mask.nxv1f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv1f16.i64(, , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c (714 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op # | ... # `---data was truncated (10240/222917) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cb7ea0257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cb7e9ff515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cb7ea02cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9b8f105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9b8f15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9b8f105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9b8f0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cb7e99824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cb7e998096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cb7e97cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cb7e62c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cb7e62be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9b8f0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9b8f0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9b8f0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cb7e62bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c (715 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_i32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_i32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_u32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_u32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32mf2x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("ri # | ... # `---data was truncated (10240/32023) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ea1bf5c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ea1bf59515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ea1bf5ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f011e905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f011e95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f011e905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f011e8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ea1bef224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ea1bef2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ea1bed6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ea1bb86176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ea1bb85e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f011e8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f011e8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f011e8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ea1bb85d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c (716 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vlnu.nxv1i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vlnu.nxv2i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vlnu.nxv4i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vlnu.nxv8i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vlnu.nxv16i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vlnu.nxv32i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vlnu.nxv64i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv8i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv8i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv16i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | ... # `---data was truncated (10240/12958) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a9bc48a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a9bc487515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a9bc48acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f70d9533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f70d958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f70d9533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f70d951b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a9bc42024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a9bc420096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a9bc404f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a9bc0b4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a9bc0b3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f70d951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f70d951d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f70d951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a9bc0b3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c (717 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpuo_f16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fcmpuo.nxv8f16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcmpuo.nxv8f16(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpuo_f32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.fcmpuo.nxv4f32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcmpuo.nxv4f32(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpuo_f64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.fcmpuo.nxv2f64( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcmpuo.nxv2f64(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpuo_n_f16( %pg, %op1, half noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca half, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store half %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, half %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fcmpuo.nxv8f16( %3, %1, %.splat) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpuo_n_f32( %pg, %op1, float noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca float, align 4 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store float %op2, ptr %op2.addr, align 4 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %.splatinsert = insertelement poison, float %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fcmpuo.nxv4f32( %3, %1, %.splat) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpuo_n_f64( %pg, %op1, double noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca double, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store double %op2, ptr %op2.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load double, ptr %op2.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %.splatinsert = insertelement poison, double %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fcmpuo.nxv2f64( %3, %1, %.splat) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055f4872c357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f4872c0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f4872c3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdf00533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdf0058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdf00533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdf0051b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f48725924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f487259096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f48723df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f486eed176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f486eece93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fdf0051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdf0051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdf0051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f486eecd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c (718 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_lane_za32_f8_vg1x2(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zm, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice, ptr %slice.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %2 = load i32, ptr %slice.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | %7 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | call void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x2(i32 %2, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x2(i32, , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_lane_za32_f8_vg1x4(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store i32 %slice, ptr %slice.addr, align 4 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %4 = load i32, ptr %slice.addr, align 4 # | %5 = load { , , , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , , , } %5, 0 # | %7 = extractvalue { , , , } %5, 1 # | %8 = extractvalue { , , , } %5, 2 # | %9 = extractvalue { , , , } %5, 3 # | %10 = load , ptr %zm.addr, align 16 # | %11 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %11) # | call void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x4(i32 %4, %6, %7, %8, %9, %10, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x4(i32, , , , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_lane_za16_f8_vg1x2(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zm, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice, ptr %slice.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %2 = load i32, ptr %slice.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | %7 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | call void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x2(i32 %2, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x2(i32, , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_lane_za16_f8_vg1x4(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store i32 %slice, ptr %slice.addr, align 4 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %4 = load i32, ptr %slice.addr, align 4 # | %5 = load { , , , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , , , } %5, 0 # | %7 = extractvalue { , , , } %5, 1 # | %8 = extractvalue { , , , } %5, 2 # | %9 = extractvalue { , , , } %5, 3 # | %10 = load , ptr %zm.addr, align 16 # | %11 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %11) # | call void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x4(i32 %4, %6, %7, %8, %9, %10, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x4(i32, , , , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_ra # | ... # `---data was truncated (10240/35066) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim # | #0 0x000055b4e7e4157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b4e7e3e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b4e7e41cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbc93a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbc93aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbc93a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbc93a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b4e7dd724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b4e7dd7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b4e7dbbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b4e7a6b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b4e7a6ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbc93a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbc93a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbc93a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b4e7a6ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c (719 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16m8(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i16.i64( %2, ptr %0, %1, i64 %3) # | # | ... # `---data was truncated (10240/132462) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563fb686857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563fb6865515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563fb6868cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5ea1449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5ea14a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5ea1449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5ea1431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563fb67fe24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563fb67fe096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563fb67e2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563fb6492176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563fb6491e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5ea1432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5ea14330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5ea14330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563fb6491d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c (720 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svwhilege_b8_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.whilege.x2.nxv16i1(i64 %0, i64 %1) # | ret { , } %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.whilege.x2.nxv16i1(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svwhilege_b8_u64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.whilehs.x2.nxv16i1(i64 %0, i64 %1) # | ret { , } %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.whilehs.x2.nxv16i1(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svwhilege_b16_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.whilege.x2.nxv8i1(i64 %0, i64 %1) # | %3 = extractvalue { , } %2, 0 # | %4 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %3) # | %5 = insertvalue { , } poison, %4, 0 # | %6 = extractvalue { , } %2, 1 # | %7 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %6) # | %8 = insertvalue { , } %5, %7, 1 # | ret { , } %8 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.whilege.x2.nxv8i1(i64, i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svwhilege_b16_u64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.whilehs.x2.nxv8i1(i64 %0, i64 %1) # | %3 = extractvalue { , } %2, 0 # | %4 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %3) # | %5 = insertvalue { , } poison, %4, 0 # | %6 = extractvalue { , } %2, 1 # | %7 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %6) # | %8 = insertvalue { , } %5, %7, 1 # | ret { , } %8 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.whilehs.x2.nxv8i1(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svwhilege_b32_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.whilege.x2.nxv4i1(i64 %0, i64 %1) # | %3 = extractvalue { , } %2, 0 # | %4 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %3) # | %5 = insertvalue { , } poison, %4, 0 # | %6 = extractvalue { , } %2, 1 # | %7 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %6) # | %8 = insertvalue { , } %5, %7, 1 # | ret { , } %8 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.whilege.x2.nxv4i1(i64, i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svwhilege_b32_u64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.whilehs.x2.nxv4i1(i64 %0, i64 %1) # | %3 = extractvalue { , } %2, 0 # | %4 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %3) # | %5 = insertvalue { , } poison, %4, 0 # | %6 = extractvalue { , } %2, 1 # | %7 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %6) # | %8 = insertvalue { , } %5, %7, 1 # | ret { , } %8 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.whilehs.x2.nxv4i1(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svwhilege_b64_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.whilege.x2.nxv2i1(i64 %0, i64 %1) # | %3 = extractvalue { , } %2, 0 # | %4 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %3) # | %5 = insertvalue { , } poison, %4, 0 # | %6 = extractvalue { , } %2, 1 # | %7 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %6) # | %8 = insertvalue { , } %5, %7, 1 # | ret { , } %8 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.whilege.x2.nxv2i1(i64, i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svwhilege_b64_u64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.whilehs.x2.nxv2i1(i64 %0, i64 %1) # | %3 = extractvalue { , } %2, 0 # | %4 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %3) # | %5 = insertvalue { , } poison, %4, 0 # | %6 = extractvalue { , } %2, 1 # | %7 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %6) # | %8 = insertvalue { , } %5, %7, 1 # | ret { , } %8 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.whilehs.x2.nxv2i1(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svwhilegt_b8_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1 # | ... # `---data was truncated (10240/37926) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000559c5086757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559c50864515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559c50867cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb683f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb683f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb683f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb683eed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559c507fd24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559c507fd096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559c507e1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559c50491176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559c50490e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb683eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb683eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb683eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559c50490d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c (721 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst4_s8( %pg, ptr noundef %base, %data.coerce0, %data.coerce1, %data.coerce2, %data.coerce3) #0 { # | entry: # | %data = alloca { , , , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %data.coerce0, 0 # | %1 = insertvalue { , , , } %0, %data.coerce1, 1 # | %2 = insertvalue { , , , } %1, %data.coerce2, 2 # | %3 = insertvalue { , , , } %2, %data.coerce3, 3 # | store { , , , } %3, ptr %data, align 16 # | %data1 = load { , , , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , , , } %data1, ptr %data.addr, align 16 # | %4 = load , ptr %pg.addr, align 2 # | %5 = load ptr, ptr %base.addr, align 8 # | %6 = load { , , , }, ptr %data.addr, align 16 # | %7 = extractvalue { , , , } %6, 0 # | %8 = extractvalue { , , , } %6, 1 # | %9 = extractvalue { , , , } %6, 2 # | %10 = extractvalue { , , , } %6, 3 # | call void @llvm.aarch64.sve.st4.nxv16i8.p0( %7, %8, %9, %10, %4, ptr %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st4.nxv16i8.p0(, , , , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst4_s16( %pg, ptr noundef %base, %data.coerce0, %data.coerce1, %data.coerce2, %data.coerce3) #0 { # | entry: # | %data = alloca { , , , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %data.coerce0, 0 # | %1 = insertvalue { , , , } %0, %data.coerce1, 1 # | %2 = insertvalue { , , , } %1, %data.coerce2, 2 # | %3 = insertvalue { , , , } %2, %data.coerce3, 3 # | store { , , , } %3, ptr %data, align 16 # | %data1 = load { , , , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , , , } %data1, ptr %data.addr, align 16 # | %4 = load , ptr %pg.addr, align 2 # | %5 = load ptr, ptr %base.addr, align 8 # | %6 = load { , , , }, ptr %data.addr, align 16 # | %7 = extractvalue { , , , } %6, 0 # | %8 = extractvalue { , , , } %6, 1 # | %9 = extractvalue { , , , } %6, 2 # | %10 = extractvalue { , , , } %6, 3 # | %11 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %4) # | call void @llvm.aarch64.sve.st4.nxv8i16.p0( %7, %8, %9, %10, %11, ptr %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st4.nxv8i16.p0(, , , , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst4_s32( %pg, ptr noundef %base, %data.coerce0, %data.coerce1, %data.coerce2, %data.coerce3) #0 { # | entry: # | %data = alloca { , , , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %data.coerce0, 0 # | %1 = insertvalue { , , , } %0, %data.coerce1, 1 # | %2 = insertvalue { , , , } %1, %data.coerce2, 2 # | %3 = insertvalue { , , , } %2, %data.coerce3, 3 # | store { , , , } %3, ptr %data, align 16 # | %data1 = load { , , , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , , , } %data1, ptr %data.addr, align 16 # | %4 = load , ptr %pg.addr, align 2 # | %5 = load ptr, ptr %base.addr, align 8 # | %6 = load { , , , }, ptr %data.addr, align 16 # | %7 = extractvalue { , , , } %6, 0 # | %8 = extractvalue { , , , } %6, 1 # | %9 = extractvalue { , , , } %6, 2 # | %10 = extractvalue { , , , } %6, 3 # | %11 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %4) # | call void @llvm.aarch64.sve.st4.nxv4i32.p0( %7, %8, %9, %10, %11, ptr %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st4.nxv4i32.p0(, , , , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst4_s64( %pg, ptr noundef %base, %data.coerce0, %data.coerce1, %data.coerce2, %data.coerce3) #0 { # | entry: # | %data = alloca { , , , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %data.coerce0, 0 # | %1 = insertvalue { , , , } %0, %data.coerce1, 1 # | %2 = insertvalue { , , , } %1, %data.coerce2, 2 # | %3 = insertvalue { , , , } %2, %da # | ... # `---data was truncated (10240/73307) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005627a128d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005627a128a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005627a128dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6abc133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6abc18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6abc133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6abc11b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005627a122324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005627a1223096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005627a1207f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005627a0eb7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005627a0eb6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6abc11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6abc11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6abc11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005627a0eb6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c (722 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv64i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv64i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv32i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv32i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv16i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv16i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv8i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv8i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv4i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv4i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv2i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv2i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv1i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv1i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv64i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.mask.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv32i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.mask.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv16i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.mask.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv8i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.mask.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b16_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv4i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.mask.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b32_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv2i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosy # | ... # `---data was truncated (10240/11958) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559456a1757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559456a14515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559456a17cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9c19933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9c1998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9c19933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9c1991b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005594569ad24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005594569ad096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559456991f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559456641176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559456640e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9c1991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9c1991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9c1991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559456640d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c (723 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f64m1x3(ptr noundef %base, %binde # | ... # `---data was truncated (10240/99754) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555a34b2d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555a34b2a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555a34b2dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa80a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa80a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa80a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa80a91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555a34ac324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555a34ac3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555a34aa7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555a34757176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555a34756e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa80a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa80a91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa80a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555a34756d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqdmulhq.c (724 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqdmulhq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmulhq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vqdmulh.v16i8(<16 x i8> %0, <16 x i8> %1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vqdmulh.v16i8(<16 x i8>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmulhq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vqdmulh.v8i16(<8 x i16> %0, <8 x i16> %1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vqdmulh.v8i16(<8 x i16>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulhq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vqdmulh.v4i32(<4 x i32> %0, <4 x i32> %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vqdmulh.v4i32(<4 x i32>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmulhq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.qdmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.qdmulh.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmulhq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.qdmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.qdmulh.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulhq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.qdmulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.qdmulh.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmulhq_n_s8(<16 x i8> noundef %a, i8 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = call <16 x i8> @llvm.arm.mve.vqdmulh.v16i8(<16 x i8> %0, <16 x i8> %.splat) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmulhq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = call <8 x i16> @llvm.arm.mve.vqdmulh.v8i16(<8 x i16> %0, <8 x i16> %.splat) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulhq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = call <4 x i32> @llvm.arm.mve.vqdmulh.v4i32(<4 x i32> %0, <4 x i32> %.splat) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmulhq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.qdmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmulhq_m_n_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.qdmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: # | ... # `---data was truncated (10240/11849) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005655598b857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005655598b5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005655598b8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7f4b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7f4b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7f4b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7f4b431507 abort ./stdlib/abort.c:85:3 # | #7 0x000056555984e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056555984e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000565559832f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005655594e2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005655594e1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7f4b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7f4b4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7f4b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005655594e1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c (725 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste16_bf16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.sf.vste16.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste16_f16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste16_i16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste16_u16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvfbfmin,+zvfhmin,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfhmin1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fc0ce7157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fc0ce6e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fc0ce71cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f91fc849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f91fc8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f91fc849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f91fc831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fc0ce0724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fc0ce07096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fc0cdebf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fc0ca9b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fc0ca9ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f91fc832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f91fc8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f91fc8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fc0ca9ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c (726 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf8( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c (727 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8dot2 -target-feature +fp8dot4 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8dot2 -target-feature +fp8dot4 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_f32_mf8( %zda, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fdot.nxv4f32( %0, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fdot.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_f32_mf8( %zda, %zn, <1 x i8> %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca <1 x i8>, align 1 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store <1 x i8> %zm, ptr %zm.addr, align 1 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load <1 x i8>, ptr %zm.addr, align 1 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = extractelement <1 x i8> %2, i64 0 # | %.splatinsert = insertelement poison, i8 %4, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %5 = call @llvm.aarch64.sve.fp8.fdot.nxv4f32( %0, %1, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_f16_mf8( %zda, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fdot.nxv8f16( %0, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fdot.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_f16_mf8( %zda, %zn, <1 x i8> %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca <1 x i8>, align 1 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store <1 x i8> %zm, ptr %zm.addr, align 1 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load <1 x i8>, ptr %zm.addr, align 1 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = extractelement <1 x i8> %2, i64 0 # | %.splatinsert = insertelement poison, i8 %4, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %5 = call @llvm.aarch64.sve.fp8.fdot.nxv8f16( %0, %1, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_lane_f32_mf8( %zda, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fdot.lane.nxv4f32( %0, %1, %2, i32 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fdot.lane.nxv4f32(, , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_lane_f16_mf8( %zda, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fdot.lane.nxv8f16( %0, %1, %2, i32 7) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fdot.lane.nxv8f16(, , , i32 immarg) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp8dot2,+fp8dot4,+sve,+sve2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000564cfc00357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564cfc000515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564cfc003cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9483649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f94836a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9483649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9483631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564cfbf9924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564cfbf99096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564cfbf7df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564cfbc2d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564cfbc2ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9483632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f94836330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f94836330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564cfbc2cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c (728 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.sub.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sub.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sub.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sub.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sub.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sub.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sub.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sub.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.sub.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sub.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sub.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sub.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_s8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, pt # | ... # `---data was truncated (10240/72449) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000555b6002357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555b60020515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555b60023cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efe04c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efe04ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efe04c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efe04c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555b5ffb924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555b5ffb9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555b5ff9df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555b5fc4d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555b5fc4ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efe04c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efe04c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efe04c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555b5fc4cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c (729 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16mf4( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16mf2( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16m1( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16m2( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, pt # | ... # `---data was truncated (10240/79679) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005559fa45757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005559fa454515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005559fa457cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb475849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb4758a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb475849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb475831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005559fa3ed24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005559fa3ed096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005559fa3d1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005559fa081176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005559fa080e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb475832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb4758330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb4758330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005559fa080d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c (730 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = allo # | ... # `---data was truncated (10240/98179) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eba2f9057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055eba2f8d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055eba2f90cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc7c5733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc7c578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc7c5733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc7c571b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eba2f2624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055eba2f26096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055eba2f0af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055eba2bba176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055eba2bb9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc7c571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc7c571d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc7c571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eba2bb9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c (731 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c (732 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vx_i16mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wx_i16mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.w.nxv1i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vx_i16mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wx_i16mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.w.nxv2i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vx_i16m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wv_i16m1(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c (733 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16mf4_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16mf2_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16m1_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16m2_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd # | ... # `---data was truncated (10240/110070) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005565a8a8f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005565a8a8c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005565a8a8fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc90f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc90f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc90f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc90f11b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005565a8a2524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005565a8a25096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005565a8a09f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005565a86b9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005565a86b8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc90f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc90f11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc90f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005565a86b8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c (734 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_svbool_svcnt(target("aarch64.svcount") %cnt) #0 { # | entry: # | %cnt.addr = alloca target("aarch64.svcount"), align 2 # | store target("aarch64.svcount") %cnt, ptr %cnt.addr, align 2 # | %0 = load target("aarch64.svcount"), ptr %cnt.addr, align 2 # | %1 = call @llvm.aarch64.sve.convert.from.svcount(target("aarch64.svcount") %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svcount(target("aarch64.svcount")) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local target("aarch64.svcount") @test_svreinterpret_svcnt_svbool( %pg) #0 { # | entry: # | %pg.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = call target("aarch64.svcount") @llvm.aarch64.sve.convert.to.svcount( %0) # | ret target("aarch64.svcount") %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare target("aarch64.svcount") @llvm.aarch64.sve.convert.to.svcount() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000559d0776c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559d07769515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559d0776ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7bb6333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7bb638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7bb6333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7bb631b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559d0770224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559d07702096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559d076e6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559d07396176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559d07395e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7bb631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7bb631d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7bb631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559d07395d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c (735 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f64m1x3(ptr noundef %base, %binde # | ... # `---data was truncated (10240/99754) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056539020c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000565390209515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056539020ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f356e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f356e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f356e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f356e51b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005653901a224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005653901a2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000565390186f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056538fe36176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056538fe35e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f356e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f356e51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f356e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056538fe35d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c (736 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv8i8.nxv8i8.i64(, , , , i # | ... # `---data was truncated (10240/116267) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cbc572c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cbc5729515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cbc572ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efd56333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efd5638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efd56333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efd5631b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cbc56c224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cbc56c2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cbc56a6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cbc5356176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cbc5355e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efd5631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efd5631d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efd5631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cbc5355d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c (737 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | stor # | ... # `---data was truncated (10240/94371) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056316d63e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056316d63b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056316d63ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7e6e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7e6e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7e6e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7e6e431507 abort ./stdlib/abort.c:85:3 # | #7 0x000056316d5d424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056316d5d4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056316d5b8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056316d268176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056316d267e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7e6e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7e6e4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7e6e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056316d267d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c (738 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = loa # | ... # `---data was truncated (10240/14529) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e4cadd957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e4cadd6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e4cadd9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc81bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc81bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc81bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc81bf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e4cad6f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e4cad6f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e4cad53f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e4caa03176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e4caa02e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc81bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc81bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc81bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e4caa02d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c (739 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align # | ... # `---data was truncated (10240/94379) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005562c727057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005562c726d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005562c7270cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcfe2333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcfe238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcfe2333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcfe231b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005562c720624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005562c7206096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005562c71eaf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005562c6e9a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005562c6e99e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcfe231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcfe231d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcfe231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005562c6e99d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c (740 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincb_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqincb.n32(i32 %0, i32 31, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqincb.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincb_n_s32_1(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqincb.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincb_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqincb.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqincb.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincb_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqincb.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqincb.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincb_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqincb.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uqincb.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincb_pat_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqincb.n32(i32 %0, i32 5, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincb_pat_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqincb.n64(i64 %0, i32 6, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincb_pat_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqincb.n32(i32 %0, i32 7, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincb_pat_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqincb.n64(i64 %0, i32 8, i32 1) # | ret i64 %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000560c8ae1457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560c8ae11515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560c8ae14cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6599849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f65998a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6599849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6599831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560c8adaa24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560c8adaa096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560c8ad8ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560c8aa3e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560c8aa3de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6599832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f65998330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f65998330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560c8aa3dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c (741 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nx # | ... # `---data was truncated (10240/75125) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055918041857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559180415515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559180418cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe098a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe098aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe098a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe098a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005591803ae24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005591803ae096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559180392f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559180042176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559180041e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe098a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe098a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe098a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559180041d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c (742 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d307b5057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d307b4d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d307b50cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8413933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f841398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8413933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f841391b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d307ae624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d307ae6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d307acaf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d30777a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d307779e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f841391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f841391d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f841391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d307779d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c (743 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/80500) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e677a0457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e677a01515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e677a04cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3adc249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3adc2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3adc249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3adc231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e67799a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e67799a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e67797ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e67762e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e67762de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3adc232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3adc2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3adc2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e67762dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/arm-neon-vld.c (744 of 27911) ******************** TEST 'Clang :: CodeGen/arm-neon-vld.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | %struct.float16x4x2_t = type { [2 x <4 x half>] } # | %struct.float16x4x3_t = type { [3 x <4 x half>] } # | %struct.float16x4x4_t = type { [4 x <4 x half>] } # | %struct.float32x2x2_t = type { [2 x <2 x float>] } # | %struct.float32x2x3_t = type { [3 x <2 x float>] } # | %struct.float32x2x4_t = type { [4 x <2 x float>] } # | %struct.poly16x4x2_t = type { [2 x <4 x i16>] } # | %struct.poly16x4x3_t = type { [3 x <4 x i16>] } # | %struct.poly16x4x4_t = type { [4 x <4 x i16>] } # | %struct.poly8x8x2_t = type { [2 x <8 x i8>] } # | %struct.poly8x8x3_t = type { [3 x <8 x i8>] } # | %struct.poly8x8x4_t = type { [4 x <8 x i8>] } # | %struct.int16x4x2_t = type { [2 x <4 x i16>] } # | %struct.int16x4x3_t = type { [3 x <4 x i16>] } # | %struct.int16x4x4_t = type { [4 x <4 x i16>] } # | %struct.int32x2x2_t = type { [2 x <2 x i32>] } # | %struct.int32x2x3_t = type { [3 x <2 x i32>] } # | %struct.int32x2x4_t = type { [4 x <2 x i32>] } # | %struct.int64x1x2_t = type { [2 x <1 x i64>] } # | %struct.int64x1x3_t = type { [3 x <1 x i64>] } # | %struct.int64x1x4_t = type { [4 x <1 x i64>] } # | %struct.int8x8x2_t = type { [2 x <8 x i8>] } # | %struct.int8x8x3_t = type { [3 x <8 x i8>] } # | %struct.int8x8x4_t = type { [4 x <8 x i8>] } # | %struct.uint16x4x2_t = type { [2 x <4 x i16>] } # | %struct.uint16x4x3_t = type { [3 x <4 x i16>] } # | %struct.uint16x4x4_t = type { [4 x <4 x i16>] } # | %struct.uint32x2x2_t = type { [2 x <2 x i32>] } # | %struct.uint32x2x3_t = type { [3 x <2 x i32>] } # | %struct.uint32x2x4_t = type { [4 x <2 x i32>] } # | %struct.uint64x1x2_t = type { [2 x <1 x i64>] } # | %struct.uint64x1x3_t = type { [3 x <1 x i64>] } # | %struct.uint64x1x4_t = type { [4 x <1 x i64>] } # | %struct.uint8x8x2_t = type { [2 x <8 x i8>] } # | %struct.uint8x8x3_t = type { [3 x <8 x i8>] } # | %struct.uint8x8x4_t = type { [4 x <8 x i8>] } # | %struct.float16x8x2_t = type { [2 x <8 x half>] } # | %struct.float16x8x3_t = type { [3 x <8 x half>] } # | %struct.float16x8x4_t = type { [4 x <8 x half>] } # | %struct.float32x4x2_t = type { [2 x <4 x float>] } # | %struct.float32x4x3_t = type { [3 x <4 x float>] } # | %struct.float32x4x4_t = type { [4 x <4 x float>] } # | %struct.poly16x8x2_t = type { [2 x <8 x i16>] } # | %struct.poly16x8x3_t = type { [3 x <8 x i16>] } # | %struct.poly16x8x4_t = type { [4 x <8 x i16>] } # | %struct.poly8x16x2_t = type { [2 x <16 x i8>] } # | %struct.poly8x16x3_t = type { [3 x <16 x i8>] } # | %struct.poly8x16x4_t = type { [4 x <16 x i8>] } # | %struct.int16x8x2_t = type { [2 x <8 x i16>] } # | %struct.int16x8x3_t = type { [3 x <8 x i16>] } # | %struct.int16x8x4_t = type { [4 x <8 x i16>] } # | %struct.int32x4x2_t = type { [2 x <4 x i32>] } # | %struct.int32x4x3_t = type { [3 x <4 x i32>] } # | %struct.int32x4x4_t = type { [4 x <4 x i32>] } # | %struct.int64x2x2_t = type { [2 x <2 x i64>] } # | %struct.int64x2x3_t = type { [3 x <2 x i64>] } # | %struct.int64x2x4_t = type { [4 x <2 x i64>] } # | %struct.int8x16x2_t = type { [2 x <16 x i8>] } # | %struct.int8x16x3_t = type { [3 x <16 x i8>] } # | %struct.int8x16x4_t = type { [4 x <16 x i8>] } # | %struct.uint16x8x2_t = type { [2 x <8 x i16>] } # | %struct.uint16x8x3_t = type { [3 x <8 x i16>] } # | %struct.uint16x8x4_t = type { [4 x <8 x i16>] } # | %struct.uint32x4x2_t = type { [2 x <4 x i32>] } # | %struct.uint32x4x3_t = type { [3 x <4 x i32>] } # | %struct.uint32x4x4_t = type { [4 x <4 x i32>] } # | %struct.uint64x2x2_t = type { [2 x <2 x i64>] } # | %struct.uint64x2x3_t = type { [3 x <2 x i64>] } # | %struct.uint64x2x4_t = type { [4 x <2 x i64>] } # | %struct.uint8x16x2_t = type { [2 x <16 x i8>] } # | %struct.uint8x16x3_t = type { [3 x <16 x i8>] } # | %struct.uint8x16x4_t = type { [4 x <16 x i8>] } # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float16x4x2_t @test_vld1_f16_x2(ptr noundef %a) #0 { # | entry: # | %retval = alloca %struct.float16x4x2_t, align 8 # | %a.addr = alloca ptr, align 8 # | %__ret = alloca %struct.float16x4x2_t, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %vld1xN = call { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x2.v4f16.p0(ptr %0) # | store { <4 x half>, <4 x half> } %vld1xN, ptr %__ret, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 16, i1 false) # | %1 = load %struct.float16x4x2_t, ptr %retval, align 8 # | ret %struct.float16x4x2_t %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x2.v4f16.p0(ptr) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.memcpy.p0.p0.i64(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i64, i1 immarg) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float16x4x3_t @test_vld1_f16_x3(ptr noundef %a) #0 { # | entry: # | %retval = alloca %struct.float16x4x3_t, align 8 # | %a.addr = alloca ptr, align 8 # | %__ret = alloca %struct.float16x4x3_t, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %vld1xN = call { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x3.v4f16.p0(ptr %0) # | store { <4 x half>, <4 x half>, <4 x half> } %vld1xN, ptr %__ret, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 24, i1 false) # | %1 = load %struct.float16x4x3_t, ptr %retval, align 8 # | ret %struct.float16x4x3_t %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x3.v4f16.p0(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float16x4x4_t @test_vld1_f16_x4(ptr noundef %a) #0 { # | entry: # | %retval = alloca %struct.float16x4x4_t, align 8 # | %a.addr = alloca ptr, align 8 # | %__ret = alloca %struct.float16x4x4_t, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %vld1xN = call { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x4.v4f16.p0(ptr %0) # | store { <4 x half>, <4 x half>, <4 x half>, <4 x half> } %vld1xN, ptr %__ret, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 32, i1 false) # | %1 = load %struct.float16x4x4_t, ptr %retval, align 8 # | ret %struct.float16x4x4_t %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x4.v4f16.p0(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float32x2x2_t @test_vld1_f32_x2(ptr noundef %a) #0 { # | entry: # | %retval = alloca %struct.float32x2x2_t, align 8 # | %a.addr = alloca ptr, align 8 # | %__ret = alloca %struct.float32x2x2_t, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %vld1xN = call { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x2.v2f32.p0(ptr %0) # | store { <2 x float>, <2 x float> } %vld1xN, ptr %__ret, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 16, i1 false) # | %1 = load %struct.float32x2x2_t, ptr %retval, align 8 # | ret %struct.float32x2x2_t %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x2.v2f32.p0(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float32x2x3_t @test_vld1_f32_x3(ptr noundef %a) #0 { # | entry: # | %retval = alloca %struct.float32x2x3_t, align 8 # | %a.addr = alloca ptr, align 8 # | %__ret = alloca %struct.float32x2x3_t, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %vld1xN = call { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x3.v2f32.p0(ptr %0) # | store { <2 x float>, <2 x float>, <2 x float> } %vld1xN, ptr %__ret, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 24, i1 false) # | %1 = load %struct.float32x2x3_t, ptr %retval, align 8 # | ret %struct.float32x2x3_t %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x3.v2f32.p0(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float32x2x4_t @test_vld1_f32_x4(ptr noundef %a) #0 { # | entry: # | %retval = alloca %struct.float32x2x4_t, align 8 # | %a.addr = alloca ptr, align 8 # | %__ret = alloca %struct.float32x2x4_t, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %vld1xN = call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x4.v2f32.p0(ptr %0) # | store { <2 x float>, <2 x float>, <2 x float>, <2 x float> } %vld1xN, ptr %__ret, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 32, i1 false) # | %1 = load %struct.float32x2x4_t, ptr %retval, align 8 # | ret %struct.float32x2x4_t %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x4.v2f32.p0(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.poly16x4x2_t @test_vld1_p16_x2(ptr noundef %a) #0 { # | entry: # | %retval = alloca %struct.poly16x4x2_t, align 8 # | %a.addr = alloca ptr, align 8 # | %__ret = alloca %struct.poly16x4x2_t, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %vld1xN = call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x2.v4i16.p0(ptr %0) # | store { <4 x i16>, <4 x i16> } %vld1xN, ptr %__ret, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 16, i1 false) # | %1 = load %struct.poly16x4x2_t, ptr %retval, align 8 # | ret %struct.poly16x4x2_t %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x2.v4i16.p0(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.poly16x4x3_t @test_vld1_p16_x3(ptr noundef %a) #0 { # | entry: # | %retval = alloca %struct.poly16x4x3_t, align 8 # | %a.addr = alloca ptr, align 8 # | %__ret = alloca %struct.poly16 # | ... # `---data was truncated (10240/109928) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560b6861457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560b68611515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560b68614cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0454649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f04546a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0454649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0454631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560b685aa24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560b685aa096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560b6858ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560b6823e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560b6823de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0454632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f04546330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f04546330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560b6823dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c (745 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m4( % # | ... # `---data was truncated (10240/149145) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056297f8e157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056297f8de515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056297f8e1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbc78d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbc78d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbc78d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbc78ced507 abort ./stdlib/abort.c:85:3 # | #7 0x000056297f87724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056297f877096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056297f85bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056297f50b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056297f50ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbc78ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbc78cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbc78cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056297f50ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c (746 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_i8mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/69980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005572f884b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005572f8848515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005572f884bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f19af333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f19af38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f19af333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f19af31b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005572f87e124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005572f87e1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005572f87c5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005572f8475176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005572f8474e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f19af31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f19af31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f19af31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005572f8474d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c (747 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv8i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv8i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv4i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv2i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv8i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_vnum_s16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv8i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv4i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv2i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_vnum_u16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv8i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c (748 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svcreate4_b( %x0, %x1, %x2, %x4) #0 { # | entry: # | %x0.addr = alloca , align 2 # | %x1.addr = alloca , align 2 # | %x2.addr = alloca , align 2 # | %x4.addr = alloca , align 2 # | store %x0, ptr %x0.addr, align 2 # | store %x1, ptr %x1.addr, align 2 # | store %x2, ptr %x2.addr, align 2 # | store %x4, ptr %x4.addr, align 2 # | %0 = load , ptr %x0.addr, align 2 # | %1 = load , ptr %x1.addr, align 2 # | %2 = load , ptr %x2.addr, align 2 # | %3 = load , ptr %x4.addr, align 2 # | %4 = insertvalue { , , , } poison, %0, 0 # | %5 = insertvalue { , , , } %4, %1, 1 # | %6 = insertvalue { , , , } %5, %2, 2 # | %7 = insertvalue { , , , } %6, %3, 3 # | ret { , , , } %7 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055ab0e2f957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ab0e2f6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ab0e2f9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbf15c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbf15ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbf15c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbf15c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ab0e28f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ab0e28f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ab0e273f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ab0df23176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ab0df22e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbf15c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbf15c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbf15c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ab0df22d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c (749 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_lane_bf16_idx1( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmla.lane.nxv8bf16( %0, %1, %2, i32 1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmla.lane.nxv8bf16(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_lane_bf16_idx3( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmla.lane.nxv8bf16( %0, %1, %2, i32 3) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_lane_bf16_idx7( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmla.lane.nxv8bf16( %0, %1, %2, i32 7) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16b16,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000557ea201457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557ea2011515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557ea2014cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f29ec449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f29ec4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f29ec449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f29ec431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557ea1faa24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557ea1faa096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557ea1f8ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557ea1c3e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557ea1c3de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f29ec432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f29ec4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f29ec4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557ea1c3dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c (750 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget4_s8( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.addr, align 16 # | %4 = load { , , , }, ptr %tuple.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget4_s16( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.addr, align 16 # | %4 = load { , , , }, ptr %tuple.addr, align 16 # | %5 = extractvalue { , , , } %4, 2 # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget4_s32( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.addr, align 16 # | %4 = load { , , , }, ptr %tuple.addr, align 16 # | %5 = extractvalue { , , , } %4, 2 # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget4_s64( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.addr, align 16 # | %4 = load { , , , }, ptr %tuple.addr, align 16 # | %5 = extractvalue { , , , } %4, 3 # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget4_u8( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.addr, align 16 # | %4 = load { , , , }, ptr %tuple.addr, align 16 # | %5 = extractvalue { , , , } %4, 2 # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget4_u16( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.a # | ... # `---data was truncated (10240/28771) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055cbe318c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cbe3189515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cbe318ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f92bcd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f92bcd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f92bcd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f92bcd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cbe312224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cbe3122096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cbe3106f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cbe2db6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cbe2db5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f92bcd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f92bcd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f92bcd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cbe2db5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c (751 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv16f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv16f16.f16.i64( poison, %0, half %1, i # | ... # `---data was truncated (10240/125641) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560e9490d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560e9490a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560e9490dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb201c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb201ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb201c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb201c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560e948a324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560e948a3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560e94887f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560e94537176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560e94536e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb201c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb201c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb201c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560e94536d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c (752 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | # | ... # `---data was truncated (10240/424835) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f9641ab57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f9641a8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f9641abcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4e58f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4e58f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4e58f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4e58f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f96414124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f964141096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f964125f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f963dd5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f963dd4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4e58f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4e58f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4e58f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f963dd4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c (753 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b697b0e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b697b0b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b697b0ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb97a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb97a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb97a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb97a31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b697aa424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b697aa4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b697a88f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b697738176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b697737e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb97a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb97a31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb97a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b697737d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c (754 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c (755 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv8i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv8i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv4i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv2i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv8i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_vnum_s16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv8i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv4i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv2i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_vnum_u16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv8i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c (756 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv8i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv8i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv4i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv2i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv8i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_vnum_s16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv8i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv4i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv2i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_vnum_u16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv8i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c (757 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c (758 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_s8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.cnot.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cnot.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_s16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.cnot.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cnot.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.cnot.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cnot.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.cnot.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cnot.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_u8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.cnot.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_u16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.cnot.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_u32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.cnot.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.cnot.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_s8_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.cnot.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_s16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.cnot.nxv8i16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c (759 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m1_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = # | ... # `---data was truncated (10240/26564) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562d9731657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562d97313515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562d97316cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fea94a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fea94aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fea94a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fea94a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562d972ac24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562d972ac096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562d97290f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562d96f40176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562d96f3fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fea94a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fea94a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fea94a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562d96f3fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c (760 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16mf4_f8e4m3mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16mf4_f8e4m3mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16mf2_f8e4m3mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16mf2_f8e4m3mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m1_f8e4m3mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m1_f8e4m3mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m2_f8e4m3m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m2_f8e4m3m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m4_f8e4m3m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m4_f8e4m3m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, ali # | ... # `---data was truncated (10240/201234) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561a3df2f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561a3df2c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561a3df2fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6aa0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6aa08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6aa0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6aa0831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561a3dec524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561a3dec5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561a3dea9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561a3db59176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561a3db58e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6aa0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6aa08330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6aa08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561a3db58d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c (761 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv1i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv2i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv4i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv8i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv16i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv32i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv64i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv1i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv2i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv4i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv8i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv16i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv16i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c (762 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16m8(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretur # | ... # `---data was truncated (10240/136005) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055793a70a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055793a707515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055793a70acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3320733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f332078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3320733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f332071b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055793a6a024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055793a6a0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055793a684f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055793a334176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055793a333e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f332071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f332071d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f332071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055793a333d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c (763 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf4x8_tumu( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2. # | ... # `---data was truncated (10240/18498) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561467a7557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561467a72515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561467a75cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa0ba133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa0ba18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa0ba133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa0ba11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561467a0b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561467a0b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005614679eff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056146769f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056146769ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa0ba11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa0ba11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa0ba11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056146769ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c (764 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple # | ... # `---data was truncated (10240/113757) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d9c052757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d9c0524515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d9c0527cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fde30133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fde3018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fde30133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fde3011b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d9c04bd24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d9c04bd096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d9c04a1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d9c0151176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d9c0150e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fde3011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fde3011d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fde3011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d9c0150d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c (765 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv2f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv4f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv8f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv16f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv32f16.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv2f32.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv4f32.nxv2f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv8f32.nxv4f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscal # | ... # `---data was truncated (10240/235596) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a2576d257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a2576cf515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a2576d2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f888af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f888af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f888af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f888af1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a25766824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a257668096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a25764cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a2572fc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a2572fbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f888af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f888af1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f888af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a2572fbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c (766 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/175163) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005608936d757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005608936d4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005608936d7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1cebe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1cebea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1cebe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1cebe31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056089366d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056089366d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560893651f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560893301176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560893300e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1cebe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1cebe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1cebe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560893300d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c (767 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call < # | ... # `---data was truncated (10240/66998) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005573b787157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005573b786e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005573b7871cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3606249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f36062a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3606249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3606231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005573b780724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005573b7807096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005573b77ebf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005573b749b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005573b749ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3606232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f36062330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f36062330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005573b749ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c (768 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_f16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmaxnm.nxv8f16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmaxnm.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_f32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmaxnm.nxv4f32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmaxnm.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_f64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmaxnm.nxv2f64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmaxnm.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_f16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmaxnm.nxv8f16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_f32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.fmaxnm.nxv4f32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_f64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.fmaxnm.nxv2f64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_f16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmaxnm.u.nxv8f16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmaxnm.u.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_f32_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.fmaxnm.u.nxv4f32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmaxnm.u.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_f64_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.ad # | ... # `---data was truncated (10240/22107) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055899afaa57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055899afa7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055899afaacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f544461bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f54446725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f544461ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5444603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055899af4024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055899af40096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055899af24f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055899abd4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055899abd3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5444604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f54446050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f54446050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055899abd3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c (769 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf8x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf4x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf8x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf4x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf8x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf4x4_m( %mask, ptr noundef %bas # | ... # `---data was truncated (10240/20340) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ea8bfbd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ea8bfba515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ea8bfbdcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9a00a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9a00aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9a00a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9a00a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ea8bf5324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ea8bf53096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ea8bf37f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ea8bbe7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ea8bbe6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9a00a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9a00a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9a00a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ea8bbe6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_index.c (770 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_index.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svindex_s8(i8 noundef %base, i8 noundef %step) #0 { # | entry: # | %base.addr = alloca i8, align 1 # | %step.addr = alloca i8, align 1 # | store i8 %base, ptr %base.addr, align 1 # | store i8 %step, ptr %step.addr, align 1 # | %0 = load i8, ptr %base.addr, align 1 # | %1 = load i8, ptr %step.addr, align 1 # | %2 = call @llvm.aarch64.sve.index.nxv16i8(i8 %0, i8 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.index.nxv16i8(i8, i8) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svindex_s16(i16 noundef %base, i16 noundef %step) #0 { # | entry: # | %base.addr = alloca i16, align 2 # | %step.addr = alloca i16, align 2 # | store i16 %base, ptr %base.addr, align 2 # | store i16 %step, ptr %step.addr, align 2 # | %0 = load i16, ptr %base.addr, align 2 # | %1 = load i16, ptr %step.addr, align 2 # | %2 = call @llvm.aarch64.sve.index.nxv8i16(i16 %0, i16 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.index.nxv8i16(i16, i16) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svindex_s32(i32 noundef %base, i32 noundef %step) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | %step.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | store i32 %step, ptr %step.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = load i32, ptr %step.addr, align 4 # | %2 = call @llvm.aarch64.sve.index.nxv4i32(i32 %0, i32 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.index.nxv4i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svindex_s64(i64 noundef %base, i64 noundef %step) #0 { # | entry: # | %base.addr = alloca i64, align 8 # | %step.addr = alloca i64, align 8 # | store i64 %base, ptr %base.addr, align 8 # | store i64 %step, ptr %step.addr, align 8 # | %0 = load i64, ptr %base.addr, align 8 # | %1 = load i64, ptr %step.addr, align 8 # | %2 = call @llvm.aarch64.sve.index.nxv2i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.index.nxv2i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svindex_u8(i8 noundef %base, i8 noundef %step) #0 { # | entry: # | %base.addr = alloca i8, align 1 # | %step.addr = alloca i8, align 1 # | store i8 %base, ptr %base.addr, align 1 # | store i8 %step, ptr %step.addr, align 1 # | %0 = load i8, ptr %base.addr, align 1 # | %1 = load i8, ptr %step.addr, align 1 # | %2 = call @llvm.aarch64.sve.index.nxv16i8(i8 %0, i8 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svindex_u16(i16 noundef %base, i16 noundef %step) #0 { # | entry: # | %base.addr = alloca i16, align 2 # | %step.addr = alloca i16, align 2 # | store i16 %base, ptr %base.addr, align 2 # | store i16 %step, ptr %step.addr, align 2 # | %0 = load i16, ptr %base.addr, align 2 # | %1 = load i16, ptr %step.addr, align 2 # | %2 = call @llvm.aarch64.sve.index.nxv8i16(i16 %0, i16 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svindex_u32(i32 noundef %base, i32 noundef %step) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | %step.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | store i32 %step, ptr %step.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = load i32, ptr %step.addr, align 4 # | %2 = call @llvm.aarch64.sve.index.nxv4i32(i32 %0, i32 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svindex_u64(i64 noundef %base, i64 noundef %step) #0 { # | entry: # | %base.addr = alloca i64, align 8 # | %step.addr = alloca i64, align 8 # | store i64 %base, ptr %base.addr, align 8 # | store i64 %step, ptr %step.addr, align 8 # | %0 = load i64, ptr %base.addr, align 8 # | %1 = load i64, ptr %step.addr, align 8 # | %2 = call @llvm.aarch64.sve.index.nxv2i64(i64 %0, i64 %1) # | ret %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000560211d0557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560211d02515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560211d05cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd6a6e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd6a6ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd6a6e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd6a6e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560211c9b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560211c9b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560211c7ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056021192f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056021192ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd6a6e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd6a6e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd6a6e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056021192ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c (771 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_s8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call { , , } @llvm.aarch64.sve.ld3.sret.nxv16i8.p0( %0, ptr %1) # | ret { , , } %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , } @llvm.aarch64.sve.ld3.sret.nxv16i8.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , , } @llvm.aarch64.sve.ld3.sret.nxv8i16.p0( %2, ptr %1) # | ret { , , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , } @llvm.aarch64.sve.ld3.sret.nxv8i16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , , } @llvm.aarch64.sve.ld3.sret.nxv4i32.p0( %2, ptr %1) # | ret { , , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , } @llvm.aarch64.sve.ld3.sret.nxv4i32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call { , , } @llvm.aarch64.sve.ld3.sret.nxv2i64.p0( %2, ptr %1) # | ret { , , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , } @llvm.aarch64.sve.ld3.sret.nxv2i64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_u8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call { , , } @llvm.aarch64.sve.ld3.sret.nxv16i8.p0( %0, ptr %1) # | ret { , , } %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , , } @llvm.aarch64.sve.ld3.sret.nxv8i16.p0( %2, ptr %1) # | ret { , , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , , } @llvm.aarch64.sve.ld3.sret.nxv4i32.p0( %2, ptr %1) # | ret { , , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call { , , } @llvm.aarch64.sve.ld3.sret.nxv2i64.p0( %2, ptr %1) # | ret { , , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_f16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , , } @llvm.aarch64.sve.ld3.sret.nxv8f16.p0( %2, ptr %1) # | ret { , , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , } @llvm.aarch64.sve.ld3.sret.nxv8f16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_f32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , , } @llvm.aarch64.sve.ld3.sret.nxv4f32.p0( %2, ptr %1) # | ret { , , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , } @llvm.aarch64.sve.ld3.sret.nxv4f32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_f64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c (772 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vx_u16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wv_u16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wx_u16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.w.nxv1i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vx_u16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wv_u16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wx_u16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.w.nxv2i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vx_u16m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c (773 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsl_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.lsl.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.lsl.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsl_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.lsl.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.lsl.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsl_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.lsl.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.lsl.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsl_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.lsl.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.lsl.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsl_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.lsl.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsl_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.lsl.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsl_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.lsl.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsl_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.lsl.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsl_s8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, pt # | ... # `---data was truncated (10240/53158) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055f90c58d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f90c58a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f90c58dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff837533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff83758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff837533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff83751b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f90c52324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f90c523096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f90c507f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f90c1b7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f90c1b6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff83751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff83751d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff83751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f90c1b6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve/maxnmv.c (774 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve/maxnmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local half @test_svmaxnmv_f16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call half @llvm.aarch64.sve.fmaxnmv.nxv8f16( %2, %1) # | ret half %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.aarch64.sve.fmaxnmv.nxv8f16(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local float @test_svmaxnmv_f32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call float @llvm.aarch64.sve.fmaxnmv.nxv4f32( %2, %1) # | ret float %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.aarch64.sve.fmaxnmv.nxv4f32(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local double @test_svmaxnmv_f64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call double @llvm.aarch64.sve.fmaxnmv.nxv2f64( %2, %1) # | ret double %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.aarch64.sve.fmaxnmv.nxv2f64(, ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x00005604545be57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005604545bb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005604545becbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f437b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f437b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f437b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f437b231507 abort ./stdlib/abort.c:85:3 # | #7 0x000056045455424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560454554096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560454538f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005604541e8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005604541e7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f437b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f437b2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f437b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005604541e7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c (775 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005637fe6de57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005637fe6db515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005637fe6decbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9f8b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9f8b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9f8b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9f8b91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005637fe67424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005637fe674096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005637fe658f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005637fe308176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005637fe307e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9f8b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9f8b91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9f8b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005637fe307d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c (776 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f # | ... # `---data was truncated (10240/165246) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555eea08957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555eea086515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555eea089cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8d10705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8d1075c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8d10705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8d106ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555eea01f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555eea01f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555eea003f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555ee9cb3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555ee9cb2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8d106eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8d106ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8d106ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555ee9cb2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c (777 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretur # | ... # `---data was truncated (10240/69677) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d617f0b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d617f08515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d617f0bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb00e905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb00e95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb00e905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb00e8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d617ea124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d617ea1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d617e85f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d617b35176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d617b34e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb00e8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb00e8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb00e8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d617b34d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c (778 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svminnm_single_bf16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fminnm.single.x2.nxv8bf16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fminnm.single.x2.nxv8bf16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svminnm_single_f16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fminnm.single.x2.nxv8f16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fminnm.single.x2.nxv8f16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svminnm_single_f32_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fminnm.single.x2.nxv4f32( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fminnm.single.x2.nxv4f32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svminnm_single_f64_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fminnm.single.x2.nxv2f64( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fminnm.single.x2.nxv2f64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svminnm_single_bf16_x4( %zdn.coerce0, %zdn.coerce1, %zdn.coerce2, %zdn.coerce3, %zm) #0 { # | entry: # | %zdn = alloca { , , , }, align 16 # | %zdn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zdn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zdn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zdn.coerce3, 3 # | store { , , , } %3, ptr %zdn, align 16 # | %zdn1 = load { , , , }, ptr %zdn, align 16 # | store { , , , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %4 = load { , , , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = load , ptr %zm.addr, align 16 # | %10 = call { , , , } @llvm.aarch64.sve.fminnm.single.x4.nxv8bf16( %5, %6, %7, %8, %9) # | ret { , , , } %10 # | } # | # | ; Funct # | ... # `---data was truncated (10240/50311) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000557eeacdc57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557eeacd9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557eeacdccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f17e7649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f17e76a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f17e7649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f17e7631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557eeac7224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557eeac72096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557eeac56f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557eea906176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557eea905e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f17e7632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f17e76330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f17e76330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557eea905d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c (779 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tupl # | ... # `---data was truncated (10240/88444) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ada7f7a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ada7f77515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ada7f7acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f37e0333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f37e038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f37e0333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f37e031b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ada7f1024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ada7f10096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ada7ef4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ada7ba4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ada7ba3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f37e031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f37e031d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f37e031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ada7ba3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c (780 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv4i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree n # | ... # `---data was truncated (10240/15237) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056120ea3b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056120ea38515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056120ea3bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc7beb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc7beb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc7beb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc7beb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056120e9d124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056120e9d1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056120e9b5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056120e665176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056120e664e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc7beb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc7beb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc7beb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056120e664d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c (781 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf4x7(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf2x7(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16m1x7(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf4x7_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf2x7_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16m1x7_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056057490f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056057490c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056057490fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3ed8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3ed898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3ed8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3ed891b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005605748a524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005605748a5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560574889f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560574539176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560574538e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3ed891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3ed891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3ed891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560574538d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c (782 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uw_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i32.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv2i32.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uw_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i32.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uw_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv2i32.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uw_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv2i32.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055629605357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556296050515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556296053cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcda1649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcda16a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcda1649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcda1631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556295fe924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556295fe9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556295fcdf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556295c7d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556295c7ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcda1632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcda16330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcda16330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556295c7cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c (783 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f32m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_t # | ... # `---data was truncated (10240/128436) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055556624557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555566242515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555566245cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbaf0649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbaf06a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbaf0649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbaf0631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005555661db24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005555661db096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005555661bff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555565e6f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555565e6ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbaf0632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbaf06330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbaf06330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555565e6ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c (784 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svscale_single_f16_x2( %op1.coerce0, %op1.coerce1, %op2) #0 { # | entry: # | %op1 = alloca { , }, align 16 # | %op1.addr = alloca { , }, align 16 # | %op2.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %op1.coerce0, 0 # | %1 = insertvalue { , } %0, %op1.coerce1, 1 # | store { , } %1, ptr %op1, align 16 # | %op11 = load { , }, ptr %op1, align 16 # | store { , } %op11, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %2 = load { , }, ptr %op1.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %op2.addr, align 16 # | %6 = call { , } @llvm.aarch64.sme.fp8.scale.single.x2.nxv8f16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sme.fp8.scale.single.x2.nxv8f16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svscale_single_f32_x2( %op1.coerce0, %op1.coerce1, %op2) #0 { # | entry: # | %op1 = alloca { , }, align 16 # | %op1.addr = alloca { , }, align 16 # | %op2.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %op1.coerce0, 0 # | %1 = insertvalue { , } %0, %op1.coerce1, 1 # | store { , } %1, ptr %op1, align 16 # | %op11 = load { , }, ptr %op1, align 16 # | store { , } %op11, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %2 = load { , }, ptr %op1.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %op2.addr, align 16 # | %6 = call { , } @llvm.aarch64.sme.fp8.scale.single.x2.nxv4f32( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sme.fp8.scale.single.x2.nxv4f32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svscale_single_f64_x2( %op1.coerce0, %op1.coerce1, %op2) #0 { # | entry: # | %op1 = alloca { , }, align 16 # | %op1.addr = alloca { , }, align 16 # | %op2.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %op1.coerce0, 0 # | %1 = insertvalue { , } %0, %op1.coerce1, 1 # | store { , } %1, ptr %op1, align 16 # | %op11 = load { , }, ptr %op1, align 16 # | store { , } %op11, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %2 = load { , }, ptr %op1.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %op2.addr, align 16 # | %6 = call { , } @llvm.aarch64.sme.fp8.scale.single.x2.nxv2f64( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sme.fp8.scale.single.x2.nxv2f64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svscale_single_f16_x4( %op1.coerce0, %op1.coerce1, %op1.coerce2, %op1.coerce3, %op2) #0 { # | entry: # | %op1 = alloca { , , , }, align 16 # | %op1.addr = alloca { , , , }, align 16 # | %op2.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %op1.coerce0, 0 # | %1 = insertvalue { , , , } %0, %op1.coerce1, 1 # | %2 = insertvalue { , , , } %1, %op1.coerce2, 2 # | %3 = insertvalue { , , , } %2, %op1.coerce3, 3 # | store { , , , } %3, ptr %op1, align 16 # | %op11 = load { , , , }, ptr %op1, align 16 # | store { , , , } %op11, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %4 = load { , , , }, ptr %op1.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = load , ptr %op2.addr, align 16 # | %10 = call { , , , } @llvm.aarch64.sme.fp8.scale.single.x4.nxv8f16( %5, %6, %7, %8, %9) # | ret { , , , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sme.fp8.scale.single.x4.nxv8f16(, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svscale_single_f32_x4( %op1.coerce0, %op1.coerce1, %op1.coerce2, %op1.coerce3, %op2) #0 { # | entry: # | %op1 = alloca { , , , }, align 16 # | %op1.addr = alloca { , , , }, align 16 # | %op2.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %op1.coerce0, 0 # | %1 = insertvalue { , , , } %0, %op1.coerce1, 1 # | %2 = insertvalue { , , , } %1, %op1.coerce2, 2 # | %3 = insertvalue { , , , } %2, %op1.coerce3, 3 # | store { , , , } %3, ptr %op1, align 16 # | %op11 = load { , , , }, ptr %op1, align 16 # | store { , , , } %op11, ptr # | ... # `---data was truncated (10240/37349) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000564c7ce4057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564c7ce3d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564c7ce40cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f62dd533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f62dd58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f62dd533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f62dd51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564c7cdd624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564c7cdd6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564c7cdbaf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564c7ca6a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564c7ca69e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f62dd51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f62dd51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f62dd51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564c7ca69d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c (785 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/97913) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055691429957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556914296515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556914299cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f10f6c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f10f6ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f10f6c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f10f6c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055691422f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055691422f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556914213f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556913ec3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556913ec2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f10f6c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f10f6c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f10f6c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556913ec2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16.c (786 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c --check-prefixes=ALL,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vfma_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %6 = bitcast <8 x i8> %3 to <4 x half> # | %7 = bitcast <8 x i8> %4 to <4 x half> # | %8 = bitcast <8 x i8> %5 to <4 x half> # | %9 = call <4 x half> @llvm.fma.v4f16(<4 x half> %7, <4 x half> %8, <4 x half> %6) # | store <4 x half> %9, ptr %ref.tmp.i, align 8 # | %10 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %10, ptr %__ret.i, align 8 # | %11 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vfmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store <8 x half> %c, ptr %c.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | %2 = load <8 x half>, ptr %c.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %6 = bitcast <16 x i8> %3 to <8 x half> # | %7 = bitcast <16 x i8> %4 to <8 x half> # | %8 = bitcast <16 x i8> %5 to <8 x half> # | %9 = call <8 x half> @llvm.fma.v8f16(<8 x half> %7, <8 x half> %8, <8 x half> %6) # | store <8 x half> %9, ptr %ref.tmp.i, align 16 # | %10 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %10, ptr %__ret.i, align 16 # | %11 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vfms_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i.i = alloca <4 x half>, align 8 # | %__p1.addr.i.i = alloca <4 x half>, align 8 # | %__p2.addr.i.i = alloca <4 x half>, align 8 # | %__ret.i.i = alloca <4 x half>, align 8 # | %ref.tmp.i.i = alloca <8 x i8>, align 8 # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <4 x half>, ptr %__p0.addr.i, align 8 # | %4 = load <4 x half>, ptr %__p1.addr.i, align 8 # | %fneg.i = fneg <4 x half> %4 # | %5 = load <4 x half>, ptr %__p2.addr.i, align 8 # | store <4 x half> %3, ptr %__p0.addr.i.i, align 8 # | store <4 x half> %fneg.i, ptr %__p1.addr.i.i, align 8 # | store <4 x half> %5, ptr %__p2.addr.i.i, align 8 # | %6 = load <8 x i8>, ptr %__p0.addr.i.i, align 8 # | %7 = load <8 x i8>, ptr %__p1.addr.i.i, align 8 # | %8 = load <8 x i8>, ptr %__p2.addr.i.i, align 8 # | %9 = bitcast <8 x i8> %6 to <4 x half> # | %10 = bitcast <8 x i8> %7 to <4 x half> # | %11 = bitcast <8 x i8> %8 to <4 x half> # | %12 = call <4 x half> @llvm.fma.v4f16(<4 x half> %10, <4 x half> %11, <4 x half> %9) # | store <4 x half> %12, ptr %ref.tmp.i.i, align 8 # | %13 = load <4 x half>, ptr %ref.tmp.i.i, align 8 # | store <4 x half> %13, ptr %__ret.i.i, align 8 # | %14 = load <4 x half>, ptr %__ret.i.i, align 8 # | store <4 x half> %14, ptr %__ret.i, align 8 # | %15 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %15 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vfmsq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i.i = alloca <8 x half>, align 16 # | %__p1.addr.i.i = alloca <8 x half>, align 16 # | %__p2.addr.i.i = alloca <8 x half>, align 16 # | %__ret.i.i = alloca <8 x half>, align 16 # | %ref.tmp.i.i = alloca <16 x i8>, align 16 # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store <8 x half> %c, ptr %c.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | %2 = load <8 x half>, ptr %c.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <8 x half>, ptr %__p0.addr.i, align 16 # | %4 = load <8 x half>, ptr %__p1.addr.i, align 16 # | %fneg.i = fneg <8 x half> %4 # | %5 = load <8 x half>, ptr %__p2.addr.i, align 16 # | store <8 x half> %3, ptr %__p0.addr.i.i, align 16 # | store <8 x half> %fneg.i, ptr %__p1.addr.i.i, align 16 # | store <8 x half> %5, ptr %__p2.addr.i.i, align 16 # | %6 = load <16 x i8>, ptr %__p0.addr.i.i, align 16 # | %7 = load <16 x i8>, ptr %__p1.addr.i.i, align 16 # | %8 = load <16 x i8>, ptr %__p2.addr.i.i, align 16 # | %9 = bitcast <16 x i8> %6 to <8 x half> # | %10 = bitcast <16 x i8> %7 to <8 x half> # | %11 = bitcast <16 x i8> %8 to <8 x half> # | %12 = call <8 x half> @llvm.fma.v8f16(<8 x half> %10, <8 x half> %11, <8 x half> %9) # | store <8 x half> %12, ptr %ref.tmp.i.i, align 16 # | %13 = load <8 x half>, ptr %ref.tmp.i.i, align 16 # | store <8 x half> %13, ptr %__ret.i.i, align 16 # | %14 = load <8 x half>, ptr %__ret.i.i, align 16 # | store <8 x half> %14, ptr %__ret.i, align 16 # | %15 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %15 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vfma_lane_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | %__ret = alloca <4 x half>, align 8 # | %__s0 = alloca <4 x half>, align 8 # | %__s1 = alloca <4 x half>, align 8 # | %__s2 = alloca <4 x half>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__s0, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %1, ptr %__s1, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <4 x half> %2, ptr %__s2, align 8 # | %3 = load <8 x i8>, ptr %__s0, align 8 # | %4 = load <8 x i8>, ptr %__s1, align 8 # | %5 = load <8 x i8>, ptr %__s2, align 8 # | %6 = bitcast <8 x i8> %5 to <4 x half> # | %lane = shufflevector <4 x half> %6, <4 x half> %6, <4 x i32> # | %fmla = bitcast <8 x i8> %4 to <4 x half> # | %fmla1 = bitcast <8 x i8> %3 to <4 x half> # | %fmla2 = call <4 x half> @llvm.fma.v4f16(<4 x half> %fmla, <4 x half> %lane, <4 x half> %fmla1) # | store <4 x half> %fmla2, ptr %ref.tmp, align 8 # | %7 = load <4 x half>, ptr %ref.tmp, align 8 # | store <4 x half> %7, ptr %__ret, align 8 # | %8 = load <4 x half>, ptr %__ret, align 8 # | store <4 x half> %8, ptr %tmp, align 8 # | %9 = load <4 x half>, ptr %tmp, align 8 # | ret <4 x half> %9 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x half> @llvm.fma.v4f16(<4 x half>, <4 x half>, <4 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vfmaq_lane_f16(<8 x half> noundef %a, <8 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <4 x half>, align 8 # | %__ret = alloca <8 x half>, align 16 # | %__s0 = alloca <8 x half>, align 16 # | %__s1 = alloca <8 x half>, align 16 # | %__s2 = alloca <4 x half>, align 8 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__s0, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %1, ptr %__s1 # | ... # `---data was truncated (10240/42739) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055d5026df57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d5026dc515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d5026dfcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efd24733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efd2478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efd24733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efd2471b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d50267524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d502675096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d502659f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d502309176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d502308e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efd2471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efd2471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efd2471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d502308d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c --check-prefixes=ALL,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c --check-prefixes=ALL,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c (787 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbrkpa_b_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.brkpa.z.nxv16i1( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.brkpa.z.nxv16i1(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055b02804f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b02804c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b02804fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f93bc305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f93bc35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f93bc305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f93bc2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b027fe524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b027fe5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b027fc9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b027c79176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b027c78e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f93bc2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f93bc2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f93bc2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b027c78d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c (788 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m4( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c (789 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf8_tu( %maskedoff, %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv1i8.nxv1i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv1i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf4_tu( %maskedoff, %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv2i8.nxv2i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv2i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf2_tu( %maskedoff, %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv4i8.nxv4i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv4i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8m1_tu( %maskedoff, %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv8i8.nxv8i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | # | ... # `---data was truncated (10240/116957) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560aa7fb657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560aa7fb3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560aa7fb6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9fb8e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9fb8ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9fb8e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9fb8e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560aa7f4c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560aa7f4c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560aa7f30f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560aa7be0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560aa7bdfe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9fb8e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9fb8e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9fb8e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560aa7bdfd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c (790 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vx_u16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wv_u16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wx_u16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.w.nxv1i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vx_u16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wv_u16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wx_u16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.w.nxv2i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vx_u16m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c (791 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_i8mf4x6(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dce218b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055dce2188515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055dce218bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f86b2f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f86b2f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f86b2f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f86b2f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dce212124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055dce2121096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055dce2105f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055dce1db5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055dce1db4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f86b2f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f86b2f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f86b2f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dce1db4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c (792 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf4x8_tumu( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 0, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector. # | ... # `---data was truncated (10240/16808) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f91550757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f915504515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f915507cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc57e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc57e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc57e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc57e831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f91549d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f91549d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f915481f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f915131176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f915130e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc57e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc57e8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc57e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f915130d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c (793 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintx_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frintx.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintx.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintx_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frintx.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintx.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintx_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frintx.nxv2f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintx.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintx_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.frintx.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintx_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.frintx.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintx_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.frintx.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintx_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frintx.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintx_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frintx.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintx_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frintx.nxv2f64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055e16b72a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e16b727515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e16b72acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6b92733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6b9278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6b92733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6b9271b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e16b6c024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e16b6c0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e16b6a4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e16b354176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e16b353e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6b9271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6b9271d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6b9271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e16b353d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_div.c (794 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_div.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdiv_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sdiv.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdiv.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdiv_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sdiv.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdiv.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdiv_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.udiv.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.udiv.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdiv_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.udiv.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.udiv.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdiv_s32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.sdiv.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdiv_s64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.sdiv.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdiv_u32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.udiv.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdiv_u64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.udiv.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdiv_s32_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call # | ... # `---data was truncated (10240/48703) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000560c56f1157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560c56f0e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560c56f11cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa961f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa961f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa961f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa961f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560c56ea724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560c56ea7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560c56e8bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560c56b3b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560c56b3ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa961f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa961f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa961f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560c56b3ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c (795 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv1i8.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv2i8.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv4i8.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv8i8.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv16i8.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv32i8.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv32i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv64i8.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv64i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_u8mf8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv1i8.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_u8mf4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv2i8.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_u8mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv4i8.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_u8m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, al # | ... # `---data was truncated (10240/30013) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558f5b10957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558f5b106515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558f5b109cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1128133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f112818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1128133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f112811b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558f5b09f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558f5b09f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558f5b083f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558f5ad33176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558f5ad32e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f112811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f112811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f112811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558f5ad32d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c (796 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m4( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c (797 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | stor # | ... # `---data was truncated (10240/94371) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005627b214457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005627b2141515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005627b2144cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2b60b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2b60b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2b60b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2b60b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005627b20da24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005627b20da096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005627b20bef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005627b1d6e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005627b1d6de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2b60b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2b60b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2b60b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005627b1d6dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c (798 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/82983) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d636d1b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d636d18515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d636d1bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdda8733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdda878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdda8733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdda871b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d636cb124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d636cb1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d636c95f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d636945176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d636944e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fdda871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdda871d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdda871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d636944d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c (799 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_bf16m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv32bf16.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv32bf16.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_f16m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv32f16.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv32f16.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_f32m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv16f32.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv16f32.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_f64m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv8f64.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv8f64.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_i8m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_i16m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_i32m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_i64m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_u8m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_u16m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_u32m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_u64m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_f8e4m3m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c (800 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , a # | ... # `---data was truncated (10240/98437) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fd2ee7357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fd2ee70515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fd2ee73cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f67a6649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f67a66a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f67a6649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f67a6631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fd2ee0924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fd2ee09096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fd2ededf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fd2ea9d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fd2ea9ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f67a6632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f67a66330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f67a66330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fd2ea9cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c (801 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c (802 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_i32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_i32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_u32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_u32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32mf2x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret ta # | ... # `---data was truncated (10240/32031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056267a11857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056267a115515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056267a118cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2317449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f23174a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2317449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2317431507 abort ./stdlib/abort.c:85:3 # | #7 0x000056267a0ae24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056267a0ae096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056267a092f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562679d42176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562679d41e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2317432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f23174330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f23174330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562679d41d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c (803 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c (804 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf4_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf2_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m1_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m2_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m4_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv16bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m8_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv32bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv32bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vle.mask.nxv1bf16.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vle.mask.nxv2bf16.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vle.mask.nxv4bf16.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m2_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, # | ... # `---data was truncated (10240/24959) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055918d58d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055918d58a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055918d58dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3e8a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3e8a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3e8a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3e8a231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055918d52324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055918d523096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055918d507f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055918d1b7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055918d1b6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3e8a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3e8a2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3e8a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055918d1b6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c (805 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055699c08757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055699c084515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055699c087cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f46c8905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f46c895c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f46c8905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f46c88ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055699c01d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055699c01d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055699c001f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055699bcb1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055699bcb0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f46c88eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f46c88ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f46c88ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055699bcb0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c (806 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @ # | ... # `---data was truncated (10240/60228) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c3d93f457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c3d93f1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c3d93f4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f96d2105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f96d215c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f96d2105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f96d20ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c3d938a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c3d938a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c3d936ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c3d901e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c3d901de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f96d20eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f96d20ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f96d20ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c3d901dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c (807 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv1i16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv2i16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv4i16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv8i16.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv16i16.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv32i16.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv1i32.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv2i32.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv4i32.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv8i32.nxv8i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: n # | ... # `---data was truncated (10240/66036) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d788b0f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d788b0c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d788b0fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f214c105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f214c15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f214c105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f214c0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d788aa524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d788aa5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d788a89f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d788739176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d788738e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f214c0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f214c0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f214c0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d788738d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c (808 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m4( %vd, %vs1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c (809 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16mf4x8(ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16mf2x8(ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16m1x8(ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16m1x8_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557eada0657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557eada03515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557eada06cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6d75849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6d758a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6d75849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6d75831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557ead99c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557ead99c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557ead980f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557ead630176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557ead62fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6d75832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6d758330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6d758330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557ead62fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c (810 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf8( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf4( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf2( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8m1( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8m2( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca # | ... # `---data was truncated (10240/97514) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055695590257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005569558ff515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556955902cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f764bc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f764bca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f764bc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f764bc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055695589824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556955898096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055695587cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055695552c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055695552be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f764bc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f764bc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f764bc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055695552bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c (811 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, a # | ... # `---data was truncated (10240/424843) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055976ae5257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055976ae4f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055976ae52cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb1c3249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb1c32a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb1c3249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb1c3231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055976ade824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055976ade8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055976adccf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055976aa7c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055976aa7be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb1c3232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb1c32330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb1c32330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055976aa7bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c (812 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c (813 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.prf.nxv8i1.p0(, ptr, i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_1( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_2( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_3( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_4( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_5( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_6( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 8) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_7( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 9) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 10) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_9( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 11) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_10( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 12) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_11( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 13) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_vnum( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %3, ptr %4, i32 0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_gather_u32base( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prfh.gather.scalar.offset.nxv4i32( %2, %1, i64 0, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) # | declare void @llvm.aarch64.sve.prfh.gather.scalar.offset.nxv4i32(, , i64, i32 immarg) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_gather_u64base( %pg, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c (814 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_bf16_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fmla.nxv8bf16( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmla.nxv8bf16(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_bf16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fmla.nxv8bf16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_bf16_x( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fmla.u.nxv8bf16( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmla.u.nxv8bf16(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_n_bf16_m( %pg, %op1, %op2, bfloat noundef %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store bfloat %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load bfloat, ptr %op3.addr, align 2 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %3, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmla.nxv8bf16( %4, %1, %2, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_n_bf16_z( %pg, %op1, %op2, bfloat noundef %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store bfloat %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load bfloat, ptr %op3.addr, align 2 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %3, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fmla.nxv8bf16( %4, %5, %2, %.splat) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_n_bf16_x( %pg, %op1, %op2, bfloat noundef %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store bfloat %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load bfloat, ptr %op3.addr, align 2 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %3, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmla.u.nxv8bf16( %4, %1, %2, %.splat) # | ret %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000563774c7557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563774c72515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563774c75cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe1cd049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe1cd0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe1cd049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe1cd031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563774c0b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563774c0b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563774beff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056377489f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056377489ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe1cd032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe1cd0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe1cd0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056377489ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c (815 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m4_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c (816 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16mf4_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv1f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16mf2_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv2f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m1_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv4f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv4f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m2_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv8f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv8f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m4_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv16f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv16f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m8_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv32f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv32f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32mf2_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv1f32.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32m1_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv2f32.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32m2_tu( %maskedoff, %src, i64 noundef %offset, i64 no # | ... # `---data was truncated (10240/287205) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f33dcff57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f33dcfc515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f33dcffcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f87b0c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f87b0ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f87b0c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f87b0c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f33dc9524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f33dc95096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f33dc79f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f33d929176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f33d928e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f87b0c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f87b0c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f87b0c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f33d928d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c (817 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_bf16mf4_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_bf16mf4_f32mf2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_bf16mf4_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_bf16_f32mf2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_bf16mf2_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_bf16mf2_f32m1_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_bf16mf2_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_bf16_f32m1_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c (818 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16mf4( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16mf2( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m1( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m2( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m4( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m8( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32mf2( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64( %0, i16 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(, i16, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32m1( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64( %0, i16 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(, i16, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32m2( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.addr, align # | ... # `---data was truncated (10240/39226) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eed74f057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055eed74ed515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055eed74f0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbb07733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbb0778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbb07733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbb0771b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eed748624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055eed7486096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055eed746af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055eed711a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055eed7119e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbb0771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbb0771d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbb0771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eed7119d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c (819 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005607eeb6c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005607eeb69515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005607eeb6ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff4f8c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff4f8ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff4f8c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff4f8c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005607eeb0224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005607eeb02096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005607eeae6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005607ee796176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005607ee795e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff4f8c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff4f8c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff4f8c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005607ee795d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c (820 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64( %0, %1, bfloat %2, # | ... # `---data was truncated (10240/65194) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560433f1b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560433f18515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560433f1bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f753441bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f75344725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f753441ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7534403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560433eb124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560433eb1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560433e95f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560433b45176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560433b44e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7534404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f75344050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f75344050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560433b44d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c (821 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv16i8.nxv16i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c (822 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c (823 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f32.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f32.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16f32.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f32.p0.nxv16i32.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c (824 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_i32mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_i32m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_u32mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_u32m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32mf2x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: # | ... # `---data was truncated (10240/16382) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005586e1b0557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005586e1b02515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005586e1b05cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc885b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc885b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc885b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc885b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005586e1a9b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005586e1a9b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005586e1a7ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005586e172f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005586e172ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc885b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc885b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc885b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005586e172ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c (825 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m4_bf16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.r # | ... # `---data was truncated (10240/53678) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056328e65c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056328e659515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056328e65ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5711649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f57116a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5711649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5711631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056328e5f224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056328e5f2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056328e5d6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056328e286176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056328e285e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5711632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f57116330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f57116330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056328e285d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c (826 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f1d8fdc57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f1d8fd9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f1d8fdccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4238933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f423898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4238933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f423891b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f1d8f7224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f1d8f72096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f1d8f56f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f1d8c06176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f1d8c05e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f423891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f423891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f423891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f1d8c05d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c (827 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpnext_b8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.pnext.nxv16i1( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pnext.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpnext_b16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.pnext.nxv8i1( %2, %3) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pnext.nxv8i1(, ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpnext_b32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.pnext.nxv4i1( %2, %3) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pnext.nxv4i1(, ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpnext_b64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.pnext.nxv2i1( %2, %3) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pnext.nxv2i1(, ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055b3bb78057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b3bb77d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b3bb780cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe2ea249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe2ea2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe2ea249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe2ea231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b3bb71624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b3bb716096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b3bb6faf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b3bb3aa176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b3bb3a9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe2ea232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe2ea2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe2ea2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b3bb3a9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c (828 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m4( %vd, %vs1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c (829 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrdffr() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.rdffr() # | ret %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.rdffr() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrdffr_z( %pg) #0 { # | entry: # | %pg.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = call @llvm.aarch64.sve.rdffr.z( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.rdffr.z() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x000055e6fb71357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e6fb710515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e6fb713cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe51fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe51fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe51fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe51fc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e6fb6a924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e6fb6a9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e6fb68df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e6fb33d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e6fb33ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe51fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe51fc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe51fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e6fb33cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c (830 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf8x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf4x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf2x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf8x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf4x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf2x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf8x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf4x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = c # | ... # `---data was truncated (10240/16451) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005652ded1457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005652ded11515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005652ded14cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7072449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f70724a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7072449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7072431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005652decaa24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005652decaa096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005652dec8ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005652de93e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005652de93de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7072432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f70724330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f70724330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005652de93dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c (831 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_u8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq2.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_u16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq2.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_u32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq2.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_u64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq2.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_s8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_s16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_s32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_s64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_f16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq2.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_f32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq2.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_f64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq2.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_bf16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq2.nxv8bf16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_mf8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv16i8( %0, %1) # | ret % # | ... # `---data was truncated (10240/10910) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055d5b8a2957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d5b8a26515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d5b8a29cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8dd3449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8dd34a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8dd3449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8dd3431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d5b89bf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d5b89bf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d5b89a3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d5b8653176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d5b8652e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8dd3432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8dd34330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8dd34330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d5b8652d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c (832 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_i8mf4x7(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ad97e3657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ad97e33515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ad97e36cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4e1c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4e1c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4e1c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4e1c91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ad97dcc24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ad97dcc096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ad97db0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ad97a60176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ad97a5fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4e1c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4e1c91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4e1c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ad97a5fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c (833 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p2 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p2 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrint32x_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.frint32x.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frint32x.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrint32x_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.frint32x.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frint32x.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrint32x_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frint32x.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrint32x_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frint32x.nxv2f64( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrint32x_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frint32x.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrint32x_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frint32x.nxv2f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrint32z_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.frint32z.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frint32z.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrint32z_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.frint32z.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frint32z.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrint32z_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frint32z.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrint32z_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frint32z.nxv2f64( undef, %2, %1) # | # | ... # `---data was truncated (10240/23662) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005634b73a457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005634b73a1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005634b73a4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbbffd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbbffd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbbffd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbbffd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005634b733a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005634b733a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005634b731ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005634b6fce176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005634b6fcde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbbffd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbbffd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbbffd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005634b6fcdd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c (834 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_i8mf4x7(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563fadf4357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563fadf40515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563fadf43cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff092e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff092ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff092e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff092e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563faded924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563faded9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563fadebdf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563fadb6d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563fadb6ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff092e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff092e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff092e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563fadb6cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c (835 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv1i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv2i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv4i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv8i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv16i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv32i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv64i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv1i16.i16.i64( poison, %0, i16 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv2i16.i16.i64( poison, %0, i16 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv4i16.i16.i64( poison, %0, i16 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv8i16.i16.i64( poison, %0, i16 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv16i16.i16.i64( poison, %0, i16 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv16i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c (836 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b8_s32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilele.nxv16i1.i32(i32 %0, i32 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilele.nxv16i1.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b16_s32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilele.nxv8i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilele.nxv8i1.i32(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b32_s32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilele.nxv4i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilele.nxv4i1.i32(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b64_s32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilele.nxv2i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilele.nxv2i1.i32(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b8_u32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilels.nxv16i1.i32(i32 %0, i32 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilels.nxv16i1.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b16_u32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilels.nxv8i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilels.nxv8i1.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b32_u32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilels.nxv4i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilels.nxv4i1.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b64_u32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilels.nxv2i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilels.nxv2i1.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b8_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.whilele.nxv16i1.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilele.nxv16i1.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b16_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.whilele.nxv8i1.i64(i64 %0, i64 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilele.nxv8i1.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b32_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.whilele.nxv4i1.i64(i64 %0, i64 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilele.nxv4i1.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b64_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.whilele.nxv2i1.i64(i64 %0, i64 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilele.nxv2i1.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b8_u64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | % # | ... # `---data was truncated (10240/13340) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000555f9fa8657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555f9fa83515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555f9fa86cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7499f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7499f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7499f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7499eed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555f9fa1c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555f9fa1c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555f9fa00f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555f9f6b0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555f9f6afe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7499eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7499eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7499eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555f9f6afd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c (837 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinta_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frinta.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frinta.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinta_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frinta.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frinta.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinta_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frinta.nxv2f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frinta.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinta_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.frinta.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinta_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.frinta.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinta_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.frinta.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinta_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frinta.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinta_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frinta.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinta_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frinta.nxv2f64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055b82779257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b82778f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b827792cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f16a2133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f16a218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f16a2133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f16a211b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b82772824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b827728096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b82770cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b8273bc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b8273bbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f16a211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f16a211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f16a211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b8273bbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c (838 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, pt # | ... # `---data was truncated (10240/66557) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005599e30bd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005599e30ba515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005599e30bdcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f43a5e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f43a5ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f43a5e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f43a5e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005599e305324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005599e3053096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005599e3037f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005599e2ce7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005599e2ce6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f43a5e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f43a5e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f43a5e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005599e2ce6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c (839 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m8_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = a # | ... # `---data was truncated (10240/288050) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a790b9e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a790b9b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a790b9ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcc67933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcc6798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcc67933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcc6791b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a790b3424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a790b34096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a790b18f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a7907c8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a7907c7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcc6791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcc6791d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcc6791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a7907c7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c (840 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextw_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.sxtw.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sxtw.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextw_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.uxtw.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uxtw.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextw_s64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.sxtw.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextw_u64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.uxtw.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextw_s64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.sxtw.nxv2i64( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextw_u64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.uxtw.nxv2i64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000563dc09fb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563dc09f8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563dc09fbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7fba933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7fba98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7fba933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7fba91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563dc099124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563dc0991096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563dc0975f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563dc0625176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563dc0624e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7fba91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7fba91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7fba91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563dc0624d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c (841 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_i8mf4x5(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a93581757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a935814515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a935817cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd9c7f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd9c7f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd9c7f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd9c7eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a9357ad24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a9357ad096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a935791f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a935441176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a935440e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd9c7eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd9c7eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd9c7eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a935440d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c (842 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv # | ... # `---data was truncated (10240/20082) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562e3338757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562e33384515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562e33387cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8663449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f86634a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8663449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8663431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562e3331d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562e3331d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562e33301f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562e32fb1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562e32fb0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8663432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f86634330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f86634330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562e32fb0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c (843 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_i32mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_i32m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_u32mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_u32m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_i32mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_i32m1x5_m( %mask, ptr noundef % # | ... # `---data was truncated (10240/14001) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556347b7f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556347b7c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556347b7fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9433249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f94332a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9433249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9433231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556347b1524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556347b15096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556347af9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005563477a9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005563477a8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9433232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f94332330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f94332330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005563477a8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c (844 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_bf16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fscale.nxv8bf16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fscale.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_bf16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fscale.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_bf16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fscale.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_n_bf16_z( %pg, %op1, i16 noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i16, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store i16 %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load i16, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, i16 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fscale.nxv8bf16( %3, %4, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_n_bf16_m( %pg, %op1, i16 noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i16, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store i16 %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load i16, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, i16 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fscale.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_n_bf16_x( %pg, %op1, i16 noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i16, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store i16 %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load i16, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, i16 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fscale.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-bfscale" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000556b4032557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556b40322515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556b40325cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb2dd933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb2dd98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb2dd933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb2dd91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556b402bb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556b402bb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556b4029ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556b3ff4f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556b3ff4ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb2dd91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb2dd91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb2dd91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556b3ff4ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c (845 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_i32mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_i32m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_u32mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_u32m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557c3646857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557c36465515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557c36468cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0959649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f09596a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0959649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0959631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557c363fe24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557c363fe096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557c363e2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557c36092176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557c36091e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0959632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f09596330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f09596330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557c36091d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve/recpe.c (846 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve/recpe.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpe_f16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.frecpe.x.nxv8f16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frecpe.x.nxv8f16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpe_f32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.frecpe.x.nxv4f32( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frecpe.x.nxv4f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpe_f64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.frecpe.x.nxv2f64( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frecpe.x.nxv2f64() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x0000557ae2a8e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557ae2a8b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557ae2a8ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0eede49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0eedea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0eede49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0eede31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557ae2a2424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557ae2a24096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557ae2a08f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557ae26b8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557ae26b7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0eede32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0eede330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0eede330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557ae26b7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c (847 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c (848 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16mf4_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m4_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m8_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f32mf2_f64m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f32m1_f64m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, ali # | ... # `---data was truncated (10240/60334) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558b2113c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558b21139515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558b2113ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1f1ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1f1cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1f1ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1f1ce31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558b210d224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558b210d2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558b210b6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558b20d66176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558b20d65e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1f1ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1f1ce330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1f1ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558b20d65d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c (849 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m8_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function A # | ... # `---data was truncated (10240/30415) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005635b5ff057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005635b5fed515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005635b5ff0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1832b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1832b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1832b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1832b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005635b5f8624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005635b5f86096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005635b5f6af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005635b5c1a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005635b5c19e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1832b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1832b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1832b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005635b5c19d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c (850 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf8x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf8x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf8x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %m # | ... # `---data was truncated (10240/22258) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ac428f157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ac428ee515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ac428f1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fed7d905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fed7d95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fed7d905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fed7d8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ac4288724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ac42887096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ac4286bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ac4251b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ac4251ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fed7d8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fed7d8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fed7d8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ac4251ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c (851 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captu # | ... # `---data was truncated (10240/87308) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a44e1e757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a44e1e4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a44e1e7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd8bae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd8baea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd8bae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd8bae31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a44e17d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a44e17d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a44e161f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a44de11176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a44de10e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd8bae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd8bae330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd8bae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a44de10d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c (852 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv32i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv32i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vx_u8m4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %o # | ... # `---data was truncated (10240/65883) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056239451b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562394518515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056239451bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f22d7249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f22d72a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f22d7249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f22d7231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005623944b124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005623944b1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562394495f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562394145176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562394144e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f22d7232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f22d72330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f22d72330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562394144d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c (853 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svunpk_s16_x2( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sve.sunpk.x2.nxv8i16( %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sunpk.x2.nxv8i16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svunpk_u16_x2( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sve.uunpk.x2.nxv8i16( %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.uunpk.x2.nxv8i16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svunpk_s32_x2( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sve.sunpk.x2.nxv4i32( %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sunpk.x2.nxv4i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svunpk_u32_x2( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sve.uunpk.x2.nxv4i32( %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.uunpk.x2.nxv4i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svunpk_s64_x2( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sve.sunpk.x2.nxv2i64( %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sunpk.x2.nxv2i64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svunpk_u64_x2( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sve.uunpk.x2.nxv2i64( %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.uunpk.x2.nxv2i64() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055ebb022957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ebb0226515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ebb0229cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efc5ad05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efc5ad5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efc5ad05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efc5aced507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ebb01bf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ebb01bf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ebb01a3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ebafe53176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ebafe52e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efc5aceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efc5acef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efc5acef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ebafe52d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c (854 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32mf2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m1_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.add # | ... # `---data was truncated (10240/14453) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005555d366357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005555d3660515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005555d3663cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd74a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd74a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd74a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd74a431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005555d35f924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005555d35f9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005555d35ddf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005555d328d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005555d328ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd74a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd74a4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd74a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005555d328cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c (855 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a77714957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a777146515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a777149cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7076049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f70760a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7076049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7076031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a7770df24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a7770df096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a7770c3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a776d73176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a776d72e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7076032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f70760330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f70760330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a776d72d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c (856 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32mf2x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_i32mf2x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_i32m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_u32mf2x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_u32m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557c7d0d157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557c7d0ce515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557c7d0d1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4638133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f463818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4638133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f463811b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557c7d06724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557c7d067096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557c7d04bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557c7ccfb176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557c7ccfae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f463811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f463811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f463811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557c7ccfad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c (857 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f64m1x4(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c (858 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16m2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i6 # | ... # `---data was truncated (10240/151253) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d9831a357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d9831a0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d9831a3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8913849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f89138a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8913849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8913831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d98313924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d983139096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d98311df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d982dcd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d982dcce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8913832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f89138330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f89138330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d982dccd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c (859 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/97913) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005597a50db57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005597a50d8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005597a50dbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8d6fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8d6fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8d6fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8d6fc31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005597a507124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005597a5071096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005597a5055f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005597a4d05176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005597a4d04e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8d6fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8d6fc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8d6fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005597a4d04d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c (860 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1b_s16( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv8i8.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv8i8.p0(, , ptr captures(none)) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1b_s32( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv4i8.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv4i8.p0(, , ptr captures(none)) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1b_s64( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv2i8.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv2i8.p0(, , ptr captures(none)) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1b_u16( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv8i8.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1b_u32( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv4i8.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1b_u64( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv2i8.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1b_vnum_s16( %pg, ptr noundef %base, i64 noundef %vnum, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = getelementptr , ptr %1, i64 %2 # | %6 = trunc %3 to # | call void @llvm.aarch64.sve.st1.nxv8i8.p0( %6, %4, ptr %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1b_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = getelementptr , ptr %1, i64 %2 # | %6 = trunc %3 to # | call void @llvm.aarch64.sve.st1.nxv4i8.p0( %6, %4, ptr %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1b_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = getelementptr , ptr %1, i64 %2 # | %6 = trunc %3 to # | call void @llvm.aarch64.sve.st1.nxv2i8.p0( %6, %4, ptr %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1b_vnum_u16( %pg, ptr noundef %base, i64 noundef %vnum, %data) #0 { # | e # | ... # `---data was truncated (10240/32866) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x0000564ef9fab57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564ef9fa8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564ef9fabcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f01ff733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f01ff78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f01ff733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f01ff71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564ef9f4124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564ef9f41096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564ef9f25f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564ef9bd5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564ef9bd4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f01ff71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f01ff71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f01ff71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564ef9bd4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c (861 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple # | ... # `---data was truncated (10240/96919) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563377f1357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563377f10515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563377f13cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fed35d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fed35d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fed35d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fed35d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563377ea924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563377ea9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563377e8df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563377b3d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563377b3ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fed35d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fed35d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fed35d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563377b3cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c (862 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vx_u16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wv_u16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wx_u16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.w.nxv1i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vx_u16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wv_u16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wx_u16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.w.nxv2i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/306627) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bf31f1657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bf31f13515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bf31f16cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9233449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f92334a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9233449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9233431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bf31eac24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bf31eac096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bf31e90f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bf31b40176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bf31b3fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9233432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f92334330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f92334330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bf31b3fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c (863 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmla_f16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fcmla.nxv8f16( %4, %5, %2, %3, i32 0) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcmla.nxv8f16(, , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmla_f16_z_1( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fcmla.nxv8f16( %4, %5, %2, %3, i32 90) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmla_f16_z_2( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fcmla.nxv8f16( %4, %5, %2, %3, i32 180) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmla_f16_z_3( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fcmla.nxv8f16( %4, %5, %2, %3, i32 270) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmla_f32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fcmla.nxv4f32( %4, %5, %2, %3, i32 0) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcmla.nxv4f32(, , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmla_f64_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fcmla.nxv2f64( %4, %5, %2, %3, i32 90) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcmla.nxv2f64(, , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmla_f16_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c (864 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_bf16_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.fcvt.bf16f32.v2( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcvt.bf16f32.v2(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_bf16_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.fcvt.bf16f32.v2( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_bf16_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.fcvt.bf16f32.v2( %0, %3, %2) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055752dc0857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055752dc05515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055752dc08cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe9ad249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe9ad2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe9ad249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe9ad231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055752db9e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055752db9e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055752db82f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055752d832176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055752d831e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe9ad232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe9ad2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe9ad2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055752d831d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c (865 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.revh.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.revh.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.revh.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.revh.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_u32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.revh.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.revh.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.revh.nxv4i32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_s64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.revh.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_u32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.revh.nxv4i32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_u64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.revh.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_s32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.revh.nxv4i32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_s64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.revh.nxv2i64( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_u32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.revh.nxv4i32( undef, %2, %1) # | # | ... # `---data was truncated (10240/11488) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000564962ba957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564962ba6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564962ba9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8b4641bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8b464725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8b4641ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8b46403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564962b3f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564962b3f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564962b23f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005649627d3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005649627d2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8b46404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8b464050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8b464050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005649627d2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c (866 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16mf4_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16mf2_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m1_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m2_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m4_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv16f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv16f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m8_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv32f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv32f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32mf2_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load float, ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv1f32.f32.i64( %0, %1, float %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32m1_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load float, ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv2f32.f32.i64( %0, %1, float %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32m2_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/78328) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a4e11bc57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a4e11b9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a4e11bccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f770ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f770ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f770ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f770ad1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a4e115224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a4e1152096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a4e1136f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a4e0de6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a4e0de5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f770ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f770ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f770ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a4e0de5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c (867 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu # | ... # `---data was truncated (10240/156765) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056394304a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563943047515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056394304acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1ce6d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1ce6d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1ce6d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1ce6d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563942fe024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563942fe0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563942fc4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563942c74176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563942c73e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1ce6d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1ce6d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1ce6d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563942c73d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c (868 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(, , , i64, i64 # | ... # `---data was truncated (10240/27063) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cfa453f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cfa453c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cfa453fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe91ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe91eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe91ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe91ea31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cfa44d524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cfa44d5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cfa44b9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cfa4169176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cfa4168e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe91ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe91ea330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe91ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cfa4168d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c (869 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | ... # `---data was truncated (10240/40669) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e5cf57957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e5cf576515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e5cf579cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdd6f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdd6f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdd6f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdd6f231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e5cf50f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e5cf50f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e5cf4f3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e5cf1a3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e5cf1a2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fdd6f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdd6f2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdd6f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e5cf1a2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c (870 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_s_u_w4_i8m8_u8m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.s.u.i64.nxv64i8.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.s.u.i64.nxv64i8.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a622aef57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a622aec515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a622aefcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5c3c505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5c3c55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5c3c505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5c3c4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a622a8524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a622a85096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a622a69f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a622719176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a622718e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5c3c4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5c3c4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5c3c4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a622718d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c (871 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zkne -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c -check-prefix=RV32ZKNE # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zkne -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @aes32esi(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | %2 = call i32 @llvm.riscv.aes32esi(i32 %0, i32 %1, i32 3) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.aes32esi(i32, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @aes32esmi(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | %2 = call i32 @llvm.riscv.aes32esmi(i32 %0, i32 %1, i32 3) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.aes32esmi(i32, i32, i32 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zkne" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_zkne1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c9a7af757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c9a7af4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c9a7af7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0c63c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0c63ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0c63c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0c63c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c9a7a8d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c9a7a8d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c9a7a71f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c9a7721176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c9a7720e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0c63c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0c63c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0c63c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c9a7720d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c -check-prefix=RV32ZKNE # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c -check-prefix=RV32ZKNE # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c (872 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, p # | ... # `---data was truncated (10240/14521) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055924452157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055924451e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559244521cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4d95b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4d95b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4d95b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4d95b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005592444b724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005592444b7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055924449bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055924414b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055924414ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4d95b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4d95b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4d95b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055924414ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c (873 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf8( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf8( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv1i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf4( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf4( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv2i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf2( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf2( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv4i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8m1( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8m1( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv8i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv8i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8m2( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.ad # | ... # `---data was truncated (10240/98581) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005587e3eb257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005587e3eaf515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005587e3eb2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f43e8d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f43e8d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f43e8d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f43e8ced507 abort ./stdlib/abort.c:85:3 # | #7 0x00005587e3e4824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005587e3e48096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005587e3e2cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005587e3adc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005587e3adbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f43e8ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f43e8cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f43e8cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005587e3adbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c (874 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8 # | ... # `---data was truncated (10240/96911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561413c1657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561413c13515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561413c16cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f462de1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f462de725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f462de1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f462de03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561413bac24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561413bac096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561413b90f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561413840176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056141383fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f462de04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f462de050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f462de050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056141383fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c (875 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_f32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_f32m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_f32m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_f32m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_i32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_i32m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_i32m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_i32m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_u32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, # | ... # `---data was truncated (10240/30874) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055576830b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555768308515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055576830bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd6e9849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd6e98a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd6e9849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd6e9831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005557682a124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005557682a1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555768285f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555767f35176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555767f34e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd6e9832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd6e98330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd6e98330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555767f34d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c (876 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_s8( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbl.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_s16( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbl.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_s32( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbl.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_s64( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbl.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_u8( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_u16( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_u32( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_u64( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_f16( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbl.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_f32( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbl.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_f64( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbl.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_bf16( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbl.nxv8bf16(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptra # | ... # `---data was truncated (10240/10361) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000556da511257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556da510f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556da5112cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f28bc133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f28bc18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f28bc133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f28bc11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556da50a824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556da50a8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556da508cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556da4d3c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556da4d3be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f28bc11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f28bc11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f28bc11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556da4d3bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c (877 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv16f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv16f16.f16.i64( poison, %0, half %1, i # | ... # `---data was truncated (10240/125641) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a35ba1c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a35ba19515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a35ba1ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6229649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f62296a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6229649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6229631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a35b9b224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a35b9b2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a35b996f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a35b646176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a35b645e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6229632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f62296330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f62296330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a35b645d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c (878 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8mf8(i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i8, ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.x.nxv1i8.i64( poison, i8 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv1i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8mf4(i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i8, ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.x.nxv2i8.i64( poison, i8 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv2i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8mf2(i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i8, ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.x.nxv4i8.i64( poison, i8 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv4i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8m1(i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i8, ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.x.nxv8i8.i64( poison, i8 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv8i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8m2(i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i8, ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.x.nxv16i8.i64( poison, i8 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv16i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8m4(i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i8, ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.x.nxv32i8.i64( poison, i8 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv32i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8m8(i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i8, ptr %src.addr, align 1 # | %1 = load # | ... # `---data was truncated (10240/121927) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561fef36a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561fef367515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561fef36acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5553533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f555358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5553533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f555351b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561fef30024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561fef300096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561fef2e4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561feef94176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561feef93e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f555351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f555351d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f555351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561feef93d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c (879 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf8_b64( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf4_b32( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf2_b16( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8m1_b8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8m2_b4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv32i8.n # | ... # `---data was truncated (10240/95347) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d2699a657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d2699a3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d2699a6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8705849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f87058a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8705849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8705831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d26993c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d26993c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d269920f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d2695d0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d2695cfe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8705832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f87058330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f87058330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d2695cfd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c (880 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m4( %vd, %vs1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c (881 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16m2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c (882 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055879d55a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055879d557515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055879d55acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f510e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f510e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f510e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f510e31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055879d4f024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055879d4f0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055879d4d4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055879d184176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055879d183e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f510e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f510e31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f510e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055879d183d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c (883 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64( %1, ptr %2, %3, %0, i64 %4, i # | ... # `---data was truncated (10240/25624) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056105351557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561053512515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561053515cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3cd9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3cd9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3cd9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3cd9f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005610534ab24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005610534ab096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056105348ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056105313f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056105313ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3cd9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3cd9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3cd9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056105313ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c (884 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vaeskf1.nxv1i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv1i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vaeskf1.nxv2i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv2i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vaeskf1.nxv4i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv4i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vaeskf1.nxv8i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv8i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vaeskf1.nxv16i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv16i32.i64.i64(, , i64 immarg, i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e18cf2357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e18cf20515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e18cf23cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0296533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f029658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0296533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f029651b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e18ceb924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e18ceb9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e18ce9df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e18cb4d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e18cb4ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f029651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f029651d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f029651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e18cb4cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmaxq.c (885 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmaxq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = icmp sge <16 x i8> %0, %1 # | %3 = select <16 x i1> %2, <16 x i8> %0, <16 x i8> %1 # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = icmp uge <8 x i16> %0, %1 # | %3 = select <8 x i1> %2, <8 x i16> %0, <8 x i16> %1 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = icmp sge <4 x i32> %0, %1 # | %3 = select <4 x i1> %2, <4 x i32> %0, <4 x i32> %1 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxq_m_u8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.max.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.max.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.max.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.max.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxq_m_u32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.max.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.max.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxq_x_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055814684f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055814684c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055814684fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbd86133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbd8618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbd86133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbd8611b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005581467e524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005581467e5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005581467c9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558146479176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558146478e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbd8611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbd8611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbd8611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558146478d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c (886 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16mf4_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16mf4_f32mf2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16mf2_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16mf2_f32m1_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16m1_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16m1_f32m2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16m2_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16m2_f32m4_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c (887 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv64i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv32i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv16i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv8i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv4i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv2i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv1i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056355f7d457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056355f7d1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056355f7d4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3952e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3952e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3952e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3952e03507 abort ./stdlib/abort.c:85:3 # | #7 0x000056355f76a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056355f76a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056355f74ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056355f3fe176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056355f3fde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3952e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3952e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3952e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056355f3fdd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c (888 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32mf2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b96f19f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b96f19c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b96f19fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f42b0705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f42b075c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f42b0705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f42b06ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b96f13524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b96f135096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b96f119f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b96edc9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b96edc8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f42b06eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f42b06ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f42b06ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b96edc8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c (889 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/neon-vcombine.c (890 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon-vcombine.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vcombine_s8(<8 x i8> noundef %low, <8 x i8> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <16 x i8>, align 16 # | %low.addr = alloca <8 x i8>, align 8 # | %high.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %low, ptr %low.addr, align 8 # | store <8 x i8> %high, ptr %high.addr, align 8 # | %0 = load <8 x i8>, ptr %low.addr, align 8 # | %1 = load <8 x i8>, ptr %high.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <8 x i8> %2, <8 x i8> %3, <16 x i32> # | store <16 x i8> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcombine_s16(<4 x i16> noundef %low, <4 x i16> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <8 x i16>, align 16 # | %low.addr = alloca <4 x i16>, align 8 # | %high.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %low, ptr %low.addr, align 8 # | store <4 x i16> %high, ptr %high.addr, align 8 # | %0 = load <4 x i16>, ptr %low.addr, align 8 # | %1 = load <4 x i16>, ptr %high.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <4 x i16> %2, <4 x i16> %3, <8 x i32> # | store <8 x i16> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vcombine_s32(<2 x i32> noundef %low, <2 x i32> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <4 x i32>, align 16 # | %low.addr = alloca <2 x i32>, align 8 # | %high.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %low, ptr %low.addr, align 8 # | store <2 x i32> %high, ptr %high.addr, align 8 # | %0 = load <2 x i32>, ptr %low.addr, align 8 # | %1 = load <2 x i32>, ptr %high.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <2 x i32> %2, <2 x i32> %3, <4 x i32> # | store <4 x i32> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vcombine_s64(<1 x i64> noundef %low, <1 x i64> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <2 x i64>, align 16 # | %low.addr = alloca <1 x i64>, align 8 # | %high.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %low, ptr %low.addr, align 8 # | store <1 x i64> %high, ptr %high.addr, align 8 # | %0 = load <1 x i64>, ptr %low.addr, align 8 # | %1 = load <1 x i64>, ptr %high.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <1 x i64>, ptr %__p0.addr.i, align 8 # | %3 = load <1 x i64>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <1 x i64> %2, <1 x i64> %3, <2 x i32> # | store <2 x i64> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vcombine_u8(<8 x i8> noundef %low, <8 x i8> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <16 x i8>, align 16 # | %low.addr = alloca <8 x i8>, align 8 # | %high.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %low, ptr %low.addr, align 8 # | store <8 x i8> %high, ptr %high.addr, align 8 # | %0 = load <8 x i8>, ptr %low.addr, align 8 # | %1 = load <8 x i8>, ptr %high.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <8 x i8> %2, <8 x i8> %3, <16 x i32> # | store <16 x i8> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcombine_u16(<4 x i16> noundef %low, <4 x i16> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <8 x i16>, align 16 # | %low.addr = alloca <4 x i16>, align 8 # | %high.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %low, ptr %low.addr, align 8 # | store <4 x i16> %high, ptr %high.addr, align 8 # | %0 = load <4 x i16>, ptr %low.addr, align 8 # | %1 = load <4 x i16>, ptr %high.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <4 x i16> %2, <4 x i16> %3, <8 x i32> # | store <8 x i16> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vcombine_u32(<2 x i32> noundef %low, <2 x i32> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <4 x i32>, align 16 # | %low.addr = alloca <2 x i32>, align 8 # | %high.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %low, ptr %low.addr, align 8 # | store <2 x i32> %high, ptr %high.addr, align 8 # | %0 = load <2 x i32>, ptr %low.addr, align 8 # | %1 = load <2 x i32>, ptr %high.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <2 x i32> %2, <2 x i32> %3, <4 x i32> # | store <4 x i32> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vcombine_u64(<1 x i64> noundef %low, <1 x i64> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <2 x i64>, align 16 # | %low.addr = alloca <1 x i64>, align 8 # | %high.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %low, ptr %low.addr, align 8 # | store <1 x i64> %high, ptr %high.addr, align 8 # | %0 = load <1 x i64>, ptr %low.addr, align 8 # | %1 = load <1 x i64>, ptr %high.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <1 x i64>, ptr %__p0.addr.i, align 8 # | %3 = load <1 x i64>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <1 x i64> %2, <1 x i64> %3, <2 x i32> # | store <2 x i64> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vcombine_p64(<1 x i64> noundef %low, <1 x i64> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <2 x i64>, align 16 # | %low.addr = alloca <1 x i64>, align 8 # | %high.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %low, ptr %low.addr, align 8 # | store <1 x i64> %high, ptr %high.addr, align 8 # | %0 = load <1 x i64>, ptr %low.addr, align 8 # | %1 = load <1 x i64>, ptr %high.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <1 x i64>, ptr %__p0.addr.i, align 8 # | %3 = load <1 x i64>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <1 x i64> %2, <1 x i64> %3, <2 x i32> # | store <2 x i64> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vcombine_f16(<4 x half> noundef %low, <4 x half> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <8 x half>, align 16 # | %low.addr = alloca <4 x half>, align 8 # | %high.addr = alloca <4 x half>, align 8 # | store <4 x half> %low, ptr %low.addr, align 8 # | store <4 x half> %high, ptr %high.addr, align 8 # | %0 = load <4 x half>, ptr %low.addr, align 8 # | %1 = load <4 x half>, ptr %high.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x half>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x half>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <4 x half> %2, <4 x half> %3, <8 x i32> # | store <8 x half> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vcombine_f32(<2 x float> noundef %low, <2 x float> noundef %high) #0 { # | entry: # | %__p0.addr. # | ... # `---data was truncated (10240/14613) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563bf35c557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563bf35c2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563bf35c5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcbf6a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcbf6aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcbf6a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcbf6a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563bf355b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563bf355b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563bf353ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563bf31ef176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563bf31eee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcbf6a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcbf6a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcbf6a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563bf31eed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c (891 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1f32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2f32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4f32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8f32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv16f32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2i32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4i32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8i32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c (892 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv8i8.nxv8i8.i64(, , , , i # | ... # `---data was truncated (10240/116267) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d01c5e857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d01c5e5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d01c5e8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fccac933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fccac98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fccac933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fccac91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d01c57e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d01c57e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d01c562f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d01c212176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d01c211e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fccac91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fccac91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fccac91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d01c211d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c (893 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca # | ... # `---data was truncated (10240/14311) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c0d208257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c0d207f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c0d2082cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f43a7a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f43a7aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f43a7a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f43a7a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c0d201824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c0d2018096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c0d1ffcf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c0d1cac176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c0d1cabe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f43a7a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f43a7a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f43a7a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c0d1cabd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c (894 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv32i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv32i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vx_i8m4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, al # | ... # `---data was truncated (10240/65723) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005632b7f5757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005632b7f54515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005632b7f57cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6add933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6add98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6add933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6add91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005632b7eed24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005632b7eed096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005632b7ed1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005632b7b81176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005632b7b80e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6add91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6add91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6add91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005632b7b80d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c (895 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf8_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf4_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf2_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m1_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m2_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv16i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m4_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv32i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m8_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv64i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16mf4_tu( %maskedoff, %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i16, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv1i16.i16.i64( %0, %1, i16 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16mf2_tu( %maskedoff, %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c (896 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_f16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_f16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_f16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_i16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_i16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_i16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_u16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_u16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_u16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c (897 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_v # | ... # `---data was truncated (10240/228865) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564fbe4f757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564fbe4f4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564fbe4f7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1f58b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1f58b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1f58b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1f58aed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564fbe48d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564fbe48d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564fbe471f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564fbe121176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564fbe120e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1f58aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1f58aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1f58aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564fbe120d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c (898 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_cvt_f16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.fcvt.x2.nxv4f32( %3, %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcvt.x2.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_cvt_bf16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.bfcvt.x2( %3, %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfcvt.x2(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcvt_f32_u32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.ucvtf.x2.nxv4f32.nxv4i32( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.ucvtf.x2.nxv4f32.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcvt_f32_s32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.scvtf.x2.nxv4f32.nxv4i32( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.scvtf.x2.nxv4f32.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcvt_u32_f32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.fcvtzu.x2.nxv4i32.nxv4f32( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fcvtzu.x2.nxv4i32.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcvt_s32_f32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.fcvtzs.x2.nxv4i32.nxv4f32( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fcvtzs.x2.nxv4i32.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svcvt_f32_u32_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, p # | ... # `---data was truncated (10240/39207) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055e74186157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e74185e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e741861cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe8faf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe8faf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe8faf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe8faf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e7417f724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e7417f7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e7417dbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e74148b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e74148ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe8faf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe8faf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe8faf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e74148ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c (899 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf8( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf4( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf2( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8m1( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8m2( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align # | ... # `---data was truncated (10240/97506) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e891ceb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e891ce8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e891cebcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fed5df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fed5df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fed5df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fed5df1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e891c8124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e891c81096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e891c65f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e891915176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e891914e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fed5df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fed5df1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fed5df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e891914d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c (900 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f32m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f64m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f64.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret voi # | ... # `---data was truncated (10240/102304) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005611e931357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005611e9310515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005611e9313cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcdb1249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcdb12a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcdb1249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcdb1231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005611e92a924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005611e92a9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005611e928df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005611e8f3d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005611e8f3ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcdb1232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcdb12330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcdb12330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005611e8f3cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c (901 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf2 # | ... # `---data was truncated (10240/54694) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561b5d3ab57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561b5d3a8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561b5d3abcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9e70905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9e7095c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9e70905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9e708ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561b5d34124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561b5d341096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561b5d325f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561b5cfd5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561b5cfd4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9e708eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9e708ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9e708ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561b5cfd4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c (902 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/97647) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005557e288757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005557e2884515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005557e2887cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f447d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f447d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f447d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f447d31b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005557e281d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005557e281d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005557e2801f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005557e24b1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005557e24b0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f447d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f447d31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f447d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005557e24b0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm64_vcreate.c (903 of 27911) ******************** TEST 'Clang :: CodeGen/arm64_vcreate.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c" # | target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-apple-ios7" # | # | ; Function Attrs: noinline nounwind optnone # | define <2 x float> @test_vcreate_f32(i64 noundef %a1) #0 { # | entry: # | %a1.addr = alloca i64, align 8 # | %__ret = alloca <2 x float>, align 8 # | %__promote = alloca i64, align 8 # | %tmp = alloca <2 x float>, align 8 # | store i64 %a1, ptr %a1.addr, align 8 # | %0 = load i64, ptr %a1.addr, align 8 # | store i64 %0, ptr %__promote, align 8 # | %1 = load <2 x float>, ptr %__promote, align 8 # | store <2 x float> %1, ptr %__ret, align 8 # | %2 = load <2 x float>, ptr %__ret, align 8 # | store <2 x float> %2, ptr %tmp, align 8 # | %3 = load <2 x float>, ptr %tmp, align 8 # | ret <2 x float> %3 # | } # | # | attributes #0 = { noinline nounwind optnone "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c3e9bfe57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c3e9bfb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c3e9bfecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0b4af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0b4af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0b4af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0b4af1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c3e9b9424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c3e9b94096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c3e9b78f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c3e9828176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c3e9827e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0b4af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0b4af1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0b4af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c3e9827d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c (904 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme2 -target-feature +sme -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme2 -target-feature +sme -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_u8_1( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv16i8(i32 0, %0, i32 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite) # | declare void @llvm.aarch64.sme.write.lane.zt.nxv16i8(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_s8_2( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv16i8(i32 0, %0, i32 2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_u16_3( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv8i16(i32 0, %0, i32 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite) # | declare void @llvm.aarch64.sme.write.lane.zt.nxv8i16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_s16_1( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv8i16(i32 0, %0, i32 1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_u32_2( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv4i32(i32 0, %0, i32 2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite) # | declare void @llvm.aarch64.sme.write.lane.zt.nxv4i32(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_s32_3( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv4i32(i32 0, %0, i32 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_u64_0( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv2i64(i32 0, %0, i32 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite) # | declare void @llvm.aarch64.sme.write.lane.zt.nxv2i64(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_s64_1( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv2i64(i32 0, %0, i32 1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_f16_2( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv8f16(i32 0, %0, i32 2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite) # | declare void @llvm.aarch64.sme.write.lane.zt.nxv8f16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_bf16_3( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv8bf16(i32 0, %0, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite) # | declare void @llvm.aarch64.sme.write.lane.zt.nxv8bf16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_f32_0( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv4f32(i32 0, %0, i32 2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite) # | declare void @llvm.aarch64.sme.write.lane.zt.nxv4f32(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_f64_1( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv2f64(i32 0, %0, i32 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite) # | declare void @llvm.aarch64.sme.write.lane.zt.nxv2f64(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_zt_u8( %v) #2 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.zt.nxv16i8(i32 0, %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write) # | declare void @llvm.aarch64.sme.write.zt.nxv16i8(i32 immarg, ) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_zt_s8( %v) #2 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.zt.nxv16i8(i32 0, %0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_zt_u16( %v) #2 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.zt.nxv8i16(i32 0, %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write) # | declare void @llvm.aarch64.sme.write.zt.nxv8i16(i32 immarg, ) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_zt_s16( %v) #2 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.zt.nxv8i16(i32 0, %0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_zt_u32( %v) #2 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.zt.nxv4i32(i32 0, %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write) # | declare void @llvm.aarch64.sme.write.zt.nxv4i32(i32 immarg, ) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_zt_s32( %v) #2 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.zt.nxv4i32(i32 0, %0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_zt_u64( %v) #2 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.zt.nxv2i64(i32 0, %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write) # | declare void @llvm.aarch64.sme.write.zt.nxv2i64(i32 immarg, ) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_zt_s64( %v) #2 { # | entry: # | % # | ... # `---data was truncated (10240/13584) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000557e628f057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557e628ed515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557e628f0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff195b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff195b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff195b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff195b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557e6288624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557e62886096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557e6286af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557e6251a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557e62519e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff195b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff195b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff195b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557e62519d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c (905 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c (906 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv1f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv2f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv4f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv8f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m8_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+xsfvfexpa,+xsfvfexpa64e,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfvfexpa0p2_xsfvfexpa64e0p2"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005650b465a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005650b4657515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005650b465acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdbb8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdbb818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdbb8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdbb811b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005650b45f024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005650b45f0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005650b45d4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005650b4284176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005650b4283e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fdbb811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdbb811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdbb811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005650b4283d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c (907 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16mf4x2(ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16mf2x2(ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16m1x2(ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16m2x2(ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16m4x2(ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16m1x2_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16m2x2_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/13255) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dbd2df557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055dbd2df2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055dbd2df5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feeeef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feeeef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feeeef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feeeef1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dbd2d8b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055dbd2d8b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055dbd2d6ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055dbd2a1f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055dbd2a1ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007feeeef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feeeef1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feeeef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dbd2a1ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c (908 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op # | ... # `---data was truncated (10240/222917) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c36970957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c369706515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c369709cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe3d0933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe3d098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe3d0933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe3d091b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c36969f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c36969f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c369683f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c369333176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c369332e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe3d091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe3d091d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe3d091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c369332d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c (909 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_i16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = e # | ... # `---data was truncated (10240/100513) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ca5b8d857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ca5b8d5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ca5b8d8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff335a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff335aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff335a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff335a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ca5b86e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ca5b86e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ca5b852f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ca5b502176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ca5b501e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff335a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff335a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff335a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ca5b501d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c (910 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf4_f16mf2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv2f16.nxv1f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2f16.nxv1f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf4_f16m1( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv4f16.nxv1f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4f16.nxv1f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf4_f16m2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8f16.nxv1f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f16.nxv1f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf4_f16m4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16f16.nxv1f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv1f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf4_f16m8( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32f16.nxv1f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv1f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf2_f16m1( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv4f16.nxv2f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4f16.nxv2f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf2_f16m2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8f16.nxv2f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f16.nxv2f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf2_f16m4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16f16.nxv2f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv2f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf2_f16m8( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32f16.nxv2f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv2f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16m1_f16m2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8f16.nxv4f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16m1_f16m4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16f16.nxv4f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16m1_f16m8( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32f16.nxv4f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16m2_f16m4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16f16.nxv8f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv8f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16m2_f16m8( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32f16.nxv8f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv8f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | ... # `---data was truncated (10240/83080) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fc1f15557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fc1f152515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fc1f155cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb9b6333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb9b638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb9b6333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb9b631b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fc1f0eb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fc1f0eb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fc1f0cff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fc1ed7f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fc1ed7ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb9b631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb9b631d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb9b631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fc1ed7ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c (911 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3e # | ... # `---data was truncated (10240/216250) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ea0ce6c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ea0ce69515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ea0ce6ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f367381bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f36738725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f367381ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3673803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ea0ce0224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ea0ce02096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ea0cde6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ea0ca96176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ea0ca95e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3673804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f36738050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f36738050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ea0ca95d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c (912 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_i64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_i64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_u64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_u64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m1x4_tum( %mask, target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c (913 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | # | ... # `---data was truncated (10240/424835) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c7b5be357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c7b5be0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c7b5be3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f650c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f650c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f650c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f650c11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c7b5b7924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c7b5b79096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c7b5b5df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c7b580d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c7b580ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f650c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f650c11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f650c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c7b580cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c (914 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/97913) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f3db25457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f3db251515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f3db254cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6975933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f697598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6975933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f697591b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f3db1ea24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f3db1ea096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f3db1cef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f3dae7e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f3dae7de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f697591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f697591d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f697591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f3dae7dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c (915 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f64m1x3(ptr noundef %base, %binde # | ... # `---data was truncated (10240/94227) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055992253857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559922535515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559922538cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c40533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c4058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c40533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c4051b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005599224ce24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005599224ce096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005599224b2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559922162176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559922161e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2c4051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c4051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c4051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559922161d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c (916 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_v # | ... # `---data was truncated (10240/216258) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056329cbd457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056329cbd1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056329cbd4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8ae0e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8ae0ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8ae0e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8ae0e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056329cb6a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056329cb6a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056329cb4ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056329c7fe176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056329c7fde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8ae0e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8ae0e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8ae0e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056329c7fdd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c (917 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f32.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f32.p0.nxv8i16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c (918 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv8i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv8i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv4i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv2i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv8i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_vnum_s16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv8i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv4i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv2i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_vnum_u16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv8i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv4i8.p0( %3, ptr %4) # | %6 = sext ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/v8.1a-neon-intrinsics.c (919 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/v8.1a-neon-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-linux-gnu -target-feature +neon -target-feature +v8.1a -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-linux-gnu -target-feature +neon -target-feature +v8.1a -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-unknown-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vqrdmlah_laneq_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <8 x i16> noundef %v) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__p2.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | %v.addr = alloca <8 x i16>, align 16 # | %__ret_790 = alloca <4 x i16>, align 8 # | %__s0_790 = alloca <4 x i16>, align 8 # | %__s1_790 = alloca <4 x i16>, align 8 # | %__s2_790 = alloca <8 x i16>, align 16 # | %__ret = alloca <4 x i16>, align 8 # | %__s0 = alloca <8 x i16>, align 16 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x i16>, align 8 # | %tmp1 = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %v, ptr %v.addr, align 16 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__s0_790, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %1, ptr %__s1_790, align 8 # | %2 = load <8 x i16>, ptr %v.addr, align 16 # | store <8 x i16> %2, ptr %__s2_790, align 16 # | %3 = load <4 x i16>, ptr %__s0_790, align 8 # | %4 = load <4 x i16>, ptr %__s1_790, align 8 # | %5 = load <8 x i16>, ptr %__s2_790, align 16 # | store <8 x i16> %5, ptr %__s0, align 16 # | %6 = load <16 x i8>, ptr %__s0, align 16 # | %7 = bitcast <16 x i8> %6 to <8 x i16> # | %lane = shufflevector <8 x i16> %7, <8 x i16> %7, <4 x i32> # | store <4 x i16> %lane, ptr %ref.tmp, align 8 # | %8 = load <4 x i16>, ptr %ref.tmp, align 8 # | store <4 x i16> %8, ptr %__ret, align 8 # | %9 = load <4 x i16>, ptr %__ret, align 8 # | store <4 x i16> %9, ptr %tmp, align 8 # | %10 = load <4 x i16>, ptr %tmp, align 8 # | store <4 x i16> %3, ptr %__p0.addr.i, align 8 # | store <4 x i16> %4, ptr %__p1.addr.i, align 8 # | store <4 x i16> %10, ptr %__p2.addr.i, align 8 # | %11 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %12 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %13 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vqrdmlah_s16.i = bitcast <8 x i8> %11 to <4 x i16> # | %vqrdmlah_s161.i = bitcast <8 x i8> %12 to <4 x i16> # | %vqrdmlah_s162.i = bitcast <8 x i8> %13 to <4 x i16> # | %vqrdmlah_s163.i = call <4 x i16> @llvm.aarch64.neon.sqrdmlah.v4i16(<4 x i16> %vqrdmlah_s16.i, <4 x i16> %vqrdmlah_s161.i, <4 x i16> %vqrdmlah_s162.i) # | %vqrdmlah_s164.i = bitcast <4 x i16> %vqrdmlah_s163.i to <8 x i8> # | store <8 x i8> %vqrdmlah_s164.i, ptr %ref.tmp.i, align 8 # | %14 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %14, ptr %__ret.i, align 8 # | %15 = load <4 x i16>, ptr %__ret.i, align 8 # | store <4 x i16> %15, ptr %__ret_790, align 8 # | %16 = load <4 x i16>, ptr %__ret_790, align 8 # | store <4 x i16> %16, ptr %tmp1, align 8 # | %17 = load <4 x i16>, ptr %tmp1, align 8 # | ret <4 x i16> %17 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vqrdmlah_laneq_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <4 x i32> noundef %v) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__p2.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <2 x i32>, align 8 # | %v.addr = alloca <4 x i32>, align 16 # | %__ret_788 = alloca <2 x i32>, align 8 # | %__s0_788 = alloca <2 x i32>, align 8 # | %__s1_788 = alloca <2 x i32>, align 8 # | %__s2_788 = alloca <4 x i32>, align 16 # | %__ret = alloca <2 x i32>, align 8 # | %__s0 = alloca <4 x i32>, align 16 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x i32>, align 8 # | %tmp1 = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <2 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %v, ptr %v.addr, align 16 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__s0_788, align 8 # | %1 = load <2 x i32>, ptr %b.addr, align 8 # | store <2 x i32> %1, ptr %__s1_788, align 8 # | %2 = load <4 x i32>, ptr %v.addr, align 16 # | store <4 x i32> %2, ptr %__s2_788, align 16 # | %3 = load <2 x i32>, ptr %__s0_788, align 8 # | %4 = load <2 x i32>, ptr %__s1_788, align 8 # | %5 = load <4 x i32>, ptr %__s2_788, align 16 # | store <4 x i32> %5, ptr %__s0, align 16 # | %6 = load <16 x i8>, ptr %__s0, align 16 # | %7 = bitcast <16 x i8> %6 to <4 x i32> # | %lane = shufflevector <4 x i32> %7, <4 x i32> %7, <2 x i32> # | store <2 x i32> %lane, ptr %ref.tmp, align 8 # | %8 = load <2 x i32>, ptr %ref.tmp, align 8 # | store <2 x i32> %8, ptr %__ret, align 8 # | %9 = load <2 x i32>, ptr %__ret, align 8 # | store <2 x i32> %9, ptr %tmp, align 8 # | %10 = load <2 x i32>, ptr %tmp, align 8 # | store <2 x i32> %3, ptr %__p0.addr.i, align 8 # | store <2 x i32> %4, ptr %__p1.addr.i, align 8 # | store <2 x i32> %10, ptr %__p2.addr.i, align 8 # | %11 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %12 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %13 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vqrdmlah_s32.i = bitcast <8 x i8> %11 to <2 x i32> # | %vqrdmlah_s321.i = bitcast <8 x i8> %12 to <2 x i32> # | %vqrdmlah_s322.i = bitcast <8 x i8> %13 to <2 x i32> # | %vqrdmlah_s323.i = call <2 x i32> @llvm.aarch64.neon.sqrdmlah.v2i32(<2 x i32> %vqrdmlah_s32.i, <2 x i32> %vqrdmlah_s321.i, <2 x i32> %vqrdmlah_s322.i) # | %vqrdmlah_s324.i = bitcast <2 x i32> %vqrdmlah_s323.i to <8 x i8> # | store <8 x i8> %vqrdmlah_s324.i, ptr %ref.tmp.i, align 8 # | %14 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %14, ptr %__ret.i, align 8 # | %15 = load <2 x i32>, ptr %__ret.i, align 8 # | store <2 x i32> %15, ptr %__ret_788, align 8 # | %16 = load <2 x i32>, ptr %__ret_788, align 8 # | store <2 x i32> %16, ptr %tmp1, align 8 # | %17 = load <2 x i32>, ptr %tmp1, align 8 # | ret <2 x i32> %17 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vqrdmlahq_laneq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %v) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x i16>, align 16 # | %__p2.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x i16>, align 16 # | %v.addr = alloca <8 x i16>, align 16 # | %__ret_786 = alloca <8 x i16>, align 16 # | %__s0_786 = alloca <8 x i16>, align 16 # | %__s1_786 = alloca <8 x i16>, align 16 # | %__s2_786 = alloca <8 x i16>, align 16 # | %__ret = alloca <8 x i16>, align 16 # | %__s0 = alloca <8 x i16>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x i16>, align 16 # | %tmp1 = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | store <8 x i16> %b, ptr %b.addr, align 16 # | store <8 x i16> %v, ptr %v.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__s0_786, align 16 # | %1 = load <8 x i16>, ptr %b.addr, align 16 # | store <8 x i16> %1, ptr %__s1_786, align 16 # | %2 = load <8 x i16>, ptr %v.addr, align 16 # | store <8 x i16> %2, ptr %__s2_786, align 16 # | %3 = load <8 x i16>, ptr %__s0_786, align 16 # | %4 = load <8 x i16>, ptr %__s1_786, align 16 # | %5 = load <8 x i16>, ptr %__s2_786, align 16 # | store <8 x i16> %5, ptr %__s0, align 16 # | %6 = load <16 x i8>, ptr %__s0, align 16 # | %7 = bitcast <16 x i8> %6 to <8 x i16> # | %lane = shufflevector <8 x i16> %7, <8 x i16> %7, <8 x i32> # | store <8 x i16> %lane, ptr %ref.tmp, align 16 # | %8 = load <8 x i16>, ptr %ref.tmp, align 16 # | store <8 x i16> %8, ptr %__ret, align 16 # | %9 = load <8 x i16>, ptr %__ret, align 16 # | store <8 x i16> %9, ptr %tmp, align 16 # | %10 = load <8 x i16>, ptr %tmp, align 16 # | store <8 x i16> %3, ptr %__p0.addr.i, align 16 # | store <8 x i16> %4, ptr %__p1.addr.i, align 16 # | store <8 x i16> %10, ptr %__p2.addr.i, align 16 # | %11 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %12 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %13 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vqrdmlahq_s16.i = bitcast <16 x i8> %11 to <8 x i16> # | %vqrdmlahq_s161.i = bitcast <16 x i8> %12 to <8 x i16> # | %vqrdmlahq_s162.i = bitcast <16 x i8> %13 to <8 x i16> # | %vqrdmlahq_s163.i = call <8 x i16> @llvm.aarch64.neon.sqrdmlah.v8i16(<8 x i16> %vqrdmlahq_s16.i, <8 x i16> %vqrdmlahq_s161.i, <8 x i16> %vqrdmlahq_s162.i) # | %vqrdmlahq_s164.i = bitcast <8 x i16> %vqrdmlahq_s163.i to <16 x i8> # | store <16 x i8> %vqrdmlahq_s164.i, ptr %ref.tmp.i, align 16 # | %14 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %14, ptr %__ret.i, align 16 # | %15 = load <8 x i16>, ptr %__ret.i, align 16 # | store <8 x i16> %15, ptr %__ret_786, align 16 # | %16 = load <8 x i16>, ptr %__ret_786, align 16 # | store <8 x i16> %16, ptr %tmp1, align 16 # | %17 = load <8 x i16>, ptr %tmp1, align 16 # | ret <8 x i16> %17 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vqrdmlahq_laneq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %v) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <4 x i32>, align 16 # | %__p2.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | %b.addr = alloca <4 x i32>, align 16 # | %v.addr = alloca <4 x i32>, align 16 # | %__ret_784 = alloca <4 x i32>, align 16 # | %__s0_784 = alloca <4 x i32>, align 16 # | %__s1_784 = alloca <4 x i32>, align 16 # | %__s2_784 = alloca <4 x i32>, align 16 # | %__ret = alloca <4 x i32>, align 16 # | %__s0 = alloca <4 x i32>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <4 x i32>, align 16 # | %tmp1 = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | store <4 x i32> %b, ptr %b.addr, align 16 # | store <4 x i32> %v, ptr %v.addr, align 16 # | %0 = load <4 # | ... # `---data was truncated (10240/50621) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S # | #0 0x000055d57c50a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d57c507515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d57c50acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1e1e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1e1e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1e1e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1e1e631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d57c4a024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d57c4a0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d57c484f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d57c134176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d57c133e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1e1e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1e1e6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1e1e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d57c133d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c (920 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf4x5_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf2x5_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16m1x5_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564f896b757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564f896b4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564f896b7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcc05533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcc0558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcc05533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcc0551b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564f8964d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564f8964d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564f89631f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564f892e1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564f892e0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcc0551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcc0551d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcc0551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564f892e0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c (921 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, a # | ... # `---data was truncated (10240/424843) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005624b5e1157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005624b5e0e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005624b5e11cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f10fb133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f10fb18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f10fb133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f10fb11b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005624b5da724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005624b5da7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005624b5d8bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005624b5a3b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005624b5a3ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f10fb11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f10fb11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f10fb11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005624b5a3ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c (922 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_u16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_u16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c (923 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv1f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv2f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv4f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv8f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m8_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m1_tumu( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 8 # | %2 = load , ptr %vs2.addr, align # | ... # `---data was truncated (10240/18311) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f8ff7b957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f8ff7b6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f8ff7b9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb801449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb8014a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb801449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb801431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f8ff74f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f8ff74f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f8ff733f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f8ff3e3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f8ff3e2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb801432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb8014330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb8014330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f8ff3e2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c (924 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m4_tu( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c (925 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_i8mf4x5(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ddd244257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ddd243f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ddd2442cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1707b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1707b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1707b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1707b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ddd23d824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ddd23d8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ddd23bcf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ddd206c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ddd206be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1707b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1707b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1707b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ddd206bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c (926 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf8_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf4_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8m1_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c (927 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrd_u32base_s32index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrd.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.adrd.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrd_u64base_s64index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrd.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.adrd.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrd_u32base_u32index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrd.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrd_u64base_u64index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrd.nxv2i64( %0, %1) # | ret %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056419e79657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056419e793515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056419e796cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efd83d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efd83d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efd83d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efd83d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056419e72c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056419e72c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056419e710f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056419e3c0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056419e3bfe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efd83d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efd83d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efd83d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056419e3bfd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c (928 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0. # | ... # `---data was truncated (10240/87884) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056342cffb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056342cff8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056342cffbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4a5521bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4a552725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4a5521ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4a55203507 abort ./stdlib/abort.c:85:3 # | #7 0x000056342cf9124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056342cf91096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056342cf75f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056342cc25176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056342cc24e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4a55204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4a552050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4a552050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056342cc24d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c (929 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32mf2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32m1x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32m2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32mf2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32m1x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32m2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_u32mf2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractval # | ... # `---data was truncated (10240/13669) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056326e6fc57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056326e6f9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056326e6fccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1ce7049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1ce70a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1ce7049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1ce7031507 abort ./stdlib/abort.c:85:3 # | #7 0x000056326e69224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056326e692096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056326e676f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056326e326176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056326e325e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1ce7032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1ce70330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1ce70330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056326e325d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_and.c (930 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_and.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svand_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.and.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.and.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svand_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.and.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.and.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svand_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.and.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.and.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svand_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.and.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.and.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svand_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.and.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svand_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.and.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svand_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.and.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svand_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.and.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svand_s8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, pt # | ... # `---data was truncated (10240/52880) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000562c809f457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562c809f1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562c809f4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fad55133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fad5518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fad55133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fad5511b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562c8098a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562c8098a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562c8096ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562c8061e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562c8061de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fad5511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fad5511d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fad5511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562c8061dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c (931 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u8mf8(i8 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i32, align 4 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i8, ptr %rs1.addr, align 1 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 5, i32 %1) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 immarg, i32 immarg, i32 immarg, i8, i32 immarg, i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u8mf4(i8 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i32, align 4 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i8, ptr %rs1.addr, align 1 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 6, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u8mf2(i8 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i32, align 4 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i8, ptr %rs1.addr, align 1 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 7, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u8m1(i8 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i32, align 4 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i8, ptr %rs1.addr, align 1 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 0, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u8m2(i8 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i32, align 4 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i8, ptr %rs1.addr, align 1 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 1, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u8m4(i8 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i32, align 4 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i8, ptr %rs1.addr, align 1 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 2, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u8m8(i8 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i32, align 4 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i8, ptr %rs1.addr, align 1 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 3, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u16mf4(i16 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i16, align 2 # | %vl.addr = alloca i32, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i16, ptr %rs1.addr, align 2 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 6, i32 %1) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 immarg, i32 immarg, i32 immarg, i16, i32 immarg, i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u16mf2(i16 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i16, align 2 # | %vl.addr = alloca i32, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i16, ptr %rs1.addr, align 2 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 7, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u16m1(i16 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i16, align 2 # | %vl.addr = alloca i32, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i16, ptr %rs1.addr, align 2 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 0, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u16m2(i16 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i16, align 2 # | %vl.addr = alloca i32, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i16, ptr %rs1.addr, align 2 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 1, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u16m4(i16 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i16, align 2 # | %vl.addr = alloca i32, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i16, ptr %rs1.addr, align 2 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 2, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u16m8(i16 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i16, align 2 # | %vl.addr = alloca i32, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i16, ptr %rs1.addr, align 2 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 3, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u32mf2(i32 noundef %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 7, i32 %1) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 immarg, i32 immarg, i32 immarg, i32, i32 immarg, i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u32m1(i32 noundef %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 0, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u32m2(i32 noundef %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 1, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u32m4(i32 noundef %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 2, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u32m8(i32 noundef %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 3, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_x_se_u8mf8(i8 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i32, align 4 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i8, ptr %rs1.addr, align 1 # | %1 = load i32, ptr %vl.addr, align 4 # | %2 = call @llvm.riscv.sf.vc.v.x.se.nxv1i8.i32.i8.i32(i32 3, i32 31, i8 %0, i32 %1) # | ret %2 # | } # | # | ; Function Attrs: nounwind # | ... # `---data was truncated (10240/66298) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f6f62f557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f6f62f2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f6f62f5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6cd0649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6cd06a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6cd0649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6cd0631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f6f628b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f6f628b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f6f626ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f6f5f1f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f6f5f1ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6cd0632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6cd06330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6cd06330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f6f5f1ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c (932 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16mf4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16mf2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m1_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m8_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f32mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f32m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f32m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv2f32.nxv4f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare # | ... # `---data was truncated (10240/68054) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e5aa9b957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e5aa9b6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e5aa9b9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5348049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f53480a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5348049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5348031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e5aa94f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e5aa94f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e5aa933f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e5aa5e3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e5aa5e2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5348032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f53480330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f53480330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e5aa5e2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c (933 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_i8mf4x5(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d91e9e057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d91e9dd515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d91e9e0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcd99933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcd9998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcd99933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcd9991b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d91e97624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d91e976096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d91e95af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d91e60a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d91e609e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcd9991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcd9991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcd9991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d91e609d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c (934 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv16i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c (935 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_v # | ... # `---data was truncated (10240/228865) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565381fb157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000565381fae515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000565381fb1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa9e9d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa9e9d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa9e9d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa9e9d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565381f4724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000565381f47096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000565381f2bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000565381bdb176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000565381bdae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa9e9d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa9e9d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa9e9d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565381bdad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c (936 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32mf2_tum( %mask, %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 4 # | %src.a # | ... # `---data was truncated (10240/41678) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e5fa16157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e5fa15e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e5fa161cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5f45649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5f456a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5f45649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5f45631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e5fa0f724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e5fa0f7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e5fa0dbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e5f9d8b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e5f9d8ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5f45632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5f456330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5f456330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e5f9d8ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c (937 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e167b0857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e167b05515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e167b08cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f56b4e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f56b4e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f56b4e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f56b4e03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e167a9e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e167a9e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e167a82f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e167732176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e167731e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f56b4e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f56b4e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f56b4e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e167731d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c (938 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.prf.nxv2i1.p0(, ptr, i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_1( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_2( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_3( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_4( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_5( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_6( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 8) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_7( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 9) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 10) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_9( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 11) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_10( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 12) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_11( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 13) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_vnum( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %3, ptr %4, i32 0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_gather_u32base( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prfd.gather.scalar.offset.nxv4i32( %2, %1, i64 0, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) # | declare void @llvm.aarch64.sve.prfd.gather.scalar.offset.nxv4i32(, , i64, i32 immarg) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_gather_u64base( %pg, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c (939 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16mf4_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv1bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv1bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16mf2_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv2bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv2bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m1_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv4bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv4bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m2_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv8bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv8bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m4_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv16bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv16bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m8_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv32bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv32bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16mf4_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.s.f.nxv1bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv1bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16mf2_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.s.f.nxv2bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv2bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16m1_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.s.f.nxv4bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv4bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16m2_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.s.f.nxv8bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv8bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16m4_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %ma # | ... # `---data was truncated (10240/12656) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ca4256b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ca42568515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ca4256bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb82ef05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb82ef5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb82ef05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb82eeed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ca4250124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ca42501096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ca424e5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ca42195176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ca42194e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb82eeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb82eeef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb82eeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ca42194d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c (940 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 31) # | ret i64 %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.cntw(i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_1() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_2() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_3() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 3) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_4() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 4) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_5() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 5) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_6() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 6) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_7() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_8() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 8) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_9() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 9) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_10() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 10) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_11() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 11) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_12() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 12) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_13() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 13) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_14() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 29) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_15() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 30) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_16() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 31) # | ret i64 %0 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x0000555eae9cb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555eae9c8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555eae9cbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2193d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2193d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2193d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2193d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555eae96124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555eae961096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555eae945f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555eae5f5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555eae5f4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2193d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2193d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2193d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555eae5f4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c (941 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_i64m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_i64m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_u64m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_u64m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m1x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/16424) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bfb78bb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bfb78b8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bfb78bbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f32b5d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f32b5d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f32b5d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f32b5d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bfb785124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bfb7851096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bfb7835f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bfb74e5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bfb74e4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f32b5d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f32b5d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f32b5d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bfb74e4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c (942 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c (943 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_v # | ... # `---data was truncated (10240/216258) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cfa77ca57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cfa77c7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cfa77cacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f03c2c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f03c2ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f03c2c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f03c2c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cfa776024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cfa7760096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cfa7744f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cfa73f4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cfa73f3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f03c2c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f03c2c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f03c2c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cfa73f3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c (944 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte32_f32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vlte32.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte32_i32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte32_u32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056009421157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056009420e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560094211cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc3b3f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc3b3f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc3b3f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc3b3f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005600941a724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005600941a7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056009418bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560093e3b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560093e3ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc3b3f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc3b3f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc3b3f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560093e3ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c (945 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056160631857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561606315515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561606318cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4083c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4083ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4083c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4083c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005616062ae24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005616062ae096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561606292f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561605f42176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561605f41e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4083c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4083c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4083c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561605f41d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c (946 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/87892) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005577aee9e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005577aee9b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005577aee9ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe38e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe38e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe38e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe38e71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005577aee3424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005577aee34096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005577aee18f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005577aeac8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005577aeac7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe38e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe38e71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe38e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005577aeac7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c (947 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16mf4x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16mf2x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16m1x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16m1x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c01616757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c016164515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c016167cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0a6be49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0a6bea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0a6be49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0a6be31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c0160fd24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c0160fd096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c0160e1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c015d91176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c015d90e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0a6be32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0a6be330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0a6be330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c015d90d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c (948 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fcf3d9d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fcf3d9a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fcf3d9dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff377d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff377d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff377d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff377d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fcf3d3324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fcf3d33096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fcf3d17f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fcf39c7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fcf39c6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff377d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff377d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff377d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fcf39c6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c (949 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv1i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv2i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv4i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv8i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv16i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv32i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv64i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv1i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv2i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv4i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4 # | ... # `---data was truncated (10240/96257) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560e85b3657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560e85b33515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560e85b36cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc8ab449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc8ab4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc8ab449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc8ab431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560e85acc24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560e85acc096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560e85ab0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560e85760176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560e8575fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc8ab432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc8ab4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc8ab4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560e8575fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c (950 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsubr_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.subr.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.subr.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsubr_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.subr.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.subr.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsubr_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.subr.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.subr.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsubr_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.subr.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.subr.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsubr_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.subr.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsubr_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.subr.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsubr_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.subr.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsubr_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.subr.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsubr_s8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c (951 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_v # | ... # `---data was truncated (10240/253156) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a98a89757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a98a894515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a98a897cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbe0f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbe0f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbe0f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbe0f51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a98a82d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a98a82d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a98a811f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a98a4c1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a98a4c0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbe0f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbe0f51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbe0f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a98a4c0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c (952 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv32i8.nxv32i8.i64( %0, # | ... # `---data was truncated (10240/171381) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557eb0c8e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557eb0c8b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557eb0c8ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc4b7105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc4b715c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc4b7105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc4b70ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557eb0c2424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557eb0c24096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557eb0c08f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557eb08b8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557eb08b7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc4b70eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc4b70ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc4b70ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557eb08b7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c (953 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_u8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv16i8.p0( %0, ptr %1) # | ret { , } %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2q.sret.nxv16i8.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_s8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv16i8.p0( %0, ptr %1) # | ret { , } %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv8i16.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2q.sret.nxv8i16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv8i16.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv4i32.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2q.sret.nxv4i32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv4i32.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv2i64.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2q.sret.nxv2i64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv2i64.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_f16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv8f16.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2q.sret.nxv8f16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_bf16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv8bf16.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2q.sret.nxv8bf16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_f32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv4f32.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | d # | ... # `---data was truncated (10240/75038) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000564dda92357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564dda920515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564dda923cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc612933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc61298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc612933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc61291b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564dda8b924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564dda8b9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564dda89df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564dda54d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564dda54ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc61291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc61291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc61291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564dda54cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c (954 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlastp_b8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call i64 @llvm.aarch64.sve.lastp.nxv16i1( %0, %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.lastp.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlastp_b16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call i64 @llvm.aarch64.sve.lastp.nxv8i1( %2, %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.lastp.nxv8i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlastp_b32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call i64 @llvm.aarch64.sve.lastp.nxv4i1( %2, %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.lastp.nxv4i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlastp_b64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call i64 @llvm.aarch64.sve.lastp.nxv2i1( %2, %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.lastp.nxv2i1(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2p2" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005651218ff57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005651218fc515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005651218ffcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa081c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa081ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa081c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa081c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056512189524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000565121895096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000565121879f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000565121529176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000565121528e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa081c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa081c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa081c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565121528d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c (955 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3 # | ... # `---data was truncated (10240/64366) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005624c553457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005624c5531515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005624c5534cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f186e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f186e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f186e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f186e031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005624c54ca24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005624c54ca096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005624c54aef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005624c515e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005624c515de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f186e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f186e0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f186e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005624c515dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c (956 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c (957 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_f32mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_f32mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv1f32.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_f32m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_f32m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv2f32.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willret # | ... # `---data was truncated (10240/365423) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e9fe65c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e9fe659515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e9fe65ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f61a0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f61a08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f61a0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f61a0831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e9fe5f224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e9fe5f2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e9fe5d6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e9fe286176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e9fe285e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f61a0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f61a08330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f61a08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e9fe285d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c (958 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xtheadbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c -check-prefix=RV32XTHEADBB # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xtheadbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @clz_32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call i32 @llvm.ctlz.i32(i32 %0, i1 false) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.ctlz.i32(i32, i1 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @clo_32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %not = xor i32 %0, -1 # | %1 = call i32 @llvm.ctlz.i32(i32 %not, i1 false) # | ret i32 %1 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+xtheadbb" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_xtheadbb1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560dc0dbc57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560dc0db9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560dc0dbccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f489261bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f48926725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f489261ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4892603507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560dc0d5224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560dc0d52096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560dc0d36f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560dc09e6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560dc09e5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4892604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f48926050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f48926050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560dc09e5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c -check-prefix=RV32XTHEADBB # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c -check-prefix=RV32XTHEADBB # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c (959 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | # | ... # `---data was truncated (10240/116259) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005634bc82857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005634bc825515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005634bc828cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff3b0049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff3b00a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff3b0049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff3b0031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005634bc7be24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005634bc7be096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005634bc7a2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005634bc452176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005634bc451e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff3b0032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff3b00330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff3b00330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005634bc451d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c (960 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, # | ... # `---data was truncated (10240/288103) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056387cb5a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056387cb57515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056387cb5acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f85de533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f85de58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f85de533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f85de51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056387caf024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056387caf0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056387cad4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056387c784176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056387c783e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f85de51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f85de51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f85de51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056387c783d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c (961 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_i64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_u64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_f64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_i64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_u64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_f64m1x6_tumu( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 0, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_i64m1x6_tumu( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tu # | ... # `---data was truncated (10240/16560) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005589464c257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005589464bf515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005589464c2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f89a2449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f89a24a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f89a2449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f89a2431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055894645824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558946458096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055894643cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005589460ec176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005589460ebe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f89a2432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f89a24330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f89a24330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005589460ebd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c (962 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562f441bf57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562f441bc515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562f441bfcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb854049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb8540a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb854049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb854031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562f4415524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562f44155096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562f44139f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562f43de9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562f43de8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb854032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb8540330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb8540330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562f43de8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c (963 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_i8mf8x8 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e56af1e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e56af1b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e56af1ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbce1649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbce16a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbce1649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbce1631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e56aeb424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e56aeb4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e56ae98f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e56ab48176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e56ab47e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbce1632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbce16330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbce16330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e56ab47d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c (964 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | # | ... # `---data was truncated (10240/67482) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fa7660b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fa76608515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fa7660bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6b1d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6b1d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6b1d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6b1d831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fa765a124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fa765a1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fa76585f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fa76235176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fa76234e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6b1d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6b1d8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6b1d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fa76234d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c (965 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005568bb49957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005568bb496515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005568bb499cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f78e8249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f78e82a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f78e8249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f78e8231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005568bb42f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005568bb42f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005568bb413f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005568bb0c3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005568bb0c2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f78e8232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f78e82330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f78e82330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005568bb0c2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c (966 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv4i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv2i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv4i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv2i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv4i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv2i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_gather_u32base_s32( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32( %2, %1, i64 0) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32(, , i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_gather_u64base_s64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64( %2, %1, i64 0) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64(, , i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_gather_u32base_u32( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, # | ... # `---data was truncated (10240/37388) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055a2f696457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a2f6961515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a2f6964cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc934f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc934f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc934f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc934f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a2f68fa24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a2f68fa096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a2f68def49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a2f658e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a2f658de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc934f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc934f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc934f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a2f658dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c (967 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vect # | ... # `---data was truncated (10240/108856) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ba92f8a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ba92f87515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ba92f8acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2ccd649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2ccd6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2ccd649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2ccd631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ba92f2024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ba92f20096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ba92f04f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ba92bb4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ba92bb3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2ccd632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2ccd6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2ccd6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ba92bb3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c (968 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1q.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1q.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1q.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1q.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1q.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1q.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1q.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_bf16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1q.nxv8bf16(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056084c4bc57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056084c4b9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056084c4bccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6856e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6856e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6856e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6856e03507 abort ./stdlib/abort.c:85:3 # | #7 0x000056084c45224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056084c452096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056084c436f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056084c0e6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056084c0e5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6856e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6856e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6856e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056084c0e5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c (969 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | # | ... # `---data was truncated (10240/424835) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e38451757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e384514515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e384517cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f248e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f248e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f248e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f248e51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e3844ad24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e3844ad096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e384491f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e384141176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e384140e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f248e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f248e51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f248e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e384140d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c (970 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_u16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca # | ... # `---data was truncated (10240/60551) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558b93ce857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558b93ce5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558b93ce8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4d79c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4d79ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4d79c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4d79c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558b93c7e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558b93c7e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558b93c62f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558b93912176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558b93911e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4d79c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4d79c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4d79c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558b93911d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c (971 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf4_tum( %mask, %maskedoff, %src, i64 noundef %vl # | ... # `---data was truncated (10240/78896) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a019d0157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a019cfe515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a019d01cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f49ce049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f49ce0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f49ce049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f49ce031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a019c9724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a019c97096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a019c7bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a01992b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a01992ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f49ce032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f49ce0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f49ce0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a01992ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c (972 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m1_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv1i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv2i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m4_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv4i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m8_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv8i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m1_tum( %mask, %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %m # | ... # `---data was truncated (10240/41661) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563f5cd3157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563f5cd2e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563f5cd31cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5edca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5edcaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5edca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5edca31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563f5ccc724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563f5ccc7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563f5ccabf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563f5c95b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563f5c95ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5edca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5edca330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5edca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563f5c95ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c (973 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv1i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv2i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv4i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv8i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv16i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv16i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8 # | ... # `---data was truncated (10240/99577) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d00c5e257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d00c5df515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d00c5e2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbceb049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbceb0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbceb049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbceb031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d00c57824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d00c578096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d00c55cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d00c20c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d00c20be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbceb032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbceb0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbceb0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d00c20bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c (974 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_i8mf8x6 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005580fe47c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005580fe479515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005580fe47ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6bcac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6bcaca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6bcac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6bcac31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005580fe41224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005580fe412096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005580fe3f6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005580fe0a6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005580fe0a5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6bcac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6bcac330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6bcac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005580fe0a5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c (975 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vvm_i8mf8_b64( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vxm_i8mf8_b64( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbc.borrow.in.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.borrow.in.nxv1i8.i8.i64(, i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbc.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbc.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vvm_i8mf4_b32( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbc.borrow.in.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.borrow.in.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vxm_i8mf4_b32( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbc.borrow.in.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.borrow.in.nxv2i8.i8.i64(, i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbc.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbc.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vvm_i8mf2_b16( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbc.borrow.in.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.borrow.in.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vxm_i8mf2_b16( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | ... # `---data was truncated (10240/170489) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005581bde7657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005581bde73515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005581bde76cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fca28133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fca2818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fca28133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fca2811b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005581bde0c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005581bde0c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005581bddf0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005581bdaa0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005581bda9fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fca2811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fca2811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fca2811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005581bda9fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c (976 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_f64m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_f64m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_f64m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_i64m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_i64m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_i64m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_u64m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_u64m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_u64m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_f64m1x2_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(arg # | ... # `---data was truncated (10240/20531) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055db5e13357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055db5e130515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055db5e133cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe97d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe97d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe97d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe97d231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055db5e0c924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055db5e0c9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055db5e0adf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055db5dd5d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055db5dd5ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe97d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe97d2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe97d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055db5dd5cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c (977 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_i8mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef # | ... # `---data was truncated (10240/69988) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005620ffa3957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005620ffa36515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005620ffa39cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3da9c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3da9c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3da9c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3da9c03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005620ff9cf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005620ff9cf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005620ff9b3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005620ff663176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005620ff662e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3da9c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3da9c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3da9c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005620ff662d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c (978 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e079b3557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e079b32515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e079b35cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9542133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f954218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9542133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f954211b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e079acb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e079acb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e079aaff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e07975f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e07975ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f954211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f954211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f954211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e07975ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c (979 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_ran # | ... # `---data was truncated (10240/95347) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055deb653257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055deb652f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055deb6532cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe495849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe4958a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe495849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe495831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055deb64c824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055deb64c8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055deb64acf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055deb615c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055deb615be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe495832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe4958330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe4958330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055deb615bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c (980 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_b8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.uzp1.nxv16i1( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_b16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.uzp1.b16( %0, %1) # | ret %2 # | ... # `---data was truncated (10240/13404) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005616476e157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005616476de515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005616476e1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8256133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f825618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8256133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f825611b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056164767724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561647677096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056164765bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056164730b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056164730ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f825611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f825611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f825611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056164730ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c (981 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ta # | ... # `---data was truncated (10240/47488) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005599e097e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005599e097b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005599e097ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5fb5e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5fb5e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5fb5e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5fb5e03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005599e091424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005599e0914096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005599e08f8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005599e05a8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005599e05a7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5fb5e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5fb5e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5fb5e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005599e05a7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c (982 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p3 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p3 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_s16_x2( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sdot.x2.nxv8i16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdot.x2.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_u16_x2( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.udot.x2.nxv8i16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.udot.x2.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_s16_x2( %op1, %op2, i8 noundef %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca i8, align 1 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store i8 %op3, ptr %op3.addr, align 1 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load i8, ptr %op3.addr, align 1 # | %.splatinsert = insertelement poison, i8 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.sdot.x2.nxv8i16( %0, %1, %.splat) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_u16_x2( %op1, %op2, i8 noundef %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca i8, align 1 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store i8 %op3, ptr %op3.addr, align 1 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load i8, ptr %op3.addr, align 1 # | %.splatinsert = insertelement poison, i8 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.udot.x2.nxv8i16( %0, %1, %.splat) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_lane_s16_x2( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sdot.lane.x2.nxv8i16( %0, %1, %2, i32 7) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdot.lane.x2.nxv8i16(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_lane_u16_x2( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.udot.lane.x2.nxv8i16( %0, %1, %2, i32 7) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.udot.lane.x2.nxv8i16(, , , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2p3" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055e7f2c2857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e7f2c25515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e7f2c28cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2775933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f277598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2775933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f277591b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e7f2bbe24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e7f2bbe096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e7f2ba2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e7f2852176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e7f2851e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f277591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f277591d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f277591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e7f2851d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c (983 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_i8mf4x8(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a1106ef57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a1106ec515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a1106efcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbba9249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbba92a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbba9249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbba9231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a11068524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a110685096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a110669f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a110319176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a110318e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbba9232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbba92330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbba92330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a110318d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c (984 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_lo # | ... # `---data was truncated (10240/70863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005614fede557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005614fede2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005614fede5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f33dc849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f33dc8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f33dc849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f33dc831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005614fed7b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005614fed7b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005614fed5ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005614fea0f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005614fea0ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f33dc832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f33dc8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f33dc8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005614fea0ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c (985 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), p # | ... # `---data was truncated (10240/87316) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557a2098d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557a2098a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557a2098dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fae2c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fae2c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fae2c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fae2c31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557a2092324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557a20923096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557a20907f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557a205b7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557a205b6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fae2c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fae2c31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fae2c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557a205b6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/bf16-dotprod-intrinsics.c (986 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/bf16-dotprod-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +bf16 -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +bf16 -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vbfdot_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x bfloat>, align 8 # | %__p2.addr.i = alloca <4 x bfloat>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x float>, align 8 # | %a.addr = alloca <4 x bfloat>, align 8 # | %b.addr = alloca <4 x bfloat>, align 8 # | store <2 x float> %r, ptr %r.addr, align 8 # | store <4 x bfloat> %a, ptr %a.addr, align 8 # | store <4 x bfloat> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %r.addr, align 8 # | %1 = load <4 x bfloat>, ptr %a.addr, align 8 # | %2 = load <4 x bfloat>, ptr %b.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__p1.addr.i, align 8 # | store <4 x bfloat> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vbfdot.i = bitcast <8 x i8> %3 to <2 x float> # | %vbfdot1.i = bitcast <8 x i8> %4 to <4 x bfloat> # | %vbfdot2.i = bitcast <8 x i8> %5 to <4 x bfloat> # | %vbfdot3.i = call <2 x float> @llvm.aarch64.neon.bfdot.v2f32.v4bf16(<2 x float> %vbfdot.i, <4 x bfloat> %vbfdot1.i, <4 x bfloat> %vbfdot2.i) # | store <2 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %6, ptr %__ret.i, align 8 # | %7 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vbfdotq_f32(<4 x float> noundef %r, <8 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <8 x bfloat>, align 16 # | %__p2.addr.i = alloca <8 x bfloat>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %r.addr = alloca <4 x float>, align 16 # | %a.addr = alloca <8 x bfloat>, align 16 # | %b.addr = alloca <8 x bfloat>, align 16 # | store <4 x float> %r, ptr %r.addr, align 16 # | store <8 x bfloat> %a, ptr %a.addr, align 16 # | store <8 x bfloat> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %r.addr, align 16 # | %1 = load <8 x bfloat>, ptr %a.addr, align 16 # | %2 = load <8 x bfloat>, ptr %b.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <8 x bfloat> %1, ptr %__p1.addr.i, align 16 # | store <8 x bfloat> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vbfdot.i = bitcast <16 x i8> %3 to <4 x float> # | %vbfdot1.i = bitcast <16 x i8> %4 to <8 x bfloat> # | %vbfdot2.i = bitcast <16 x i8> %5 to <8 x bfloat> # | %vbfdot3.i = call <4 x float> @llvm.aarch64.neon.bfdot.v4f32.v8bf16(<4 x float> %vbfdot.i, <8 x bfloat> %vbfdot1.i, <8 x bfloat> %vbfdot2.i) # | store <4 x float> %vbfdot3.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %6, ptr %__ret.i, align 16 # | %7 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vbfdot_lane_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x bfloat>, align 8 # | %__p2.addr.i = alloca <4 x bfloat>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x float>, align 8 # | %a.addr = alloca <4 x bfloat>, align 8 # | %b.addr = alloca <4 x bfloat>, align 8 # | %__ret_810 = alloca <2 x float>, align 8 # | %__s0_810 = alloca <2 x float>, align 8 # | %__s1_810 = alloca <4 x bfloat>, align 8 # | %__s2_810 = alloca <4 x bfloat>, align 8 # | %ref.tmp = alloca <2 x float>, align 8 # | %__ret = alloca <2 x float>, align 8 # | %__s0 = alloca <2 x float>, align 8 # | %ref.tmp1 = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x float>, align 8 # | %tmp2 = alloca <2 x float>, align 8 # | store <2 x float> %r, ptr %r.addr, align 8 # | store <4 x bfloat> %a, ptr %a.addr, align 8 # | store <4 x bfloat> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %r.addr, align 8 # | store <2 x float> %0, ptr %__s0_810, align 8 # | %1 = load <4 x bfloat>, ptr %a.addr, align 8 # | store <4 x bfloat> %1, ptr %__s1_810, align 8 # | %2 = load <4 x bfloat>, ptr %b.addr, align 8 # | store <4 x bfloat> %2, ptr %__s2_810, align 8 # | %3 = load <2 x float>, ptr %__s0_810, align 8 # | %4 = load <4 x bfloat>, ptr %__s1_810, align 8 # | %5 = load <2 x float>, ptr %__s2_810, align 8 # | store <2 x float> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x float> # | %lane = shufflevector <2 x float> %7, <2 x float> %7, <2 x i32> zeroinitializer # | store <2 x float> %lane, ptr %ref.tmp1, align 8 # | %8 = load <2 x float>, ptr %ref.tmp1, align 8 # | store <2 x float> %8, ptr %__ret, align 8 # | %9 = load <2 x float>, ptr %__ret, align 8 # | store <2 x float> %9, ptr %tmp, align 8 # | %10 = load <2 x float>, ptr %tmp, align 8 # | store <2 x float> %10, ptr %ref.tmp, align 8 # | %11 = load <4 x bfloat>, ptr %ref.tmp, align 8 # | store <2 x float> %3, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %4, ptr %__p1.addr.i, align 8 # | store <4 x bfloat> %11, ptr %__p2.addr.i, align 8 # | %12 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %13 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %14 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vbfdot.i = bitcast <8 x i8> %12 to <2 x float> # | %vbfdot1.i = bitcast <8 x i8> %13 to <4 x bfloat> # | %vbfdot2.i = bitcast <8 x i8> %14 to <4 x bfloat> # | %vbfdot3.i = call <2 x float> @llvm.aarch64.neon.bfdot.v2f32.v4bf16(<2 x float> %vbfdot.i, <4 x bfloat> %vbfdot1.i, <4 x bfloat> %vbfdot2.i) # | store <2 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8 # | %15 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %15, ptr %__ret.i, align 8 # | %16 = load <2 x float>, ptr %__ret.i, align 8 # | store <2 x float> %16, ptr %__ret_810, align 8 # | %17 = load <2 x float>, ptr %__ret_810, align 8 # | store <2 x float> %17, ptr %tmp2, align 8 # | %18 = load <2 x float>, ptr %tmp2, align 8 # | ret <2 x float> %18 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vbfdotq_laneq_f32(<4 x float> noundef %r, <8 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <8 x bfloat>, align 16 # | %__p2.addr.i = alloca <8 x bfloat>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %r.addr = alloca <4 x float>, align 16 # | %a.addr = alloca <8 x bfloat>, align 16 # | %b.addr = alloca <8 x bfloat>, align 16 # | %__ret_812 = alloca <4 x float>, align 16 # | %__s0_812 = alloca <4 x float>, align 16 # | %__s1_812 = alloca <8 x bfloat>, align 16 # | %__s2_812 = alloca <8 x bfloat>, align 16 # | %ref.tmp = alloca <4 x float>, align 16 # | %__ret = alloca <4 x float>, align 16 # | %__s0 = alloca <4 x float>, align 16 # | %ref.tmp1 = alloca <16 x i8>, align 16 # | %tmp = alloca <4 x float>, align 16 # | %tmp2 = alloca <4 x float>, align 16 # | store <4 x float> %r, ptr %r.addr, align 16 # | store <8 x bfloat> %a, ptr %a.addr, align 16 # | store <8 x bfloat> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %r.addr, align 16 # | store <4 x float> %0, ptr %__s0_812, align 16 # | %1 = load <8 x bfloat>, ptr %a.addr, align 16 # | store <8 x bfloat> %1, ptr %__s1_812, align 16 # | %2 = load <8 x bfloat>, ptr %b.addr, align 16 # | store <8 x bfloat> %2, ptr %__s2_812, align 16 # | %3 = load <4 x float>, ptr %__s0_812, align 16 # | %4 = load <8 x bfloat>, ptr %__s1_812, align 16 # | %5 = load <4 x float>, ptr %__s2_812, align 16 # | store <4 x float> %5, ptr %__s0, align 16 # | %6 = load <16 x i8>, ptr %__s0, align 16 # | %7 = bitcast <16 x i8> %6 to <4 x float> # | %lane = shufflevector <4 x float> %7, <4 x float> %7, <4 x i32> # | store <4 x float> %lane, ptr %ref.tmp1, align 16 # | %8 = load <4 x float>, ptr %ref.tmp1, align 16 # | store <4 x float> %8, ptr %__ret, align 16 # | %9 = load <4 x float>, ptr %__ret, align 16 # | store <4 x float> %9, ptr %tmp, align 16 # | %10 = load <4 x float>, ptr %tmp, align 16 # | store <4 x float> %10, ptr %ref.tmp, align 16 # | %11 = load <8 x bfloat>, ptr %ref.tmp, align 16 # | store <4 x float> %3, ptr %__p0.addr.i, align 16 # | store <8 x bfloat> %4, ptr %__p1.addr.i, align 16 # | store <8 x bfloat> %11, ptr %__p2.addr.i, align 16 # | %12 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %13 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %14 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vbfdot.i = bitcast <16 x i8> %12 to <4 x float> # | %vbfdot1.i = bitcast <16 x i8> %13 to <8 x bfloat> # | %vbfdot2.i = bitcast <16 x i8> %14 to <8 x bfloat> # | %vbfdot3.i = call <4 x float> @llvm.aarch64.neon.bfdot.v4f32.v8bf16(<4 x float> %vbfdot.i, <8 x bfloat> %vbfdot1.i, <8 x bfloat> %vbfdot2.i) # | store <4 x float> %vbfdot3.i, ptr %ref.tmp.i, align 16 # | %15 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %15, ptr %__ret.i, align 16 # | %16 = load <4 x float>, ptr %__ret.i, align 16 # | store <4 x float> %16, ptr %__ret_812, align 16 # | %17 = load <4 x float>, ptr %__ret_812, align 16 # | store <4 x float> %17, ptr %tmp2, align 16 # | %18 = load <4 x float>, ptr %tmp2, align 16 # | ret <4 x float> %18 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vbfdot_laneq_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x bfloat>, align 8 # | %__p2.addr.i = alloca <4 x bfloat>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x float>, # | ... # `---data was truncated (10240/54685) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055be5778557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055be57782515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055be57785cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa124333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa12438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa124333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa12431b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055be5771b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055be5771b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055be576fff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055be573af176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055be573aee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa12431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa12431d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa12431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055be573aed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c (987 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f32.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f32.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vsc # | ... # `---data was truncated (10240/121179) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b85910457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b859101515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b859104cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbdaca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbdacaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbdaca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbdaca31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b85909a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b85909a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b85907ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b858d2e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b858d2de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbdaca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbdaca330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbdaca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b858d2dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c (988 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0. # | ... # `---data was truncated (10240/87884) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056128dfca57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056128dfc7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056128dfcacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe90fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe90faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe90fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe90fa31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056128df6024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056128df60096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056128df44f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056128dbf4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056128dbf3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe90fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe90fa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe90fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056128dbf3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c (989 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv16f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv16f16.f16.i64( poison, %0, half %1, i # | ... # `---data was truncated (10240/125641) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564be0ec057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564be0ebd515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564be0ec0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa516a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa516aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa516a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa516a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564be0e5624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564be0e56096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564be0e3af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564be0aea176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564be0ae9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa516a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa516a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa516a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564be0ae9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c (990 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf4_bf16mf2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv2bf16.nxv1bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2bf16.nxv1bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf4_bf16m1( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv4bf16.nxv1bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4bf16.nxv1bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf4_bf16m2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8bf16.nxv1bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8bf16.nxv1bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf4_bf16m4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16bf16.nxv1bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv1bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf4_bf16m8( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32bf16.nxv1bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv1bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf2_bf16m1( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv4bf16.nxv2bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4bf16.nxv2bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf2_bf16m2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8bf16.nxv2bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8bf16.nxv2bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf2_bf16m4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16bf16.nxv2bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv2bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf2_bf16m8( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32bf16.nxv2bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv2bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16m1_bf16m2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8bf16.nxv4bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16m1_bf16m4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16bf16.nxv4bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16m1_bf16m8( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16m2_bf16m4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16bf16.nxv8bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv8bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16m2_bf16m8( %value) #0 { # | entry: # | %value.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c (991 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056084fe1357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056084fe10515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056084fe13cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2305649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f23056a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2305649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2305631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056084fda924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056084fda9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056084fd8df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056084fa3d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056084fa3ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2305632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f23056330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f23056330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056084fa3cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c (992 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561c383b657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561c383b3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561c383b6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efdf2c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efdf2ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efdf2c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efdf2c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561c3834c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561c3834c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561c38330f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561c37fe0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561c37fdfe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efdf2c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efdf2c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efdf2c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561c37fdfd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c (993 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf8_f8e4m3mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf4_f8e4m3mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf2_f8e4m3mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m1_f8e4m3m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m2_f8e4m3m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m4_f8e4m3m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m8_f8e4m3m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3mf8_u8mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3mf4_u8mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3mf2_u8mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3m1_u8m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3m2_u8m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3m4_u8m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3m8_u8m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf8_f8e5m2mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf4_f8e5m2mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf2_f8e5m2mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m1_f8e5m2m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m2_f8e5m2m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m4_f8e5m2m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m8_f8e5m2m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2mf8_u8mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2mf4_u8mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2mf2_u8mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2m1_u8m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2m2_u8m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2m4_u8m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2m8_u8m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = # | ... # `---data was truncated (10240/10936) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564be753e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564be753b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564be753ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa501a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa501aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa501a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa501a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564be74d424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564be74d4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564be74b8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564be7168176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564be7167e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa501a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa501a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa501a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564be7167d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c (994 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16mf4_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16mf4_f32mf2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16mf2_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16mf2_f32m1( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16m1_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16m1_f32m2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16m2_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16m2_f32m4( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv. # | ... # `---data was truncated (10240/51804) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005574fcb2757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005574fcb24515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005574fcb27cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6698449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f66984a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6698449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6698431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005574fcabd24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005574fcabd096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005574fcaa1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005574fc751176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005574fc750e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6698432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f66984330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f66984330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005574fc750d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c (995 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m1x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_i64m1x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_i64m2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_u64m1x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_u64m2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056155eba757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056155eba4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056155eba7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2283133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f228318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2283133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f228311b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056155eb3d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056155eb3d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056155eb21f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056155e7d1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056155e7d0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f228311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f228311d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f228311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056155e7d0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c (996 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32mf2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m1( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m4( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i6 # | ... # `---data was truncated (10240/90867) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005597c180b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005597c1808515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005597c180bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6cce049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6cce0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6cce049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6cce031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005597c17a124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005597c17a1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005597c1785f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005597c1435176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005597c1434e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6cce032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6cce0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6cce0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005597c1434d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c (997 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf4x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf2x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m1x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m2x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m4x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m1x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwin # | ... # `---data was truncated (10240/13581) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fce092557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fce0922515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fce0925cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f22aad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f22aad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f22aad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f22aad1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fce08bb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fce08bb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fce089ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fce054f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fce054ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f22aad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f22aad1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f22aad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fce054ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c (998 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, a # | ... # `---data was truncated (10240/424843) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fbbb73057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fbbb72d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fbbb730cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0d7b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0d7b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0d7b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0d7b71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fbbb6c624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fbbb6c6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fbbb6aaf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fbbb35a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fbbb359e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0d7b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0d7b71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0d7b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fbbb359d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c (999 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte64_f64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vlte64.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte64_i64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte64_u64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556a9980757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556a99804515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556a99807cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0f6a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0f6a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0f6a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0f6a51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556a9979d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556a9979d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556a99781f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556a99431176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556a99430e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0f6a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0f6a51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0f6a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556a99430d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c (1000 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr # | ... # `---data was truncated (10240/97905) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055662b59257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055662b58f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055662b592cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f79d1133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f79d118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f79d1133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f79d111b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055662b52824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055662b528096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055662b50cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055662b1bc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055662b1bbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f79d111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f79d111d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f79d111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055662b1bbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c (1001 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define ds # | ... # `---data was truncated (10240/95215) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558d1254457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558d12541515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558d12544cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f32ba449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f32ba4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f32ba449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f32ba431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558d124da24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558d124da096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558d124bef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558d1216e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558d1216de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f32ba432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f32ba4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f32ba4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558d1216dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c (1002 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16m1x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562eea69657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562eea693515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562eea696cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f624c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f624c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f624c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f624c91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562eea62c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562eea62c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562eea610f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562eea2c0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562eea2bfe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f624c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f624c91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f624c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562eea2bfd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c (1003 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f64m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f64.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f64.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f64m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f64.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f64.p0.nxv2i64.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c (1004 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcadd_f16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fcadd.nxv8f16( %3, %4, %2, i32 90) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcadd.nxv8f16(, , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcadd_f16_z_1( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fcadd.nxv8f16( %3, %4, %2, i32 270) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcadd_f32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fcadd.nxv4f32( %3, %4, %2, i32 90) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcadd.nxv4f32(, , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcadd_f64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fcadd.nxv2f64( %3, %4, %2, i32 90) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcadd.nxv2f64(, , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcadd_f16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fcadd.nxv8f16( %3, %1, %2, i32 90) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcadd_f32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.fcadd.nxv4f32( %3, %1, %2, i32 90) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcadd_f64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.fcadd.nxv2f64( %3, %1, %2, i32 90) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcadd_f16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fcadd.nxv8f16( %3, %1, %2, i32 90) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcadd_f32_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.ad # | ... # `---data was truncated (10240/12234) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055e32551857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e325515515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e325518cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f76bcf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f76bcf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f76bcf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f76bcf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e3254ae24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e3254ae096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e325492f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e325142176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e325141e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f76bcf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f76bcf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f76bcf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e325141d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c (1005 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcreate_v_bf16m1_bf16m2( %v0, %v1) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = call @llvm.vector.insert.nxv8bf16.nxv4bf16( poison, %0, i64 0) # | %3 = call @llvm.vector.insert.nxv8bf16.nxv4bf16( %2, %1, i64 4) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcreate_v_bf16m1_bf16m4( %v0, %v1, %v2, %v3) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | %v2.addr = alloca , align 2 # | %v3.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | store %v2, ptr %v2.addr, align 2 # | store %v3, ptr %v3.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = load , ptr %v2.addr, align 2 # | %3 = load , ptr %v3.addr, align 2 # | %4 = call @llvm.vector.insert.nxv16bf16.nxv4bf16( poison, %0, i64 0) # | %5 = call @llvm.vector.insert.nxv16bf16.nxv4bf16( %4, %1, i64 4) # | %6 = call @llvm.vector.insert.nxv16bf16.nxv4bf16( %5, %2, i64 8) # | %7 = call @llvm.vector.insert.nxv16bf16.nxv4bf16( %6, %3, i64 12) # | ret %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcreate_v_bf16m1_bf16m8( %v0, %v1, %v2, %v3, %v4, %v5, %v6, %v7) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | %v2.addr = alloca , align 2 # | %v3.addr = alloca , align 2 # | %v4.addr = alloca , align 2 # | %v5.addr = alloca , align 2 # | %v6.addr = alloca , align 2 # | %v7.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | store %v2, ptr %v2.addr, align 2 # | store %v3, ptr %v3.addr, align 2 # | store %v4, ptr %v4.addr, align 2 # | store %v5, ptr %v5.addr, align 2 # | store %v6, ptr %v6.addr, align 2 # | store %v7, ptr %v7.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = load , ptr %v2.addr, align 2 # | %3 = load , ptr %v3.addr, align 2 # | %4 = load , ptr %v4.addr, align 2 # | %5 = load , ptr %v5.addr, align 2 # | %6 = load , ptr %v6.addr, align 2 # | %7 = load , ptr %v7.addr, align 2 # | %8 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( poison, %0, i64 0) # | %9 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( %8, %1, i64 4) # | %10 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( %9, %2, i64 8) # | %11 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( %10, %3, i64 12) # | %12 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( %11, %4, i64 16) # | %13 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( %12, %5, i64 20) # | %14 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( %13, %6, i64 24) # | %15 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( %14, %7, i64 28) # | ret %15 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcreate_v_bf16m2_bf16m4( %v0, %v1) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = call @llvm.vector.insert.nxv16bf16.nxv8bf16( poison, %0, i64 0) # | %3 = call @llvm.vector.insert.nxv16bf16.nxv8bf16( %2, %1, i64 8) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv8bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcreate_v_bf16m2_bf16m8( %v0, %v1, %v2, %v3) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | %v2.addr = alloca , align 2 # | %v3.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | store %v2, ptr %v2.addr, align 2 # | store %v3, ptr %v3.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = load , ptr %v2.addr, align 2 # | %3 = load , ptr %v3.addr, align 2 # | %4 = call @llvm.vector.insert.nxv32bf16.nxv8bf16( poison, %0, i64 0) # | %5 = call @llvm.vector.insert.nxv32bf16.nxv8bf16( %4, %1, i64 8) # | %6 = call @llvm.vector.insert.nxv32bf16.nxv8bf16( %5, %2, i64 16) # | %7 = call @llvm.vector.insert.nxv32bf16.nxv8bf16( %6, %3, i64 24) # | ret %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv8bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcreate_v_bf16m4_bf16m8( %v0, %v1) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32bf16.nxv16bf16( poison, %0, i64 0) # | %3 = call @llvm.vector.insert.nxv32bf16.nxv16bf16( %2, %1, i64 16) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv16bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vcreate_v_bf16mf4x2( %v0, %v1) #0 { # | entry: # | %v0.add # | ... # `---data was truncated (10240/71275) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bcf48df57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bcf48dc515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bcf48dfcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcc98e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcc98ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcc98e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcc98e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bcf487524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bcf4875096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bcf4859f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bcf4509176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bcf4508e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcc98e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcc98e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcc98e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bcf4508d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c (1006 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv8f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv16f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv32f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff. # | ... # `---data was truncated (10240/128424) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559e1f64257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559e1f63f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559e1f642cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd909a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd909a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd909a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd909a03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559e1f5d824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559e1f5d8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559e1f5bcf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559e1f26c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559e1f26be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd909a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd909a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd909a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559e1f26bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c (1007 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32mf2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m1( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m4( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m8( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32mf2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m1_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_ # | ... # `---data was truncated (10240/13617) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005606b6dd357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005606b6dd0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005606b6dd3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff18fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff18fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff18fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff18fd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005606b6d6924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005606b6d69096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005606b6d4df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005606b69fd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005606b69fce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff18fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff18fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff18fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005606b69fcd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c (1008 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7 # | ... # `---data was truncated (10240/64374) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557be3ea457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557be3ea1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557be3ea4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f886c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f886c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f886c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f886c71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557be3e3a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557be3e3a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557be3e1ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557be3ace176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557be3acde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f886c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f886c71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f886c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557be3acdd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c (1009 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16mf4_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16mf2_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m1_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m2_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m4_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv16f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv16f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m8_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv32f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv32f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32mf2_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load float, ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv1f32.f32.i64( %0, %1, float %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32m1_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load float, ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv2f32.f32.i64( %0, %1, float %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32m2_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/SystemZ/zvector.c (1010 of 27911) ******************** TEST 'Clang :: CodeGen/SystemZ/zvector.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple s390x-linux-gnu -target-cpu z13 -fzvector -emit-llvm -o - -W -Wall -Werror /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple s390x-linux-gnu -target-cpu z13 -fzvector -emit-llvm -o - -W -Wall -Werror /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c" # | target datalayout = "E-S64-m:e-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64" # | target triple = "s390x-unknown-linux-gnu" # | # | @sc2 = global <16 x i8> zeroinitializer, align 8 # | @sc = global <16 x i8> zeroinitializer, align 8 # | @uc2 = global <16 x i8> zeroinitializer, align 8 # | @uc = global <16 x i8> zeroinitializer, align 8 # | @ss2 = global <8 x i16> zeroinitializer, align 8 # | @ss = global <8 x i16> zeroinitializer, align 8 # | @us2 = global <8 x i16> zeroinitializer, align 8 # | @us = global <8 x i16> zeroinitializer, align 8 # | @si2 = global <4 x i32> zeroinitializer, align 8 # | @si = global <4 x i32> zeroinitializer, align 8 # | @ui2 = global <4 x i32> zeroinitializer, align 8 # | @ui = global <4 x i32> zeroinitializer, align 8 # | @sl2 = global <2 x i64> zeroinitializer, align 8 # | @sl = global <2 x i64> zeroinitializer, align 8 # | @ul2 = global <2 x i64> zeroinitializer, align 8 # | @ul = global <2 x i64> zeroinitializer, align 8 # | @slll2 = global <1 x i128> zeroinitializer, align 8 # | @slll = global <1 x i128> zeroinitializer, align 8 # | @ulll2 = global <1 x i128> zeroinitializer, align 8 # | @ulll = global <1 x i128> zeroinitializer, align 8 # | @fd2 = global <2 x double> zeroinitializer, align 8 # | @fd = global <2 x double> zeroinitializer, align 8 # | @bc2 = global <16 x i8> zeroinitializer, align 8 # | @bc = global <16 x i8> zeroinitializer, align 8 # | @bs2 = global <8 x i16> zeroinitializer, align 8 # | @bs = global <8 x i16> zeroinitializer, align 8 # | @bi2 = global <4 x i32> zeroinitializer, align 8 # | @bi = global <4 x i32> zeroinitializer, align 8 # | @bl2 = global <2 x i64> zeroinitializer, align 8 # | @bl = global <2 x i64> zeroinitializer, align 8 # | @blll2 = global <1 x i128> zeroinitializer, align 8 # | @blll = global <1 x i128> zeroinitializer, align 8 # | @cnt = global i32 0, align 4 # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @test_assign() #0 { # | entry: # | %0 = load volatile <16 x i8>, ptr @sc2, align 8 # | store volatile <16 x i8> %0, ptr @sc, align 8 # | %1 = load volatile <16 x i8>, ptr @uc2, align 8 # | store volatile <16 x i8> %1, ptr @uc, align 8 # | %2 = load volatile <8 x i16>, ptr @ss2, align 8 # | store volatile <8 x i16> %2, ptr @ss, align 8 # | %3 = load volatile <8 x i16>, ptr @us2, align 8 # | store volatile <8 x i16> %3, ptr @us, align 8 # | %4 = load volatile <4 x i32>, ptr @si2, align 8 # | store volatile <4 x i32> %4, ptr @si, align 8 # | %5 = load volatile <4 x i32>, ptr @ui2, align 8 # | store volatile <4 x i32> %5, ptr @ui, align 8 # | %6 = load volatile <2 x i64>, ptr @sl2, align 8 # | store volatile <2 x i64> %6, ptr @sl, align 8 # | %7 = load volatile <2 x i64>, ptr @ul2, align 8 # | store volatile <2 x i64> %7, ptr @ul, align 8 # | %8 = load volatile <1 x i128>, ptr @slll2, align 8 # | store volatile <1 x i128> %8, ptr @slll, align 8 # | %9 = load volatile <1 x i128>, ptr @ulll2, align 8 # | store volatile <1 x i128> %9, ptr @ulll, align 8 # | %10 = load volatile <2 x double>, ptr @fd2, align 8 # | store volatile <2 x double> %10, ptr @fd, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @test_pos() #0 { # | entry: # | %0 = load volatile <16 x i8>, ptr @sc2, align 8 # | store volatile <16 x i8> %0, ptr @sc, align 8 # | %1 = load volatile <16 x i8>, ptr @uc2, align 8 # | store volatile <16 x i8> %1, ptr @uc, align 8 # | %2 = load volatile <8 x i16>, ptr @ss2, align 8 # | store volatile <8 x i16> %2, ptr @ss, align 8 # | %3 = load volatile <8 x i16>, ptr @us2, align 8 # | store volatile <8 x i16> %3, ptr @us, align 8 # | %4 = load volatile <4 x i32>, ptr @si2, align 8 # | store volatile <4 x i32> %4, ptr @si, align 8 # | %5 = load volatile <4 x i32>, ptr @ui2, align 8 # | store volatile <4 x i32> %5, ptr @ui, align 8 # | %6 = load volatile <2 x i64>, ptr @sl2, align 8 # | store volatile <2 x i64> %6, ptr @sl, align 8 # | %7 = load volatile <2 x i64>, ptr @ul2, align 8 # | store volatile <2 x i64> %7, ptr @ul, align 8 # | %8 = load volatile <1 x i128>, ptr @slll2, align 8 # | store volatile <1 x i128> %8, ptr @slll, align 8 # | %9 = load volatile <1 x i128>, ptr @ulll2, align 8 # | store volatile <1 x i128> %9, ptr @ulll, align 8 # | %10 = load volatile <2 x double>, ptr @fd2, align 8 # | store volatile <2 x double> %10, ptr @fd, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @test_neg() #0 { # | entry: # | %0 = load volatile <16 x i8>, ptr @sc2, align 8 # | %sub = sub <16 x i8> zeroinitializer, %0 # | store volatile <16 x i8> %sub, ptr @sc, align 8 # | %1 = load volatile <8 x i16>, ptr @ss2, align 8 # | %sub1 = sub <8 x i16> zeroinitializer, %1 # | store volatile <8 x i16> %sub1, ptr @ss, align 8 # | %2 = load volatile <4 x i32>, ptr @si2, align 8 # | %sub2 = sub <4 x i32> zeroinitializer, %2 # | store volatile <4 x i32> %sub2, ptr @si, align 8 # | %3 = load volatile <2 x i64>, ptr @sl2, align 8 # | %sub3 = sub <2 x i64> zeroinitializer, %3 # | store volatile <2 x i64> %sub3, ptr @sl, align 8 # | %4 = load volatile <1 x i128>, ptr @slll2, align 8 # | %sub4 = sub <1 x i128> zeroinitializer, %4 # | store volatile <1 x i128> %sub4, ptr @slll, align 8 # | %5 = load volatile <2 x double>, ptr @fd2, align 8 # | %fneg = fneg <2 x double> %5 # | store volatile <2 x double> %fneg, ptr @fd, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @test_preinc() #0 { # | entry: # | %0 = load volatile <16 x i8>, ptr @sc2, align 8 # | %inc = add <16 x i8> %0, splat (i8 1) # | store volatile <16 x i8> %inc, ptr @sc2, align 8 # | %1 = load volatile <16 x i8>, ptr @uc2, align 8 # | %inc1 = add <16 x i8> %1, splat (i8 1) # | store volatile <16 x i8> %inc1, ptr @uc2, align 8 # | %2 = load volatile <8 x i16>, ptr @ss2, align 8 # | %inc2 = add <8 x i16> %2, splat (i16 1) # | store volatile <8 x i16> %inc2, ptr @ss2, align 8 # | %3 = load volatile <8 x i16>, ptr @us2, align 8 # | %inc3 = add <8 x i16> %3, splat (i16 1) # | store volatile <8 x i16> %inc3, ptr @us2, align 8 # | %4 = load volatile <4 x i32>, ptr @si2, align 8 # | %inc4 = add <4 x i32> %4, splat (i32 1) # | store volatile <4 x i32> %inc4, ptr @si2, align 8 # | %5 = load volatile <4 x i32>, ptr @ui2, align 8 # | %inc5 = add <4 x i32> %5, splat (i32 1) # | store volatile <4 x i32> %inc5, ptr @ui2, align 8 # | %6 = load volatile <2 x i64>, ptr @sl2, align 8 # | %inc6 = add <2 x i64> %6, splat (i64 1) # | store volatile <2 x i64> %inc6, ptr @sl2, align 8 # | %7 = load volatile <2 x i64>, ptr @ul2, align 8 # | %inc7 = add <2 x i64> %7, splat (i64 1) # | store volatile <2 x i64> %inc7, ptr @ul2, align 8 # | %8 = load volatile <1 x i128>, ptr @slll2, align 8 # | %inc8 = add <1 x i128> %8, splat (i128 1) # | store volatile <1 x i128> %inc8, ptr @slll2, align 8 # | %9 = load volatile <1 x i128>, ptr @ulll2, align 8 # | %inc9 = add <1 x i128> %9, splat (i128 1) # | store volatile <1 x i128> %inc9, ptr @ulll2, align 8 # | %10 = load volatile <2 x double>, ptr @fd2, align 8 # | %inc10 = fadd <2 x double> %10, splat (double 1.000000e+00) # | store volatile <2 x double> %inc10, ptr @fd2, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @test_postinc() #0 { # | entry: # | %0 = load volatile <16 x i8>, ptr @sc2, align 8 # | %inc = add <16 x i8> %0, splat (i8 1) # | store volatile <16 x i8> %inc, ptr @sc2, align 8 # | %1 = load volatile <16 x i8>, ptr @uc2, align 8 # | %inc1 = add <16 x i8> %1, splat (i8 1) # | store volatile <16 x i8> %inc1, ptr @uc2, align 8 # | %2 = load volatile <8 x i16>, ptr @ss2, align 8 # | %inc2 = add <8 x i16> %2, splat (i16 1) # | store volatile <8 x i16> %inc2, ptr @ss2, align 8 # | %3 = load volatile <8 x i16>, ptr @us2, align 8 # | %inc3 = add <8 x i16> %3, splat (i16 1) # | store volatile <8 x i16> %inc3, ptr @us2, align 8 # | %4 = load volatile <4 x i32>, ptr @si2, align 8 # | %inc4 = add <4 x i32> %4, splat (i32 1) # | store volatile <4 x i32> %inc4, ptr @si2, align 8 # | %5 = load volatile <4 x i32>, ptr @ui2, align 8 # | %inc5 = add <4 x i32> %5, splat (i32 1) # | store volatile <4 x i32> %inc5, ptr @ui2, align 8 # | %6 = load volatile <2 x i64>, ptr @sl2, align 8 # | %inc6 = add <2 x i64> %6, splat (i64 1) # | store volatile <2 x i64> %inc6, ptr @sl2, align 8 # | %7 = load volatile <2 x i64>, ptr @ul2, align 8 # | %inc7 = add <2 x i64> %7, splat (i64 1) # | store volatile <2 x i64> %inc7, ptr @ul2, align 8 # | %8 = load volatile <1 x i128>, ptr @slll2, align 8 # | %inc8 = add <1 x i128> %8, splat (i128 1) # | store volatile <1 x i128> %inc8, ptr @slll2, align 8 # | %9 = load volatile <1 x i128>, ptr @ulll2, align 8 # | %inc9 = add <1 x i128> %9, splat (i128 1) # | store volatile <1 x i128> %inc9, ptr @ulll2, align 8 # | %10 = load volatile <2 x double>, ptr @fd2, align 8 # | %inc10 = fadd <2 x double> %10, splat (double 1.000000e+00) # | store volatile <2 x double> %inc10, ptr @fd2, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @test_predec() #0 { # | entry: # | %0 = load volatile <16 x i8>, ptr @sc2, align 8 # | %dec = add <16 x i8> %0, splat (i8 -1) # | store volatile <16 x i8> %dec, ptr @sc2, align 8 # | %1 = load volatile <16 x i8>, ptr @uc2, align 8 # | %dec1 = add <16 x i8> %1, splat (i8 -1) # | store volatile <16 x i8> %dec1, ptr @uc2, align 8 # | %2 = load volatile <8 x i16>, ptr @ss2, align 8 # | %dec2 = add <8 x i16> %2, splat (i16 -1) # | store volatile <8 x i16> %dec2, ptr @ss2, align 8 # | %3 = load volatile <8 x i16>, ptr @us2, align 8 # | %dec3 = add <8 x i16> %3, splat (i16 -1) # | store volatile <8 x i16> %dec3, ptr @us2, align 8 # | %4 = load volatile <4 x i32>, ptr @si2, align 8 # | %dec4 = add <4 x i32> %4, splat (i32 -1) # | store volatile <4 x i32> %dec4, ptr @si2, align 8 # | %5 = load volatile <4 x i32>, ptr @ui2, align 8 # | %dec5 = add <4 x i32> %5, splat (i32 -1) # | store volatile <4 x i32> %dec5, ptr @ui2, align 8 # | %6 = load volatile <2 x i64>, ptr @sl2, align 8 # | %dec6 = add <2 x i64> %6, splat (i64 -1) # | store volatile <2 x i64> %dec6, ptr @sl2, align 8 # | %7 = load volatile <2 x i64>, ptr @ul2, align 8 # | %dec7 = add <2 x i64> %7, splat (i64 -1) # | store volatile <2 x i64> %dec7, ptr @ul2, align 8 # | %8 = load volatile <1 x i128>, ptr @slll2, align 8 # | %dec8 = add <1 x i128> %8, splat (i128 -1) # | store volatile <1 x i128> %dec8, ptr @slll2, align 8 # | %9 = load volatile <1 x i128>, ptr @ulll2, align 8 # | %dec # | ... # `---data was truncated (10240/152876) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a81593157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a81592e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a815931cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f380ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f380caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f380ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f380ca31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a8158c724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a8158c7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a8158abf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a81555b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a81555ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f380ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f380ca330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f380ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a81555ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c (1011 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_i8mf8x8_tu(target("riscv.vector.tuple", , 8) %m # | ... # `---data was truncated (10240/160133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005558f7def57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005558f7dec515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005558f7defcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9b6241bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9b624725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9b6241ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9b62403507 abort ./stdlib/abort.c:85:3 # | #7 0x00005558f7d8524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005558f7d85096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005558f7d69f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005558f7a19176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005558f7a18e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9b62404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9b624050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9b624050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005558f7a18d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c (1012 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple # | ... # `---data was truncated (10240/108848) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556c9f61857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556c9f615515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556c9f618cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f20c141bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f20c14725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f20c141ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f20c1403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556c9f5ae24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556c9f5ae096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556c9f592f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556c9f242176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556c9f241e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f20c1404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f20c14050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f20c14050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556c9f241d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c (1013 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqinch_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqinch.n32(i32 %0, i32 31, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqinch.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqinch_n_s32_1(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqinch.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqinch_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqinch.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqinch.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqinch_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqinch.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqinch.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqinch_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqinch.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uqinch.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqinch_pat_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqinch.n32(i32 %0, i32 30, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqinch_pat_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqinch.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqinch_pat_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqinch.n32(i32 %0, i32 0, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqinch_pat_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqinch.n64(i64 %0, i32 1, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqinch_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqinch.nxv8i16( %0, i32 31, i32 16) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqinch.nxv8i16(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqinch_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqinch.nxv8i16( %0, i32 31, i32 1) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqinch.nxv8i16(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqinch_pat_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqinch.nxv8i16( %0, i32 2, i32 16) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqinch_pat_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqinch.nxv8i16( %0, i32 3, i32 1) # | ret %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005582629df57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005582629dc515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005582629dfcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd14cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd14cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd14cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd14cb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055826297524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558262975096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558262959f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558262609176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558262608e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd14cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd14cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd14cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558262608d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c (1014 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c (1015 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv # | ... # `---data was truncated (10240/25519) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b7c747d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b7c747a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b7c747dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f64d2a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f64d2aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f64d2a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f64d2a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b7c741324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b7c7413096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b7c73f7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b7c70a7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b7c70a6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f64d2a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f64d2a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f64d2a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b7c70a6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c (1016 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv2f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32m2_tu # | ... # `---data was truncated (10240/288275) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055575001557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555750012515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555750015cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f41b7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f41b778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f41b7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f41b771b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055574ffab24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055574ffab096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055574ff8ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055574fc3f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055574fc3ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f41b771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f41b771d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f41b771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055574fc3ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c (1017 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f64m1x4(ptr noundef %base, %binde # | ... # `---data was truncated (10240/94227) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055584afa657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055584afa3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055584afa6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f53de505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f53de55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f53de505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f53de4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055584af3c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055584af3c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055584af20f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055584abd0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055584abcfe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f53de4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f53de4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f53de4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055584abcfd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c (1018 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf8_f8e4m3mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf4_f8e4m3mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf2_f8e4m3mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m1_f8e4m3m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m2_f8e4m3m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m4_f8e4m3m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m8_f8e4m3m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3mf8_u8mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3mf4_u8mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3mf2_u8mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3m1_u8m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3m2_u8m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3m4_u8m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3m8_u8m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf8_f8e5m2mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf4_f8e5m2mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf2_f8e5m2mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m1_f8e5m2m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m2_f8e5m2m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m4_f8e5m2m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m8_f8e5m2m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2mf8_u8mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2mf4_u8mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2mf2_u8mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2m1_u8m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2m2_u8m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2m4_u8m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2m8_u8m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align # | ... # `---data was truncated (10240/10944) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005573c015857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005573c0155515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005573c0158cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f947fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f947fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f947fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f947fc31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005573c00ee24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005573c00ee096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005573c00d2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005573bfd82176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005573bfd81e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f947fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f947fc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f947fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005573bfd81d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c (1019 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_i8mf8x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_i8mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_i8mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_i8m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_i8m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_u8mf8x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_u8mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_u8mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_u8m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/26713) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005565960f857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005565960f5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005565960f8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4fef933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4fef98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4fef933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4fef91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055659608e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055659608e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556596072f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556595d22176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556595d21e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4fef91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4fef91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4fef91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556595d21d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c (1020 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf8_tu( %maskedoff, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf4_tu( %maskedoff, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf2_tu( %maskedoff, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8m1_tu( %maskedoff, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | # | ... # `---data was truncated (10240/223129) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c574b2757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c574b24515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c574b27cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4796b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4796b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4796b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4796b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c574abd24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c574abd096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c574aa1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c574751176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c574750e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4796b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4796b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4796b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c574750d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c (1021 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16mf4_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16mf2_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16m1_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16m2_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c (1022 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_2x1_za32_s8_s8( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.smop4a.wide.2x1.nxv16i8(i32 1, %3, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smop4a.wide.2x1.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_2x1_za32_s8_s8( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.smop4s.wide.2x1.nxv16i8(i32 1, %3, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smop4s.wide.2x1.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_2x1_za32_u8_u8( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.umop4a.wide.2x1.nxv16i8(i32 1, %3, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umop4a.wide.2x1.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_2x1_za32_u8_u8( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.umop4s.wide.2x1.nxv16i8(i32 1, %3, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umop4s.wide.2x1.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_2x1_za32_s8_u8( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.sumop4a.wide.2x1.nxv16i8(i32 1, %3, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.sumop4a.wide.2x1.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_2x1_za32_s8_u8( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.sumop4s.wide.2x1.nxv16i8(i32 1, %3, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.sumop4s.wide.2x1.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_2x1_za32_u8_s8( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { < # | ... # `---data was truncated (10240/50499) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005568ae99a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005568ae997515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005568ae99acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f532c21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f532c2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f532c21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f532c203507 abort ./stdlib/abort.c:85:3 # | #7 0x00005568ae93024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005568ae930096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005568ae914f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005568ae5c4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005568ae5c3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f532c204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f532c2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f532c2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005568ae5c3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c (1023 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2q.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2q.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2q.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2q.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2q.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2q.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2q.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_bf16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2q.nxv8bf16(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055c8ce4f357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c8ce4f0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c8ce4f3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3e3fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3e3fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3e3fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3e3fc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c8ce48924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c8ce489096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c8ce46df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c8ce11d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c8ce11ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3e3fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3e3fc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3e3fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c8ce11cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c (1024 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_i64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_u64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_f64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_i64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_u64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_f64m1x6_tumu( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target(" # | ... # `---data was truncated (10240/18506) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005604e351d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005604e351a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005604e351dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1a5f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1a5f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1a5f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1a5f31b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005604e34b324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005604e34b3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005604e3497f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005604e3147176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005604e3146e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1a5f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1a5f31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1a5f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005604e3146d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c (1025 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align # | ... # `---data was truncated (10240/94149) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562c9680157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562c967fe515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562c96801cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9183733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f918378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9183733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f918371b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562c9679724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562c96797096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562c9677bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562c9642b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562c9642ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f918371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f918371d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f918371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562c9642ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c (1026 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16mf4(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16mf2(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m1(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m2(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m4(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv16bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv16bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m8(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv32bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv32bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16mf4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.mask.nxv1bf16.p0.i64( %3, ptr %1, i64 %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.mask.nxv1bf16.p0.i64(, ptr captures(none), i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16mf2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.mask.nxv2bf16.p0.i64( %3, ptr %1, i64 %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.mask.nxv2bf16.p0.i64(, ptr captures(none), i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m1_m( %vm, ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.mask.nxv4bf16.p0.i64( %3, ptr %1, i64 %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.mask.nxv4bf16.p0.i64(, ptr captures(none), i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, %vs3 # | ... # `---data was truncated (10240/14330) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f81118857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f811185515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f811188cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2d29333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2d2938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2d29333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2d2931b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f81111e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f81111e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f811102f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f810db2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f810db1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2d2931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2d2931d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2d2931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f810db1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c (1027 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64( %0, %1, bf # | ... # `---data was truncated (10240/65202) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ee7cfcc57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ee7cfc9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ee7cfcccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6721449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f67214a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6721449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6721431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ee7cf6224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ee7cf62096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ee7cf46f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ee7cbf6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ee7cbf5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6721432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f67214330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f67214330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ee7cbf5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c (1028 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f32m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_t # | ... # `---data was truncated (10240/128436) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b58039657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b580393515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b580396cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcfb6333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcfb638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcfb6333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcfb631b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b58032c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b58032c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b580310f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b57ffc0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b57ffbfe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcfb631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcfb631d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcfb631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b57ffbfd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c (1029 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055de57abe57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055de57abb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055de57abecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdc32533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdc3258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdc32533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdc3251b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055de57a5424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055de57a54096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055de57a38f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055de576e8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055de576e7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fdc3251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdc3251d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdc3251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055de576e7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c (1030 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_i8mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef # | ... # `---data was truncated (10240/69988) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005640d6c5f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005640d6c5c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005640d6c5fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f223fe1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f223fe725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f223fe1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f223fe03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005640d6bf524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005640d6bf5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005640d6bd9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005640d6889176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005640d6888e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f223fe04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f223fe050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f223fe050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005640d6888d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c (1031 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv2f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv4f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv8f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv16f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv32f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv2f32.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv4f32.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv8f32.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv16f32.nxv8f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv16f32.nxv8f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f64m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | sto # | ... # `---data was truncated (10240/102864) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ff0226057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ff0225d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ff02260cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa5f1333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa5f138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa5f1333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa5f131b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ff021f624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ff021f6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ff021daf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ff01e8a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ff01e89e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa5f131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa5f131d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa5f131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ff01e89d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c (1032 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16mf4_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16mf2_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m1_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv4f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv4f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m2_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv8f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv8f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m4_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv16f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv16f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m8_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv32f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv32f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32mf2_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1f32.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32m1_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2f32.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32m2_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, ali # | ... # `---data was truncated (10240/280217) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d33e88257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d33e87f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d33e882cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fed13649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fed136a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fed13649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fed13631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d33e81824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d33e818096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d33e7fcf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d33e4ac176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d33e4abe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fed13632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fed136330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fed136330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d33e4abd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c (1033 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32m2x4_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c (1034 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf8( %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf4( %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf2( %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8m1( %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8m2( %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64 # | ... # `---data was truncated (10240/97248) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559d6c97457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559d6c971515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559d6c974cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1569b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1569b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1569b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1569b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559d6c90a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559d6c90a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559d6c8eef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559d6c59e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559d6c59de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1569b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1569b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1569b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559d6c59dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c (1035 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_f64m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_i64m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_u64m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_f64m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_i64m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_u64m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055596a59357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055596a590515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055596a593cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fda9eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fda9eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fda9eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fda9eb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055596a52924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055596a529096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055596a50df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055596a1bd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055596a1bce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fda9eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fda9eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fda9eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055596a1bcd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c (1036 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.sxth.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sxth.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.sxth.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sxth.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_u32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.uxth.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uxth.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.uxth.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uxth.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.sxth.nxv4i32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_s64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.sxth.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_u32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.uxth.nxv4i32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_u64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.uxth.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_s32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.sxth.nxv4i32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_s64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.sxth.nxv2i64( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_u32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, # | ... # `---data was truncated (10240/11908) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055960a5cd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055960a5ca515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055960a5cdcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fde40449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fde404a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fde40449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fde40431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055960a56324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055960a563096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055960a547f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055960a1f7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055960a1f6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fde40432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fde404330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fde404330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055960a1f6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c (1037 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv1i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv1i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv2i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv2i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv4i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv4i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv8i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv8i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv16i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv16i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; # | ... # `---data was truncated (10240/100289) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056130484557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561304842515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561304845cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9738933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f973898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9738933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f973891b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005613047db24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005613047db096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005613047bff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056130446f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056130446ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f973891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f973891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f973891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056130446ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c (1038 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564557c1e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564557c1b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564557c1ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc2bdd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc2bdd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc2bdd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc2bdd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564557bb424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564557bb4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564557b98f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564557848176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564557847e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc2bdd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc2bdd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc2bdd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564557847d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c (1039 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005562b7b4557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005562b7b42515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005562b7b45cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6f7b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6f7b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6f7b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6f7b431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005562b7adb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005562b7adb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005562b7abff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005562b776f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005562b776ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6f7b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6f7b4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6f7b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005562b776ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c (1040 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16mf4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f64m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f64m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv2f64.nxv4f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2f64.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f64m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv4f64.nxv8f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4f64.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @ # | ... # `---data was truncated (10240/35774) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005649d66b357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005649d66b0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005649d66b3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efc88b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efc88b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efc88b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efc88b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005649d664924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005649d6649096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005649d662df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005649d62dd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005649d62dce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efc88b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efc88b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efc88b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005649d62dcd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c (1041 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16mf4x8(ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16mf2x8(ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16m1x8(ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16m1x8_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e3106e957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e3106e6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e3106e9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7d3941bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7d394725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7d3941ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7d39403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e31067f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e31067f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e310663f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e310313176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e310312e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7d39404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7d394050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7d394050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e310312d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c (1042 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt1_bf16_mf8( %zn, i64 noundef %fpm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %1) # | %2 = call @llvm.aarch64.sve.fp8.cvt1.nxv8bf16( %0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvt1.nxv8bf16() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt2_bf16_mf8( %zn, i64 noundef %fpm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %1) # | %2 = call @llvm.aarch64.sve.fp8.cvt2.nxv8bf16( %0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvt2.nxv8bf16() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvtlt1_bf16_mf8( %zn, i64 noundef %fpm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %1) # | %2 = call @llvm.aarch64.sve.fp8.cvtlt1.nxv8bf16( %0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvtlt1.nxv8bf16() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvtlt2_bf16_mf8( %zn, i64 noundef %fpm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %1) # | %2 = call @llvm.aarch64.sve.fp8.cvtlt2.nxv8bf16( %0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvtlt2.nxv8bf16() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt1_f16_mf8( %zn, i64 noundef %fpm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %1) # | %2 = call @llvm.aarch64.sve.fp8.cvt1.nxv8f16( %0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvt1.nxv8f16() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt2_f16_mf8( %zn, i64 noundef %fpm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %1) # | %2 = call @llvm.aarch64.sve.fp8.cvt2.nxv8f16( %0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvt2.nxv8f16() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvtlt1_f16_mf8( %zn, i64 noundef %fpm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %1) # | %2 = call @llvm.aarch64.sve.fp8.cvtlt1.nxv8f16( %0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvtlt1.nxv8f16() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvtlt2_f16_mf8( %zn, i64 noundef %fpm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %1) # | %2 = call @llvm.aarch64.sve.fp8.cvtlt2.nxv8f16( %0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvtlt2.nxv8f16() #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp8,+sve,+sve2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055bb1821857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bb18215515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bb18218cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbc31933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbc3198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbc31933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbc3191b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bb181ae24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bb181ae096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bb18192f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bb17e42176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bb17e41e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbc3191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbc3191d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbc3191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bb17e41d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/builtins-arm.c (1043 of 27911) ******************** TEST 'Clang :: CodeGen/builtins-arm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple thumbv7-eabi -target-cpu cortex-a8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple thumbv7-eabi -target-cpu cortex-a8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv7-unknown-unknown-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local ptr @f0() #0 { # | entry: # | %0 = call ptr @llvm.thread.pointer.p0() # | ret ptr %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ptr @llvm.thread.pointer.p0() #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @f1(ptr noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 4 # | %b.addr = alloca ptr, align 4 # | store ptr %a, ptr %a.addr, align 4 # | store ptr %b, ptr %b.addr, align 4 # | %0 = load ptr, ptr %a.addr, align 4 # | %1 = load ptr, ptr %b.addr, align 4 # | call void @llvm.clear_cache.p0(ptr %0, ptr %1) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.clear_cache.p0(ptr, ptr) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vcvtrf0(float noundef %f) #0 { # | entry: # | %f.addr = alloca float, align 4 # | store float %f, ptr %f.addr, align 4 # | %0 = load float, ptr %f.addr, align 4 # | %vcvtr = call float @llvm.arm.vcvtr.f32(float %0) # | ret float %vcvtr # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.arm.vcvtr.f32(float) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vcvtrf1(float noundef %f) #0 { # | entry: # | %f.addr = alloca float, align 4 # | store float %f, ptr %f.addr, align 4 # | %0 = load float, ptr %f.addr, align 4 # | %vcvtr = call float @llvm.arm.vcvtru.f32(float %0) # | ret float %vcvtr # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.arm.vcvtru.f32(float) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_vcvtrd0(double noundef %d) #0 { # | entry: # | %d.addr = alloca double, align 8 # | store double %d, ptr %d.addr, align 8 # | %0 = load double, ptr %d.addr, align 8 # | %vcvtr = call float @llvm.arm.vcvtr.f64(double %0) # | %conv = fpext float %vcvtr to double # | ret double %conv # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.arm.vcvtr.f64(double) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_vcvtrd1(double noundef %d) #0 { # | entry: # | %d.addr = alloca double, align 8 # | store double %d, ptr %d.addr, align 8 # | %0 = load double, ptr %d.addr, align 8 # | %vcvtr = call float @llvm.arm.vcvtru.f64(double %0) # | %conv = fpext float %vcvtr to double # | ret double %conv # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.arm.vcvtru.f64(double) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_eh_return_data_regno() #0 { # | entry: # | %res = alloca i32, align 4 # | store volatile i32 0, ptr %res, align 4 # | store volatile i32 1, ptr %res, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @nop() #0 { # | entry: # | call void @llvm.arm.hint(i32 0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.hint(i32) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @yield() #0 { # | entry: # | call void @llvm.arm.hint(i32 1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @wfe() #0 { # | entry: # | call void @llvm.arm.hint(i32 2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @wfi() #0 { # | entry: # | call void @llvm.arm.hint(i32 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @sev() #0 { # | entry: # | call void @llvm.arm.hint(i32 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @sevl() #0 { # | entry: # | call void @llvm.arm.hint(i32 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @dbg() #0 { # | entry: # | call void @llvm.arm.dbg(i32 0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.dbg(i32) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_barrier() #0 { # | entry: # | call void @llvm.arm.dmb(i32 1) # | call void @llvm.arm.dsb(i32 2) # | call void @llvm.arm.isb(i32 3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.dmb(i32) #2 # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.dsb(i32) #2 # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.isb(i32) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @rbit(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %rbit = call i32 @llvm.bitreverse.i32(i32 %0) # | ret i32 %rbit # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.bitreverse.i32(i32) #3 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @prefetch(i32 noundef %i) #0 { # | entry: # | %i.addr = alloca i32, align 4 # | store i32 %i, ptr %i.addr, align 4 # | call void @llvm.prefetch.p0(ptr %i.addr, i32 0, i32 3, i32 1) # | call void @llvm.prefetch.p0(ptr %i.addr, i32 1, i32 3, i32 1) # | call void @llvm.prefetch.p0(ptr %i.addr, i32 1, i32 3, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) # | declare void @llvm.prefetch.p0(ptr readonly captures(none), i32 immarg range(i32 0, 2), i32 immarg range(i32 0, 4), i32 immarg range(i32 0, 2)) #4 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @ldc(ptr noundef %i) #0 { # | entry: # | %i.addr = alloca ptr, align 4 # | store ptr %i, ptr %i.addr, align 4 # | %0 = load ptr, ptr %i.addr, align 4 # | call void @llvm.arm.ldc(i32 1, i32 2, ptr %0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.ldc(i32 immarg, i32 immarg, ptr) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @ldcl(ptr noundef %i) #0 { # | entry: # | %i.addr = alloca ptr, align 4 # | store ptr %i, ptr %i.addr, align 4 # | %0 = load ptr, ptr %i.addr, align 4 # | call void @llvm.arm.ldcl(i32 1, i32 2, ptr %0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.ldcl(i32 immarg, i32 immarg, ptr) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @ldc2(ptr noundef %i) #0 { # | entry: # | %i.addr = alloca ptr, align 4 # | store ptr %i, ptr %i.addr, align 4 # | %0 = load ptr, ptr %i.addr, align 4 # | call void @llvm.arm.ldc2(i32 1, i32 2, ptr %0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.ldc2(i32 immarg, i32 immarg, ptr) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @ldc2l(ptr noundef %i) #0 { # | entry: # | %i.addr = alloca ptr, align 4 # | store ptr %i, ptr %i.addr, align 4 # | %0 = load ptr, ptr %i.addr, align 4 # | call void @llvm.arm.ldc2l(i32 1, i32 2, ptr %0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.ldc2l(i32 immarg, i32 immarg, ptr) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @stc(ptr noundef %i) #0 { # | entry: # | %i.addr = alloca ptr, align 4 # | store ptr %i, ptr %i.addr, align 4 # | %0 = load ptr, ptr %i.addr, align 4 # | call void @llvm.arm.stc(i32 1, i32 2, ptr %0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.stc(i32 immarg, i32 immarg, ptr) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @stcl(ptr noundef %i) #0 { # | entry: # | %i.addr = alloca ptr, align 4 # | store ptr %i, ptr %i.addr, align 4 # | %0 = load ptr, ptr %i.addr, align 4 # | call void @llvm.arm.stcl(i32 1, i32 2, ptr %0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.stcl(i32 immarg, i32 immarg, ptr) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @stc2(ptr noundef %i) #0 { # | entry: # | %i.addr = alloca ptr, align 4 # | store ptr %i, ptr %i.addr, align 4 # | %0 = load ptr, ptr %i.addr, align 4 # | call void @llvm.arm.stc2(i32 1, i32 2, ptr %0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.stc2(i32 immarg, i32 immarg, ptr) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @stc2l(ptr noundef %i) #0 { # | entry: # | %i.addr = alloca ptr, align 4 # | store ptr %i, ptr %i.addr, align 4 # | %0 = load ptr, ptr %i.addr, align 4 # | call void @llvm.arm.stc2l(i32 1, i32 2, ptr %0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.stc2l(i32 immarg, i32 immarg, ptr) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @cdp() #0 { # | entry: # | call void @llvm.arm.cdp(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.cdp(i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @cdp2() #0 { # | entry: # | call void @llvm.arm.cdp2(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.cdp2(i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @mrc() #0 { # | entry: # | %0 = call i32 @llvm.arm.mrc(i32 15, i32 0, i32 13, i32 0, i32 3) # | ret i32 %0 # | } # | # | ; Function Attrs: nounwind # | declare i32 @llvm.arm.mrc(i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @mrc2() #0 { # | entry: # | %0 = call i32 @llvm.arm.mrc2(i32 15, i32 0, i32 13, i32 0, i32 3) # | ret i32 %0 # | } # | # | ; Function Attrs: nounwind # | declare i32 @llvm.arm.mrc2(i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @mcr(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | call void @llvm.arm.mcr(i32 15, i32 0, i32 %0, i32 13, i32 0, i32 3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.mcr(i32 immarg, i32 immarg, i32, i32 immarg, i32 immarg, i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @mcr2(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | call void @llvm.arm.mcr2(i32 15, i32 0, i32 %0, i32 13, i32 0, i32 3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.mcr2(i32 immarg, i32 immarg, i32, i32 immarg, i32 immarg, i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_lo # | ... # `---data was truncated (10240/15632) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005555d262857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005555d2625515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005555d2628cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f062db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f062db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f062db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f062db1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005555d25be24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005555d25be096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005555d25a2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005555d2252176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005555d2251e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f062db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f062db1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f062db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005555d2251d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c (1044 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_i64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_i64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_u64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_u64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m1x4_tum( %mask, target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local t # | ... # `---data was truncated (10240/36031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005592c7a8157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005592c7a7e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005592c7a81cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feeca449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feeca4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feeca449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feeca431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005592c7a1724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005592c7a17096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005592c79fbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005592c76ab176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005592c76aae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007feeca432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feeca4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feeca4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005592c76aad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c (1045 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr % # | ... # `---data was truncated (10240/20631) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005563842b257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005563842af515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005563842b2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f76a7e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f76a7e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f76a7e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f76a7e03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055638424824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556384248096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055638422cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556383edc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556383edbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f76a7e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f76a7e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f76a7e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556383edbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c (1046 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u8mf8( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv1i8.nxv1i8.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv1i8.nxv1i8.i32(i32 immarg, i32 immarg, , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u8mf4( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv2i8.nxv2i8.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv2i8.nxv2i8.i32(i32 immarg, i32 immarg, , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u8mf2( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv4i8.nxv4i8.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv4i8.nxv4i8.i32(i32 immarg, i32 immarg, , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u8m1( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv8i8.nxv8i8.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv8i8.nxv8i8.i32(i32 immarg, i32 immarg, , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u8m2( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv16i8.nxv16i8.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv16i8.nxv16i8.i32(i32 immarg, i32 immarg, , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u8m4( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv32i8.nxv32i8.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv32i8.nxv32i8.i32(i32 immarg, i32 immarg, , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u8m8( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv64i8.nxv64i8.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv64i8.nxv64i8.i32(i32 immarg, i32 immarg, , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u16mf4( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv1i16.nxv1i16.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv1i16.nxv1i16.i32(i32 immarg, i32 immarg, , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u16mf2( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv2i16.nxv2i16.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv2i16.nxv2i16.i32(i32 immarg, i32 immarg, , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u16m1( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv4i16.nxv4i16.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv4i16.nxv4i16.i32(i32 immarg, i32 immarg, , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u16m2( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv8i16.nxv8i16.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function # | ... # `---data was truncated (10240/200802) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056188d3fd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056188d3fa515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056188d3fdcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efd5c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efd5c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efd5c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efd5c31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056188d39324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056188d393096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056188d377f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056188d027176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056188d026e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efd5c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efd5c31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efd5c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056188d026d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c (1047 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf8x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv1i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv1i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf4x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf2x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf8x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv1i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf4x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf2x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/12668) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560a90bda57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560a90bd7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560a90bdacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa776449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa7764a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa776449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa776431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560a90b7024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560a90b70096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560a90b54f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560a90804176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560a90803e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa776432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa7764330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa7764330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560a90803d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c (1048 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564a5e73557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564a5e732515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564a5e735cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fecbdc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fecbdca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fecbdc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fecbdc31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564a5e6cb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564a5e6cb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564a5e6aff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564a5e35f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564a5e35ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fecbdc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fecbdc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fecbdc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564a5e35ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c (1049 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056351e37557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056351e372515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056351e375cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8663933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f866398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8663933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f866391b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056351e30b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056351e30b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056351e2eff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056351df9f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056351df9ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f866391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f866391d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f866391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056351df9ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c (1050 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m1_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv1i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv2i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m4_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv4i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m8_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv8i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m1_tum( %mask, %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = all # | ... # `---data was truncated (10240/41587) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557fa33f557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557fa33f2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557fa33f5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcf3a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcf3a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcf3a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcf3a31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557fa338b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557fa338b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557fa336ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557fa301f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557fa301ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcf3a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcf3a31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcf3a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557fa301ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c (1051 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_u16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca # | ... # `---data was truncated (10240/60551) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563ce9ee357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563ce9ee0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563ce9ee3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2efb849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2efb8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2efb849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2efb831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563ce9e7924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563ce9e79096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563ce9e5df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563ce9b0d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563ce9b0ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2efb832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2efb8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2efb8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563ce9b0cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c (1052 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf4x5_tumu( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 0, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector. # | ... # `---data was truncated (10240/16808) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055edbaada57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055edbaad7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055edbaadacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4f22849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4f228a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4f22849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4f22831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055edbaa7024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055edbaa70096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055edbaa54f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055edba704176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055edba703e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4f22832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4f228330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4f228330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055edba703d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c (1053 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_v # | ... # `---data was truncated (10240/228865) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fbf8bd357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fbf8bd0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fbf8bd3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f04dec1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f04dec725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f04dec1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f04dec03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fbf8b6924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fbf8b69096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fbf8b4df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fbf87fd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fbf87fce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f04dec04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f04dec050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f04dec050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fbf87fcd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c (1054 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563da83e557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563da83e2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563da83e5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2186c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2186ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2186c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2186c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563da837b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563da837b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563da835ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563da800f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563da800ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2186c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2186c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2186c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563da800ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c (1055 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c (1056 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_u_s_w4_u8m8_i8m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.u.s.i64.nxv64i8.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.u.s.i64.nxv64i8.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f55838c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f558389515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f55838ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbf74733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbf7478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbf74733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbf7471b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f55832224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f558322096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f558306f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f557fb6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f557fb5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbf7471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbf7471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbf7471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f557fb5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c (1057 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv1i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv2i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv4i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv8i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv16i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv32i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv64i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf8_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf4_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf2_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret # | ... # `---data was truncated (10240/29371) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055762519557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557625192515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557625195cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4079e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4079ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4079e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4079e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055762512b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055762512b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055762510ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557624dbf176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557624dbee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4079e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4079e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4079e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557624dbed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c (1058 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_v # | ... # `---data was truncated (10240/228865) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e56145157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e56144e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e561451cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd960f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd960f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd960f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd960f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e5613e724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e5613e7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e5613cbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e56107b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e56107ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd960f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd960f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd960f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e56107ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c (1059 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_i8mf4x6(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562f598df57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562f598dc515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562f598dfcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f673d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f673d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f673d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f673d31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562f5987524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562f59875096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562f59859f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562f59509176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562f59508e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f673d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f673d31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f673d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562f59508d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c (1060 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_f64m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_i64m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_u64m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_f64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_i64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_u64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a57520857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a575205515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a575208cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe9ed049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe9ed0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe9ed049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe9ed031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a57519e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a57519e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a575182f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a574e32176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a574e31e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe9ed032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe9ed0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe9ed0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a574e31d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c (1061 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", # | ... # `---data was truncated (10240/19492) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a79291b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a792918515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a79291bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc9e1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc9e178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc9e1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc9e171b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a7928b124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a7928b1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a792895f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a792545176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a792544e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc9e171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc9e171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc9e171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a792544d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c (1062 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = al # | ... # `---data was truncated (10240/97675) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cc58c8457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cc58c81515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cc58c84cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa64f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa64f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa64f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa64f031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cc58c1a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cc58c1a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cc58bfef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cc588ae176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cc588ade93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa64f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa64f0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa64f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cc588add81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c (1063 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16m2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.add # | ... # `---data was truncated (10240/153913) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e9455da57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e9455d7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e9455dacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff2af649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff2af6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff2af649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff2af631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e94557024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e945570096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e945554f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e945204176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e945203e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff2af632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff2af6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff2af6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e945203d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c (1064 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | # | ... # `---data was truncated (10240/23255) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556ea807c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556ea8079515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556ea807ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f727cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f727cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f727cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f727cb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556ea801224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556ea8012096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556ea7ff6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556ea7ca6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556ea7ca5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f727cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f727cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f727cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556ea7ca5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c (1065 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16mf4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16mf4( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16mf2( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16m1( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16m2( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, ali # | ... # `---data was truncated (10240/58334) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555e6bf8357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555e6bf80515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555e6bf83cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f31daf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f31daf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f31daf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f31daf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555e6bf1924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555e6bf19096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555e6befdf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555e6bbad176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555e6bbace93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f31daf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f31daf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f31daf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555e6bbacd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c (1066 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf8x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8mf8x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_ # | ... # `---data was truncated (10240/23574) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c0f3bc957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c0f3bc6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c0f3bc9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f014a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f014a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f014a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f014a91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c0f3b5f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c0f3b5f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c0f3b43f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c0f37f3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c0f37f2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f014a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f014a91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f014a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c0f37f2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c (1067 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvw_se_u8mf8( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvw.se.i32.nxv1i16.nxv1i8.nxv1i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv1i16.nxv1i8.nxv1i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvw_se_u8mf4( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvw.se.i32.nxv2i16.nxv2i8.nxv2i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv2i16.nxv2i8.nxv2i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvw_se_u8mf2( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvw.se.i32.nxv4i16.nxv4i8.nxv4i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv4i16.nxv4i8.nxv4i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvw_se_u8m1( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvw.se.i32.nxv8i16.nxv8i8.nxv8i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv8i16.nxv8i8.nxv8i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvw_se_u8m2( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvw.se.i32.nxv16i16.nxv16i8.nxv16i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv16i16.nxv16i8.nxv16i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvw_se_u8m4( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvw.se.i32.nxv32i16.nxv32i8.nxv32i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv32i16.nxv32i8.nxv32i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvw_se_u16mf4( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvw.se.i32.nxv1i32.nxv1i16.nxv1i16.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv1i32.nxv1i16.nxv1i16.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvw_se_u16mf2( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvw.se.i32.nxv2i32.nxv2i16.nxv2i16.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv2i32.nxv2i16.nxv2i16.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvw_se_u16m1( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i32, ptr %vl.addr, align 4 # | call void # | ... # `---data was truncated (10240/179328) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005622571a657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005622571a3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005622571a6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0bd1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0bd178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0bd1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0bd171b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056225713c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056225713c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562257120f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562256dd0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562256dcfe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0bd171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0bd171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0bd171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562256dcfd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c (1068 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eb9cdad57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055eb9cdaa515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055eb9cdadcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa6b9133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa6b918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa6b9133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa6b911b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eb9cd4324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055eb9cd43096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055eb9cd27f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055eb9c9d7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055eb9c9d6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa6b911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa6b911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa6b911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eb9c9d6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c (1069 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32mf2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32mf2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32mf2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32mf2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32m2x3_m( %mask, ptr noun # | ... # `---data was truncated (10240/17567) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cd602cd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cd602ca515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cd602cdcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff1d2649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff1d26a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff1d2649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff1d2631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cd6026324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cd60263096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cd60247f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cd5fef7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cd5fef6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff1d2632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff1d26330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff1d26330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cd5fef6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c (1070 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_i8mf8x7 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561e0b80357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561e0b800515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561e0b803cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1217049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f12170a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1217049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1217031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561e0b79924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561e0b799096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561e0b77df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561e0b42d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561e0b42ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1217032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f12170330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f12170330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561e0b42cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c (1071 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinti_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frinti.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frinti.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinti_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frinti.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frinti.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinti_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frinti.nxv2f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frinti.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinti_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.frinti.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinti_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.frinti.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinti_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.frinti.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinti_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frinti.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinti_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frinti.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinti_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frinti.nxv2f64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000561b7781357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561b77810515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561b77813cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdb66705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdb6675c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdb66705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdb666ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561b777a924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561b777a9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561b7778df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561b7743d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561b7743ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fdb666eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdb666ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdb666ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561b7743cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c (1072 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqrshrn_s16_s32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.sqrshrn.x2.nxv4i32( %3, %4, i32 16) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.sqrshrn.x2.nxv4i32(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqrshrn_u16_u32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.uqrshrn.x2.nxv4i32( %3, %4, i32 16) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.uqrshrn.x2.nxv4i32(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqrshrun_u16_s32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.sqrshrun.x2.nxv4i32( %3, %4, i32 16) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.sqrshrun.x2.nxv4i32(, , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x000055cd624ec57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cd624e9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cd624eccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb6e8f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb6e8f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb6e8f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb6e8f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cd6248224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cd62482096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cd62466f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cd62116176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cd62115e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb6e8f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb6e8f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb6e8f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cd62115d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c (1073 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005608c89a157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005608c899e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005608c89a1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5f69733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5f6978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5f69733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5f6971b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005608c893724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005608c8937096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005608c891bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005608c85cb176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005608c85cae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5f6971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5f6971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5f6971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005608c85cad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c (1074 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captu # | ... # `---data was truncated (10240/87308) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e3f7d6657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e3f7d63515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e3f7d66cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0b46449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0b464a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0b46449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0b46431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e3f7cfc24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e3f7cfc096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e3f7ce0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e3f7990176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e3f798fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0b46432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0b464330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0b464330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e3f798fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c (1075 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.a # | ... # `---data was truncated (10240/97683) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d52816c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d528169515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d52816ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5591e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5591ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5591e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5591e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d52810224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d528102096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d5280e6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d527d96176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d527d95e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5591e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5591e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5591e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d527d95d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/neon-vcmla.c (1076 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon-vcmla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64 -target-feature +neon -target-feature +v8.3a -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes="mem2reg,instsimplify,sroa" | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64 -target-feature +neon -target-feature +v8.3a -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vcmla_f16(<4 x half> noundef %acc, <4 x half> noundef %lhs, <4 x half> noundef %rhs) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %acc.addr = alloca <4 x half>, align 8 # | %lhs.addr = alloca <4 x half>, align 8 # | %rhs.addr = alloca <4 x half>, align 8 # | store <4 x half> %acc, ptr %acc.addr, align 8 # | store <4 x half> %lhs, ptr %lhs.addr, align 8 # | store <4 x half> %rhs, ptr %rhs.addr, align 8 # | %0 = load <4 x half>, ptr %acc.addr, align 8 # | %1 = load <4 x half>, ptr %lhs.addr, align 8 # | %2 = load <4 x half>, ptr %rhs.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vcmla_f16.i = bitcast <8 x i8> %3 to <4 x half> # | %vcmla_f161.i = bitcast <8 x i8> %4 to <4 x half> # | %vcmla_f162.i = bitcast <8 x i8> %5 to <4 x half> # | %vcmla_f163.i = call <4 x half> @llvm.aarch64.neon.vcmla.rot0.v4f16(<4 x half> %vcmla_f16.i, <4 x half> %vcmla_f161.i, <4 x half> %vcmla_f162.i) # | %vcmla_f164.i = bitcast <4 x half> %vcmla_f163.i to <8 x i8> # | store <8 x i8> %vcmla_f164.i, ptr %ref.tmp.i, align 8 # | %6 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %6, ptr %__ret.i, align 8 # | %7 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vcmla_f32(<2 x float> noundef %acc, <2 x float> noundef %lhs, <2 x float> noundef %rhs) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__p2.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %acc.addr = alloca <2 x float>, align 8 # | %lhs.addr = alloca <2 x float>, align 8 # | %rhs.addr = alloca <2 x float>, align 8 # | store <2 x float> %acc, ptr %acc.addr, align 8 # | store <2 x float> %lhs, ptr %lhs.addr, align 8 # | store <2 x float> %rhs, ptr %rhs.addr, align 8 # | %0 = load <2 x float>, ptr %acc.addr, align 8 # | %1 = load <2 x float>, ptr %lhs.addr, align 8 # | %2 = load <2 x float>, ptr %rhs.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | store <2 x float> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vcmla_f32.i = bitcast <8 x i8> %3 to <2 x float> # | %vcmla_f321.i = bitcast <8 x i8> %4 to <2 x float> # | %vcmla_f322.i = bitcast <8 x i8> %5 to <2 x float> # | %vcmla_f323.i = call <2 x float> @llvm.aarch64.neon.vcmla.rot0.v2f32(<2 x float> %vcmla_f32.i, <2 x float> %vcmla_f321.i, <2 x float> %vcmla_f322.i) # | %vcmla_f324.i = bitcast <2 x float> %vcmla_f323.i to <8 x i8> # | store <8 x i8> %vcmla_f324.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %6, ptr %__ret.i, align 8 # | %7 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vcmlaq_f16(<8 x half> noundef %acc, <8 x half> noundef %lhs, <8 x half> noundef %rhs) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %acc.addr = alloca <8 x half>, align 16 # | %lhs.addr = alloca <8 x half>, align 16 # | %rhs.addr = alloca <8 x half>, align 16 # | store <8 x half> %acc, ptr %acc.addr, align 16 # | store <8 x half> %lhs, ptr %lhs.addr, align 16 # | store <8 x half> %rhs, ptr %rhs.addr, align 16 # | %0 = load <8 x half>, ptr %acc.addr, align 16 # | %1 = load <8 x half>, ptr %lhs.addr, align 16 # | %2 = load <8 x half>, ptr %rhs.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vcmlaq_f16.i = bitcast <16 x i8> %3 to <8 x half> # | %vcmlaq_f161.i = bitcast <16 x i8> %4 to <8 x half> # | %vcmlaq_f162.i = bitcast <16 x i8> %5 to <8 x half> # | %vcmlaq_f163.i = call <8 x half> @llvm.aarch64.neon.vcmla.rot0.v8f16(<8 x half> %vcmlaq_f16.i, <8 x half> %vcmlaq_f161.i, <8 x half> %vcmlaq_f162.i) # | %vcmlaq_f164.i = bitcast <8 x half> %vcmlaq_f163.i to <16 x i8> # | store <16 x i8> %vcmlaq_f164.i, ptr %ref.tmp.i, align 16 # | %6 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %6, ptr %__ret.i, align 16 # | %7 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vcmlaq_f32(<4 x float> noundef %acc, <4 x float> noundef %lhs, <4 x float> noundef %rhs) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <4 x float>, align 16 # | %__p2.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %acc.addr = alloca <4 x float>, align 16 # | %lhs.addr = alloca <4 x float>, align 16 # | %rhs.addr = alloca <4 x float>, align 16 # | store <4 x float> %acc, ptr %acc.addr, align 16 # | store <4 x float> %lhs, ptr %lhs.addr, align 16 # | store <4 x float> %rhs, ptr %rhs.addr, align 16 # | %0 = load <4 x float>, ptr %acc.addr, align 16 # | %1 = load <4 x float>, ptr %lhs.addr, align 16 # | %2 = load <4 x float>, ptr %rhs.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <4 x float> %1, ptr %__p1.addr.i, align 16 # | store <4 x float> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vcmlaq_f32.i = bitcast <16 x i8> %3 to <4 x float> # | %vcmlaq_f321.i = bitcast <16 x i8> %4 to <4 x float> # | %vcmlaq_f322.i = bitcast <16 x i8> %5 to <4 x float> # | %vcmlaq_f323.i = call <4 x float> @llvm.aarch64.neon.vcmla.rot0.v4f32(<4 x float> %vcmlaq_f32.i, <4 x float> %vcmlaq_f321.i, <4 x float> %vcmlaq_f322.i) # | %vcmlaq_f324.i = bitcast <4 x float> %vcmlaq_f323.i to <16 x i8> # | store <16 x i8> %vcmlaq_f324.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %6, ptr %__ret.i, align 16 # | %7 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vcmlaq_f64(<2 x double> noundef %acc, <2 x double> noundef %lhs, <2 x double> noundef %rhs) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__p1.addr.i = alloca <2 x double>, align 16 # | %__p2.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %acc.addr = alloca <2 x double>, align 16 # | %lhs.addr = alloca <2 x double>, align 16 # | %rhs.addr = alloca <2 x double>, align 16 # | store <2 x double> %acc, ptr %acc.addr, align 16 # | store <2 x double> %lhs, ptr %lhs.addr, align 16 # | store <2 x double> %rhs, ptr %rhs.addr, align 16 # | %0 = load <2 x double>, ptr %acc.addr, align 16 # | %1 = load <2 x double>, ptr %lhs.addr, align 16 # | %2 = load <2 x double>, ptr %rhs.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | store <2 x double> %1, ptr %__p1.addr.i, align 16 # | store <2 x double> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vcmlaq_f64.i = bitcast <16 x i8> %3 to <2 x double> # | %vcmlaq_f641.i = bitcast <16 x i8> %4 to <2 x double> # | %vcmlaq_f642.i = bitcast <16 x i8> %5 to <2 x double> # | %vcmlaq_f643.i = call <2 x double> @llvm.aarch64.neon.vcmla.rot0.v2f64(<2 x double> %vcmlaq_f64.i, <2 x double> %vcmlaq_f641.i, <2 x double> %vcmlaq_f642.i) # | %vcmlaq_f644.i = bitcast <2 x double> %vcmlaq_f643.i to <16 x i8> # | store <16 x i8> %vcmlaq_f644.i, ptr %ref.tmp.i, align 16 # | %6 = load <2 x double>, ptr %ref.tmp.i, align 16 # | store <2 x double> %6, ptr %__ret.i, align 16 # | %7 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vcmla_rot90_f16(<4 x half> noundef %acc, <4 x half> noundef %lhs, <4 x half> noundef %rhs) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %acc.addr = alloca <4 x half>, align 8 # | %lhs.addr = alloca <4 x half>, align 8 # | %rhs.addr = alloca <4 x half>, align 8 # | store <4 x half> %acc, ptr %acc.addr, align 8 # | store <4 x half> %lhs, ptr %lhs.addr, align 8 # | store <4 x half> %rhs, ptr %rhs.addr, align 8 # | %0 = load <4 x half>, ptr %acc.addr, align 8 # | %1 = load <4 x half>, ptr %lhs.addr, align 8 # | %2 = load <4 x half>, ptr %rhs.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vcmla_rot90_f16.i = bitcast <8 x i8> %3 to <4 x half> # | %vcmla_rot90_f161.i = bitcast <8 x i8> %4 to <4 x half> # | %vcmla_rot90_f162.i = bitcast <8 x i8> %5 to <4 x half> # | %vcmla_rot90_f163.i = call <4 x half> @llvm.aarch64.neon.vcmla.rot90.v # | ... # `---data was truncated (10240/166298) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instsimplify,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instsimplify,sroa # | #0 0x00005565d4f5057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005565d4f4d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005565d4f50cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8e77333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8e7738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8e77333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8e7731b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005565d4ee624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005565d4ee6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005565d4ecaf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005565d4b7a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005565d4b79e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8e7731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8e7731d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8e7731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005565d4b79d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c (1077 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vx_u16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wv_u16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wx_u16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.w.nxv1i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vx_u16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wv_u16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wx_u16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.w.nxv2i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.ad # | ... # `---data was truncated (10240/306619) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559da99bb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559da99b8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559da99bbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fed33705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fed3375c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fed33705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fed336ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559da995124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559da9951096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559da9935f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559da95e5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559da95e4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fed336eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fed336ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fed336ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559da95e4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c (1078 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562cb207457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562cb2071515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562cb2074cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd05b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd05b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd05b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd05b031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562cb200a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562cb200a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562cb1feef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562cb1c9e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562cb1c9de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd05b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd05b0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd05b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562cb1c9dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c (1079 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_u32mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_u32m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_u32m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32mf2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg # | ... # `---data was truncated (10240/20483) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564e6cab857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564e6cab5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564e6cab8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3e8f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3e8f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3e8f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3e8f231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564e6ca4e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564e6ca4e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564e6ca32f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564e6c6e2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564e6c6e1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3e8f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3e8f2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3e8f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564e6c6e1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c (1080 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_i32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_i32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_u32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_u32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32mf2x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("ri # | ... # `---data was truncated (10240/32023) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005568963cf57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005568963cc515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005568963cfcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4d40649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4d406a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4d40649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4d40631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055689636524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556896365096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556896349f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556895ff9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556895ff8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4d40632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4d406330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4d406330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556895ff8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c (1081 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16mf4x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16mf2x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16m1x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16m1x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563af7a6757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563af7a64515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563af7a67cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb2a5733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb2a578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb2a5733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb2a571b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563af79fd24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563af79fd096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563af79e1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563af7691176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563af7690e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb2a571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb2a571d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb2a571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563af7690d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c (1082 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv8bf16.p0.nxv8i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target # | ... # `---data was truncated (10240/10700) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559e9823957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559e98236515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559e98239cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd9e6449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd9e64a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd9e6449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd9e6431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559e981cf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559e981cf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559e981b3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559e97e63176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559e97e62e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd9e6432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd9e64330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd9e64330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559e97e62d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c (1083 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, pt # | ... # `---data was truncated (10240/66557) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cc38d0857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cc38d05515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cc38d08cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0832b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0832b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0832b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0832b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cc38c9e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cc38c9e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cc38c82f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cc38932176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cc38931e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0832b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0832b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0832b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cc38931d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c (1084 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16mf4_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16mf2_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m1_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m2_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m4_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv16f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv16f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m8_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv32f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv32f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32mf2_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load float, ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv1f32.f32.i64( %0, %1, float %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32m1_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load float, ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv2f32.f32.i64( %0, %1, float %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32m2_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vornq.c (1085 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vornq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vornq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = xor <16 x i8> %1, splat (i8 -1) # | %3 = or <16 x i8> %0, %2 # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vornq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = xor <8 x i16> %1, splat (i16 -1) # | %3 = or <8 x i16> %0, %2 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vornq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = xor <4 x i32> %1, splat (i32 -1) # | %3 = or <4 x i32> %0, %2 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vornq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = bitcast <4 x float> %2 to <4 x i32> # | %4 = xor <4 x i32> %3, splat (i32 -1) # | %5 = or <4 x i32> %1, %4 # | %6 = bitcast <4 x i32> %5 to <4 x float> # | ret <4 x float> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vornq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.orn.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.orn.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vornq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vornq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.orn.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.orn.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vornq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = bitcast <8 x half> %0 to <8 x i16> # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = bitcast <8 x half> %2 to <8 x i16> # | %4 = load i16, ptr %p.addr, align 2 # | %5 = zext i16 %4 to i32 # | %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5) # | %7 = load <8 x half>, ptr %inactive.addr, align 8 # | %8 = bitcast <8 x half> %7 to <8 x i16> # | %9 = call <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8) # | %10 = bitcast <8 x i16> %9 to <8 x half> # | ret <8 x half> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vornq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.orn.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vornq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vornq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.orn.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vornq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = bitcast <4 x float> %2 to <4 x i32> # | %4 = load i16, ptr %p.addr, al # | ... # `---data was truncated (10240/11056) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055832339557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558323392515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558323395cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f17f321bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f17f32725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f17f321ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f17f3203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055832332b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055832332b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055832330ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558322fbf176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558322fbee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f17f3204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f17f32050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f17f32050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558322fbed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c (1086 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16mf4x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16mf2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16m1x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16m2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16mf4x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16mf2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16m1x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tu # | ... # `---data was truncated (10240/17844) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f23dcf557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f23dcf2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f23dcf5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0bfc733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0bfc78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0bfc733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0bfc71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f23dc8b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f23dc8b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f23dc6ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f23d91f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f23d91ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0bfc71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0bfc71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0bfc71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f23d91ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c (1087 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svfrinta_f32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.frinta.x2.nxv4f32( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.frinta.x2.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svfrinta_f32_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call { , , , } @llvm.aarch64.sve.frinta.x4.nxv4f32( %5, %6, %7, %8) # | ret { , , , } %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.frinta.x4.nxv4f32(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svfrintam_f32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.frintm.x2.nxv4f32( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.frintm.x2.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svfrintm_f32_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call { , , , } @llvm.aarch64.sve.frintm.x4.nxv4f32( %5, %6, %7, %8) # | ret { , , , } %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.frintm.x4.nxv4f32(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svfrintn_f32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.frintn.x2.nxv4f32( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn me # | ... # `---data was truncated (10240/17932) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055ed91dd457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ed91dd1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ed91dd4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3512e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3512ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3512e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3512e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ed91d6a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ed91d6a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ed91d4ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ed919fe176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ed919fde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3512e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3512e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3512e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ed919fdd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c (1088 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32mf2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m1_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m4_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call < # | ... # `---data was truncated (10240/101483) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556402abd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556402aba515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556402abdcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0383d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0383d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0383d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0383d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556402a5324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556402a53096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556402a37f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005564026e7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005564026e6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0383d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0383d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0383d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005564026e6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c (1089 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbfmlalb_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfmlalb( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfmlalb(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmlalb_lane_0_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfmlalb.lane.v2( %0, %1, %2, i32 0) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfmlalb.lane.v2(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmlalb_lane_7_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfmlalb.lane.v2( %0, %1, %2, i32 7) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmlalb_n_f32( %x, %y, bfloat noundef %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca bfloat, align 2 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store bfloat %z, ptr %z.addr, align 2 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load bfloat, ptr %z.addr, align 2 # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.bfmlalb( %0, %1, %.splat) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055dcbf77d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055dcbf77a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055dcbf77dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f656341bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f65634725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f656341ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6563403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dcbf71324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055dcbf713096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055dcbf6f7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055dcbf3a7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055dcbf3a6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6563404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f65634050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f65634050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dcbf3a6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c (1090 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range # | ... # `---data was truncated (10240/302397) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056252cccc57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056252ccc9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056252cccccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9861f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9861f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9861f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9861f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056252cc6224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056252cc62096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056252cc46f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056252c8f6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056252c8f5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9861f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9861f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9861f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056252c8f5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c (1091 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captu # | ... # `---data was truncated (10240/87308) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564d8500a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564d85007515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564d8500acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1da6849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1da68a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1da6849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1da6831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564d84fa024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564d84fa0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564d84f84f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564d84c34176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564d84c33e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1da6832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1da68330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1da68330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564d84c33d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c (1092 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf8_tu( %maskedoff, %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv1i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf4_tu( %maskedoff, %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv2i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf2_tu( %maskedoff, %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv4i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8m1_tu( %maskedoff, %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso # | ... # `---data was truncated (10240/148012) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056518f91657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056518f913515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056518f916cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc74d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc74d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc74d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc74d431507 abort ./stdlib/abort.c:85:3 # | #7 0x000056518f8ac24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056518f8ac096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056518f890f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056518f540176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056518f53fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc74d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc74d4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc74d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056518f53fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c (1093 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562ef4bcf57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562ef4bcc515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562ef4bcfcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4334f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4334f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4334f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4334f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562ef4b6524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562ef4b65096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562ef4b49f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562ef47f9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562ef47f8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4334f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4334f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4334f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562ef47f8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c (1094 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf8( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf4( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf2( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8m1( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8m2( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c (1095 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f32m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | re # | ... # `---data was truncated (10240/120915) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564da36dc57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564da36d9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564da36dccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdf0ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdf0ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdf0ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdf0ff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564da367224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564da3672096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564da3656f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564da3306176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564da3305e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fdf0ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdf0ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdf0ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564da3305d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm-neon-vcvtX.c (1096 of 27911) ******************** TEST 'Clang :: CodeGen/arm-neon-vcvtX.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8-unknown-linux-gnueabihf" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vcvta_s32_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vcvta_s32_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vcvta_s32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtas.v2i32.v2f32(<2 x float> %vcvta_s32_v.i) # | store <2 x i32> %vcvta_s32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vcvta_u32_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vcvta_u32_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vcvta_u32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtau.v2i32.v2f32(<2 x float> %vcvta_u32_v.i) # | store <2 x i32> %vcvta_u32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vcvtaq_s32_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vcvtaq_s32_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vcvtaq_s32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtas.v4i32.v4f32(<4 x float> %vcvtaq_s32_v.i) # | store <4 x i32> %vcvtaq_s32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x i32>, ptr %ref.tmp.i, align 8 # | store <4 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <4 x i32>, ptr %__ret.i, align 8 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vcvtaq_u32_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vcvtaq_u32_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vcvtaq_u32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtau.v4i32.v4f32(<4 x float> %vcvtaq_u32_v.i) # | store <4 x i32> %vcvtaq_u32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x i32>, ptr %ref.tmp.i, align 8 # | store <4 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <4 x i32>, ptr %__ret.i, align 8 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vcvtn_s32_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vcvtn_s32_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vcvtn_s32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtns.v2i32.v2f32(<2 x float> %vcvtn_s32_v.i) # | store <2 x i32> %vcvtn_s32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vcvtn_u32_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vcvtn_u32_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vcvtn_u32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtnu.v2i32.v2f32(<2 x float> %vcvtn_u32_v.i) # | store <2 x i32> %vcvtn_u32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vcvtnq_s32_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vcvtnq_s32_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vcvtnq_s32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtns.v4i32.v4f32(<4 x float> %vcvtnq_s32_v.i) # | store <4 x i32> %vcvtnq_s32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x i32>, ptr %ref.tmp.i, align 8 # | store <4 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <4 x i32>, ptr %__ret.i, align 8 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vcvtnq_u32_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vcvtnq_u32_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vcvtnq_u32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtnu.v4i32.v4f32(<4 x float> %vcvtnq_u32_v.i) # | store <4 x i32> %vcvtnq_u32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x i32>, ptr %ref.tmp.i, align 8 # | store <4 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <4 x i32>, ptr %__ret.i, align 8 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vcvtp_s32_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vcvtp_s32_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vcvtp_s32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtps.v2i32.v2f32(<2 x float> %vcvtp_s32_v.i) # | store <2 x i32> %vcvtp_s32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vcvtp_u32_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vcvtp_u32_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vcvtp_u32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtpu.v2i32.v2f32(<2 x float> %vcvtp_u32_v.i) # | store <2 x i32> %vcvtp_u32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vcvtpq_s32_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vcvtpq_s32_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vcvtpq_s32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtps.v4i32.v4f32(<4 x float> %vcvtpq_s32_v.i) # | store <4 x i32> %vcvtpq_s32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x i32>, ptr %ref.tmp.i, align 8 # | store <4 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <4 x i32>, ptr %__ret.i, align 8 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vcvtpq_u32_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vcvtpq_u32_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vcvtpq_u32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtpu.v4i32.v4f32(<4 x float> %vcvtpq_u32_v.i) # | st # | ... # `---data was truncated (10240/16770) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055d2cee5357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d2cee50515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d2cee53cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc895c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc895ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc895c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc895c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d2cede924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d2cede9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d2cedcdf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d2cea7d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d2cea7ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc895c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc895c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc895c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d2cea7cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/veorq.c (1097 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/veorq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_veorq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = xor <16 x i8> %0, %1 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_veorq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = xor <8 x i16> %0, %1 # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_veorq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = xor <4 x i32> %0, %1 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_veorq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = bitcast <4 x float> %2 to <4 x i32> # | %4 = xor <4 x i32> %1, %3 # | %5 = bitcast <4 x i32> %4 to <4 x float> # | ret <4 x float> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_veorq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.eor.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.eor.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_veorq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_veorq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_veorq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = bitcast <8 x half> %0 to <8 x i16> # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = bitcast <8 x half> %2 to <8 x i16> # | %4 = load i16, ptr %p.addr, align 2 # | %5 = zext i16 %4 to i32 # | %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5) # | %7 = load <8 x half>, ptr %inactive.addr, align 8 # | %8 = bitcast <8 x half> %7 to <8 x i16> # | %9 = call <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8) # | %10 = bitcast <8 x i16> %9 to <8 x half> # | ret <8 x half> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_veorq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.eor.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_veorq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_veorq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_veorq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = bitcast <4 x float> %2 to <4 x i32> # | %4 = load i16, ptr %p.addr, align 2 # | %5 = zext i16 %4 to i32 # | %6 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %5) # | %7 = call <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x # | ... # `---data was truncated (10240/10901) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559d5aa3457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559d5aa31515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559d5aa34cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcc71733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcc7178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcc71733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcc7171b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559d5a9ca24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559d5a9ca096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559d5a9aef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559d5a65e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559d5a65de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcc7171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcc7171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcc7171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559d5a65dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/neon-extract.c (1098 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon-extract.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vext_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = load <8 x i8>, ptr %__s1, align 8 # | %vext = shufflevector <8 x i8> %2, <8 x i8> %3, <8 x i32> # | store <8 x i8> %vext, ptr %ref.tmp, align 8 # | %4 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %4, ptr %__ret, align 8 # | %5 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %5, ptr %tmp, align 8 # | %6 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vext_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | %__ret = alloca <4 x i16>, align 8 # | %__s0 = alloca <4 x i16>, align 8 # | %__s1 = alloca <4 x i16>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__s0, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = load <8 x i8>, ptr %__s1, align 8 # | %4 = bitcast <8 x i8> %2 to <4 x i16> # | %5 = bitcast <8 x i8> %3 to <4 x i16> # | %vext = shufflevector <4 x i16> %4, <4 x i16> %5, <4 x i32> # | store <4 x i16> %vext, ptr %ref.tmp, align 8 # | %6 = load <4 x i16>, ptr %ref.tmp, align 8 # | store <4 x i16> %6, ptr %__ret, align 8 # | %7 = load <4 x i16>, ptr %__ret, align 8 # | store <4 x i16> %7, ptr %tmp, align 8 # | %8 = load <4 x i16>, ptr %tmp, align 8 # | ret <4 x i16> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vext_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <2 x i32>, align 8 # | %__ret = alloca <2 x i32>, align 8 # | %__s0 = alloca <2 x i32>, align 8 # | %__s1 = alloca <2 x i32>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <2 x i32> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__s0, align 8 # | %1 = load <2 x i32>, ptr %b.addr, align 8 # | store <2 x i32> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = load <8 x i8>, ptr %__s1, align 8 # | %4 = bitcast <8 x i8> %2 to <2 x i32> # | %5 = bitcast <8 x i8> %3 to <2 x i32> # | %vext = shufflevector <2 x i32> %4, <2 x i32> %5, <2 x i32> # | store <2 x i32> %vext, ptr %ref.tmp, align 8 # | %6 = load <2 x i32>, ptr %ref.tmp, align 8 # | store <2 x i32> %6, ptr %__ret, align 8 # | %7 = load <2 x i32>, ptr %__ret, align 8 # | store <2 x i32> %7, ptr %tmp, align 8 # | %8 = load <2 x i32>, ptr %tmp, align 8 # | ret <2 x i32> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vext_s64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca <1 x i64>, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | %__ret = alloca <1 x i64>, align 8 # | %__s0 = alloca <1 x i64>, align 8 # | %__s1 = alloca <1 x i64>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | store <1 x i64> %0, ptr %__s0, align 8 # | %1 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = load <8 x i8>, ptr %__s1, align 8 # | %4 = bitcast <8 x i8> %2 to <1 x i64> # | %5 = bitcast <8 x i8> %3 to <1 x i64> # | %vext = shufflevector <1 x i64> %4, <1 x i64> %5, <1 x i32> zeroinitializer # | store <1 x i64> %vext, ptr %ref.tmp, align 8 # | %6 = load <1 x i64>, ptr %ref.tmp, align 8 # | store <1 x i64> %6, ptr %__ret, align 8 # | %7 = load <1 x i64>, ptr %__ret, align 8 # | store <1 x i64> %7, ptr %tmp, align 8 # | %8 = load <1 x i64>, ptr %tmp, align 8 # | ret <1 x i64> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vextq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | %__ret = alloca <16 x i8>, align 16 # | %__s0 = alloca <16 x i8>, align 16 # | %__s1 = alloca <16 x i8>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__s0, align 16 # | %1 = load <16 x i8>, ptr %b.addr, align 16 # | store <16 x i8> %1, ptr %__s1, align 16 # | %2 = load <16 x i8>, ptr %__s0, align 16 # | %3 = load <16 x i8>, ptr %__s1, align 16 # | %vext = shufflevector <16 x i8> %2, <16 x i8> %3, <16 x i32> # | store <16 x i8> %vext, ptr %ref.tmp, align 16 # | %4 = load <16 x i8>, ptr %ref.tmp, align 16 # | store <16 x i8> %4, ptr %__ret, align 16 # | %5 = load <16 x i8>, ptr %__ret, align 16 # | store <16 x i8> %5, ptr %tmp, align 16 # | %6 = load <16 x i8>, ptr %tmp, align 16 # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vextq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x i16>, align 16 # | %__ret = alloca <8 x i16>, align 16 # | %__s0 = alloca <8 x i16>, align 16 # | %__s1 = alloca <8 x i16>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | store <8 x i16> %b, ptr %b.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__s0, align 16 # | %1 = load <8 x i16>, ptr %b.addr, align 16 # | store <8 x i16> %1, ptr %__s1, align 16 # | %2 = load <16 x i8>, ptr %__s0, align 16 # | %3 = load <16 x i8>, ptr %__s1, align 16 # | %4 = bitcast <16 x i8> %2 to <8 x i16> # | %5 = bitcast <16 x i8> %3 to <8 x i16> # | %vext = shufflevector <8 x i16> %4, <8 x i16> %5, <8 x i32> # | store <8 x i16> %vext, ptr %ref.tmp, align 16 # | %6 = load <8 x i16>, ptr %ref.tmp, align 16 # | store <8 x i16> %6, ptr %__ret, align 16 # | %7 = load <8 x i16>, ptr %__ret, align 16 # | store <8 x i16> %7, ptr %tmp, align 16 # | %8 = load <8 x i16>, ptr %tmp, align 16 # | ret <8 x i16> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vextq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 16 # | %b.addr = alloca <4 x i32>, align 16 # | %__ret = alloca <4 x i32>, align 16 # | %__s0 = alloca <4 x i32>, align 16 # | %__s1 = alloca <4 x i32>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | store <4 x i32> %b, ptr %b.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__s0, align 16 # | %1 = load <4 x i32>, ptr %b.addr, align 16 # | store <4 x i32> %1, ptr %__s1, align 16 # | %2 = load <16 x i8>, ptr %__s0, align 16 # | %3 = load <16 x i8>, ptr %__s1, align 16 # | %4 = bitcast <16 x i8> %2 to <4 x i32> # | %5 = bitcast <16 x i8> %3 to <4 x i32> # | %vext = shufflevector <4 x i32> %4, <4 x i32> %5, <4 x i32> # | store <4 x i32> %vext, ptr %ref.tmp, align 16 # | %6 = load <4 x i32>, ptr %ref.tmp, align 16 # | store <4 x i32> %6, ptr %__ret, align 16 # | %7 = load <4 x i32>, ptr %__ret, align 16 # | store <4 x i32> %7, ptr %tmp, align 16 # | %8 = load <4 x i32>, ptr %tmp, align 16 # | ret <4 x i32> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vextq_s64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 16 # | %b.addr = alloca <2 x i64>, align 16 # | %__ret = alloca <2 x i64>, align 16 # | %__s0 = alloca <2 x i64>, align 16 # | %__s1 = alloca <2 x i64>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__s0, align 16 # | %1 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %1, ptr %__s1, align 16 # | %2 = load <16 x i8>, ptr %__s0, align 16 # | %3 = load <16 x i8>, ptr %__s1, align 16 # | %4 = bitcast <16 x i8> %2 to <2 x i64> # | %5 = bitcast <16 x i8> %3 to <2 x i64> # | %vext = shufflevector <2 x i64> %4, <2 x i64> %5, <2 x i32> # | store <2 x i64> %vext, ptr %ref.tmp, align 16 # | %6 = load <2 x i64>, ptr %ref.tmp, align 16 # | store <2 x i64> %6, ptr %__ret, align 16 # | %7 = load <2 x i64>, ptr %__ret, align 16 # | store <2 x i64> %7, ptr %tmp, align 16 # | %8 = load <2 x i64>, ptr %tmp, align 16 # | ret <2 x i64> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vext_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> # | ... # `---data was truncated (10240/29598) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055e37f63157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e37f62e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e37f631cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe5d6b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe5d6b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe5d6b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe5d6b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e37f5c724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e37f5c7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e37f5abf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e37f25b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e37f25ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe5d6b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe5d6b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe5d6b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e37f25ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/neon-intrinsics-constrained.c (1099 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon-intrinsics-constrained.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vadd_f32(<2 x float> noundef %v1, <2 x float> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %v1.addr = alloca <2 x float>, align 8 # | %v2.addr = alloca <2 x float>, align 8 # | store <2 x float> %v1, ptr %v1.addr, align 8 # | store <2 x float> %v2, ptr %v2.addr, align 8 # | %0 = load <2 x float>, ptr %v1.addr, align 8 # | %1 = load <2 x float>, ptr %v2.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x float>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x float>, ptr %__p1.addr.i, align 8 # | %add.i = fadd <2 x float> %2, %3 # | store <2 x float> %add.i, ptr %__ret.i, align 8 # | %4 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vaddq_f32(<4 x float> noundef %v1, <4 x float> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %v1.addr = alloca <4 x float>, align 16 # | %v2.addr = alloca <4 x float>, align 16 # | store <4 x float> %v1, ptr %v1.addr, align 16 # | store <4 x float> %v2, ptr %v2.addr, align 16 # | %0 = load <4 x float>, ptr %v1.addr, align 16 # | %1 = load <4 x float>, ptr %v2.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <4 x float> %1, ptr %__p1.addr.i, align 16 # | %2 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %3 = load <4 x float>, ptr %__p1.addr.i, align 16 # | %add.i = fadd <4 x float> %2, %3 # | store <4 x float> %add.i, ptr %__ret.i, align 16 # | %4 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vsub_f32(<2 x float> noundef %v1, <2 x float> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %v1.addr = alloca <2 x float>, align 8 # | %v2.addr = alloca <2 x float>, align 8 # | store <2 x float> %v1, ptr %v1.addr, align 8 # | store <2 x float> %v2, ptr %v2.addr, align 8 # | %0 = load <2 x float>, ptr %v1.addr, align 8 # | %1 = load <2 x float>, ptr %v2.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x float>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x float>, ptr %__p1.addr.i, align 8 # | %sub.i = fsub <2 x float> %2, %3 # | store <2 x float> %sub.i, ptr %__ret.i, align 8 # | %4 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vsubq_f32(<4 x float> noundef %v1, <4 x float> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %v1.addr = alloca <4 x float>, align 16 # | %v2.addr = alloca <4 x float>, align 16 # | store <4 x float> %v1, ptr %v1.addr, align 16 # | store <4 x float> %v2, ptr %v2.addr, align 16 # | %0 = load <4 x float>, ptr %v1.addr, align 16 # | %1 = load <4 x float>, ptr %v2.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <4 x float> %1, ptr %__p1.addr.i, align 16 # | %2 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %3 = load <4 x float>, ptr %__p1.addr.i, align 16 # | %sub.i = fsub <4 x float> %2, %3 # | store <4 x float> %sub.i, ptr %__ret.i, align 16 # | %4 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vsubq_f64(<2 x double> noundef %v1, <2 x double> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__p1.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %v1.addr = alloca <2 x double>, align 16 # | %v2.addr = alloca <2 x double>, align 16 # | store <2 x double> %v1, ptr %v1.addr, align 16 # | store <2 x double> %v2, ptr %v2.addr, align 16 # | %0 = load <2 x double>, ptr %v1.addr, align 16 # | %1 = load <2 x double>, ptr %v2.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | store <2 x double> %1, ptr %__p1.addr.i, align 16 # | %2 = load <2 x double>, ptr %__p0.addr.i, align 16 # | %3 = load <2 x double>, ptr %__p1.addr.i, align 16 # | %sub.i = fsub <2 x double> %2, %3 # | store <2 x double> %sub.i, ptr %__ret.i, align 16 # | %4 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vmul_f32(<2 x float> noundef %v1, <2 x float> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %v1.addr = alloca <2 x float>, align 8 # | %v2.addr = alloca <2 x float>, align 8 # | store <2 x float> %v1, ptr %v1.addr, align 8 # | store <2 x float> %v2, ptr %v2.addr, align 8 # | %0 = load <2 x float>, ptr %v1.addr, align 8 # | %1 = load <2 x float>, ptr %v2.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x float>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x float>, ptr %__p1.addr.i, align 8 # | %mul.i = fmul <2 x float> %2, %3 # | store <2 x float> %mul.i, ptr %__ret.i, align 8 # | %4 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vmulq_f32(<4 x float> noundef %v1, <4 x float> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %v1.addr = alloca <4 x float>, align 16 # | %v2.addr = alloca <4 x float>, align 16 # | store <4 x float> %v1, ptr %v1.addr, align 16 # | store <4 x float> %v2, ptr %v2.addr, align 16 # | %0 = load <4 x float>, ptr %v1.addr, align 16 # | %1 = load <4 x float>, ptr %v2.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <4 x float> %1, ptr %__p1.addr.i, align 16 # | %2 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %3 = load <4 x float>, ptr %__p1.addr.i, align 16 # | %mul.i = fmul <4 x float> %2, %3 # | store <4 x float> %mul.i, ptr %__ret.i, align 16 # | %4 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vmulq_f64(<2 x double> noundef %v1, <2 x double> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__p1.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %v1.addr = alloca <2 x double>, align 16 # | %v2.addr = alloca <2 x double>, align 16 # | store <2 x double> %v1, ptr %v1.addr, align 16 # | store <2 x double> %v2, ptr %v2.addr, align 16 # | %0 = load <2 x double>, ptr %v1.addr, align 16 # | %1 = load <2 x double>, ptr %v2.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | store <2 x double> %1, ptr %__p1.addr.i, align 16 # | %2 = load <2 x double>, ptr %__p0.addr.i, align 16 # | %3 = load <2 x double>, ptr %__p1.addr.i, align 16 # | %mul.i = fmul <2 x double> %2, %3 # | store <2 x double> %mul.i, ptr %__ret.i, align 16 # | %4 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vmla_f32(<2 x float> noundef %v1, <2 x float> noundef %v2, <2 x float> noundef %v3) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__p2.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %v1.addr = alloca <2 x float>, align 8 # | %v2.addr = alloca <2 x float>, align 8 # | %v3.addr = alloca <2 x float>, align 8 # | store <2 x float> %v1, ptr %v1.addr, align 8 # | store <2 x float> %v2, ptr %v2.addr, align 8 # | store <2 x float> %v3, ptr %v3.addr, align 8 # | %0 = load <2 x float>, ptr %v1.addr, align 8 # | %1 = load <2 x float>, ptr %v2.addr, align 8 # | %2 = load <2 x float>, ptr %v3.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | store <2 x float> %2, ptr %__p2.addr.i, align 8 # | %3 = load <2 x float>, ptr %__p0.addr.i, align 8 # | %4 = load <2 x float>, ptr %__p1.addr.i, align 8 # | %5 = load <2 x float>, ptr %__p2.addr.i, align 8 # | %mul.i = fmul <2 x float> %4, %5 # | %add.i = fadd <2 x float> %3, %mul.i # | store <2 x float> %add.i, ptr %__ret.i, align 8 # | %6 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vmlaq_f32(<4 x float> noundef %v1, <4 x float> noundef %v2, <4 x float> noundef %v3) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <4 x float>, align 16 # | %__p2.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %v1.addr = alloca <4 x float>, align 16 # | %v2.addr = alloca <4 x float>, align 16 # | %v3.addr = alloca <4 x float>, align 16 # | store <4 x float> %v1, ptr %v1.addr, align 16 # | store <4 x float> %v2, ptr %v2.addr, align 16 # | store <4 x float> %v3, ptr %v3.addr, align 16 # | %0 = load <4 x float>, ptr %v1.addr, align 16 # | %1 = load <4 x float>, ptr %v2.addr, align 16 # | %2 = load <4 x float>, ptr %v3.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <4 x float> %1, ptr %__p1.addr.i, align 16 # | store <4 x float> %2, ptr %__p2.addr.i, align 16 # | %3 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %4 = load <4 x float>, ptr %__p1.addr.i, align 16 # | %5 = load <4 x float>, ptr %__p2.addr.i, align 16 # | %mul.i = fmul <4 x float> %4, %5 # | %add.i = fadd <4 x float> %3, %mul.i # | store <4 x float> %add.i, ptr %__ret.i, align 16 # | %6 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %6 # | } # | # | ; F # | ... # `---data was truncated (10240/91378) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055b3c5c2857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b3c5c25515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b3c5c28cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f021c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f021c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f021c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f021c231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b3c5bbe24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b3c5bbe096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b3c5ba2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b3c5852176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b3c5851e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f021c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f021c2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f021c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b3c5851d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c (1100 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_i64m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_i64m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_u64m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_u64m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_i64m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_i64m2x3_m(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c (1101 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.a # | ... # `---data was truncated (10240/97683) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b1d3cce57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b1d3ccb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b1d3ccecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa918133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa91818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa918133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa91811b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b1d3c6424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b1d3c64096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b1d3c48f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b1d38f8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b1d38f7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa91811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa91811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa91811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b1d38f7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c (1102 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16mf4x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16mf2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m1x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m4x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_i16mf4x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_i16mf2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | # | ... # `---data was truncated (10240/22074) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056357985357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563579850515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563579853cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fac4c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fac4c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fac4c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fac4c031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005635797e924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005635797e9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005635797cdf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056357947d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056357947ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fac4c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fac4c0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fac4c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056357947cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c (1103 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_f64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_i64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_u64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563bc137557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563bc1372515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563bc1375cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0a0fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0a0faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0a0fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0a0fa31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563bc130b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563bc130b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563bc12eff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563bc0f9f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563bc0f9ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0a0fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0a0fa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0a0fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563bc0f9ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c (1104 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none # | ... # `---data was truncated (10240/61673) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ad92cf057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ad92ced515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ad92cf0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f347fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f347fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f347fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f347fc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ad92c8624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ad92c86096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ad92c6af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ad9291a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ad92919e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f347fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f347fc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f347fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ad92919d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c (1105 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_f64m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_i64m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_u64m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_f64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_i64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_u64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a64a3b057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a64a3ad515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a64a3b0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f05ddc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f05ddca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f05ddc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f05ddc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a64a34624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a64a346096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a64a32af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a649fda176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a649fd9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f05ddc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f05ddc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f05ddc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a649fd9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c (1106 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , # | ... # `---data was truncated (10240/15607) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005585faf1757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005585faf14515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005585faf17cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8491d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8491d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8491d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8491ced507 abort ./stdlib/abort.c:85:3 # | #7 0x00005585faead24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005585faead096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005585fae91f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005585fab41176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005585fab40e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8491ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8491cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8491cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005585fab40d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c (1107 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_i8mf4x7(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005578c2b9057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005578c2b8d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005578c2b90cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5ba0533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5ba058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5ba0533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5ba051b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005578c2b2624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005578c2b26096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005578c2b0af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005578c27ba176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005578c27b9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5ba051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5ba051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5ba051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005578c27b9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c (1108 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16mf4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f64m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f64m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv2f64.nxv4f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2f64.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f64m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv4f64.nxv8f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4f64.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c (1109 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf8_tu( %maskedoff, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf4_tu( %maskedoff, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf2_tu( %maskedoff, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8m1_tu( %maskedoff, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, al # | ... # `---data was truncated (10240/223137) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005649095ad57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005649095aa515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005649095adcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fae8bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fae8bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fae8bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fae8bd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056490954324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564909543096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564909527f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005649091d7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005649091d6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fae8bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fae8bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fae8bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005649091d6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c (1110 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, ali # | ... # `---data was truncated (10240/223367) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e94f96357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e94f960515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e94f963cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f14e6a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f14e6aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f14e6a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f14e6a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e94f8f924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e94f8f9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e94f8ddf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e94f58d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e94f58ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f14e6a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f14e6a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f14e6a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e94f58cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c (1111 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m4_tu( %maskedoff, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c (1112 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf8( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | # | ... # `---data was truncated (10240/207749) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563c4d2af57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563c4d2ac515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563c4d2afcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7888133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f788818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7888133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f788811b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563c4d24524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563c4d245096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563c4d229f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563c4ced9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563c4ced8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f788811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f788811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f788811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563c4ced8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c (1113 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c (1114 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv16f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv32f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv32f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2i16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4i16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nx # | ... # `---data was truncated (10240/83629) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f8f3b6957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f8f3b66515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f8f3b69cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4776849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f47768a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4776849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4776831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f8f3aff24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f8f3aff096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f8f3ae3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f8f3793176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f8f3792e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4776832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f47768330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f47768330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f8f3792d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c (1115 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f10554957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f105546515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f105549cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f743ee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f743eea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f743ee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f743ee31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f1054df24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f1054df096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f1054c3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f105173176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f105172e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f743ee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f743ee330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f743ee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f105172d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c (1116 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3e # | ... # `---data was truncated (10240/228857) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557ba102957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557ba1026515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557ba1029cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa4b0449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa4b04a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa4b0449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa4b0431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557ba0fbf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557ba0fbf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557ba0fa3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557ba0c53176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557ba0c52e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa4b0432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa4b04330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa4b04330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557ba0c52d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c (1117 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c (1118 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = allo # | ... # `---data was truncated (10240/154609) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b5f659d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b5f659a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b5f659dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff658733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff65878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff658733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff65871b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b5f653324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b5f6533096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b5f6517f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b5f61c7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b5f61c6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff65871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff65871d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff65871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b5f61c6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/builtin-shufflevector-fp8.c (1119 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/builtin-shufflevector-fp8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-linux -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-linux -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-unknown-linux" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_8x8(<8 x i8> %x) #0 { # | entry: # | %x.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %x, ptr %x.addr, align 8 # | %0 = load <8 x i8>, ptr %x.addr, align 8 # | %1 = load <8 x i8>, ptr %x.addr, align 8 # | %shuffle = shufflevector <8 x i8> %0, <8 x i8> %1, <8 x i32> # | ret <8 x i8> %shuffle # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_8x8_v(<8 x i8> %x, <8 x i8> noundef %p) #0 { # | entry: # | %x.addr = alloca <8 x i8>, align 8 # | %p.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %x, ptr %x.addr, align 8 # | store <8 x i8> %p, ptr %p.addr, align 8 # | %0 = load <8 x i8>, ptr %x.addr, align 8 # | %1 = load <8 x i8>, ptr %p.addr, align 8 # | %mask = and <8 x i8> %1, splat (i8 7) # | %shuf_idx = extractelement <8 x i8> %mask, i64 0 # | %shuf_elt = extractelement <8 x i8> %0, i8 %shuf_idx # | %shuf_ins = insertelement <8 x i8> poison, i8 %shuf_elt, i64 0 # | %shuf_idx1 = extractelement <8 x i8> %mask, i64 1 # | %shuf_elt2 = extractelement <8 x i8> %0, i8 %shuf_idx1 # | %shuf_ins3 = insertelement <8 x i8> %shuf_ins, i8 %shuf_elt2, i64 1 # | %shuf_idx4 = extractelement <8 x i8> %mask, i64 2 # | %shuf_elt5 = extractelement <8 x i8> %0, i8 %shuf_idx4 # | %shuf_ins6 = insertelement <8 x i8> %shuf_ins3, i8 %shuf_elt5, i64 2 # | %shuf_idx7 = extractelement <8 x i8> %mask, i64 3 # | %shuf_elt8 = extractelement <8 x i8> %0, i8 %shuf_idx7 # | %shuf_ins9 = insertelement <8 x i8> %shuf_ins6, i8 %shuf_elt8, i64 3 # | %shuf_idx10 = extractelement <8 x i8> %mask, i64 4 # | %shuf_elt11 = extractelement <8 x i8> %0, i8 %shuf_idx10 # | %shuf_ins12 = insertelement <8 x i8> %shuf_ins9, i8 %shuf_elt11, i64 4 # | %shuf_idx13 = extractelement <8 x i8> %mask, i64 5 # | %shuf_elt14 = extractelement <8 x i8> %0, i8 %shuf_idx13 # | %shuf_ins15 = insertelement <8 x i8> %shuf_ins12, i8 %shuf_elt14, i64 5 # | %shuf_idx16 = extractelement <8 x i8> %mask, i64 6 # | %shuf_elt17 = extractelement <8 x i8> %0, i8 %shuf_idx16 # | %shuf_ins18 = insertelement <8 x i8> %shuf_ins15, i8 %shuf_elt17, i64 6 # | %shuf_idx19 = extractelement <8 x i8> %mask, i64 7 # | %shuf_elt20 = extractelement <8 x i8> %0, i8 %shuf_idx19 # | %shuf_ins21 = insertelement <8 x i8> %shuf_ins18, i8 %shuf_elt20, i64 7 # | ret <8 x i8> %shuf_ins21 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_8x16(<16 x i8> %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %x, ptr %x.addr, align 16 # | %0 = load <16 x i8>, ptr %x.addr, align 16 # | %1 = load <16 x i8>, ptr %x.addr, align 16 # | %shuffle = shufflevector <16 x i8> %0, <16 x i8> %1, <16 x i32> # | ret <16 x i8> %shuffle # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_8x16_v(<16 x i8> %x, <16 x i8> noundef %p) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 16 # | %p.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %x, ptr %x.addr, align 16 # | store <16 x i8> %p, ptr %p.addr, align 16 # | %0 = load <16 x i8>, ptr %x.addr, align 16 # | %1 = load <16 x i8>, ptr %p.addr, align 16 # | %mask = and <16 x i8> %1, splat (i8 15) # | %shuf_idx = extractelement <16 x i8> %mask, i64 0 # | %shuf_elt = extractelement <16 x i8> %0, i8 %shuf_idx # | %shuf_ins = insertelement <16 x i8> poison, i8 %shuf_elt, i64 0 # | %shuf_idx1 = extractelement <16 x i8> %mask, i64 1 # | %shuf_elt2 = extractelement <16 x i8> %0, i8 %shuf_idx1 # | %shuf_ins3 = insertelement <16 x i8> %shuf_ins, i8 %shuf_elt2, i64 1 # | %shuf_idx4 = extractelement <16 x i8> %mask, i64 2 # | %shuf_elt5 = extractelement <16 x i8> %0, i8 %shuf_idx4 # | %shuf_ins6 = insertelement <16 x i8> %shuf_ins3, i8 %shuf_elt5, i64 2 # | %shuf_idx7 = extractelement <16 x i8> %mask, i64 3 # | %shuf_elt8 = extractelement <16 x i8> %0, i8 %shuf_idx7 # | %shuf_ins9 = insertelement <16 x i8> %shuf_ins6, i8 %shuf_elt8, i64 3 # | %shuf_idx10 = extractelement <16 x i8> %mask, i64 4 # | %shuf_elt11 = extractelement <16 x i8> %0, i8 %shuf_idx10 # | %shuf_ins12 = insertelement <16 x i8> %shuf_ins9, i8 %shuf_elt11, i64 4 # | %shuf_idx13 = extractelement <16 x i8> %mask, i64 5 # | %shuf_elt14 = extractelement <16 x i8> %0, i8 %shuf_idx13 # | %shuf_ins15 = insertelement <16 x i8> %shuf_ins12, i8 %shuf_elt14, i64 5 # | %shuf_idx16 = extractelement <16 x i8> %mask, i64 6 # | %shuf_elt17 = extractelement <16 x i8> %0, i8 %shuf_idx16 # | %shuf_ins18 = insertelement <16 x i8> %shuf_ins15, i8 %shuf_elt17, i64 6 # | %shuf_idx19 = extractelement <16 x i8> %mask, i64 7 # | %shuf_elt20 = extractelement <16 x i8> %0, i8 %shuf_idx19 # | %shuf_ins21 = insertelement <16 x i8> %shuf_ins18, i8 %shuf_elt20, i64 7 # | %shuf_idx22 = extractelement <16 x i8> %mask, i64 8 # | %shuf_elt23 = extractelement <16 x i8> %0, i8 %shuf_idx22 # | %shuf_ins24 = insertelement <16 x i8> %shuf_ins21, i8 %shuf_elt23, i64 8 # | %shuf_idx25 = extractelement <16 x i8> %mask, i64 9 # | %shuf_elt26 = extractelement <16 x i8> %0, i8 %shuf_idx25 # | %shuf_ins27 = insertelement <16 x i8> %shuf_ins24, i8 %shuf_elt26, i64 9 # | %shuf_idx28 = extractelement <16 x i8> %mask, i64 10 # | %shuf_elt29 = extractelement <16 x i8> %0, i8 %shuf_idx28 # | %shuf_ins30 = insertelement <16 x i8> %shuf_ins27, i8 %shuf_elt29, i64 10 # | %shuf_idx31 = extractelement <16 x i8> %mask, i64 11 # | %shuf_elt32 = extractelement <16 x i8> %0, i8 %shuf_idx31 # | %shuf_ins33 = insertelement <16 x i8> %shuf_ins30, i8 %shuf_elt32, i64 11 # | %shuf_idx34 = extractelement <16 x i8> %mask, i64 12 # | %shuf_elt35 = extractelement <16 x i8> %0, i8 %shuf_idx34 # | %shuf_ins36 = insertelement <16 x i8> %shuf_ins33, i8 %shuf_elt35, i64 12 # | %shuf_idx37 = extractelement <16 x i8> %mask, i64 13 # | %shuf_elt38 = extractelement <16 x i8> %0, i8 %shuf_idx37 # | %shuf_ins39 = insertelement <16 x i8> %shuf_ins36, i8 %shuf_elt38, i64 13 # | %shuf_idx40 = extractelement <16 x i8> %mask, i64 14 # | %shuf_elt41 = extractelement <16 x i8> %0, i8 %shuf_idx40 # | %shuf_ins42 = insertelement <16 x i8> %shuf_ins39, i8 %shuf_elt41, i64 14 # | %shuf_idx43 = extractelement <16 x i8> %mask, i64 15 # | %shuf_elt44 = extractelement <16 x i8> %0, i8 %shuf_idx43 # | %shuf_ins45 = insertelement <16 x i8> %shuf_ins42, i8 %shuf_elt44, i64 15 # | ret <16 x i8> %shuf_ins45 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005578575c857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005578575c5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005578575c8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f776cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f776cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f776cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f776cd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055785755e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055785755e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557857542f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005578571f2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005578571f1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f776cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f776cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f776cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005578571f1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c (1120 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("ri # | ... # `---data was truncated (10240/47480) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e32e8e857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e32e8e5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e32e8e8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7106249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f71062a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7106249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7106231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e32e87e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e32e87e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e32e862f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e32e512176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e32e511e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7106232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f71062330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f71062330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e32e511d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c (1121 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv1i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv2i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv4i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv8i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m1_m( %mask, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.mask.nxv1i64.nxv1i64.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m1_m( %mask, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | # | ... # `---data was truncated (10240/18867) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055868a2ea57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055868a2e7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055868a2eacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc81af05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc81af5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc81af05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc81aeed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055868a28024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055868a280096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055868a264f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558689f14176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558689f13e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc81aeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc81aeef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc81aeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558689f13d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c (1122 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16m8(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i8.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i8.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs # | ... # `---data was truncated (10240/15504) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e55639257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e55638f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e556392cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff76fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff76fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff76fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff76fe31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e55632824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e556328096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e55630cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e555fbc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e555fbbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff76fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff76fe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff76fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e555fbbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c (1123 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16mf4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16mf2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv16i16.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv16i16.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv16i16.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv16i16.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounw # | ... # `---data was truncated (10240/68141) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559ecc84657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559ecc843515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559ecc846cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f749d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f749d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f749d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f749d91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559ecc7dc24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559ecc7dc096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559ecc7c0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559ecc470176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559ecc46fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f749d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f749d91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f749d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559ecc46fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c (1124 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_i8mf4x5(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056343a2b457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056343a2b1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056343a2b4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb454049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb4540a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb454049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb454031507 abort ./stdlib/abort.c:85:3 # | #7 0x000056343a24a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056343a24a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056343a22ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563439ede176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563439edde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb454032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb4540330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb4540330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563439eddd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c (1125 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16mf4_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16mf2_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m1_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m2_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m4_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m8_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32mf2_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32m1_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv2f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretu # | ... # `---data was truncated (10240/77054) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b6c2f2d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b6c2f2a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b6c2f2dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f250e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f250e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f250e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f250e31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b6c2ec324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b6c2ec3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b6c2ea7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b6c2b57176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b6c2b56e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f250e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f250e31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f250e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b6c2b56d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c (1126 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | # | ... # `---data was truncated (10240/40891) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005605f3e1057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005605f3e0d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005605f3e10cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f082f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f082f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f082f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f082f11b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005605f3da624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005605f3da6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005605f3d8af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005605f3a3a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005605f3a39e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f082f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f082f11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f082f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005605f3a39d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c (1127 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_f32mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_f32mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv1f32.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_f32m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_f32m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv2f32.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind # | ... # `---data was truncated (10240/365431) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555ff905457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555ff9051515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555ff9054cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1a08f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1a08f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1a08f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1a08f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555ff8fea24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555ff8fea096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555ff8fcef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555ff8c7e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555ff8c7de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1a08f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1a08f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1a08f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555ff8c7dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c (1128 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005606d2a4557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005606d2a42515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005606d2a45cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9e4f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9e4f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9e4f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9e4f31b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005606d29db24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005606d29db096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005606d29bff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005606d266f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005606d266ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9e4f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9e4f31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9e4f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005606d266ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c (1129 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005596e246c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005596e2469515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005596e246ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fac93649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fac936a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fac93649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fac93631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005596e240224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005596e2402096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005596e23e6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005596e2096176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005596e2095e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fac93632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fac936330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fac936330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005596e2095d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c (1130 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32mf2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m1_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load # | ... # `---data was truncated (10240/14493) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056331562b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563315628515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056331562bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f83cac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f83caca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f83cac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f83cac31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005633155c124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005633155c1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005633155a5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563315255176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563315254e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f83cac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f83cac330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f83cac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563315254d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c (1131 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32mf2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1f32.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1f32.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2f32.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2f32.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv4f32.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4f32.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv8f32.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv8f32.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv16f32.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv16f32.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32mf2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1i32.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1i32.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2i32.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2i32.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv4i32.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4i32.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv8i32.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv8i32.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv16i32.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv16i32.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; # | ... # `---data was truncated (10240/14699) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a4e24e857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a4e24e5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a4e24e8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbaed849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbaed8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbaed849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbaed831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a4e247e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a4e247e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a4e2462f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a4e2112176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a4e2111e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbaed832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbaed8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbaed8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a4e2111d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c (1132 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32mf2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m1_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load < # | ... # `---data was truncated (10240/14421) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563b5e86657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563b5e863515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563b5e866cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7257049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f72570a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7257049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7257031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563b5e7fc24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563b5e7fc096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563b5e7e0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563b5e490176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563b5e48fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7257032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f72570330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f72570330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563b5e48fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c (1133 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b1_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv64i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b2_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv32i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b4_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv16i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b8_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv8i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b16_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv4i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv4i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b32_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv2i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv2i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b64_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv1i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv1i1.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056372433b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563724338515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056372433bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9c68649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9c686a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9c68649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9c68631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005637242d124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005637242d1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005637242b5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563723f65176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563723f64e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9c68632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9c686330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9c686330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563723f64d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c (1134 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv1i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv2i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv4i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv8i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv16i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv32i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv64i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv1i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv2i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv4i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv8i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv8i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv16i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv16i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = c # | ... # `---data was truncated (10240/41433) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056199bba857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056199bba5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056199bba8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7a0381bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7a038725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7a0381ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7a03803507 abort ./stdlib/abort.c:85:3 # | #7 0x000056199bb3e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056199bb3e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056199bb22f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056199b7d2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056199b7d1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7a03804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7a038050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7a038050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056199b7d1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c (1135 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zknh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c -check-prefix=RV32ZKNH # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zknh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sha256sig0(i32 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.sha256sig0(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sha256sig1(i32 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.sha256sig1(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sha256sum0(i32 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.sha256sum0(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sha256sum1(i32 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.sha256sum1(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sha512sig0h(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.sha512sig0h(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sha512sig0l(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.sha512sig0l(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sha512sig1h(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.sha512sig1h(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sha512sig1l(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.sha512sig1l(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sha512sum0r(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.sha512sum0r(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sha512sum1r(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.sha512sum1r(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha256sig0(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha256sig1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha256sum0(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha256sum1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha512sig0h(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha512sig0l(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha512sig1h(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha512sig1l(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha512sum0r(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha512sum1r(i32, i32) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zknh" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_zknh1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005620badd057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005620badcd515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005620badd0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffbb4849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffbb48a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffbb4849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffbb4831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005620bad6624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005620bad66096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005620bad4af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005620ba9fa176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005620ba9f9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ffbb4832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffbb48330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffbb48330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005620ba9f9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c -check-prefix=RV32ZKNH # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c -check-prefix=RV32ZKNH # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c (1136 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf8( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c (1137 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | ... # `---data was truncated (10240/302389) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fb639c657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fb639c3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fb639c6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7ae3133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7ae318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7ae3133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7ae311b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fb6395c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fb6395c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fb63940f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fb635f0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fb635efe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7ae311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7ae311d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7ae311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fb635efd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c (1138 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4e # | ... # `---data was truncated (10240/216250) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560856cb757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560856cb4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560856cb7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2671049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f26710a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2671049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2671031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560856c4d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560856c4d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560856c31f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005608568e1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005608568e0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2671032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f26710330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f26710330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005608568e0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcmlaq.c (1139 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcmlaq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %c.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store <8 x half> %c, ptr %c.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load <8 x half>, ptr %c.addr, align 8 # | %3 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 0, <8 x half> %0, <8 x half> %1, <8 x half> %2) # | ret <8 x half> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32, <8 x half>, <8 x half>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %c.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store <4 x float> %c, ptr %c.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load <4 x float>, ptr %c.addr, align 8 # | %3 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 0, <4 x float> %0, <4 x float> %1, <4 x float> %2) # | ret <4 x float> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32, <4 x float>, <4 x float>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot90_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %c.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store <8 x half> %c, ptr %c.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load <8 x half>, ptr %c.addr, align 8 # | %3 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 1, <8 x half> %0, <8 x half> %1, <8 x half> %2) # | ret <8 x half> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot90_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %c.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store <4 x float> %c, ptr %c.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load <4 x float>, ptr %c.addr, align 8 # | %3 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 1, <4 x float> %0, <4 x float> %1, <4 x float> %2) # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot180_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %c.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store <8 x half> %c, ptr %c.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load <8 x half>, ptr %c.addr, align 8 # | %3 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 2, <8 x half> %0, <8 x half> %1, <8 x half> %2) # | ret <8 x half> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot180_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %c.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store <4 x float> %c, ptr %c.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load <4 x float>, ptr %c.addr, align 8 # | %3 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 2, <4 x float> %0, <4 x float> %1, <4 x float> %2) # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot270_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %c.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store <8 x half> %c, ptr %c.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load <8 x half>, ptr %c.addr, align 8 # | %3 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 3, <8 x half> %0, <8 x half> %1, <8 x half> %2) # | ret <8 x half> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot270_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %c.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store <4 x float> %c, ptr %c.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load <4 x float>, ptr %c.addr, align 8 # | %3 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 3, <4 x float> %0, <4 x float> %1, <4 x float> %2) # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_m_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %c.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store <8 x half> %c, ptr %c.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load <8 x half>, ptr %c.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4) # | %6 = call <8 x half> @llvm.arm.mve.vcmlaq.predicated.v8f16.v8i1(i32 0, <8 x half> %0, <8 x half> %1, <8 x half> %2, <8 x i1> %5) # | ret <8 x half> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vcmlaq.predicated.v8f16.v8i1(i32, <8 x half>, <8 x half>, <8 x half>, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %c.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store <4 x float> %c, ptr %c.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load <4 x float>, ptr %c.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4) # | %6 = call <4 x float> @llvm.arm.mve.vcmlaq.predicated.v4f32.v4i1(i32 0, <4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x i1> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.vcmlaq.predicated.v4f32.v4i1(i32, <4 x float>, <4 x float>, <4 x float>, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot90_m_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %c.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store <8 x half> %c, ptr %c.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load <8 x half>, ptr %c.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4) # | %6 = call <8 x half> @llvm.arm.mve.vcmlaq.predicated.v8f16.v8i1(i32 1, <8 x half> %0, <8 x half> %1, <8 x half> %2, <8 x i1> %5) # | ret <8 x half> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot90_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %c.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store <4 x float> % # | ... # `---data was truncated (10240/15051) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b1ddb3557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b1ddb32515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b1ddb35cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffa7f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffa7f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffa7f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffa7f11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b1ddacb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b1ddacb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b1ddaaff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b1dd75f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b1dd75ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ffa7f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffa7f11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffa7f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b1dd75ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c (1140 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr # | ... # `---data was truncated (10240/97905) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fd4d83457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fd4d831515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fd4d834cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7b30705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7b3075c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7b30705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7b306ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fd4d7ca24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fd4d7ca096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fd4d7aef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fd4d45e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fd4d45de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7b306eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7b306ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7b306ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fd4d45dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c (1141 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8mf8_u8mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8mf4_u8mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8mf2_u8mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8m1_u8m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8m2_u8m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8m4_u8m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8m8_u8m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf8_i8mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf4_i8mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf2_i8mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m1_i8m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m2_i8m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m4_i8m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m8_i8m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16mf4_f16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16mf2_f16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16m1_f16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16m2_f16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16m4_f16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16m8_f16m8( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16mf4_f16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16mf2_f16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16m1_f16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16m2_f16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16m4_f16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16m8_f16m8( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | # | ... # `---data was truncated (10240/136489) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f66f71657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f66f713515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f66f716cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb983449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb9834a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb983449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb983431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f66f6ac24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f66f6ac096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f66f690f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f66f340176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f66f33fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb983432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb9834330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb9834330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f66f33fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c (1142 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c8d365a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c8d3657515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c8d365acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd57c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd57c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd57c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd57c91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c8d35f024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c8d35f0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c8d35d4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c8d3284176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c8d3283e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd57c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd57c91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd57c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c8d3283d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c (1143 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_s8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.clz.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clz.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_s16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.clz.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clz.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.clz.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clz.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.clz.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clz.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_u8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.clz.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_u16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.clz.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_u32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.clz.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.clz.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_s8_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.clz.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_s16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.clz.nxv8i16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c (1144 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.sqsub.x.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqsub.x.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.sqsub.x.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqsub.x.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.sqsub.x.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqsub.x.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.sqsub.x.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqsub.x.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uqsub.x.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqsub.x.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uqsub.x.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqsub.x.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uqsub.x.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqsub.x.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uqsub.x.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqsub.x.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_n_s8( %op1, i8 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i8, align 1 # | store %op1, ptr %op1.addr, align 16 # | store i8 %op2, ptr %op2.addr, align 1 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i8, ptr %op2.addr, align 1 # | %.splatinsert = insertelement poison, i8 %1, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %2 = call @llvm.aarch64.sve.sqsub.x.nxv16i8( %0, %.splat) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_n_s16( %op1, i16 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i16, align 2 # | store %op1, ptr %op1.addr, align 16 # | store i16 %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i16, ptr %op2.addr, align 2 # | %.splatinsert = insertelement poison, i16 %1, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %2 = call @llvm.aarch64.sve.sqsub.x.nxv8i16( %0, %.splat) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_n_s32( %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i32, align 4 # | store %op1, ptr %op1.addr, align 16 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i32, ptr %op2.addr, align 4 # | %.splatinsert = insertelement poison, i32 %1, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %2 = call @llvm.aarch64.sve.sqsub.x.nxv4i32( %0, %.splat) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_n_s64( %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 16 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i64, ptr %op2.addr, align 8 # | %.splatinsert = insertelement poison, i64 %1, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %2 = call @llvm.aarch64.sve.sqsub.x.nxv2i64( %0, %.splat) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_l # | ... # `---data was truncated (10240/13780) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055a4b12f557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a4b12f2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a4b12f5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f17a7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f17a778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f17a7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f17a771b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a4b128b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a4b128b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a4b126ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a4b0f1f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a4b0f1ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f17a771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f17a771d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f17a771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a4b0f1ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c (1145 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_v # | ... # `---data was truncated (10240/228865) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056524ecb657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056524ecb3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056524ecb6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa740b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa740b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa740b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa740b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056524ec4c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056524ec4c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056524ec30f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056524e8e0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056524e8dfe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa740b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa740b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa740b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056524e8dfd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c (1146 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.6a -target-feature +f8f32mm -target-feature +fp8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.6a -target-feature +f8f32mm -target-feature +fp8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local <4 x float> @test_vmmlaq_f32_mf8(<4 x float> noundef %p0, <16 x i8> %p1, <16 x i8> %p2, i64 noundef %p3) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__p3.addr.i = alloca i64, align 8 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <4 x float>, align 16 # | %p0.addr = alloca <4 x float>, align 16 # | %p1.addr = alloca <16 x i8>, align 16 # | %p2.addr = alloca <16 x i8>, align 16 # | %p3.addr = alloca i64, align 8 # | store <4 x float> %p0, ptr %p0.addr, align 16 # | store <16 x i8> %p1, ptr %p1.addr, align 16 # | store <16 x i8> %p2, ptr %p2.addr, align 16 # | store i64 %p3, ptr %p3.addr, align 8 # | %0 = load <4 x float>, ptr %p0.addr, align 16 # | %1 = load <16 x i8>, ptr %p1.addr, align 16 # | %2 = load <16 x i8>, ptr %p2.addr, align 16 # | %3 = load i64, ptr %p3.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | store i64 %3, ptr %__p3.addr.i, align 8 # | %4 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %6 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %7 = load i64, ptr %__p3.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %fmmla.i = call <4 x float> @llvm.aarch64.neon.fmmla.v4f32.v16i8(<4 x float> %4, <16 x i8> %5, <16 x i8> %6) # | store <4 x float> %fmmla.i, ptr %ref.tmp.i, align 16 # | %8 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %8, ptr %__ret.i, align 16 # | %9 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.aarch64.neon.fmmla.v4f32.v16i8(<4 x float>, <16 x i8>, <16 x i8>) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+bti,+ccidx,+cmpbr,+complxnum,+cpa,+crc,+cssc,+dit,+dotprod,+f8f32mm,+faminmax,+flagm,+fp-armv8,+fp8,+fullfp16,+hbc,+hinte,+i8mm,+jsconv,+lse,+lsui,+lut,+mec,+mops,+neon,+occmo,+pauth,+predres,+ras,+rasv2,+rcpc,+rdm,+rme,+sb,+spe-eef,+specres2,+ssbs,+sve,+sve2,+sve2p1,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v8.9a,+v8a,+v9.1a,+v9.2a,+v9.3a,+v9.4a,+v9.5a,+v9.6a,+v9a,+wfxt" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055ebe228a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ebe2287515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ebe228acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbe24249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbe242a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbe24249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbe24231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ebe222024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ebe2220096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ebe2204f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ebe1eb4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ebe1eb3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbe24232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbe242330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbe242330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ebe1eb3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c (1147 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8mf8x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8mf4x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_u8mf8x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_u8mf4x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_u8mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_u8m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8mf8x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8mf4x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, pt # | ... # `---data was truncated (10240/18980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056354d25757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056354d254515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056354d257cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f805e01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f805e0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f805e01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f805e003507 abort ./stdlib/abort.c:85:3 # | #7 0x000056354d1ed24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056354d1ed096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056354d1d1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056354ce81176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056354ce80e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f805e004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f805e0050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f805e0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056354ce80d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c (1148 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f32m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/128444) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005634e1fa857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005634e1fa5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005634e1fa8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc39e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc39e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc39e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc39e91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005634e1f3e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005634e1f3e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005634e1f22f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005634e1bd2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005634e1bd1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc39e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc39e91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc39e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005634e1bd1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c (1149 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf8x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf4x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf8x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf4x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005568ee02e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005568ee02b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005568ee02ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0f29849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0f298a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0f29849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0f29831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005568edfc424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005568edfc4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005568edfa8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005568edc58176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005568edc57e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0f29832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0f298330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0f298330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005568edc57d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c (1150 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b1_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv64i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b2_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv32i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b4_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv16i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b8_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv8i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b16_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv4i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv4i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b32_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv2i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv2i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b64_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv1i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv1i1.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558d9445c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558d94459515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558d9445ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f17fa849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f17fa8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f17fa849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f17fa831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558d943f224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558d943f2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558d943d6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558d94086176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558d94085e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f17fa832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f17fa8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f17fa8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558d94085d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c (1151 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c (1152 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_f32mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_f32mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv1f32.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_f32m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_f32m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv2f32.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind # | ... # `---data was truncated (10240/365431) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cf86e8657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cf86e83515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cf86e86cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f24b9f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f24b9f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f24b9f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f24b9eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cf86e1c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cf86e1c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cf86e00f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cf86ab0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cf86aafe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f24b9eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f24b9eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f24b9eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cf86aafd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c (1153 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv1f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv2f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv4f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv8f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m8_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m1_tumu( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 # | ... # `---data was truncated (10240/18303) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ef1b6b357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ef1b6b0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ef1b6b3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb121f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb121f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb121f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb121f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ef1b64924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ef1b649096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ef1b62df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ef1b2dd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ef1b2dce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb121f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb121f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb121f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ef1b2dcd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c (1154 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vx_i16mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wx_i16mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.w.nxv1i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vx_i16mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wx_i16mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.w.nxv2i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vx_i16m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wv_i16m1(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c (1155 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op # | ... # `---data was truncated (10240/222917) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a5865a457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a5865a1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a5865a4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f407dd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f407dd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f407dd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f407dced507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a58653a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a58653a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a58651ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a5861ce176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a5861cde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f407dceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f407dcef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f407dcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a5861cdd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c (1156 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16mf2_f16mf4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1f16.nxv2f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f16.nxv2f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m1_f16mf4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1f16.nxv4f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f16.nxv4f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m1_f16mf2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2f16.nxv4f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f16.nxv4f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m2_f16mf4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1f16.nxv8f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f16.nxv8f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m2_f16mf2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2f16.nxv8f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f16.nxv8f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m2_f16m1( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv8f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv8f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m4_f16mf4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m4_f16mf2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m4_f16m1( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m4_f16m2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m8_f16mf4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m8_f16mf2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m8_f16m1( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m8_f16m2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m8_f16m4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv16f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv16f16.nxv32f16(, i64 im # | ... # `---data was truncated (10240/78242) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b50a2af57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b50a2ac515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b50a2afcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8538a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8538aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8538a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8538a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b50a24524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b50a245096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b50a229f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b509ed9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b509ed8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8538a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8538a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8538a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b509ed8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c (1157 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_i8mf8x8 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d9681b857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d9681b5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d9681b8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fea80305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fea8035c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fea80305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fea802ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d96814e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d96814e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d968132f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d967de2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d967de1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fea802eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fea802ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fea802ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d967de1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c (1158 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv1i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv2i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv4i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv8i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv16i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv16i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8 # | ... # `---data was truncated (10240/99577) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005628451a557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005628451a2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005628451a5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6527b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6527b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6527b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6527b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056284513b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056284513b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056284511ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562844dcf176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562844dcee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6527b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6527b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6527b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562844dced81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c (1159 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562d3b08f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562d3b08c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562d3b08fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fafdd733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fafdd78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fafdd733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fafdd71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562d3b02524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562d3b025096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562d3b009f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562d3acb9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562d3acb8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fafdd71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fafdd71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fafdd71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562d3acb8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c (1160 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32mf2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m1( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m4( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(, ha # | ... # `---data was truncated (10240/90685) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556239e2257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556239e1f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556239e22cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f316a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f316a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f316a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f316a91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556239db824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556239db8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556239d9cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556239a4c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556239a4be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f316a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f316a91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f316a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556239a4bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c (1161 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.nxv16i8( %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.pred.lane.nxv16i8(, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_s8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.nxv16i8( %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.nxv8i16( %0, i32 0) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.pred.lane.nxv8i16(, i32 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_s16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.nxv8i16( %0, i32 1) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.nxv4i32( %0, i32 0) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.pred.lane.nxv4i32(, i32 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_s32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.nxv4i32( %0, i32 3) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u64( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.nxv2i64( %0, i32 0) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.pred.lane.nxv2i64(, i32 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_s64( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.nxv2i64( %0, i32 7) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_u8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv16i8( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv16i8() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_s8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv16i8( %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_u16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv8i16( %0) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv8i16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_s16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv8i16( %0) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_u32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv4i32( %0) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv4i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_s32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv4i32( %0) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_u64( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv2i64( %0) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv2i64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c (1162 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv1i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv2i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv4i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv8i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/225205) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560097afb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560097af8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560097afbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faeced33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faeced8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faeced33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faeced1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560097a9124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560097a91096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560097a75f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560097725176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560097724e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007faeced1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faeced1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faeced1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560097724d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c (1163 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_f64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_i64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_u64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_f64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_i64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_u64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a05243257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a05242f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a052432cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcbc2d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcbc2d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcbc2d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcbc2d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a0523c824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a0523c8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a0523acf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a05205c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a05205be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcbc2d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcbc2d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcbc2d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a05205bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c (1164 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8mf8(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 5) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8mf4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 6) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8mf2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 7) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8m1(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 0) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8m2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8m4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8m8(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16mf4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 6) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16mf2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 7) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16m1(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 0) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16m2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16m4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16m8(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e32mf2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 7) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e32m1(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 0) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e32m2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e32m4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e32m8(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e64m1(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 0) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e64m2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e64m4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e64m8(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 3) # | ret i64 %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055757fa3957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055757fa36515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055757fa39cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdd1fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdd1fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdd1fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdd1fb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055757f9cf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055757f9cf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055757f9b3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055757f663176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055757f662e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fdd1fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdd1fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdd1fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055757f662d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c (1165 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16mf4x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16mf4x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16mf4x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_ # | ... # `---data was truncated (10240/10396) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055688ae1557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055688ae12515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055688ae15cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efc49933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efc4998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efc49933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efc4991b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055688adab24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055688adab096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055688ad8ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055688aa3f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055688aa3ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efc4991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efc4991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efc4991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055688aa3ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c (1166 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -target-feature +fp8dot2 -target-feature +fp8dot4 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -target-feature +fp8dot2 -target-feature +fp8dot4 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vdot_f16(<4 x half> noundef %vd, <8 x i8> %vn, <8 x i8> %vm, i64 noundef %fpmr) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__p3.addr.i = alloca i64, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <4 x half>, align 8 # | %vd.addr = alloca <4 x half>, align 8 # | %vn.addr = alloca <8 x i8>, align 8 # | %vm.addr = alloca <8 x i8>, align 8 # | %fpmr.addr = alloca i64, align 8 # | store <4 x half> %vd, ptr %vd.addr, align 8 # | store <8 x i8> %vn, ptr %vn.addr, align 8 # | store <8 x i8> %vm, ptr %vm.addr, align 8 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load <4 x half>, ptr %vd.addr, align 8 # | %1 = load <8 x i8>, ptr %vn.addr, align 8 # | %2 = load <8 x i8>, ptr %vm.addr, align 8 # | %3 = load i64, ptr %fpmr.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | store <8 x i8> %2, ptr %__p2.addr.i, align 8 # | store i64 %3, ptr %__p3.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %6 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %7 = load i64, ptr %__p3.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %fdot2.i = bitcast <8 x i8> %4 to <4 x half> # | %fdot21.i = call <4 x half> @llvm.aarch64.neon.fp8.fdot2.v4f16.v8i8(<4 x half> %fdot2.i, <8 x i8> %5, <8 x i8> %6) # | store <4 x half> %fdot21.i, ptr %ref.tmp.i, align 8 # | %8 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %8, ptr %__ret.i, align 8 # | %9 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vdotq_f16(<8 x half> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpmr) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__p3.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <8 x half>, align 16 # | %vd.addr = alloca <8 x half>, align 16 # | %vn.addr = alloca <16 x i8>, align 16 # | %vm.addr = alloca <16 x i8>, align 16 # | %fpmr.addr = alloca i64, align 8 # | store <8 x half> %vd, ptr %vd.addr, align 16 # | store <16 x i8> %vn, ptr %vn.addr, align 16 # | store <16 x i8> %vm, ptr %vm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load <8 x half>, ptr %vd.addr, align 16 # | %1 = load <16 x i8>, ptr %vn.addr, align 16 # | %2 = load <16 x i8>, ptr %vm.addr, align 16 # | %3 = load i64, ptr %fpmr.addr, align 8 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | store i64 %3, ptr %__p3.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %6 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %7 = load i64, ptr %__p3.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %fdot2.i = bitcast <16 x i8> %4 to <8 x half> # | %fdot21.i = call <8 x half> @llvm.aarch64.neon.fp8.fdot2.v8f16.v16i8(<8 x half> %fdot2.i, <16 x i8> %5, <16 x i8> %6) # | store <8 x half> %fdot21.i, ptr %ref.tmp.i, align 16 # | %8 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %8, ptr %__ret.i, align 16 # | %9 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vdot_lane_f16(<4 x half> noundef %vd, <8 x i8> %vn, <8 x i8> %vm, i64 noundef %fpmr) #0 { # | entry: # | %vd.addr = alloca <4 x half>, align 8 # | %vn.addr = alloca <8 x i8>, align 8 # | %vm.addr = alloca <8 x i8>, align 8 # | %fpmr.addr = alloca i64, align 8 # | %__ret = alloca <4 x half>, align 8 # | %__s0 = alloca <4 x half>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | %__s2 = alloca <8 x i8>, align 8 # | %__s4 = alloca i64, align 8 # | %ref.tmp = alloca <4 x half>, align 8 # | %tmp = alloca <4 x half>, align 8 # | store <4 x half> %vd, ptr %vd.addr, align 8 # | store <8 x i8> %vn, ptr %vn.addr, align 8 # | store <8 x i8> %vm, ptr %vm.addr, align 8 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load <4 x half>, ptr %vd.addr, align 8 # | store <4 x half> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %vn.addr, align 8 # | store <8 x i8> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %vm.addr, align 8 # | store <8 x i8> %2, ptr %__s2, align 8 # | %3 = load i64, ptr %fpmr.addr, align 8 # | store i64 %3, ptr %__s4, align 8 # | %4 = load <8 x i8>, ptr %__s0, align 8 # | %5 = load <8 x i8>, ptr %__s1, align 8 # | %6 = load <8 x i8>, ptr %__s2, align 8 # | %7 = load i64, ptr %__s4, align 8 # | %8 = call <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8> poison, <8 x i8> %6, i64 0) # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %fdot2_lane = bitcast <8 x i8> %4 to <4 x half> # | %fdot2_lane1 = call <4 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v4f16.v8i8(<4 x half> %fdot2_lane, <8 x i8> %5, <16 x i8> %8, i32 3) # | store <4 x half> %fdot2_lane1, ptr %ref.tmp, align 8 # | %9 = load <4 x half>, ptr %ref.tmp, align 8 # | store <4 x half> %9, ptr %__ret, align 8 # | %10 = load <4 x half>, ptr %__ret, align 8 # | store <4 x half> %10, ptr %tmp, align 8 # | %11 = load <4 x half>, ptr %tmp, align 8 # | ret <4 x half> %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8>, <8 x i8>, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare <4 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v4f16.v8i8(<4 x half>, <8 x i8>, <16 x i8>, i32 immarg) #3 # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vdot_laneq_f16(<4 x half> noundef %vd, <8 x i8> %vn, <16 x i8> %vm, i64 noundef %fpmr) #0 { # | entry: # | %vd.addr = alloca <4 x half>, align 8 # | %vn.addr = alloca <8 x i8>, align 8 # | %vm.addr = alloca <16 x i8>, align 16 # | %fpmr.addr = alloca i64, align 8 # | %__ret = alloca <4 x half>, align 8 # | %__s0 = alloca <4 x half>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | %__s2 = alloca <16 x i8>, align 16 # | %__s4 = alloca i64, align 8 # | %ref.tmp = alloca <4 x half>, align 8 # | %tmp = alloca <4 x half>, align 8 # | store <4 x half> %vd, ptr %vd.addr, align 8 # | store <8 x i8> %vn, ptr %vn.addr, align 8 # | store <16 x i8> %vm, ptr %vm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load <4 x half>, ptr %vd.addr, align 8 # | store <4 x half> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %vn.addr, align 8 # | store <8 x i8> %1, ptr %__s1, align 8 # | %2 = load <16 x i8>, ptr %vm.addr, align 16 # | store <16 x i8> %2, ptr %__s2, align 16 # | %3 = load i64, ptr %fpmr.addr, align 8 # | store i64 %3, ptr %__s4, align 8 # | %4 = load <8 x i8>, ptr %__s0, align 8 # | %5 = load <8 x i8>, ptr %__s1, align 8 # | %6 = load <16 x i8>, ptr %__s2, align 16 # | %7 = load i64, ptr %__s4, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %fdot2_lane = bitcast <8 x i8> %4 to <4 x half> # | %fdot2_lane1 = call <4 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v4f16.v8i8(<4 x half> %fdot2_lane, <8 x i8> %5, <16 x i8> %6, i32 7) # | store <4 x half> %fdot2_lane1, ptr %ref.tmp, align 8 # | %8 = load <4 x half>, ptr %ref.tmp, align 8 # | store <4 x half> %8, ptr %__ret, align 8 # | %9 = load <4 x half>, ptr %__ret, align 8 # | store <4 x half> %9, ptr %tmp, align 8 # | %10 = load <4 x half>, ptr %tmp, align 8 # | ret <4 x half> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vdotq_lane_f16(<8 x half> noundef %vd, <16 x i8> %vn, <8 x i8> %vm, i64 noundef %fpmr) #0 { # | entry: # | %vd.addr = alloca <8 x half>, align 16 # | %vn.addr = alloca <16 x i8>, align 16 # | %vm.addr = alloca <8 x i8>, align 8 # | %fpmr.addr = alloca i64, align 8 # | %__ret = alloca <8 x half>, align 16 # | %__s0 = alloca <8 x half>, align 16 # | %__s1 = alloca <16 x i8>, align 16 # | %__s2 = alloca <8 x i8>, align 8 # | %__s4 = alloca i64, align 8 # | %ref.tmp = alloca <8 x half>, align 16 # | %tmp = alloca <8 x half>, align 16 # | store <8 x half> %vd, ptr %vd.addr, align 16 # | store <16 x i8> %vn, ptr %vn.addr, align 16 # | store <8 x i8> %vm, ptr %vm.addr, align 8 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load <8 x half>, ptr %vd.addr, align 16 # | store <8 x half> %0, ptr %__s0, align 16 # | %1 = load <16 x i8>, ptr %vn.addr, align 16 # | store <16 x i8> %1, ptr %__s1, align 16 # | %2 = load <8 x i8>, ptr %vm.addr, align 8 # | store <8 x i8> %2, ptr %__s2, align 8 # | %3 = load i64, ptr %fpmr.addr, align 8 # | store i64 %3, ptr %__s4, align 8 # | %4 = load <16 x i8>, ptr %__s0, align 16 # | %5 = load <16 x i8>, ptr %__s1, align 16 # | %6 = load <8 x i8>, ptr %__s2, align 8 # | %7 = load i64, ptr %__s4, align 8 # | %8 = call <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8> poison, <8 x i8> %6, i64 0) # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %fdot2_lane = bitcast <16 x i8> %4 to <8 x half> # | %fdot2_lane1 = call <8 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v8f16.v16i8(<8 x half> %fdot2_lane, <16 x i8> %5, <16 x i8> %8, i32 3) # | store <8 x half> %fdot2_lane1, ptr %ref.tmp, align 16 # | %9 = load <8 x half>, ptr %ref.tmp, align 16 # | store <8 x half> %9, ptr %__ret, align 16 # | %10 = load <8 x half>, ptr %__ret, align 16 # | store <8 x half> %10, ptr %tmp, align 16 # | %11 = load <8 x half>, ptr %tmp, align 16 # | ret <8 x half> %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare <8 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v8f16.v16i8(<8 x half>, <16 x i8>, <16 x i8>, i32 immarg) #3 # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vdotq_laneq_f16(<8 x half> noundef %vd, <16 x i8> %vn, < # | ... # `---data was truncated (10240/24508) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa # | #0 0x0000555ec5c6557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555ec5c62515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555ec5c65cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f71d7449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f71d74a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f71d7449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f71d7431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555ec5bfb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555ec5bfb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555ec5bdff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555ec588f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555ec588ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f71d7432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f71d74330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f71d74330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555ec588ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/neon-ldst-one-rcpc3.c (1167 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon-ldst-one-rcpc3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +rcpc3 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +rcpc3 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vldap1q_lane_u64(ptr noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <2 x i64>, align 16 # | %__ret = alloca <2 x i64>, align 16 # | %__s1 = alloca <2 x i64>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <2 x i64>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %0, ptr %__s1, align 16 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %__s1, align 16 # | %3 = bitcast <16 x i8> %2 to <2 x i64> # | %4 = load atomic i64, ptr %1 acquire, align 8 # | %vldap1_lane = insertelement <2 x i64> %3, i64 %4, i32 1 # | store <2 x i64> %vldap1_lane, ptr %ref.tmp, align 16 # | %5 = load <2 x i64>, ptr %ref.tmp, align 16 # | store <2 x i64> %5, ptr %__ret, align 16 # | %6 = load <2 x i64>, ptr %__ret, align 16 # | store <2 x i64> %6, ptr %tmp, align 16 # | %7 = load <2 x i64>, ptr %tmp, align 16 # | ret <2 x i64> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vldap1q_lane_s64(ptr noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <2 x i64>, align 16 # | %__ret = alloca <2 x i64>, align 16 # | %__s1 = alloca <2 x i64>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <2 x i64>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %0, ptr %__s1, align 16 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %__s1, align 16 # | %3 = bitcast <16 x i8> %2 to <2 x i64> # | %4 = load atomic i64, ptr %1 acquire, align 8 # | %vldap1_lane = insertelement <2 x i64> %3, i64 %4, i32 1 # | store <2 x i64> %vldap1_lane, ptr %ref.tmp, align 16 # | %5 = load <2 x i64>, ptr %ref.tmp, align 16 # | store <2 x i64> %5, ptr %__ret, align 16 # | %6 = load <2 x i64>, ptr %__ret, align 16 # | store <2 x i64> %6, ptr %tmp, align 16 # | %7 = load <2 x i64>, ptr %tmp, align 16 # | ret <2 x i64> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vldap1q_lane_f64(ptr noundef %a, <2 x double> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <2 x double>, align 16 # | %__ret = alloca <2 x double>, align 16 # | %__s1 = alloca <2 x double>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <2 x double>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | store <2 x double> %b, ptr %b.addr, align 16 # | %0 = load <2 x double>, ptr %b.addr, align 16 # | store <2 x double> %0, ptr %__s1, align 16 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %__s1, align 16 # | %3 = bitcast <16 x i8> %2 to <2 x double> # | %4 = load atomic double, ptr %1 acquire, align 8 # | %vldap1_lane = insertelement <2 x double> %3, double %4, i32 1 # | store <2 x double> %vldap1_lane, ptr %ref.tmp, align 16 # | %5 = load <2 x double>, ptr %ref.tmp, align 16 # | store <2 x double> %5, ptr %__ret, align 16 # | %6 = load <2 x double>, ptr %__ret, align 16 # | store <2 x double> %6, ptr %tmp, align 16 # | %7 = load <2 x double>, ptr %tmp, align 16 # | ret <2 x double> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vldap1q_lane_p64(ptr noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <2 x i64>, align 16 # | %__ret = alloca <2 x i64>, align 16 # | %__s1 = alloca <2 x i64>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <2 x i64>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %0, ptr %__s1, align 16 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %__s1, align 16 # | %3 = bitcast <16 x i8> %2 to <2 x i64> # | %4 = load atomic i64, ptr %1 acquire, align 8 # | %vldap1_lane = insertelement <2 x i64> %3, i64 %4, i32 1 # | store <2 x i64> %vldap1_lane, ptr %ref.tmp, align 16 # | %5 = load <2 x i64>, ptr %ref.tmp, align 16 # | store <2 x i64> %5, ptr %__ret, align 16 # | %6 = load <2 x i64>, ptr %__ret, align 16 # | store <2 x i64> %6, ptr %tmp, align 16 # | %7 = load <2 x i64>, ptr %tmp, align 16 # | ret <2 x i64> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vldap1_lane_u64(ptr noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | %__ret = alloca <1 x i64>, align 8 # | %__s1 = alloca <1 x i64>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <1 x i64>, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | %3 = bitcast <8 x i8> %2 to <1 x i64> # | %4 = load atomic i64, ptr %1 acquire, align 8 # | %vldap1_lane = insertelement <1 x i64> %3, i64 %4, i32 0 # | store <1 x i64> %vldap1_lane, ptr %ref.tmp, align 8 # | %5 = load <1 x i64>, ptr %ref.tmp, align 8 # | store <1 x i64> %5, ptr %__ret, align 8 # | %6 = load <1 x i64>, ptr %__ret, align 8 # | store <1 x i64> %6, ptr %tmp, align 8 # | %7 = load <1 x i64>, ptr %tmp, align 8 # | ret <1 x i64> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vldap1_lane_s64(ptr noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | %__ret = alloca <1 x i64>, align 8 # | %__s1 = alloca <1 x i64>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <1 x i64>, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | %3 = bitcast <8 x i8> %2 to <1 x i64> # | %4 = load atomic i64, ptr %1 acquire, align 8 # | %vldap1_lane = insertelement <1 x i64> %3, i64 %4, i32 0 # | store <1 x i64> %vldap1_lane, ptr %ref.tmp, align 8 # | %5 = load <1 x i64>, ptr %ref.tmp, align 8 # | store <1 x i64> %5, ptr %__ret, align 8 # | %6 = load <1 x i64>, ptr %__ret, align 8 # | store <1 x i64> %6, ptr %tmp, align 8 # | %7 = load <1 x i64>, ptr %tmp, align 8 # | ret <1 x i64> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vldap1_lane_f64(ptr noundef %a, <1 x double> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <1 x double>, align 8 # | %__ret = alloca <1 x double>, align 8 # | %__s1 = alloca <1 x double>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <1 x double>, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store <1 x double> %b, ptr %b.addr, align 8 # | %0 = load <1 x double>, ptr %b.addr, align 8 # | store <1 x double> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | %3 = bitcast <8 x i8> %2 to <1 x double> # | %4 = load atomic double, ptr %1 acquire, align 8 # | %vldap1_lane = insertelement <1 x double> %3, double %4, i32 0 # | store <1 x double> %vldap1_lane, ptr %ref.tmp, align 8 # | %5 = load <1 x double>, ptr %ref.tmp, align 8 # | store <1 x double> %5, ptr %__ret, align 8 # | %6 = load <1 x double>, ptr %__ret, align 8 # | store <1 x double> %6, ptr %tmp, align 8 # | %7 = load <1 x double>, ptr %tmp, align 8 # | ret <1 x double> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vldap1_lane_p64(ptr noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | %__ret = alloca <1 x i64>, align 8 # | %__s1 = alloca <1 x i64>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <1 x i64>, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | %3 = bitcast <8 x i8> %2 to <1 x i64> # | %4 = load atomic i64, ptr %1 acquire, align 8 # | %vldap1_lane = insertelement <1 x i64> %3, i64 %4, i32 0 # | store <1 x i64> %vldap1_lane, ptr %ref.tmp, align 8 # | %5 = load <1 x i64>, ptr %ref.tmp, align 8 # | store <1 x i64> %5, ptr %__ret, align 8 # | %6 = load <1 x i64>, ptr %__ret, align 8 # | store <1 x i64> %6, ptr %tmp, align 8 # | %7 = load <1 x i64>, ptr %tmp, align 8 # | ret <1 x i64> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vstl1q_lane_u64(ptr noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <2 x i64>, align 16 # | %__s1 = alloca <2 x i64>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %0, ptr %__s1, align 16 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %__s1, align 16 # | %3 = bitcast <16 x i8> %2 to <2 x i64> # | %4 = extractelement <2 x i64> %3, i32 1 # | store atomic i64 %4, ptr %1 release, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vstl1q_lane_s64(ptr noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <2 x i64>, align 16 # | %__s1 = alloca <2 x i64>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %0, ptr %__s1, align 16 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %__s1, align 16 # | %3 = bitcast <16 x i8> %2 to <2 x i64> # | %4 = extractelement <2 x i64> %3, i32 1 # | store atomic i64 %4, ptr %1 release, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vstl1q_lane_f64(ptr noundef %a, <2 x double> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca # | ... # `---data was truncated (10240/14230) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000564e1510757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564e15104515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564e15107cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0790049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f07900a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0790049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0790031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564e1509d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564e1509d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564e15081f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564e14d31176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564e14d30e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0790032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f07900330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f07900330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564e14d30d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c (1168 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr # | ... # `---data was truncated (10240/97905) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056038061e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056038061b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056038061ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa387849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa3878a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa387849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa387831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005603805b424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005603805b4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560380598f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560380248176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560380247e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa387832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa3878330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa3878330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560380247d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/neon/rounding-v8.5.c (1169 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon/rounding-v8.5.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +v8.5a -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c --check-prefixes=LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +v8.5a -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrnd32x_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrnd32x_f32.i = bitcast <8 x i8> %1 to <2 x float> # | %vrnd32x_f321.i = call <2 x float> @llvm.aarch64.neon.frint32x.v2f32(<2 x float> %vrnd32x_f32.i) # | %vrnd32x_f322.i = bitcast <2 x float> %vrnd32x_f321.i to <8 x i8> # | store <8 x i8> %vrnd32x_f322.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrnd32xq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrnd32xq_f32.i = bitcast <16 x i8> %1 to <4 x float> # | %vrnd32xq_f321.i = call <4 x float> @llvm.aarch64.neon.frint32x.v4f32(<4 x float> %vrnd32xq_f32.i) # | %vrnd32xq_f322.i = bitcast <4 x float> %vrnd32xq_f321.i to <16 x i8> # | store <16 x i8> %vrnd32xq_f322.i, ptr %ref.tmp.i, align 16 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %2, ptr %__ret.i, align 16 # | %3 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrnd32z_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrnd32z_f32.i = bitcast <8 x i8> %1 to <2 x float> # | %vrnd32z_f321.i = call <2 x float> @llvm.aarch64.neon.frint32z.v2f32(<2 x float> %vrnd32z_f32.i) # | %vrnd32z_f322.i = bitcast <2 x float> %vrnd32z_f321.i to <8 x i8> # | store <8 x i8> %vrnd32z_f322.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrnd32zq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrnd32zq_f32.i = bitcast <16 x i8> %1 to <4 x float> # | %vrnd32zq_f321.i = call <4 x float> @llvm.aarch64.neon.frint32z.v4f32(<4 x float> %vrnd32zq_f32.i) # | %vrnd32zq_f322.i = bitcast <4 x float> %vrnd32zq_f321.i to <16 x i8> # | store <16 x i8> %vrnd32zq_f322.i, ptr %ref.tmp.i, align 16 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %2, ptr %__ret.i, align 16 # | %3 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrnd64x_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrnd64x_f32.i = bitcast <8 x i8> %1 to <2 x float> # | %vrnd64x_f321.i = call <2 x float> @llvm.aarch64.neon.frint64x.v2f32(<2 x float> %vrnd64x_f32.i) # | %vrnd64x_f322.i = bitcast <2 x float> %vrnd64x_f321.i to <8 x i8> # | store <8 x i8> %vrnd64x_f322.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrnd64xq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrnd64xq_f32.i = bitcast <16 x i8> %1 to <4 x float> # | %vrnd64xq_f321.i = call <4 x float> @llvm.aarch64.neon.frint64x.v4f32(<4 x float> %vrnd64xq_f32.i) # | %vrnd64xq_f322.i = bitcast <4 x float> %vrnd64xq_f321.i to <16 x i8> # | store <16 x i8> %vrnd64xq_f322.i, ptr %ref.tmp.i, align 16 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %2, ptr %__ret.i, align 16 # | %3 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrnd64z_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrnd64z_f32.i = bitcast <8 x i8> %1 to <2 x float> # | %vrnd64z_f321.i = call <2 x float> @llvm.aarch64.neon.frint64z.v2f32(<2 x float> %vrnd64z_f32.i) # | %vrnd64z_f322.i = bitcast <2 x float> %vrnd64z_f321.i to <8 x i8> # | store <8 x i8> %vrnd64z_f322.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrnd64zq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrnd64zq_f32.i = bitcast <16 x i8> %1 to <4 x float> # | %vrnd64zq_f321.i = call <4 x float> @llvm.aarch64.neon.frint64z.v4f32(<4 x float> %vrnd64zq_f32.i) # | %vrnd64zq_f322.i = bitcast <4 x float> %vrnd64zq_f321.i to <16 x i8> # | store <16 x i8> %vrnd64zq_f322.i, ptr %ref.tmp.i, align 16 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %2, ptr %__ret.i, align 16 # | %3 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vrnd32x_f64(<1 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x double>, align 8 # | %__ret.i = alloca <1 x double>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrnd32x_f64.i = bitcast <8 x i8> %1 to <1 x double> # | %vrnd32x_f641.i = call <1 x double> @llvm.aarch64.neon.frint32x.v1f64(<1 x double> %vrnd32x_f64.i) # | %vrnd32x_f642.i = bitcast <1 x double> %vrnd32x_f641.i to <8 x i8> # | store <8 x i8> %vrnd32x_f642.i, ptr %ref.tmp.i, align 8 # | %2 = load <1 x double>, ptr %ref.tmp.i, align 8 # | store <1 x double> %2, ptr %__ret.i, align 8 # | %3 = load <1 x double>, ptr %__ret.i, align 8 # | ret <1 x double> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vrnd32xq_f64(<2 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrnd32xq_f64.i = bitcast <16 x i8> %1 to <2 x double> # | %vrnd32xq_f641.i = call <2 x double> @llvm.aarch64.neon.frint32x.v2f64(<2 x double> %vrnd32xq_f64.i) # | %vrnd32xq_f642.i = bitcast <2 x double> %vrnd32xq_f641.i to <16 x i8> # | store <16 x i8> %vrnd32xq_f642.i, ptr %ref.tmp.i, align 16 # | %2 = load <2 x double>, ptr %ref.tmp.i, align 16 # | store <2 x double> %2, ptr %__ret.i, align 16 # | %3 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vrnd32z_f64(<1 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x double>, align 8 # | %__ret.i = alloca <1 x double>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrnd32z_f64.i = bitcast <8 x i8> %1 # | ... # `---data was truncated (10240/18543) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000557e7ae6f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557e7ae6c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557e7ae6fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc8e3e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc8e3ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc8e3e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc8e3e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557e7ae0524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557e7ae05096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557e7ade9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557e7aa99176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557e7aa98e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc8e3e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc8e3e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc8e3e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557e7aa98d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c --check-prefixes=LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c --check-prefixes=LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c (1170 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv1f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv1f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define d # | ... # `---data was truncated (10240/51420) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f7b5bc957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f7b5bc6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f7b5bc9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc1b8c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc1b8ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc1b8c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc1b8c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f7b5b5f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f7b5b5f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f7b5b43f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f7b57f3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f7b57f2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc1b8c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc1b8c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc1b8c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f7b57f2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c (1171 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16m2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, alig # | ... # `---data was truncated (10240/150641) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b05f0c957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b05f0c6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b05f0c9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3a30f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3a30f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3a30f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3a30f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b05f05f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b05f05f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b05f043f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b05ecf3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b05ecf2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3a30f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3a30f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3a30f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b05ecf2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c (1172 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf4_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m1_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m4_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m8_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf4_tum( %mask, %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load float, ptr %op2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf2_tum( %mask, %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load float, ptr %op2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64( %1, %2, float %3, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c (1173 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf8_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf4_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf2_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8m1_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd # | ... # `---data was truncated (10240/215044) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005561bb0b957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005561bb0b6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005561bb0b9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007febc0c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007febc0c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007febc0c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007febc0c03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005561bb04f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005561bb04f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005561bb033f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005561bace3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005561bace2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007febc0c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007febc0c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007febc0c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005561bace2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c (1174 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/175163) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e2fe82357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e2fe820515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e2fe823cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f708c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f708c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f708c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f708c51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e2fe7b924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e2fe7b9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e2fe79df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e2fe44d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e2fe44ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f708c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f708c51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f708c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e2fe44cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c (1175 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vx_i16mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wx_i16mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.w.nxv1i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vx_i16mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wx_i16mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.w.nxv2i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vx_i16m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wv_i16m # | ... # `---data was truncated (10240/134565) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558f9193d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558f9193a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558f9193dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff3e8d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff3e8d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff3e8d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff3e8ced507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558f918d324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558f918d3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558f918b7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558f91567176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558f91566e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff3e8ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff3e8cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff3e8cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558f91566d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c (1176 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c (1177 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b6839c457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b6839c1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b6839c4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5a0081bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5a008725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5a0081ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5a00803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b68395a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b68395a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b68393ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b6835ee176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b6835ede93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5a00804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5a008050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5a008050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b6835edd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c (1178 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align # | ... # `---data was truncated (10240/94379) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ad6902957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ad69026515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ad69029cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd9c2733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd9c278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd9c2733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd9c271b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ad68fbf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ad68fbf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ad68fa3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ad68c53176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ad68c52e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd9c271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd9c271d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd9c271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ad68c52d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c (1179 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv32i8.nxv32i8.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGenCXX/ctor-globalopt.cpp (1180 of 27911) ******************** TEST 'Clang :: CodeGenCXX/ctor-globalopt.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp -O2 | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp --check-prefix=O1 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp -O2 # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | %struct.B = type <{ ptr, i32, [4 x i8], %struct.A.base, [4 x i8] }> # | %struct.A.base = type <{ ptr, i32 }> # | # | @b = local_unnamed_addr global %struct.B <{ ptr getelementptr inbounds inrange(-24, 8) (i8, ptr @_ZTV1B, i64 24), i32 0, [4 x i8] zeroinitializer, %struct.A.base <{ ptr getelementptr inbounds inrange(-24, 8) (i8, ptr @_ZTV1B, i64 56), i32 0 }>, [4 x i8] zeroinitializer }>, align 8 # | @_ZTV1B = external constant { [4 x ptr], [4 x ptr] }, align 8 # | @llvm.global_ctors = appending global [0 x { i32, ptr, ptr }] zeroinitializer # | # | !llvm.ident = !{!0} # | !llvm.errno.tbaa = !{!1} # | # | !0 = !{!"clang version 24.0.0"} # | !1 = !{!2, !3, i64 0} # | !2 = !{!"__libc_errno", !3, i64 0} # | !3 = !{!"int", !4, i64 0} # | !4 = !{!"omnipotent char", !5, i64 0} # | !5 = !{!"Simple C++ TBAA"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o - # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o - # | #0 0x0000560018aac57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560018aa9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560018aaccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6331d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6331d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6331d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6331d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560018a4224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560018a42096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560018a26f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005600186d6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005600186d5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6331d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6331d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6331d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005600186d5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp --check-prefix=O1 # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp --check-prefix=O1 # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c (1181 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = allo # | ... # `---data was truncated (10240/98179) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557e9290a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557e92907515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557e9290acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa711249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa7112a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa711249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa711231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557e928a024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557e928a0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557e92884f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557e92534176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557e92533e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa711232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa7112330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa7112330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557e92533d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c (1182 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_i8mf8x6 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561df08bb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561df08b8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561df08bbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1d34e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1d34ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1d34e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1d34e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561df085124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561df0851096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561df0835f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561df04e5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561df04e4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1d34e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1d34e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1d34e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561df04e4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c (1183 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8m4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca # | ... # `---data was truncated (10240/98343) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e6a47d457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e6a47d1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e6a47d4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fea26933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fea2698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fea26933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fea2691b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e6a476a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e6a476a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e6a474ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e6a43fe176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e6a43fde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fea2691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fea2691d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fea2691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e6a43fdd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/neon/f16-getset.c (1184 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon/f16-getset.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c --check-prefixes=ALL,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vdup_n_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca <4 x half>, align 8 # | %__s0 = alloca half, align 2 # | %.compoundliteral = alloca <4 x half>, align 8 # | %tmp = alloca <4 x half>, align 8 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %vecinit = insertelement <4 x half> poison, half %1, i32 0 # | %2 = load half, ptr %__s0, align 2 # | %vecinit1 = insertelement <4 x half> %vecinit, half %2, i32 1 # | %3 = load half, ptr %__s0, align 2 # | %vecinit2 = insertelement <4 x half> %vecinit1, half %3, i32 2 # | %4 = load half, ptr %__s0, align 2 # | %vecinit3 = insertelement <4 x half> %vecinit2, half %4, i32 3 # | store <4 x half> %vecinit3, ptr %.compoundliteral, align 8 # | %5 = load <4 x half>, ptr %.compoundliteral, align 8 # | store <4 x half> %5, ptr %__ret, align 8 # | %6 = load <4 x half>, ptr %__ret, align 8 # | store <4 x half> %6, ptr %tmp, align 8 # | %7 = load <4 x half>, ptr %tmp, align 8 # | ret <4 x half> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vdupq_n_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca <8 x half>, align 16 # | %__s0 = alloca half, align 2 # | %.compoundliteral = alloca <8 x half>, align 16 # | %tmp = alloca <8 x half>, align 16 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %vecinit = insertelement <8 x half> poison, half %1, i32 0 # | %2 = load half, ptr %__s0, align 2 # | %vecinit1 = insertelement <8 x half> %vecinit, half %2, i32 1 # | %3 = load half, ptr %__s0, align 2 # | %vecinit2 = insertelement <8 x half> %vecinit1, half %3, i32 2 # | %4 = load half, ptr %__s0, align 2 # | %vecinit3 = insertelement <8 x half> %vecinit2, half %4, i32 3 # | %5 = load half, ptr %__s0, align 2 # | %vecinit4 = insertelement <8 x half> %vecinit3, half %5, i32 4 # | %6 = load half, ptr %__s0, align 2 # | %vecinit5 = insertelement <8 x half> %vecinit4, half %6, i32 5 # | %7 = load half, ptr %__s0, align 2 # | %vecinit6 = insertelement <8 x half> %vecinit5, half %7, i32 6 # | %8 = load half, ptr %__s0, align 2 # | %vecinit7 = insertelement <8 x half> %vecinit6, half %8, i32 7 # | store <8 x half> %vecinit7, ptr %.compoundliteral, align 16 # | %9 = load <8 x half>, ptr %.compoundliteral, align 16 # | store <8 x half> %9, ptr %__ret, align 16 # | %10 = load <8 x half>, ptr %__ret, align 16 # | store <8 x half> %10, ptr %tmp, align 16 # | %11 = load <8 x half>, ptr %tmp, align 16 # | ret <8 x half> %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vdup_lane_f16(<4 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x half>, align 8 # | %__ret_39 = alloca <4 x half>, align 8 # | %__s0_39 = alloca <4 x half>, align 8 # | %__ret = alloca <4 x half>, align 8 # | %__s0 = alloca <4 x half>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x half>, align 8 # | %tmp1 = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__s0_39, align 8 # | %1 = load <4 x half>, ptr %__s0_39, align 8 # | store <4 x half> %1, ptr %__s0, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = bitcast <8 x i8> %2 to <4 x half> # | %lane = shufflevector <4 x half> %3, <4 x half> %3, <4 x i32> # | store <4 x half> %lane, ptr %ref.tmp, align 8 # | %4 = load <4 x half>, ptr %ref.tmp, align 8 # | store <4 x half> %4, ptr %__ret, align 8 # | %5 = load <4 x half>, ptr %__ret, align 8 # | store <4 x half> %5, ptr %tmp, align 8 # | %6 = load <4 x half>, ptr %tmp, align 8 # | store <4 x half> %6, ptr %__ret_39, align 8 # | %7 = load <4 x half>, ptr %__ret_39, align 8 # | store <4 x half> %7, ptr %tmp1, align 8 # | %8 = load <4 x half>, ptr %tmp1, align 8 # | ret <4 x half> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vdupq_lane_f16(<4 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x half>, align 8 # | %__ret_20 = alloca <8 x half>, align 16 # | %__s0_20 = alloca <4 x half>, align 8 # | %__ret = alloca <8 x half>, align 16 # | %__s0 = alloca <4 x half>, align 8 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x half>, align 16 # | %tmp1 = alloca <8 x half>, align 16 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__s0_20, align 8 # | %1 = load <4 x half>, ptr %__s0_20, align 8 # | store <4 x half> %1, ptr %__s0, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = bitcast <8 x i8> %2 to <4 x half> # | %lane = shufflevector <4 x half> %3, <4 x half> %3, <8 x i32> # | store <8 x half> %lane, ptr %ref.tmp, align 16 # | %4 = load <8 x half>, ptr %ref.tmp, align 16 # | store <8 x half> %4, ptr %__ret, align 16 # | %5 = load <8 x half>, ptr %__ret, align 16 # | store <8 x half> %5, ptr %tmp, align 16 # | %6 = load <8 x half>, ptr %tmp, align 16 # | store <8 x half> %6, ptr %__ret_20, align 16 # | %7 = load <8 x half>, ptr %__ret_20, align 16 # | store <8 x half> %7, ptr %tmp1, align 16 # | %8 = load <8 x half>, ptr %tmp1, align 16 # | ret <8 x half> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vdup_laneq_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 16 # | %__ret_432 = alloca <4 x half>, align 8 # | %__s0_432 = alloca <8 x half>, align 16 # | %__ret = alloca <4 x half>, align 8 # | %__s0 = alloca <8 x half>, align 16 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x half>, align 8 # | %tmp1 = alloca <4 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__s0_432, align 16 # | %1 = load <8 x half>, ptr %__s0_432, align 16 # | store <8 x half> %1, ptr %__s0, align 16 # | %2 = load <16 x i8>, ptr %__s0, align 16 # | %3 = bitcast <16 x i8> %2 to <8 x half> # | %lane = shufflevector <8 x half> %3, <8 x half> %3, <4 x i32> # | store <4 x half> %lane, ptr %ref.tmp, align 8 # | %4 = load <4 x half>, ptr %ref.tmp, align 8 # | store <4 x half> %4, ptr %__ret, align 8 # | %5 = load <4 x half>, ptr %__ret, align 8 # | store <4 x half> %5, ptr %tmp, align 8 # | %6 = load <4 x half>, ptr %tmp, align 8 # | store <4 x half> %6, ptr %__ret_432, align 8 # | %7 = load <4 x half>, ptr %__ret_432, align 8 # | store <4 x half> %7, ptr %tmp1, align 8 # | %8 = load <4 x half>, ptr %tmp1, align 8 # | ret <4 x half> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vdupq_laneq_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 16 # | %__ret_408 = alloca <8 x half>, align 16 # | %__s0_408 = alloca <8 x half>, align 16 # | %__ret = alloca <8 x half>, align 16 # | %__s0 = alloca <8 x half>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x half>, align 16 # | %tmp1 = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__s0_408, align 16 # | %1 = load <8 x half>, ptr %__s0_408, align 16 # | store <8 x half> %1, ptr %__s0, align 16 # | %2 = load <16 x i8>, ptr %__s0, align 16 # | %3 = bitcast <16 x i8> %2 to <8 x half> # | %lane = shufflevector <8 x half> %3, <8 x half> %3, <8 x i32> # | store <8 x half> %lane, ptr %ref.tmp, align 16 # | %4 = load <8 x half>, ptr %ref.tmp, align 16 # | store <8 x half> %4, ptr %__ret, align 16 # | %5 = load <8 x half>, ptr %__ret, align 16 # | store <8 x half> %5, ptr %tmp, align 16 # | %6 = load <8 x half>, ptr %tmp, align 16 # | store <8 x half> %6, ptr %__ret_408, align 16 # | %7 = load <8 x half>, ptr %__ret_408, align 16 # | store <8 x half> %7, ptr %tmp1, align 16 # | %8 = load <8 x half>, ptr %tmp1, align 16 # | ret <8 x half> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vduph_lane_f16(<4 x half> noundef %vec) #0 { # | entry: # | %vec.addr = alloca <4 x half>, align 8 # | %__ret = alloca half, align 2 # | %__s0 = alloca <4 x half>, align 8 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store <4 x half> %vec, ptr %vec.addr, align 8 # | %0 = load <4 x half>, ptr %vec.addr, align 8 # | store <4 x half> %0, ptr %__s0, align 8 # | %1 = load <4 x half>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x half> %1, i32 3 # | store half %vget_lane, ptr %ref.tmp, align 2 # | %2 = load half, ptr %ref.tmp, align 2 # | store half %2, ptr %__ret, align 2 # | %3 = load half, ptr %__ret, align 2 # | store half %3, ptr %tmp, align 2 # | %4 = load half, ptr %tmp, align 2 # | ret half %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vduph_laneq_f16(<8 x half> noundef %vec) #0 { # | entry: # | %vec.addr = alloca <8 x half>, align 16 # | %__ret = alloca half, align 2 # | %__s0 = alloca <8 x half>, align 16 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store <8 x half> %vec, ptr %vec.addr, align 16 # | %0 = load <8 x half>, ptr %vec.addr, align 16 # | store <8 x half> %0, ptr %__s0, align 16 # | %1 = load <8 x half>, ptr %__s0, align 16 # | %vgetq_lane = extractelement <8 x half> %1, i32 7 # | store half %vgetq_lane, ptr %ref.tmp, align 2 # | %2 = load half, ptr %ref.tmp, align 2 # | store half %2, ptr %__ret, align 2 # | %3 = load half, ptr %__ret, align 2 # | store half %3, ptr %tmp, align 2 # | %4 = load half, ptr %tmp, align 2 # | ret half %4 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-s # | ... # `---data was truncated (10240/10414) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000561dcd76a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561dcd767515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561dcd76acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc32aa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc32aaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc32aa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc32aa31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561dcd70024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561dcd700096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561dcd6e4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561dcd394176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561dcd393e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc32aa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc32aa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc32aa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561dcd393d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c --check-prefixes=ALL,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c --check-prefixes=ALL,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c (1185 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562d7aace57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562d7aacb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562d7aacecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa78bc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa78bca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa78bc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa78bc31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562d7aa6424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562d7aa64096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562d7aa48f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562d7a6f8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562d7a6f7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa78bc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa78bc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa78bc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562d7a6f7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c (1186 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_f32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_f32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_i32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_i32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_u32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_u32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_f32mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_f32m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounw # | ... # `---data was truncated (10240/15952) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005596883b457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005596883b1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005596883b4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd6f4f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd6f4f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd6f4f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd6f4f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055968834a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055968834a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055968832ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559687fde176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559687fdde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd6f4f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd6f4f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd6f4f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559687fddd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c (1187 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0. # | ... # `---data was truncated (10240/87884) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056488d33557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056488d332515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056488d335cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f496f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f496f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f496f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f496f831507 abort ./stdlib/abort.c:85:3 # | #7 0x000056488d2cb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056488d2cb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056488d2aff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056488cf5f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056488cf5ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f496f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f496f8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f496f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056488cf5ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c (1188 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf8_tu( %maskedoff, %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv1i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf4_tu( %maskedoff, %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv2i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf2_tu( %maskedoff, %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv4i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8m1_tu( %maskedoff, %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(, , , < # | ... # `---data was truncated (10240/117389) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fceb41b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fceb418515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fceb41bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe83e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe83e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe83e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe83e71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fceb3b124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fceb3b1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fceb395f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fceb045176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fceb044e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe83e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe83e71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe83e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fceb044d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/bf16-getset-intrinsics.c (1189 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/bf16-getset-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vcreate_bf16(i64 noundef %a) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %__ret = alloca <4 x bfloat>, align 8 # | %__promote = alloca i64, align 8 # | %tmp = alloca <4 x bfloat>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | store i64 %0, ptr %__promote, align 8 # | %1 = load <4 x bfloat>, ptr %__promote, align 8 # | store <4 x bfloat> %1, ptr %__ret, align 8 # | %2 = load <4 x bfloat>, ptr %__ret, align 8 # | store <4 x bfloat> %2, ptr %tmp, align 8 # | %3 = load <4 x bfloat>, ptr %tmp, align 8 # | ret <4 x bfloat> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcombine_bf16(<4 x bfloat> noundef %low, <4 x bfloat> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <4 x bfloat>, align 8 # | %__p1.addr.i = alloca <4 x bfloat>, align 8 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %low.addr = alloca <4 x bfloat>, align 8 # | %high.addr = alloca <4 x bfloat>, align 8 # | store <4 x bfloat> %low, ptr %low.addr, align 8 # | store <4 x bfloat> %high, ptr %high.addr, align 8 # | %0 = load <4 x bfloat>, ptr %low.addr, align 8 # | %1 = load <4 x bfloat>, ptr %high.addr, align 8 # | store <4 x bfloat> %0, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x bfloat>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <4 x bfloat> %2, <4 x bfloat> %3, <8 x i32> # | store <8 x bfloat> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vset_lane_bf16(bfloat noundef %a, <4 x bfloat> noundef %v) #0 { # | entry: # | %a.addr = alloca bfloat, align 2 # | %v.addr = alloca <4 x bfloat>, align 8 # | %__ret = alloca <4 x bfloat>, align 8 # | %__s0 = alloca bfloat, align 2 # | %__s1 = alloca <4 x bfloat>, align 8 # | %ref.tmp = alloca <4 x bfloat>, align 8 # | %tmp = alloca <4 x bfloat>, align 8 # | store bfloat %a, ptr %a.addr, align 2 # | store <4 x bfloat> %v, ptr %v.addr, align 8 # | %0 = load bfloat, ptr %a.addr, align 2 # | store bfloat %0, ptr %__s0, align 2 # | %1 = load <4 x bfloat>, ptr %v.addr, align 8 # | store <4 x bfloat> %1, ptr %__s1, align 8 # | %2 = load bfloat, ptr %__s0, align 2 # | %3 = load <4 x bfloat>, ptr %__s1, align 8 # | %vset_lane = insertelement <4 x bfloat> %3, bfloat %2, i32 1 # | store <4 x bfloat> %vset_lane, ptr %ref.tmp, align 8 # | %4 = load <4 x bfloat>, ptr %ref.tmp, align 8 # | store <4 x bfloat> %4, ptr %__ret, align 8 # | %5 = load <4 x bfloat>, ptr %__ret, align 8 # | store <4 x bfloat> %5, ptr %tmp, align 8 # | %6 = load <4 x bfloat>, ptr %tmp, align 8 # | ret <4 x bfloat> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vsetq_lane_bf16(bfloat noundef %a, <8 x bfloat> noundef %v) #0 { # | entry: # | %a.addr = alloca bfloat, align 2 # | %v.addr = alloca <8 x bfloat>, align 16 # | %__ret = alloca <8 x bfloat>, align 16 # | %__s0 = alloca bfloat, align 2 # | %__s1 = alloca <8 x bfloat>, align 16 # | %ref.tmp = alloca <8 x bfloat>, align 16 # | %tmp = alloca <8 x bfloat>, align 16 # | store bfloat %a, ptr %a.addr, align 2 # | store <8 x bfloat> %v, ptr %v.addr, align 16 # | %0 = load bfloat, ptr %a.addr, align 2 # | store bfloat %0, ptr %__s0, align 2 # | %1 = load <8 x bfloat>, ptr %v.addr, align 16 # | store <8 x bfloat> %1, ptr %__s1, align 16 # | %2 = load bfloat, ptr %__s0, align 2 # | %3 = load <8 x bfloat>, ptr %__s1, align 16 # | %vset_lane = insertelement <8 x bfloat> %3, bfloat %2, i32 7 # | store <8 x bfloat> %vset_lane, ptr %ref.tmp, align 16 # | %4 = load <8 x bfloat>, ptr %ref.tmp, align 16 # | store <8 x bfloat> %4, ptr %__ret, align 16 # | %5 = load <8 x bfloat>, ptr %__ret, align 16 # | store <8 x bfloat> %5, ptr %tmp, align 16 # | %6 = load <8 x bfloat>, ptr %tmp, align 16 # | ret <8 x bfloat> %6 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x00005591003ec57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005591003e9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005591003eccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faaaf505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faaaf55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faaaf505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faaaf4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055910038224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559100382096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559100366f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559100016176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559100015e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007faaaf4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faaaf4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faaaf4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559100015d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c (1190 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_f32mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_f32m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_f32m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_i32mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_i32m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_i32m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_u32mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_u32m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_u32m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_f32mf2x3_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void # | ... # `---data was truncated (10240/20489) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005620d131557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005620d1312515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005620d1315cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f67fbc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f67fbca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f67fbc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f67fbc31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005620d12ab24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005620d12ab096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005620d128ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005620d0f3f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005620d0f3ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f67fbc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f67fbc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f67fbc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005620d0f3ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c (1191 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32mf2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m1_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m4_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c (1192 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b8_s32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilelt.nxv16i1.i32(i32 %0, i32 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelt.nxv16i1.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b16_s32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilelt.nxv8i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelt.nxv8i1.i32(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b32_s32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilelt.nxv4i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelt.nxv4i1.i32(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b64_s32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilelt.nxv2i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelt.nxv2i1.i32(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b8_u32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilelo.nxv16i1.i32(i32 %0, i32 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelo.nxv16i1.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b16_u32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilelo.nxv8i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelo.nxv8i1.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b32_u32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilelo.nxv4i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelo.nxv4i1.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b64_u32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilelo.nxv2i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelo.nxv2i1.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b8_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.whilelt.nxv16i1.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelt.nxv16i1.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b16_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.whilelt.nxv8i1.i64(i64 %0, i64 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelt.nxv8i1.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b32_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.whilelt.nxv4i1.i64(i64 %0, i64 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelt.nxv4i1.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b64_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.whilelt.nxv2i1.i64(i64 %0, i64 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelt.nxv2i1.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b8_u64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | % # | ... # `---data was truncated (10240/13340) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055bc1611f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bc1611c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bc1611fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcfc3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcfc338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcfc3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcfc331b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bc160b524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bc160b5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bc16099f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bc15d49176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bc15d48e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcfc331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcfc331d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcfc331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bc15d48d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c (1193 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32mf2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m1_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m4_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c (1194 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005644ba37e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005644ba37b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005644ba37ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3212333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f321238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3212333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f321231b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005644ba31424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005644ba314096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005644ba2f8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005644b9fa8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005644b9fa7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f321231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f321231d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f321231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005644b9fa7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c (1195 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2, # | ... # `---data was truncated (10240/70979) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559465dbc57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559465db9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559465dbccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f512b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f512b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f512b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f512b91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559465d5224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559465d52096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559465d36f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005594659e6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005594659e5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f512b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f512b91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f512b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005594659e5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c (1196 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eaa62a357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055eaa62a0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055eaa62a3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f88dd133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f88dd18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f88dd133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f88dd11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eaa623924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055eaa6239096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055eaa621df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055eaa5ecd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055eaa5ecce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f88dd11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f88dd11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f88dd11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eaa5eccd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c (1197 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclastb_s8( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.clastb.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clastb.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclastb_s16( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.clastb.nxv8i16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clastb.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclastb_s32( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.clastb.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clastb.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclastb_s64( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.clastb.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clastb.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclastb_u8( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.clastb.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclastb_u16( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.clastb.nxv8i16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclastb_u32( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.clastb.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclastb_u64( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.clastb.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclastb_f16( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.clastb.nxv8f16(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c (1198 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %o # | ... # `---data was truncated (10240/223855) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fb1416957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fb14166515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fb14169cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc5c6e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc5c6ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc5c6e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc5c6e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fb140ff24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fb140ff096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fb140e3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fb13d93176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fb13d92e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc5c6e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc5c6e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc5c6e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fb13d92d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve/pfalse.c (1199 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve/pfalse.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpfalse_b() #0 { # | entry: # | ret zeroinitializer # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x000055b2245a957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b2245a6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b2245a9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f259e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f259e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f259e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f259e631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b22453f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b22453f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b224523f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b2241d3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b2241d2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f259e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f259e6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f259e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b2241d2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c (1200 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf8_b64( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf4_b32( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf2_b16( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8m1_b8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8m2_b4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv32i8.n # | ... # `---data was truncated (10240/95347) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d5c408257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d5c407f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d5c4082cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feddfb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feddfb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feddfb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feddfb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d5c401824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d5c4018096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d5c3ffcf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d5c3cac176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d5c3cabe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007feddfb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feddfb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feddfb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d5c3cabd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c (1201 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c (1202 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | ... # `---data was truncated (10240/20149) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005636fa08557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005636fa082515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005636fa085cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f70bb61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f70bb6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f70bb61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f70bb603507 abort ./stdlib/abort.c:85:3 # | #7 0x00005636fa01b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005636fa01b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005636f9ffff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005636f9caf176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005636f9caee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f70bb604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f70bb6050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f70bb6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005636f9caed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c (1203 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005644b305657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005644b3053515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005644b3056cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8939f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8939f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8939f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8939eed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005644b2fec24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005644b2fec096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005644b2fd0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005644b2c80176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005644b2c7fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8939eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8939eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8939eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005644b2c7fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c (1204 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf8( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf4( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf2( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m1( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m2( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m4( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m8( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv64i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16mf4( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv1i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16mf2( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv2i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16m1( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv4i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16m2( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c (1205 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005627a62b857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005627a62b5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005627a62b8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f39cd333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f39cd38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f39cd333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f39cd31b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005627a624e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005627a624e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005627a6232f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005627a5ee2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005627a5ee1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f39cd31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f39cd31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f39cd31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005627a5ee1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c (1206 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv16i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_lo # | ... # `---data was truncated (10240/99851) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ac6444857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ac64445515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ac64448cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0e3ff05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0e3ff5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0e3ff05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0e3feed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ac643de24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ac643de096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ac643c2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ac64072176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ac64071e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0e3feeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0e3feef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0e3feef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ac64071d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c (1207 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwi # | ... # `---data was truncated (10240/44369) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563516e0857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563516e05515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563516e08cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd5ae41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd5ae4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd5ae41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd5ae403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563516d9e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563516d9e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563516d82f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563516a32176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563516a31e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd5ae404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd5ae4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd5ae4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563516a31d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c (1208 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8mf8x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8mf4x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_u8mf8x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_u8mf4x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_u8mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_u8m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8mf8x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8mf4x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask. # | ... # `---data was truncated (10240/18972) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f4d4a4857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f4d4a45515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f4d4a48cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f24d1849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f24d18a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f24d1849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f24d1831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f4d49de24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f4d49de096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f4d49c2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f4d4672176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f4d4671e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f24d1832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f24d18330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f24d18330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f4d4671d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm64-lanes.c (1209 of 27911) ******************** TEST 'Clang :: CodeGen/arm64-lanes.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c" # | target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-apple-ios7" # | # | ; Function Attrs: noinline nounwind # | define i8 @test_vdupb_lane_s8(<8 x i8> noundef %src) #0 { # | entry: # | %src.addr = alloca <8 x i8>, align 8 # | %__ret = alloca i8, align 1 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | store <8 x i8> %src, ptr %src.addr, align 8 # | %0 = load <8 x i8>, ptr %src.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | %vget_lane = extractelement <8 x i8> %1, i32 2 # | store i8 %vget_lane, ptr %ref.tmp, align 1 # | %2 = load i8, ptr %ref.tmp, align 1 # | store i8 %2, ptr %__ret, align 1 # | %3 = load i8, ptr %__ret, align 1 # | store i8 %3, ptr %tmp, align 1 # | %4 = load i8, ptr %tmp, align 1 # | ret i8 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define i8 @test_vdupb_lane_u8(<8 x i8> noundef %src) #0 { # | entry: # | %src.addr = alloca <8 x i8>, align 8 # | %__ret = alloca i8, align 1 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | store <8 x i8> %src, ptr %src.addr, align 8 # | %0 = load <8 x i8>, ptr %src.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | %vget_lane = extractelement <8 x i8> %1, i32 2 # | store i8 %vget_lane, ptr %ref.tmp, align 1 # | %2 = load i8, ptr %ref.tmp, align 1 # | store i8 %2, ptr %__ret, align 1 # | %3 = load i8, ptr %__ret, align 1 # | store i8 %3, ptr %tmp, align 1 # | %4 = load i8, ptr %tmp, align 1 # | ret i8 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define i16 @test_vduph_lane_s16(<4 x i16> noundef %src) #0 { # | entry: # | %src.addr = alloca <4 x i16>, align 8 # | %__ret = alloca i16, align 2 # | %__s0 = alloca <4 x i16>, align 8 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store <4 x i16> %src, ptr %src.addr, align 8 # | %0 = load <4 x i16>, ptr %src.addr, align 8 # | store <4 x i16> %0, ptr %__s0, align 8 # | %1 = load <4 x i16>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x i16> %1, i32 2 # | store i16 %vget_lane, ptr %ref.tmp, align 2 # | %2 = load i16, ptr %ref.tmp, align 2 # | store i16 %2, ptr %__ret, align 2 # | %3 = load i16, ptr %__ret, align 2 # | store i16 %3, ptr %tmp, align 2 # | %4 = load i16, ptr %tmp, align 2 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define i16 @test_vduph_lane_u16(<4 x i16> noundef %src) #0 { # | entry: # | %src.addr = alloca <4 x i16>, align 8 # | %__ret = alloca i16, align 2 # | %__s0 = alloca <4 x i16>, align 8 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store <4 x i16> %src, ptr %src.addr, align 8 # | %0 = load <4 x i16>, ptr %src.addr, align 8 # | store <4 x i16> %0, ptr %__s0, align 8 # | %1 = load <4 x i16>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x i16> %1, i32 2 # | store i16 %vget_lane, ptr %ref.tmp, align 2 # | %2 = load i16, ptr %ref.tmp, align 2 # | store i16 %2, ptr %__ret, align 2 # | %3 = load i16, ptr %__ret, align 2 # | store i16 %3, ptr %tmp, align 2 # | %4 = load i16, ptr %tmp, align 2 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define i32 @test_vdups_lane_s32(<2 x i32> noundef %src) #0 { # | entry: # | %src.addr = alloca <2 x i32>, align 8 # | %__ret = alloca i32, align 4 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store <2 x i32> %src, ptr %src.addr, align 8 # | %0 = load <2 x i32>, ptr %src.addr, align 8 # | store <2 x i32> %0, ptr %__s0, align 8 # | %1 = load <2 x i32>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x i32> %1, i32 0 # | store i32 %vget_lane, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define i32 @test_vdups_lane_u32(<2 x i32> noundef %src) #0 { # | entry: # | %src.addr = alloca <2 x i32>, align 8 # | %__ret = alloca i32, align 4 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store <2 x i32> %src, ptr %src.addr, align 8 # | %0 = load <2 x i32>, ptr %src.addr, align 8 # | store <2 x i32> %0, ptr %__s0, align 8 # | %1 = load <2 x i32>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x i32> %1, i32 0 # | store i32 %vget_lane, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define float @test_vdups_lane_f32(<2 x float> noundef %src) #0 { # | entry: # | %src.addr = alloca <2 x float>, align 8 # | %__ret = alloca float, align 4 # | %__s0 = alloca <2 x float>, align 8 # | %ref.tmp = alloca float, align 4 # | %tmp = alloca float, align 4 # | store <2 x float> %src, ptr %src.addr, align 8 # | %0 = load <2 x float>, ptr %src.addr, align 8 # | store <2 x float> %0, ptr %__s0, align 8 # | %1 = load <2 x float>, ptr %__s0, align 8 # | %vdups_lane = extractelement <2 x float> %1, i32 0 # | store float %vdups_lane, ptr %ref.tmp, align 4 # | %2 = load float, ptr %ref.tmp, align 4 # | store float %2, ptr %__ret, align 4 # | %3 = load float, ptr %__ret, align 4 # | store float %3, ptr %tmp, align 4 # | %4 = load float, ptr %tmp, align 4 # | ret float %4 # | } # | # | ; Function Attrs: noinline nounwind # | define i64 @test_vdupd_lane_s64(<1 x i64> noundef %src) #0 { # | entry: # | %src.addr = alloca <1 x i64>, align 8 # | %__ret = alloca i64, align 8 # | %__s0 = alloca <1 x i64>, align 8 # | %ref.tmp = alloca i64, align 8 # | %tmp = alloca i64, align 8 # | store <1 x i64> %src, ptr %src.addr, align 8 # | %0 = load <1 x i64>, ptr %src.addr, align 8 # | store <1 x i64> %0, ptr %__s0, align 8 # | %1 = load <1 x i64>, ptr %__s0, align 8 # | %vget_lane = extractelement <1 x i64> %1, i32 0 # | store i64 %vget_lane, ptr %ref.tmp, align 8 # | %2 = load i64, ptr %ref.tmp, align 8 # | store i64 %2, ptr %__ret, align 8 # | %3 = load i64, ptr %__ret, align 8 # | store i64 %3, ptr %tmp, align 8 # | %4 = load i64, ptr %tmp, align 8 # | ret i64 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define i64 @test_vdupd_lane_u64(<1 x i64> noundef %src) #0 { # | entry: # | %src.addr = alloca <1 x i64>, align 8 # | %__ret = alloca i64, align 8 # | %__s0 = alloca <1 x i64>, align 8 # | %ref.tmp = alloca i64, align 8 # | %tmp = alloca i64, align 8 # | store <1 x i64> %src, ptr %src.addr, align 8 # | %0 = load <1 x i64>, ptr %src.addr, align 8 # | store <1 x i64> %0, ptr %__s0, align 8 # | %1 = load <1 x i64>, ptr %__s0, align 8 # | %vget_lane = extractelement <1 x i64> %1, i32 0 # | store i64 %vget_lane, ptr %ref.tmp, align 8 # | %2 = load i64, ptr %ref.tmp, align 8 # | store i64 %2, ptr %__ret, align 8 # | %3 = load i64, ptr %__ret, align 8 # | store i64 %3, ptr %tmp, align 8 # | %4 = load i64, ptr %tmp, align 8 # | ret i64 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define double @test_vdupd_lane_f64(<1 x double> noundef %src) #0 { # | entry: # | %src.addr = alloca <1 x double>, align 8 # | %__ret = alloca double, align 8 # | %__s0 = alloca <1 x double>, align 8 # | %ref.tmp = alloca double, align 8 # | %tmp = alloca double, align 8 # | store <1 x double> %src, ptr %src.addr, align 8 # | %0 = load <1 x double>, ptr %src.addr, align 8 # | store <1 x double> %0, ptr %__s0, align 8 # | %1 = load <1 x double>, ptr %__s0, align 8 # | %vdupd_lane = extractelement <1 x double> %1, i32 0 # | store double %vdupd_lane, ptr %ref.tmp, align 8 # | %2 = load double, ptr %ref.tmp, align 8 # | store double %2, ptr %__ret, align 8 # | %3 = load double, ptr %__ret, align 8 # | store double %3, ptr %tmp, align 8 # | %4 = load double, ptr %tmp, align 8 # | ret double %4 # | } # | # | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f57696957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f576966515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f576969cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f41d5c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f41d5ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f41d5c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f41d5c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f5768ff24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f5768ff096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f5768e3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f576593176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f576592e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f41d5c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f41d5c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f41d5c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f576592d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c (1210 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4e # | ... # `---data was truncated (10240/228857) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c0608db57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c0608d8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c0608dbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff724133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff72418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff724133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff72411b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c06087124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c060871096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c060855f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c060505176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c060504e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff72411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff72411d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff72411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c060504d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c (1211 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | s # | ... # `---data was truncated (10240/223359) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b20771957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b207716515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b207719cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efd5f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efd5f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efd5f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efd5f231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b2076af24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b2076af096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b207693f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b207343176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b207342e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efd5f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efd5f2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efd5f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b207342d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c (1212 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f3cca8057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f3cca7d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f3cca80cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8cfd249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8cfd2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8cfd249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8cfd231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f3cca1624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f3cca16096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f3cc9faf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f3cc6aa176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f3cc6a9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8cfd232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8cfd2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8cfd2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f3cc6a9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c (1213 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_s_s_w4_i8m8_i8m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.s.s.i64.nxv64i8.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.s.s.i64.nxv64i8.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055afb4b1457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055afb4b11515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055afb4b14cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe355449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe3554a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe355449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe355431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055afb4aaa24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055afb4aaa096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055afb4a8ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055afb473e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055afb473de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe355432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe3554330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe3554330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055afb473dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c (1214 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf4( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf2( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m1( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv4bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv4bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m2( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv8bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv8bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m4( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv16bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv16bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m8( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv32bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv32bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf4_m( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslideup.mask.nxv1bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.mask.nxv1bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf2_m( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslideup.mask.nxv2bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.mask.nxv2bf16.i64(, , # | ... # `---data was truncated (10240/16521) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564fab8d057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564fab8cd515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564fab8d0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f826ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f826ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f826ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f826ef1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564fab86624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564fab866096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564fab84af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564fab4fa176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564fab4f9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f826ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f826ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f826ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564fab4f9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c (1215 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_u32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base # | ... # `---data was truncated (10240/60683) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fed547e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fed547b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fed547ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f679f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f679f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f679f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f679f51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fed541424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fed5414096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fed53f8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fed50a8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fed50a7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f679f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f679f51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f679f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fed50a7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c (1216 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16mf4x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16mf4x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_u16mf4x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_u16mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_u16m1x5_m(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-vls-arith-ops.c (1217 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-arith-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %add = add <32 x i8> %0, %1 # | store <32 x i8> %add, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv8i8.v32i8( poison, <32 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8i8.v32i8(, <32 x i8>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_i16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i16>, align 8 # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca <16 x i16>, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %b.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store <16 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load <16 x i16>, ptr %b.addr, align 8 # | %add = add <16 x i16> %0, %1 # | store <16 x i16> %add, ptr %retval, align 8 # | %2 = load <16 x i16>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv4i16.v16i16( poison, <16 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4i16.v16i16(, <16 x i16>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_i32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i32>, align 8 # | %a.addr = alloca <8 x i32>, align 8 # | %b.addr = alloca <8 x i32>, align 8 # | %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %a.coerce, i64 0) # | %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %b.coerce, i64 0) # | store <8 x i32> %a, ptr %a.addr, align 8 # | store <8 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i32>, ptr %b.addr, align 8 # | %add = add <8 x i32> %0, %1 # | store <8 x i32> %add, ptr %retval, align 8 # | %2 = load <8 x i32>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv2i32.v8i32( poison, <8 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2i32.v8i32(, <8 x i32>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_i64( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <4 x i64>, align 8 # | %a.addr = alloca <4 x i64>, align 8 # | %b.addr = alloca <4 x i64>, align 8 # | %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %a.coerce, i64 0) # | %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %b.coerce, i64 0) # | store <4 x i64> %a, ptr %a.addr, align 8 # | store <4 x i64> %b, ptr %b.addr, align 8 # | %0 = load <4 x i64>, ptr %a.addr, align 8 # | %1 = load <4 x i64>, ptr %b.addr, align 8 # | %add = add <4 x i64> %0, %1 # | store <4 x i64> %add, ptr %retval, align 8 # | %2 = load <4 x i64>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv1i64.v4i64( poison, <4 x i64> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv1i64.v4i64(, <4 x i64>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_u8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %add = add <32 x i8> %0, %1 # | store <32 x i8> %add, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv8i8.v32i8( poison, <32 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_u16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i16>, align 8 # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca <16 x i16>, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %b.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store <16 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load <16 x i16>, ptr %b.addr, align 8 # | %add = add <16 x i16> %0, %1 # | store <16 x i16> %add, ptr %retval, align 8 # | %2 = load <16 x i16>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv4i16.v16i16( poison, <16 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_u32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i32>, align 8 # | %a.addr = alloca <8 x i32>, align 8 # | %b.addr = alloca <8 x i32>, align 8 # | %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %a.coerce, i64 0) # | %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %b.coerce, i64 0) # | store <8 x i32> %a, ptr %a.addr, align 8 # | store <8 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i32>, ptr %b.addr, align 8 # | %add = add <8 x i32> %0, %1 # | store <8 x i32> %add, ptr %retval, align 8 # | %2 = load <8 x i32>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv2i32.v8i32( poison, <8 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_u64( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <4 x i64>, align 8 # | %a.addr = alloca <4 x i64>, align 8 # | %b.addr = alloca <4 x i64>, align 8 # | %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %a.coerce, i64 0) # | %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %b.coerce, i64 0) # | store <4 x i64> %a, ptr %a.addr, align 8 # | store <4 x i64> %b, ptr %b.addr, align 8 # | %0 = load <4 x i64>, ptr %a.addr, align 8 # | %1 = load <4 x i64>, ptr %b.addr, align 8 # | %add = add <4 x i64> %0, %1 # | store <4 x i64> %add, ptr %retval, align 8 # | %2 = load <4 x i64>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv1i64.v4i64( poison, <4 x i64> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_f32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x float>, align 8 # | %a.addr = alloca <8 x float>, align 8 # | %b.addr = alloca <8 x float>, align 8 # | %a = call <8 x float> @llvm.vector.extract.v8f32.nxv2f32( %a.coerce, i64 0) # | %b = call <8 x float> @llvm.vector.extract.v8f32.nxv2f32( %b.coerce, i64 0) # | store <8 x float> %a, ptr %a.addr, align 8 # | store <8 x float> %b, ptr %b.addr, align 8 # | %0 = load <8 x float>, ptr %a.addr, align 8 # | %1 = load <8 x float>, ptr %b.addr, align 8 # | %add = fadd <8 x float> %0, %1 # | store <8 x float> %add, ptr %retval, align 8 # | %2 = load <8 x float>, ptr %retval, # | ... # `---data was truncated (10240/145303) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x000055c021f9757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c021f94515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c021f97cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbfdd333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbfdd38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbfdd333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbfdd31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c021f2d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c021f2d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c021f11f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c021bc1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c021bc0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbfdd31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbfdd31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbfdd31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c021bc0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c (1218 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_xvv_se_u64m1( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.xvv.se.i64.nxv1i64.nxv1i64.i64.i64(i64 3, %0, %1, i64 %2, i64 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.xvv.se.i64.nxv1i64.nxv1i64.i64.i64(i64 immarg, , , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_xvv_se_u64m2( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.xvv.se.i64.nxv2i64.nxv2i64.i64.i64(i64 3, %0, %1, i64 %2, i64 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.xvv.se.i64.nxv2i64.nxv2i64.i64.i64(i64 immarg, , , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_xvv_se_u64m4( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.xvv.se.i64.nxv4i64.nxv4i64.i64.i64(i64 3, %0, %1, i64 %2, i64 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.xvv.se.i64.nxv4i64.nxv4i64.i64.i64(i64 immarg, , , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_xvv_se_u64m8( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.xvv.se.i64.nxv8i64.nxv8i64.i64.i64(i64 3, %0, %1, i64 %2, i64 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.xvv.se.i64.nxv8i64.nxv8i64.i64.i64(i64 immarg, , , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xvv_se_u64m1( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vc.v.xvv.se.nxv1i64.i64.nxv1i64.nxv1i64.i64.i64(i64 3, %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.xvv.se.nxv1i64.i64.nxv1i64.nxv1i64.i64.i64(i64 immarg, , , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xvv_se_u64m2( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vc.v.xvv.se.nxv2i64.i64.nxv2i64.nxv2i64.i64.i64(i64 3, %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.xvv.se.nxv2i64.i64.nxv2i64.nxv2i64.i64.i64(i64 immarg, , , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xvv_se_u64m4( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vc.v.xvv.se.nxv4i64.i64.nxv4i64.nxv4i64.i64.i64(i64 3, %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.xvv.se.nxv4i64.i64.nxv4i64.nxv4i64.i64.i64(i64 immarg, , , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xvv_se_u64m8( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vc.v.xvv.se.nxv8i64.i64.nxv8i64.nxv8i64.i64.i64(i64 3, %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.xvv.se.nxv8i64.i64.nxv8i64.nxv8i64.i64.i64(i64 immarg, , , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xvv_u64m1( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vc.v.xvv.nxv1i64.i64.nxv1i64.nxv1i64.i64.i64(i64 3, %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nounwind memory(none) # | declare @llvm.riscv.sf.vc.v.xvv.nxv1i64.i64.nxv1i64.nxv1i64.i64.i64(i64 immarg, , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm-bf16-dotprod-intrinsics.c (1219 of 27911) ******************** TEST 'Clang :: CodeGen/arm-bf16-dotprod-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-arm-none-eabi -target-feature +neon -target-feature +bf16 -mfloat-abi soft -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-arm-none-eabi -target-feature +neon -target-feature +bf16 -mfloat-abi soft -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8-arm-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vbfdot_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x bfloat>, align 8 # | %__p2.addr.i = alloca <4 x bfloat>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x float>, align 8 # | %a.addr = alloca <4 x bfloat>, align 8 # | %b.addr = alloca <4 x bfloat>, align 8 # | store <2 x float> %r, ptr %r.addr, align 8 # | store <4 x bfloat> %a, ptr %a.addr, align 8 # | store <4 x bfloat> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %r.addr, align 8 # | %1 = load <4 x bfloat>, ptr %a.addr, align 8 # | %2 = load <4 x bfloat>, ptr %b.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__p1.addr.i, align 8 # | store <4 x bfloat> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vbfdot.i = bitcast <8 x i8> %3 to <2 x float> # | %vbfdot1.i = bitcast <8 x i8> %4 to <4 x bfloat> # | %vbfdot2.i = bitcast <8 x i8> %5 to <4 x bfloat> # | %vbfdot3.i = call <2 x float> @llvm.arm.neon.bfdot.v2f32.v4bf16(<2 x float> %vbfdot.i, <4 x bfloat> %vbfdot1.i, <4 x bfloat> %vbfdot2.i) # | store <2 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %6, ptr %__ret.i, align 8 # | %7 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vbfdotq_f32(<4 x float> noundef %r, <8 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__p1.addr.i = alloca <8 x bfloat>, align 8 # | %__p2.addr.i = alloca <8 x bfloat>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %r.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <8 x bfloat>, align 8 # | %b.addr = alloca <8 x bfloat>, align 8 # | store <4 x float> %r, ptr %r.addr, align 8 # | store <8 x bfloat> %a, ptr %a.addr, align 8 # | store <8 x bfloat> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %r.addr, align 8 # | %1 = load <8 x bfloat>, ptr %a.addr, align 8 # | %2 = load <8 x bfloat>, ptr %b.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | store <8 x bfloat> %1, ptr %__p1.addr.i, align 8 # | store <8 x bfloat> %2, ptr %__p2.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 8 # | %vbfdot.i = bitcast <16 x i8> %3 to <4 x float> # | %vbfdot1.i = bitcast <16 x i8> %4 to <8 x bfloat> # | %vbfdot2.i = bitcast <16 x i8> %5 to <8 x bfloat> # | %vbfdot3.i = call <4 x float> @llvm.arm.neon.bfdot.v4f32.v8bf16(<4 x float> %vbfdot.i, <8 x bfloat> %vbfdot1.i, <8 x bfloat> %vbfdot2.i) # | store <4 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8 # | %6 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %6, ptr %__ret.i, align 8 # | %7 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vbfdot_lane_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x bfloat>, align 8 # | %__p2.addr.i = alloca <4 x bfloat>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x float>, align 8 # | %a.addr = alloca <4 x bfloat>, align 8 # | %b.addr = alloca <4 x bfloat>, align 8 # | %__ret_810 = alloca <2 x float>, align 8 # | %__s0_810 = alloca <2 x float>, align 8 # | %__s1_810 = alloca <4 x bfloat>, align 8 # | %__s2_810 = alloca <4 x bfloat>, align 8 # | %ref.tmp = alloca <2 x float>, align 8 # | %__ret = alloca <2 x float>, align 8 # | %__s0 = alloca <2 x float>, align 8 # | %ref.tmp1 = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x float>, align 8 # | %tmp2 = alloca <2 x float>, align 8 # | store <2 x float> %r, ptr %r.addr, align 8 # | store <4 x bfloat> %a, ptr %a.addr, align 8 # | store <4 x bfloat> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %r.addr, align 8 # | store <2 x float> %0, ptr %__s0_810, align 8 # | %1 = load <4 x bfloat>, ptr %a.addr, align 8 # | store <4 x bfloat> %1, ptr %__s1_810, align 8 # | %2 = load <4 x bfloat>, ptr %b.addr, align 8 # | store <4 x bfloat> %2, ptr %__s2_810, align 8 # | %3 = load <2 x float>, ptr %__s0_810, align 8 # | %4 = load <4 x bfloat>, ptr %__s1_810, align 8 # | %5 = load <2 x float>, ptr %__s2_810, align 8 # | store <2 x float> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x float> # | %lane = shufflevector <2 x float> %7, <2 x float> %7, <2 x i32> zeroinitializer # | store <2 x float> %lane, ptr %ref.tmp1, align 8 # | %8 = load <2 x float>, ptr %ref.tmp1, align 8 # | store <2 x float> %8, ptr %__ret, align 8 # | %9 = load <2 x float>, ptr %__ret, align 8 # | store <2 x float> %9, ptr %tmp, align 8 # | %10 = load <2 x float>, ptr %tmp, align 8 # | store <2 x float> %10, ptr %ref.tmp, align 8 # | %11 = load <4 x bfloat>, ptr %ref.tmp, align 8 # | store <2 x float> %3, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %4, ptr %__p1.addr.i, align 8 # | store <4 x bfloat> %11, ptr %__p2.addr.i, align 8 # | %12 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %13 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %14 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vbfdot.i = bitcast <8 x i8> %12 to <2 x float> # | %vbfdot1.i = bitcast <8 x i8> %13 to <4 x bfloat> # | %vbfdot2.i = bitcast <8 x i8> %14 to <4 x bfloat> # | %vbfdot3.i = call <2 x float> @llvm.arm.neon.bfdot.v2f32.v4bf16(<2 x float> %vbfdot.i, <4 x bfloat> %vbfdot1.i, <4 x bfloat> %vbfdot2.i) # | store <2 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8 # | %15 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %15, ptr %__ret.i, align 8 # | %16 = load <2 x float>, ptr %__ret.i, align 8 # | store <2 x float> %16, ptr %__ret_810, align 8 # | %17 = load <2 x float>, ptr %__ret_810, align 8 # | store <2 x float> %17, ptr %tmp2, align 8 # | %18 = load <2 x float>, ptr %tmp2, align 8 # | ret <2 x float> %18 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vbfdotq_laneq_f32(<4 x float> noundef %r, <8 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__p1.addr.i = alloca <8 x bfloat>, align 8 # | %__p2.addr.i = alloca <8 x bfloat>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %r.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <8 x bfloat>, align 8 # | %b.addr = alloca <8 x bfloat>, align 8 # | %__ret_812 = alloca <4 x float>, align 8 # | %__s0_812 = alloca <4 x float>, align 8 # | %__s1_812 = alloca <8 x bfloat>, align 8 # | %__s2_812 = alloca <8 x bfloat>, align 8 # | %ref.tmp = alloca <4 x float>, align 8 # | %__ret = alloca <4 x float>, align 8 # | %__s0 = alloca <4 x float>, align 8 # | %ref.tmp1 = alloca <16 x i8>, align 8 # | %tmp = alloca <4 x float>, align 8 # | %tmp2 = alloca <4 x float>, align 8 # | store <4 x float> %r, ptr %r.addr, align 8 # | store <8 x bfloat> %a, ptr %a.addr, align 8 # | store <8 x bfloat> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %r.addr, align 8 # | store <4 x float> %0, ptr %__s0_812, align 8 # | %1 = load <8 x bfloat>, ptr %a.addr, align 8 # | store <8 x bfloat> %1, ptr %__s1_812, align 8 # | %2 = load <8 x bfloat>, ptr %b.addr, align 8 # | store <8 x bfloat> %2, ptr %__s2_812, align 8 # | %3 = load <4 x float>, ptr %__s0_812, align 8 # | %4 = load <8 x bfloat>, ptr %__s1_812, align 8 # | %5 = load <4 x float>, ptr %__s2_812, align 8 # | store <4 x float> %5, ptr %__s0, align 8 # | %6 = load <16 x i8>, ptr %__s0, align 8 # | %7 = bitcast <16 x i8> %6 to <4 x float> # | %lane = shufflevector <4 x float> %7, <4 x float> %7, <4 x i32> # | store <4 x float> %lane, ptr %ref.tmp1, align 8 # | %8 = load <4 x float>, ptr %ref.tmp1, align 8 # | store <4 x float> %8, ptr %__ret, align 8 # | %9 = load <4 x float>, ptr %__ret, align 8 # | store <4 x float> %9, ptr %tmp, align 8 # | %10 = load <4 x float>, ptr %tmp, align 8 # | store <4 x float> %10, ptr %ref.tmp, align 8 # | %11 = load <8 x bfloat>, ptr %ref.tmp, align 8 # | store <4 x float> %3, ptr %__p0.addr.i, align 8 # | store <8 x bfloat> %4, ptr %__p1.addr.i, align 8 # | store <8 x bfloat> %11, ptr %__p2.addr.i, align 8 # | %12 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %13 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %14 = load <16 x i8>, ptr %__p2.addr.i, align 8 # | %vbfdot.i = bitcast <16 x i8> %12 to <4 x float> # | %vbfdot1.i = bitcast <16 x i8> %13 to <8 x bfloat> # | %vbfdot2.i = bitcast <16 x i8> %14 to <8 x bfloat> # | %vbfdot3.i = call <4 x float> @llvm.arm.neon.bfdot.v4f32.v8bf16(<4 x float> %vbfdot.i, <8 x bfloat> %vbfdot1.i, <8 x bfloat> %vbfdot2.i) # | store <4 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8 # | %15 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %15, ptr %__ret.i, align 8 # | %16 = load <4 x float>, ptr %__ret.i, align 8 # | store <4 x float> %16, ptr %__ret_812, align 8 # | %17 = load <4 x float>, ptr %__ret_812, align 8 # | store <4 x float> %17, ptr %tmp2, align 8 # | %18 = load <4 x float>, ptr %tmp2, align 8 # | ret <4 x float> %18 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vbfdot_laneq_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x bfloat>, align 8 # | %__p2.addr.i = alloca <4 x bfloat>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x float>, align 8 # | %a.addr = alloca <4 x bfloat>, align 8 # | %b.addr = alloca <8 x bfloat>, align 8 # | %__ret_814 = alloca <2 x float>, al # | ... # `---data was truncated (10240/54174) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000562883dca57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562883dc7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562883dcacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe44af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe44af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe44af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe44af1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562883d6024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562883d60096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562883d44f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005628839f4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005628839f3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe44af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe44af1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe44af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005628839f3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-vector-arith-ops.c (1220 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-arith-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_i8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = add %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_i16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = add %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_i32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = add %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_i64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = add %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_u8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = add %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_u16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = add %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_u32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = add %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_u64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = add %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_f16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = fadd %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_f32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = fadd %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_f64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = fadd %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_inplace_i8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %b.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %add = add %1, %0 # | store %add, ptr %a.addr, align 16 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_inplace_i16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %b.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %add = add %1, %0 # | store %add, ptr %a.addr, align 16 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_inplace_i32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %b.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %add = add %1, %0 # | store %add, ptr %a.addr, align 16 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_inplace_i64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %b.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %add = add %1, %0 # | store %add, ptr %a.addr, align 16 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_inplace_u8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %b.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %add = add %1, %0 # | store %add, ptr %a.addr, align 16 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_inplace_u16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %b.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %add = add %1, %0 # | store %add, ptr %a.addr, align 16 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_inplace_u32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca < # | ... # `---data was truncated (10240/107144) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x0000557292d9257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557292d8f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557292d92cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1718d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1718d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1718d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1718d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557292d2824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557292d28096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557292d0cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005572929bc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005572929bbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1718d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1718d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1718d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005572929bbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c (1221 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4k.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv1i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4k.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv2i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4k.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv4i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4k.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv8i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4k.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv16i32.i64.i64(, , i64 immarg, i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005649d963e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005649d963b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005649d963ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7219a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7219aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7219a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7219a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005649d95d424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005649d95d4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005649d95b8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005649d9268176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005649d9267e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7219a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7219a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7219a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005649d9267d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c (1222 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055581e0a557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055581e0a2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055581e0a5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa3a181bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa3a18725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa3a181ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa3a1803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055581e03b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055581e03b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055581e01ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055581dccf176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055581dccee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa3a1804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa3a18050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa3a18050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055581dcced81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c (1223 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_f32mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_f32m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_i32mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_i32m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_u32mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_u32m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_f32mf2x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_f32m1x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_i32mf2x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_i32m1x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry # | ... # `---data was truncated (10240/14002) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562bef2a657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562bef2a3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562bef2a6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5e43a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5e43aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5e43a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5e43a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562bef23c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562bef23c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562bef220f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562beeed0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562beeecfe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5e43a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5e43a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5e43a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562beeecfd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c (1224 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32mf2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m1x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m4x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32mf2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32m1x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32m2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32m4x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t. # | ... # `---data was truncated (10240/15486) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eceb82957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055eceb826515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055eceb829cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fad9e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fad9e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fad9e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fad9e831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eceb7bf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055eceb7bf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055eceb7a3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055eceb453176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055eceb452e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fad9e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fad9e8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fad9e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eceb452d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c (1225 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8mf8x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_u8mf8x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_u8mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range( # | ... # `---data was truncated (10240/31876) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056526285c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000565262859515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056526285ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f41f8649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f41f86a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f41f8649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f41f8631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005652627f224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005652627f2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005652627d6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000565262486176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000565262485e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f41f8632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f41f86330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f41f86330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565262485d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c (1226 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_i8mf8x5 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005608c7e4e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005608c7e4b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005608c7e4ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9917b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9917b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9917b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9917b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005608c7de424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005608c7de4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005608c7dc8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005608c7a78176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005608c7a77e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9917b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9917b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9917b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005608c7a77d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c (1227 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_bf16mf4_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_bf16mf4_f32mf2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_bf16mf4_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_bf16_f32mf2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_bf16mf2_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_bf16mf2_f32m1( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_bf16mf2_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_bf16_f32m1( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_bf16m1_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv4f32.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_bf16m1_f32m2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | # | ... # `---data was truncated (10240/86100) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559583e8057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559583e7d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559583e80cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffad3e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffad3e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffad3e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffad3e03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559583e1624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559583e16096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559583dfaf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559583aaa176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559583aa9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ffad3e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffad3e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffad3e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559583aa9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c (1228 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32mf2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m1( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m4( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m8( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32mf2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m1_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | ... # `---data was truncated (10240/13625) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055737fb4357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055737fb40515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055737fb43cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f02c6533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f02c658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f02c6533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f02c651b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055737fad924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055737fad9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055737fabdf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055737f76d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055737f76ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f02c651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f02c651d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f02c651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055737f76cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c (1229 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlm_v_b1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vlm.nxv64i1.p0.i64(ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vlm.nxv64i1.p0.i64(ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlm_v_b2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vlm.nxv32i1.p0.i64(ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vlm.nxv32i1.p0.i64(ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlm_v_b4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vlm.nxv16i1.p0.i64(ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vlm.nxv16i1.p0.i64(ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlm_v_b8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vlm.nxv8i1.p0.i64(ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vlm.nxv8i1.p0.i64(ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlm_v_b16(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vlm.nxv4i1.p0.i64(ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vlm.nxv4i1.p0.i64(ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlm_v_b32(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vlm.nxv2i1.p0.i64(ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vlm.nxv2i1.p0.i64(ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlm_v_b64(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vlm.nxv1i1.p0.i64(ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vlm.nxv1i1.p0.i64(ptr captures(none), i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a23bc0e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a23bc0b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a23bc0ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe86a105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe86a15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe86a105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe86a0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a23bba424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a23bba4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a23bb88f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a23b838176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a23b837e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe86a0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe86a0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe86a0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a23b837d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c (1230 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_i8mf4x6(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564eab9cf57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564eab9cc515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564eab9cfcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f825fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f825fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f825fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f825fd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564eab96524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564eab965096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564eab949f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564eab5f9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564eab5f8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f825fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f825fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f825fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564eab5f8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c (1231 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m4_tu( %maskedoff, ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c (1232 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf4x5_tumu( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2. # | ... # `---data was truncated (10240/18498) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ba130a957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ba130a6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ba130a9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4aee505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4aee55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4aee505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4aee4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ba1303f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ba1303f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ba13023f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ba12cd3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ba12cd2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4aee4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4aee4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4aee4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ba12cd2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c (1233 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16mf4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f64m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declar # | ... # `---data was truncated (10240/44434) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005633b878157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005633b877e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005633b8781cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6af081bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6af08725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6af081ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6af0803507 abort ./stdlib/abort.c:85:3 # | #7 0x00005633b871724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005633b8717096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005633b86fbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005633b83ab176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005633b83aae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6af0804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6af08050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6af08050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005633b83aad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c (1234 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32mf2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m1( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m4( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i6 # | ... # `---data was truncated (10240/90867) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056475bf6a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056475bf67515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056475bf6acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7b7e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7b7e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7b7e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7b7e31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056475bf0024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056475bf00096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056475bee4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056475bb94176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056475bb93e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7b7e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7b7e31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7b7e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056475bb93d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vrmulhq.c (1235 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vrmulhq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrmulhq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vrmulh.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vrmulh.v16i8(<16 x i8>, <16 x i8>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrmulhq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vrmulh.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vrmulh.v8i16(<8 x i16>, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrmulhq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vrmulh.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vrmulh.v4i32(<4 x i32>, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrmulhq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.rmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.rmulh.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrmulhq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.rmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.rmulh.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrmulhq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.rmulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.rmulh.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrmulhq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.rmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrmulhq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.rmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrmulhq_m_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.rmulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005567aa93b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005567aa938515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005567aa93bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4505a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4505aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4505a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4505a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005567aa8d124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005567aa8d1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005567aa8b5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005567aa565176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005567aa564e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4505a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4505a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4505a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005567aa564d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c (1236 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564296bc257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564296bbf515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564296bc2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff10301bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff1030725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff10301ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff103003507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564296b5824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564296b58096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564296b3cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005642967ec176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005642967ebe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff103004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff1030050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff1030050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005642967ebd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c (1237 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = loa # | ... # `---data was truncated (10240/135111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056235800157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562357ffe515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562358001cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8077f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8077f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8077f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8077f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562357f9724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562357f97096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562357f7bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562357c2b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562357c2ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8077f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8077f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8077f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562357c2ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c (1238 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d94d28e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d94d28b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d94d28ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f032c905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f032c95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f032c905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f032c8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d94d22424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d94d224096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d94d208f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d94ceb8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d94ceb7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f032c8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f032c8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f032c8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d94ceb7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c (1239 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv8f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv16f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv32f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, al # | ... # `---data was truncated (10240/128416) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e35e7f857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e35e7f5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e35e7f8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f056f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f056f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f056f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f056f631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e35e78e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e35e78e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e35e772f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e35e422176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e35e421e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f056f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f056f6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f056f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e35e421d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c (1240 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_f64m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_i64m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_u64m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056014f33a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056014f337515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056014f33acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9985333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f998538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9985333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f998531b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056014f2d024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056014f2d0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056014f2b4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056014ef64176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056014ef63e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f998531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f998531d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f998531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056014ef63d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c (1241 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f67973a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f679737515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f67973acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f26a0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f26a08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f26a0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f26a0831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f6796d024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f6796d0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f6796b4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f679364176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f679363e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f26a0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f26a08330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f26a08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f679363d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c (1242 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv1i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv2i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv4i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv8i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/225205) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556de660957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556de6606515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556de6609cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f265ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f265ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f265ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f265ed1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556de659f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556de659f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556de6583f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556de6233176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556de6232e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f265ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f265ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f265ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556de6232d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c (1243 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv64i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16mf4( %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i16, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv1i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16mf2( %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i16, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv2i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16m1( %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i16, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv4i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16m2( %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i16, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub # | ... # `---data was truncated (10240/84979) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055732e1ba57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055732e1b7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055732e1bacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9ea6a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9ea6a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9ea6a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9ea6a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055732e15024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055732e150096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055732e134f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055732dde4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055732dde3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9ea6a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9ea6a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9ea6a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055732dde3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c (1244 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005600d7a3157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005600d7a2e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005600d7a31cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe40ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe40caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe40ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe40ca31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005600d79c724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005600d79c7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005600d79abf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005600d765b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005600d765ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe40ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe40ca330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe40ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005600d765ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c (1245 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 # | ... # `---data was truncated (10240/135345) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056176f41457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056176f411515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056176f414cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f79d6e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f79d6ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f79d6e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f79d6e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056176f3aa24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056176f3aa096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056176f38ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056176f03e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056176f03de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f79d6e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f79d6e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f79d6e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056176f03dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c (1246 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range # | ... # `---data was truncated (10240/302397) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e8722ad57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e8722aa515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e8722adcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f203721bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f20372725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f203721ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2037203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e87224324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e872243096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e872227f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e871ed7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e871ed6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2037204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f20372050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f20372050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e871ed6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c (1247 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf4_f16mf2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv2f16.nxv1f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2f16.nxv1f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf4_f16m1( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv4f16.nxv1f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4f16.nxv1f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf4_f16m2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8f16.nxv1f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f16.nxv1f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf4_f16m4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16f16.nxv1f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv1f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf4_f16m8( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32f16.nxv1f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv1f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf2_f16m1( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv4f16.nxv2f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4f16.nxv2f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf2_f16m2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8f16.nxv2f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f16.nxv2f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf2_f16m4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16f16.nxv2f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv2f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf2_f16m8( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32f16.nxv2f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv2f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16m1_f16m2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8f16.nxv4f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16m1_f16m4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16f16.nxv4f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16m1_f16m8( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32f16.nxv4f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16m2_f16m4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16f16.nxv8f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv8f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16m2_f16m8( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32f16.nxv8f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv8f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline n # | ... # `---data was truncated (10240/83088) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fced5af57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fced5ac515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fced5afcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8df1849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8df18a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8df1849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8df1831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fced54524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fced545096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fced529f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fced1d9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fced1d8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8df1832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8df18330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8df18330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fced1d8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c (1248 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector. # | ... # `---data was truncated (10240/78690) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fc0f30457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fc0f301515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fc0f304cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0f55933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0f5598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0f55933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0f5591b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fc0f29a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fc0f29a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fc0f27ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fc0ef2e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fc0ef2de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0f5591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0f5591d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0f5591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fc0ef2dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c (1249 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_u32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_u32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c (1250 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr # | ... # `---data was truncated (10240/97905) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557d5440157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557d543fe515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557d54401cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fefbd133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fefbd18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fefbd133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fefbd11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557d5439724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557d54397096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557d5437bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557d5402b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557d5402ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fefbd11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fefbd11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fefbd11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557d5402ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c (1251 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m4( %vd, %v # | ... # `---data was truncated (10240/148843) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055765ad3a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055765ad37515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055765ad3acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f86a5e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f86a5ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f86a5e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f86a5e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055765acd024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055765acd0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055765acb4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055765a964176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055765a963e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f86a5e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f86a5e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f86a5e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055765a963d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c (1252 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load , ptr %vs1.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m1_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load , ptr %vs1.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloc # | ... # `---data was truncated (10240/27533) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a438c2d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a438c2a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a438c2dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa7d4a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa7d4aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa7d4a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa7d4a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a438bc324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a438bc3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a438ba7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a438857176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a438856e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa7d4a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa7d4a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa7d4a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a438856d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c (1253 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f64m1x3(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c (1254 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c (1255 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf8( %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf4( %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf2( %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8m1( %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8m2( %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align # | ... # `---data was truncated (10240/97240) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e5a4bb857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e5a4bb5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e5a4bb8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8bb7905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8bb795c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8bb7905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8bb78ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e5a4b4e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e5a4b4e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e5a4b32f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e5a47e2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e5a47e1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8bb78eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8bb78ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8bb78ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e5a47e1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c (1256 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005617ed62257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005617ed61f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005617ed622cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4900a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4900aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4900a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4900a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005617ed5b824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005617ed5b8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005617ed59cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005617ed24c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005617ed24be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4900a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4900a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4900a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005617ed24bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c (1257 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv # | ... # `---data was truncated (10240/165238) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565332cb957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000565332cb6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000565332cb9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fab5c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fab5c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fab5c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fab5c91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565332c4f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000565332c4f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000565332c33f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005653328e3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005653328e2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fab5c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fab5c91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fab5c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005653328e2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c (1258 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load # | ... # `---data was truncated (10240/410391) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c409b4957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c409b46515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c409b49cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8bced05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8bced5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8bced05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8bceced507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c409adf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c409adf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c409ac3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c409773176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c409772e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8bceceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8bcecef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8bcecef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c409772d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c (1259 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16m2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align # | ... # `---data was truncated (10240/151245) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005626861e057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005626861dd515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005626861e0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1ba8d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1ba8d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1ba8d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1ba8d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056268617624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562686176096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056268615af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562685e0a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562685e09e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1ba8d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1ba8d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1ba8d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562685e09d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c (1260 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, a # | ... # `---data was truncated (10240/81515) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056247f5d457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056247f5d1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056247f5d4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8d86e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8d86ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8d86e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8d86e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056247f56a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056247f56a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056247f54ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056247f1fe176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056247f1fde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8d86e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8d86e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8d86e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056247f1fdd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/v8.6a-neon-intrinsics.c (1261 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/v8.6a-neon-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.6a -target-feature +i8mm -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.6a -target-feature +i8mm -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vmmlaq_s32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %r.addr = alloca <4 x i32>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | store <4 x i32> %r, ptr %r.addr, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | %0 = load <4 x i32>, ptr %r.addr, align 16 # | %1 = load <16 x i8>, ptr %a.addr, align 16 # | %2 = load <16 x i8>, ptr %b.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vmmla.i = bitcast <16 x i8> %3 to <4 x i32> # | %vmmla1.i = call <4 x i32> @llvm.aarch64.neon.smmla.v4i32.v16i8(<4 x i32> %vmmla.i, <16 x i8> %4, <16 x i8> %5) # | store <4 x i32> %vmmla1.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %6, ptr %__ret.i, align 16 # | %7 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vmmlaq_u32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %r.addr = alloca <4 x i32>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | store <4 x i32> %r, ptr %r.addr, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | %0 = load <4 x i32>, ptr %r.addr, align 16 # | %1 = load <16 x i8>, ptr %a.addr, align 16 # | %2 = load <16 x i8>, ptr %b.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vmmla.i = bitcast <16 x i8> %3 to <4 x i32> # | %vmmla1.i = call <4 x i32> @llvm.aarch64.neon.ummla.v4i32.v16i8(<4 x i32> %vmmla.i, <16 x i8> %4, <16 x i8> %5) # | store <4 x i32> %vmmla1.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %6, ptr %__ret.i, align 16 # | %7 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vusmmlaq_s32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %r.addr = alloca <4 x i32>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | store <4 x i32> %r, ptr %r.addr, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | %0 = load <4 x i32>, ptr %r.addr, align 16 # | %1 = load <16 x i8>, ptr %a.addr, align 16 # | %2 = load <16 x i8>, ptr %b.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vusmmla.i = bitcast <16 x i8> %3 to <4 x i32> # | %vusmmla1.i = call <4 x i32> @llvm.aarch64.neon.usmmla.v4i32.v16i8(<4 x i32> %vusmmla.i, <16 x i8> %4, <16 x i8> %5) # | store <4 x i32> %vusmmla1.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %6, ptr %__ret.i, align 16 # | %7 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vusdot_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x i32>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | store <2 x i32> %r, ptr %r.addr, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %r.addr, align 8 # | %1 = load <8 x i8>, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %b.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | store <8 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vusdot.i = bitcast <8 x i8> %3 to <2 x i32> # | %vusdot1.i = call <2 x i32> @llvm.aarch64.neon.usdot.v2i32.v8i8(<2 x i32> %vusdot.i, <8 x i8> %4, <8 x i8> %5) # | store <2 x i32> %vusdot1.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vusdot_lane_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x i32>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret_845 = alloca <2 x i32>, align 8 # | %__s0_845 = alloca <2 x i32>, align 8 # | %__s1_845 = alloca <8 x i8>, align 8 # | %__s2_845 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <2 x i32>, align 8 # | %__ret = alloca <2 x i32>, align 8 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp1 = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x i32>, align 8 # | %tmp2 = alloca <2 x i32>, align 8 # | store <2 x i32> %r, ptr %r.addr, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %r.addr, align 8 # | store <2 x i32> %0, ptr %__s0_845, align 8 # | %1 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %1, ptr %__s1_845, align 8 # | %2 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %2, ptr %__s2_845, align 8 # | %3 = load <2 x i32>, ptr %__s0_845, align 8 # | %4 = load <8 x i8>, ptr %__s1_845, align 8 # | %5 = load <2 x i32>, ptr %__s2_845, align 8 # | store <2 x i32> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x i32> # | %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> zeroinitializer # | store <2 x i32> %lane, ptr %ref.tmp1, align 8 # | %8 = load <2 x i32>, ptr %ref.tmp1, align 8 # | store <2 x i32> %8, ptr %__ret, align 8 # | %9 = load <2 x i32>, ptr %__ret, align 8 # | store <2 x i32> %9, ptr %tmp, align 8 # | %10 = load <2 x i32>, ptr %tmp, align 8 # | store <2 x i32> %10, ptr %ref.tmp, align 8 # | %11 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <2 x i32> %3, ptr %__p0.addr.i, align 8 # | store <8 x i8> %4, ptr %__p1.addr.i, align 8 # | store <8 x i8> %11, ptr %__p2.addr.i, align 8 # | %12 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %13 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %14 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vusdot.i = bitcast <8 x i8> %12 to <2 x i32> # | %vusdot1.i = call <2 x i32> @llvm.aarch64.neon.usdot.v2i32.v8i8(<2 x i32> %vusdot.i, <8 x i8> %13, <8 x i8> %14) # | store <2 x i32> %vusdot1.i, ptr %ref.tmp.i, align 8 # | %15 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %15, ptr %__ret.i, align 8 # | %16 = load <2 x i32>, ptr %__ret.i, align 8 # | store <2 x i32> %16, ptr %__ret_845, align 8 # | %17 = load <2 x i32>, ptr %__ret_845, align 8 # | store <2 x i32> %17, ptr %tmp2, align 8 # | %18 = load <2 x i32>, ptr %tmp2, align 8 # | ret <2 x i32> %18 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vsudot_lane_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x i32>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret_841 = alloca <2 x i32>, align 8 # | %__s0_841 = alloca <2 x i32>, align 8 # | %__s1_841 = alloca <8 x i8>, align 8 # | %__s2_841 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <2 x i32>, align 8 # | %__ret = alloca <2 x i32>, align 8 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp1 = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x i32>, align 8 # | %tmp2 = alloca <2 x i32>, align 8 # | store <2 x i32> %r, ptr %r.addr, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %r.addr, align 8 # | store <2 x i32> %0, ptr %__s0_841, align 8 # | %1 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %1, ptr %__s1_841, align 8 # | %2 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %2, ptr %__s2_841, align 8 # | %3 = load <2 x i32>, ptr %__s0_841, align 8 # | %4 = load <2 x i32>, ptr %__s2_841, align 8 # | store <2 x i32> %4, ptr %__s0, align 8 # | # | ... # `---data was truncated (10240/31781) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x00005627bb45f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005627bb45c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005627bb45fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb86ba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb86baa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb86ba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb86ba31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005627bb3f524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005627bb3f5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005627bb3d9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005627bb089176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005627bb088e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb86ba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb86ba330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb86ba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005627bb088d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c (1262 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559ceb9aa57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559ceb9a7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559ceb9aacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f75f0049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f75f00a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f75f0049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f75f0031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559ceb94024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559ceb940096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559ceb924f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559ceb5d4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559ceb5d3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f75f0032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f75f00330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f75f00330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559ceb5d3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c (1263 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16m2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = # | ... # `---data was truncated (10240/154509) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005630b030657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005630b0303515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005630b0306cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2392b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2392b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2392b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2392b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005630b029c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005630b029c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005630b0280f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005630aff30176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005630aff2fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2392b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2392b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2392b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005630aff2fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c (1264 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = # | ... # `---data was truncated (10240/125488) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559e04b4757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559e04b44515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559e04b47cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcb8c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcb8c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcb8c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcb8c231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559e04add24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559e04add096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559e04ac1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559e04771176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559e04770e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcb8c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcb8c2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcb8c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559e04770d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c (1265 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.mask.nxv4bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.mask.nxv8bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c (1266 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16m8(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i8.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i8.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, # | ... # `---data was truncated (10240/15512) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eecb82057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055eecb81d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055eecb820cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0043f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0043f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0043f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0043eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eecb7b624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055eecb7b6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055eecb79af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055eecb44a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055eecb449e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0043eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0043eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0043eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eecb449d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c (1267 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf8( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv1i8.nxv1i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf8( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv1i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf4( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv2i8.nxv2i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf4( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv2i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf2( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv4i8.nxv4i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf2( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv4i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8m1( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv8i8.nxv8i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8m1( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv8i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv8i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8m2( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/98141) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558e2eacf57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558e2eacc515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558e2eacfcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f140a105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f140a15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f140a105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f140a0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558e2ea6524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558e2ea65096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558e2ea49f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558e2e6f9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558e2e6f8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f140a0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f140a0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f140a0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558e2e6f8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c (1268 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv16bf16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv16bf16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv32bf16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv32bf16 # | ... # `---data was truncated (10240/33616) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005584dbe1157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005584dbe0e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005584dbe11cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc47b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc47b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc47b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc47b31b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005584dbda724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005584dbda7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005584dbd8bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005584dba3b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005584dba3ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc47b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc47b31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc47b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005584dba3ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c (1269 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563b96a6457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563b96a61515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563b96a64cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2e0fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2e0fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2e0fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2e0fb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563b969fa24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563b969fa096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563b969def49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563b9668e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563b9668de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2e0fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2e0fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2e0fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563b9668dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c (1270 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf4x7_tumu( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 0, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", # | ... # `---data was truncated (10240/16800) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fc2ed9f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fc2ed9c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fc2ed9fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f006af05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f006af5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f006af05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f006aeed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fc2ed3524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fc2ed35096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fc2ed19f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fc2e9c9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fc2e9c8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f006aeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f006aeef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f006aeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fc2e9c8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c (1271 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f64m1x3(ptr noundef %base, %binde # | ... # `---data was truncated (10240/99754) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005597cfa8c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005597cfa89515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005597cfa8ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc872e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc872ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc872e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc872e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005597cfa2224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005597cfa22096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005597cfa06f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005597cf6b6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005597cf6b5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc872e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc872e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc872e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005597cf6b5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/memcmp-inline-builtin-to-asm.c (1272 of 27911) ******************** TEST 'Clang :: CodeGen/memcmp-inline-builtin-to-asm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=verify | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64" # | # | @con_unify_unimap_p1 = global ptr null, align 8 # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local i32 @con_unify_unimap_q1() #0 { # | entry: # | %p.addr.i = alloca ptr, align 8 # | %q.addr.i = alloca ptr, align 8 # | %size.addr.i = alloca i64, align 8 # | %0 = load ptr, ptr @con_unify_unimap_p1, align 8 # | store ptr %0, ptr %p.addr.i, align 8 # | store ptr @con_unify_unimap_q1, ptr %q.addr.i, align 8 # | store i64 4, ptr %size.addr.i, align 8 # | %1 = load ptr, ptr %p.addr.i, align 8 # | %2 = load ptr, ptr %q.addr.i, align 8 # | %3 = load i64, ptr %size.addr.i, align 8 # | %call.i = call i32 @memcmp(ptr noundef %1, ptr noundef %2, i64 noundef %3) #2 # | ret i32 %call.i # | } # | # | ; Function Attrs: alwaysinline nobuiltin nounwind # | declare i32 @memcmp(ptr noundef, ptr noundef, i64 noundef) #1 # | # | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | attributes #1 = { alwaysinline nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | attributes #2 = { nounwind } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=verify # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=verify # | #0 0x00005587738bf57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005587738bc515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005587738bfcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcaf3c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcaf3ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcaf3c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcaf3c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055877385524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558773855096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558773839f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005587734e9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005587734e8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcaf3c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcaf3c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcaf3c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005587734e8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c (1273 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c (1274 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svset3_s8( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %x) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = load , ptr %x.addr, align 16 # | %5 = insertvalue { , , } %3, %4, 1 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svset3_s16( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %x) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = load , ptr %x.addr, align 16 # | %5 = insertvalue { , , } %3, %4, 2 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svset3_s32( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %x) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = load , ptr %x.addr, align 16 # | %5 = insertvalue { , , } %3, %4, 0 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svset3_s64( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %x) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = load , ptr %x.addr, align 16 # | %5 = insertvalue { , , } %3, %4, 1 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svset3_u8( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %x) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = load , ptr %x.addr, align 16 # | %5 = insertvalue { , , } %3, %4, 2 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svset3_u16( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %x) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = load , ptr %x.addr, align 16 # | %5 = insertvalue { , , } %3, %4, 0 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svset3_u32( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c (1275 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m4_tu( %maskedoff, %op1, %op2, i6 # | ... # `---data was truncated (10240/157165) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e1351fa57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e1351f7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e1351facbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc357533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc35758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc357533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc35751b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e13519024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e135190096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e135174f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e134e24176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e134e23e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc35751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc35751d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc35751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e134e23d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c (1276 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005621887e657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005621887e3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005621887e6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdfef933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdfef98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdfef933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdfef91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056218877c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056218877c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562188760f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562188410176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056218840fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fdfef91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdfef91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdfef91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056218840fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c (1277 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m4_tu( %maskedoff, %op1, %op2, i6 # | ... # `---data was truncated (10240/157165) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558a2fe5f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558a2fe5c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558a2fe5fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f90d161bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f90d16725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f90d161ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f90d1603507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558a2fdf524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558a2fdf5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558a2fdd9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558a2fa89176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558a2fa88e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f90d1604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f90d16050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f90d16050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558a2fa88d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c (1278 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf8_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr % # | ... # `---data was truncated (10240/414517) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b11df6b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b11df68515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b11df6bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f78a0249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f78a02a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f78a0249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f78a0231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b11df0124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b11df01096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b11dee5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b11db95176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b11db94e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f78a0232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f78a02330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f78a02330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b11db94d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c (1279 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056272b73c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056272b739515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056272b73ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f95c5933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f95c598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f95c5933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f95c591b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056272b6d224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056272b6d2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056272b6b6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056272b366176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056272b365e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f95c591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f95c591d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f95c591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056272b365d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c (1280 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f64m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 # | ... # `---data was truncated (10240/99178) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c6d01dc57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c6d01d9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c6d01dccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f83dc41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f83dc4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f83dc41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f83dc403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c6d017224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c6d0172096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c6d0156f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c6cfe06176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c6cfe05e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f83dc404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f83dc4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f83dc4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c6cfe05d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c (1281 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fb8b57a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fb8b577515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fb8b57acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1a6001bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1a600725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1a6001ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1a60003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fb8b51024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fb8b510096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fb8b4f4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fb8b1a4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fb8b1a3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1a60004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1a600050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1a600050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fb8b1a3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c (1282 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m1x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: n # | ... # `---data was truncated (10240/22107) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055651d60957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055651d606515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055651d609cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8ba9733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8ba978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8ba9733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8ba971b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055651d59f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055651d59f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055651d583f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055651d233176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055651d232e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8ba971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8ba971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8ba971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055651d232d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c (1283 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0. # | ... # `---data was truncated (10240/87884) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f775bfb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f775bf8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f775bfbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3e74b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3e74b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3e74b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3e74b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f775b9124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f775b91096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f775b75f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f775825176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f775824e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3e74b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3e74b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3e74b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f775824d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c (1284 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8mf8() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 5) # | ret i64 %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vsetvlimax.i64(i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8mf4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 6) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8mf2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8m1() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8m2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8m4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8m8() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 3) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16mf4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 6) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16mf2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16m1() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16m2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16m4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16m8() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 3) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e32mf2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e32m1() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e32m2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e32m4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e32m8() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 3) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e64m1() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e64m2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e64m4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e64m8() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 3) # | ret i64 %0 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565411a2e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000565411a2b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000565411a2ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8ed8649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8ed86a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8ed8649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8ed8631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005654119c424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005654119c4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005654119a8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000565411658176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000565411657e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8ed8632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8ed86330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8ed86330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565411657d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c (1285 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv16bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv32bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv32bf16.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005597f645a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005597f6457515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005597f645acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f60fba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f60fbaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f60fba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f60fba31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005597f63f024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005597f63f0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005597f63d4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005597f6084176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005597f6083e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f60fba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f60fba330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f60fba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005597f6083d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c (1286 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf4_tum( %mask, %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c (1287 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf4x3(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf2x3(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16m1x3(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16m2x3(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf4x3_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf2x3_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16m1x3_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c (1288 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | # | ... # `---data was truncated (10240/63571) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556b057e857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556b057e5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556b057e8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9152649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f91526a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9152649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9152631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556b0577e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556b0577e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556b05762f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556b05412176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556b05411e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9152632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f91526330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f91526330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556b05411d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/neon-fp16fml.c (1289 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon-fp16fml.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +v8.2a -target-feature +neon -target-feature +fp16fml -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +v8.2a -target-feature +neon -target-feature +fp16fml -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vfmlal_low_f16(<2 x float> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vfmlal_low.i = bitcast <8 x i8> %3 to <2 x float> # | %vfmlal_low1.i = bitcast <8 x i8> %4 to <4 x half> # | %vfmlal_low2.i = bitcast <8 x i8> %5 to <4 x half> # | %vfmlal_low3.i = call <2 x float> @llvm.aarch64.neon.fmlal.v2f32.v4f16(<2 x float> %vfmlal_low.i, <4 x half> %vfmlal_low1.i, <4 x half> %vfmlal_low2.i) # | store <2 x float> %vfmlal_low3.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %6, ptr %__ret.i, align 8 # | %7 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vfmlsl_low_f16(<2 x float> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vfmlsl_low.i = bitcast <8 x i8> %3 to <2 x float> # | %vfmlsl_low1.i = bitcast <8 x i8> %4 to <4 x half> # | %vfmlsl_low2.i = bitcast <8 x i8> %5 to <4 x half> # | %vfmlsl_low3.i = call <2 x float> @llvm.aarch64.neon.fmlsl.v2f32.v4f16(<2 x float> %vfmlsl_low.i, <4 x half> %vfmlsl_low1.i, <4 x half> %vfmlsl_low2.i) # | store <2 x float> %vfmlsl_low3.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %6, ptr %__ret.i, align 8 # | %7 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vfmlal_high_f16(<2 x float> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vfmlal_high.i = bitcast <8 x i8> %3 to <2 x float> # | %vfmlal_high1.i = bitcast <8 x i8> %4 to <4 x half> # | %vfmlal_high2.i = bitcast <8 x i8> %5 to <4 x half> # | %vfmlal_high3.i = call <2 x float> @llvm.aarch64.neon.fmlal2.v2f32.v4f16(<2 x float> %vfmlal_high.i, <4 x half> %vfmlal_high1.i, <4 x half> %vfmlal_high2.i) # | store <2 x float> %vfmlal_high3.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %6, ptr %__ret.i, align 8 # | %7 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vfmlsl_high_f16(<2 x float> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vfmlsl_high.i = bitcast <8 x i8> %3 to <2 x float> # | %vfmlsl_high1.i = bitcast <8 x i8> %4 to <4 x half> # | %vfmlsl_high2.i = bitcast <8 x i8> %5 to <4 x half> # | %vfmlsl_high3.i = call <2 x float> @llvm.aarch64.neon.fmlsl2.v2f32.v4f16(<2 x float> %vfmlsl_high.i, <4 x half> %vfmlsl_high1.i, <4 x half> %vfmlsl_high2.i) # | store <2 x float> %vfmlsl_high3.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %6, ptr %__ret.i, align 8 # | %7 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vfmlalq_low_f16(<4 x float> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <8 x half>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store <8 x half> %c, ptr %c.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | %2 = load <8 x half>, ptr %c.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vfmlal_low.i = bitcast <16 x i8> %3 to <4 x float> # | %vfmlal_low1.i = bitcast <16 x i8> %4 to <8 x half> # | %vfmlal_low2.i = bitcast <16 x i8> %5 to <8 x half> # | %vfmlal_low3.i = call <4 x float> @llvm.aarch64.neon.fmlal.v4f32.v8f16(<4 x float> %vfmlal_low.i, <8 x half> %vfmlal_low1.i, <8 x half> %vfmlal_low2.i) # | store <4 x float> %vfmlal_low3.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %6, ptr %__ret.i, align 16 # | %7 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vfmlslq_low_f16(<4 x float> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <8 x half>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store <8 x half> %c, ptr %c.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | %2 = load <8 x half>, ptr %c.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vfmlsl_low.i = bitcast <16 x i8> %3 to <4 x float> # | %vfmlsl_low1.i = bitcast <16 x i8> %4 to <8 x half> # | %vfmlsl_low2.i = bitcast <16 x i8> %5 to <8 x half> # | %vfmlsl_low3.i = call <4 x float> @llvm.aarch64.neon.fmlsl.v4f32.v8f16(<4 x float> %vfmlsl_low.i, <8 x half> %vfmlsl_low1.i, <8 x half> %vfmlsl_low2.i) # | store <4 x float> %vfmlsl_low3.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %6, ptr %__ret.i, align 16 # | %7 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vfmlalq_high_f16(<4 x float> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = allo # | ... # `---data was truncated (10240/162735) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x00005597df59357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005597df590515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005597df593cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc691705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc69175c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc691705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc6916ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005597df52924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005597df529096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005597df50df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005597df1bd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005597df1bce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc6916eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc6916ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc6916ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005597df1bcd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c (1290 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_i8mf8x5 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055829f53957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055829f536515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055829f539cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f49de449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f49de4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f49de449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f49de431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055829f4cf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055829f4cf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055829f4b3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055829f163176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055829f162e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f49de432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f49de4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f49de4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055829f162d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c (1291 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv # | ... # `---data was truncated (10240/75133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564db1fab57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564db1fa8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564db1fabcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5669333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f566938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5669333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f566931b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564db1f4124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564db1f41096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564db1f25f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564db1bd5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564db1bd4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f566931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f566931d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f566931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564db1bd4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c (1292 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_i8mf4x8(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055994bb2b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055994bb28515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055994bb2bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4e74733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4e7478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4e74733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4e7471b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055994bac124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055994bac1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055994baa5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055994b755176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055994b754e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4e7471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4e7471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4e7471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055994b754d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c (1293 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 3) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractva # | ... # `---data was truncated (10240/27866) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c292b8357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c292b80515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c292b83cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd4cad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd4cad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd4cad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd4cad1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c292b1924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c292b19096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c292afdf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c2927ad176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c2927ace93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd4cad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd4cad1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd4cad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c2927acd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c (1294 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m4_tu( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c (1295 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(, , , i64, i64 immarg) # | ... # `---data was truncated (10240/27055) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e53118857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e531185515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e531188cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1d8a049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1d8a0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1d8a049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1d8a031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e53111e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e53111e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e531102f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e530db2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e530db1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1d8a032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1d8a0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1d8a0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e530db1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c (1296 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_i8mf4x5(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055632521157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055632520e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556325211cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc28d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc28d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc28d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc28d51b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005563251a724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005563251a7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055632518bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556324e3b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556324e3ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc28d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc28d51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc28d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556324e3ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c (1297 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | # | ... # `---data was truncated (10240/222475) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ae7259957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ae72596515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ae72599cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbadca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbadcaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbadca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbadca31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ae7252f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ae7252f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ae72513f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ae721c3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ae721c2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbadca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbadca330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbadca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ae721c2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c (1298 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf2 # | ... # `---data was truncated (10240/54694) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056147ac9357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056147ac90515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056147ac93cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb182649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb1826a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb182649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb182631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056147ac2924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056147ac29096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056147ac0df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056147a8bd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056147a8bce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb182632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb1826330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb1826330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056147a8bcd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c (1299 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv1i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv2i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv4i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv8i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv16i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv16i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8 # | ... # `---data was truncated (10240/99577) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d260ef657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d260ef3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d260ef6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffbfef05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffbfef5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffbfef05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffbfeeed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d260e8c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d260e8c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d260e70f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d260b20176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d260b1fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ffbfeeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffbfeeef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffbfeeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d260b1fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c (1300 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564df1e6e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564df1e6b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564df1e6ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efdbd705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efdbd75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efdbd705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efdbd6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564df1e0424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564df1e04096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564df1de8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564df1a98176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564df1a97e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efdbd6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efdbd6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efdbd6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564df1a97d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c (1301 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m4_tu( %maskedoff, ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c (1302 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_i8mf8x5_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c (1303 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_i8mf8x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_i8mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_i8mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_i8m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_u8mf8x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_u8mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_u8mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_u8m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_i8mf8x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | # | ... # `---data was truncated (10240/21558) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dced92957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055dced926515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055dced929cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f85a0e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f85a0ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f85a0e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f85a0e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dced8bf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055dced8bf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055dced8a3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055dced553176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055dced552e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f85a0e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f85a0e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f85a0e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dced552d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c (1304 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op # | ... # `---data was truncated (10240/222917) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557f0389457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557f03891515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557f03894cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f322eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f322eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f322eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f322eb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557f0382a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557f0382a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557f0380ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557f034be176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557f034bde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f322eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f322eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f322eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557f034bdd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c (1305 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste8_i8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste8.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.sf.vste8.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste8_u8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste8.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055810d2e957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055810d2e6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055810d2e9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f898b849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f898b8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f898b849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f898b831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055810d27f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055810d27f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055810d263f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055810cf13176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055810cf12e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f898b832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f898b8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f898b8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055810cf12d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c (1306 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555cea9af57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555cea9ac515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555cea9afcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f89e3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f89e338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f89e3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f89e331b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555cea94524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555cea945096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555cea929f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555cea5d9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555cea5d8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f89e331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f89e331d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f89e331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555cea5d8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c (1307 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_i8mf8x8 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005565a031257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005565a030f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005565a0312cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9118849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f91188a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9118849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9118831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005565a02a824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005565a02a8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005565a028cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055659ff3c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055659ff3be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9118832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f91188330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f91188330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055659ff3bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c (1308 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b9ad5b957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b9ad5b6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b9ad5b9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3d0e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3d0e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3d0e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3d0e11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b9ad54f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b9ad54f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b9ad533f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b9ad1e3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b9ad1e2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3d0e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3d0e11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3d0e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b9ad1e2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c (1309 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | ... # `---data was truncated (10240/302389) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005562b3b8b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005562b3b88515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005562b3b8bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3c6c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3c6c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3c6c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3c6c631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005562b3b2124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005562b3b21096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005562b3b05f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005562b37b5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005562b37b4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3c6c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3c6c6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3c6c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005562b37b4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c (1310 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/87892) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561f848ae57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561f848ab515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561f848aecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efcd3c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efcd3ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efcd3c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efcd3c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561f8484424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561f84844096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561f84828f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561f844d8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561f844d7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efcd3c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efcd3c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efcd3c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561f844d7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c (1311 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte8_i8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte8.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vlte8.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte8_u8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte8.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ec7c0fa57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ec7c0f7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ec7c0facbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8f65a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8f65a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8f65a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8f65a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ec7c09024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ec7c090096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ec7c074f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ec7bd24176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ec7bd23e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8f65a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8f65a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8f65a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ec7bd23d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/admin.c (1312 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/admin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c --check-prefixes=CHECK,CHECK-LE # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcreateq_f16(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = insertelement <2 x i64> poison, i64 %0, i64 0 # | %2 = load i64, ptr %b.addr, align 8 # | %3 = insertelement <2 x i64> %1, i64 %2, i64 1 # | %4 = bitcast <2 x i64> %3 to <8 x half> # | ret <8 x half> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcreateq_f32(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = insertelement <2 x i64> poison, i64 %0, i64 0 # | %2 = load i64, ptr %b.addr, align 8 # | %3 = insertelement <2 x i64> %1, i64 %2, i64 1 # | %4 = bitcast <2 x i64> %3 to <4 x float> # | ret <4 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcreateq_s16(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = insertelement <2 x i64> poison, i64 %0, i64 0 # | %2 = load i64, ptr %b.addr, align 8 # | %3 = insertelement <2 x i64> %1, i64 %2, i64 1 # | %4 = bitcast <2 x i64> %3 to <8 x i16> # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcreateq_s32(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = insertelement <2 x i64> poison, i64 %0, i64 0 # | %2 = load i64, ptr %b.addr, align 8 # | %3 = insertelement <2 x i64> %1, i64 %2, i64 1 # | %4 = bitcast <2 x i64> %3 to <4 x i32> # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vcreateq_s64(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = insertelement <2 x i64> poison, i64 %0, i64 0 # | %2 = load i64, ptr %b.addr, align 8 # | %3 = insertelement <2 x i64> %1, i64 %2, i64 1 # | ret <2 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcreateq_s8(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = insertelement <2 x i64> poison, i64 %0, i64 0 # | %2 = load i64, ptr %b.addr, align 8 # | %3 = insertelement <2 x i64> %1, i64 %2, i64 1 # | %4 = bitcast <2 x i64> %3 to <16 x i8> # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcreateq_u16(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = insertelement <2 x i64> poison, i64 %0, i64 0 # | %2 = load i64, ptr %b.addr, align 8 # | %3 = insertelement <2 x i64> %1, i64 %2, i64 1 # | %4 = bitcast <2 x i64> %3 to <8 x i16> # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcreateq_u32(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = insertelement <2 x i64> poison, i64 %0, i64 0 # | %2 = load i64, ptr %b.addr, align 8 # | %3 = insertelement <2 x i64> %1, i64 %2, i64 1 # | %4 = bitcast <2 x i64> %3 to <4 x i32> # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vcreateq_u64(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = insertelement <2 x i64> poison, i64 %0, i64 0 # | %2 = load i64, ptr %b.addr, align 8 # | %3 = insertelement <2 x i64> %1, i64 %2, i64 1 # | ret <2 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcreateq_u8(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = insertelement <2 x i64> poison, i64 %0, i64 0 # | %2 = load i64, ptr %b.addr, align 8 # | %3 = insertelement <2 x i64> %1, i64 %2, i64 1 # | %4 = bitcast <2 x i64> %3 to <16 x i8> # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vuninitializedq_polymorphic_f16(ptr noundef %funcptr) #0 { # | entry: # | %funcptr.addr = alloca ptr, align 4 # | store ptr %funcptr, ptr %funcptr.addr, align 4 # | ret <8 x half> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vuninitializedq_polymorphic_f32(ptr noundef %funcptr) #0 { # | entry: # | %funcptr.addr = alloca ptr, align 4 # | store ptr %funcptr, ptr %funcptr.addr, align 4 # | ret <4 x float> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vuninitializedq_polymorphic_s8(ptr noundef %funcptr) #0 { # | entry: # | %funcptr.addr = alloca ptr, align 4 # | store ptr %funcptr, ptr %funcptr.addr, align 4 # | ret <16 x i8> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vuninitializedq_polymorphic_s16(ptr noundef %funcptr) #0 { # | entry: # | %funcptr.addr = alloca ptr, align 4 # | store ptr %funcptr, ptr %funcptr.addr, align 4 # | ret <8 x i16> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vuninitializedq_polymorphic_s32(ptr noundef %funcptr) #0 { # | entry: # | %funcptr.addr = alloca ptr, align 4 # | store ptr %funcptr, ptr %funcptr.addr, align 4 # | ret <4 x i32> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vuninitializedq_polymorphic_s64(ptr noundef %funcptr) #0 { # | entry: # | %funcptr.addr = alloca ptr, align 4 # | store ptr %funcptr, ptr %funcptr.addr, align 4 # | ret <2 x i64> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vuninitializedq_polymorphic_u8(ptr noundef %funcptr) #0 { # | entry: # | %funcptr.addr = alloca ptr, align 4 # | store ptr %funcptr, ptr %funcptr.addr, align 4 # | ret <16 x i8> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vuninitializedq_polymorphic_u16(ptr noundef %funcptr) #0 { # | entry: # | %funcptr.addr = alloca ptr, align 4 # | store ptr %funcptr, ptr %funcptr.addr, align 4 # | ret <8 x i16> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vuninitializedq_polymorphic_u32(ptr noundef %funcptr) #0 { # | entry: # | %funcptr.addr = alloca ptr, align 4 # | store ptr %funcptr, ptr %funcptr.addr, align 4 # | ret <4 x i32> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vuninitializedq_polymorphic_u64(ptr noundef %funcptr) #0 { # | entry: # | %funcptr.addr = alloca ptr, align 4 # | store ptr %funcptr, ptr %funcptr.addr, align 4 # | ret <2 x i64> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vuninitializedq_f16() #0 { # | entry: # | ret <8 x half> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vuninitializedq_f32() #0 { # | entry: # | ret <4 x float> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vuninitializedq_s16() #0 { # | entry: # | ret <8 x i16> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vuninitializedq_s32() #0 { # | entry: # | ret <4 x i32> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vuninitializedq_s64() #0 { # | entry: # | ret <2 x i64> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vuninitializedq_s8() #0 { # | entry: # | ret <16 x i8> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vuninitializedq_u16() #0 { # | entry: # | ret <8 x i16> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vuninitializedq_u32() #0 { # | entry: # | ret <4 x i32> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vuninitializedq_u64() #0 { # | entry: # | ret <2 x i64> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vuninitializedq_u8() #0 { # | entry: # | ret <16 x i8> undef # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>' # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<> # | #0 0x0000561fff5f357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561fff5f0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561fff5f3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f376fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f376fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f376fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f376fd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561fff58924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561fff589096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561fff56df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561fff21d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561fff21ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f376fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f376fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f376fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561fff21cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c --check-prefixes=CHECK,CHECK-LE # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c --check-prefixes=CHECK,CHECK-LE # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c (1313 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv8i8.nxv8i8.i64(, , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-cde-reinterpret.c (1314 of 27911) ******************** TEST 'Clang :: CodeGen/arm-cde-reinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c --check-prefixes=CHECK,CHECK-LE # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_s8(<16 x i8> noundef %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %x, ptr %x.addr, align 8 # | %0 = load <16 x i8>, ptr %x.addr, align 8 # | ret <16 x i8> %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_u16(<16 x i8> noundef %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %x, ptr %x.addr, align 8 # | %0 = load <16 x i8>, ptr %x.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_s32(<16 x i8> noundef %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %x, ptr %x.addr, align 8 # | %0 = load <16 x i8>, ptr %x.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <4 x i32> # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_u32(<16 x i8> noundef %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %x, ptr %x.addr, align 8 # | %0 = load <16 x i8>, ptr %x.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <4 x i32> # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_s64(<16 x i8> noundef %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %x, ptr %x.addr, align 8 # | %0 = load <16 x i8>, ptr %x.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <2 x i64> # | ret <2 x i64> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_u64(<16 x i8> noundef %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %x, ptr %x.addr, align 8 # | %0 = load <16 x i8>, ptr %x.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <2 x i64> # | ret <2 x i64> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_f16(<16 x i8> noundef %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %x, ptr %x.addr, align 8 # | %0 = load <16 x i8>, ptr %x.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_f32(<16 x i8> noundef %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %x, ptr %x.addr, align 8 # | %0 = load <16 x i8>, ptr %x.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+cdecp0,+mve.fp,+thumb-mode" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c485a9557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c485a92515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c485a95cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f31cdf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f31cdf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f31cdf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f31cdf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c485a2b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c485a2b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c485a0ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c4856bf176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c4856bee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f31cdf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f31cdf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f31cdf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c4856bed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c --check-prefixes=CHECK,CHECK-LE # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c --check-prefixes=CHECK,CHECK-LE # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c (1315 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.6a -target-feature +f8f16mm -target-feature +fp8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.6a -target-feature +f8f16mm -target-feature +fp8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local <8 x half> @test_vmmlaq_f16_mf8(<8 x half> noundef %p0, <16 x i8> %p1, <16 x i8> %p2, i64 noundef %p3) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__p3.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <8 x half>, align 16 # | %p0.addr = alloca <8 x half>, align 16 # | %p1.addr = alloca <16 x i8>, align 16 # | %p2.addr = alloca <16 x i8>, align 16 # | %p3.addr = alloca i64, align 8 # | store <8 x half> %p0, ptr %p0.addr, align 16 # | store <16 x i8> %p1, ptr %p1.addr, align 16 # | store <16 x i8> %p2, ptr %p2.addr, align 16 # | store i64 %p3, ptr %p3.addr, align 8 # | %0 = load <8 x half>, ptr %p0.addr, align 16 # | %1 = load <16 x i8>, ptr %p1.addr, align 16 # | %2 = load <16 x i8>, ptr %p2.addr, align 16 # | %3 = load i64, ptr %p3.addr, align 8 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | store i64 %3, ptr %__p3.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %6 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %7 = load i64, ptr %__p3.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %fmmla.i = bitcast <16 x i8> %4 to <8 x half> # | %fmmla1.i = call <8 x half> @llvm.aarch64.neon.fmmla.v8f16.v16i8(<8 x half> %fmmla.i, <16 x i8> %5, <16 x i8> %6) # | store <8 x half> %fmmla1.i, ptr %ref.tmp.i, align 16 # | %8 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %8, ptr %__ret.i, align 16 # | %9 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.aarch64.neon.fmmla.v8f16.v16i8(<8 x half>, <16 x i8>, <16 x i8>) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+bti,+ccidx,+cmpbr,+complxnum,+cpa,+crc,+cssc,+dit,+dotprod,+f8f16mm,+faminmax,+flagm,+fp-armv8,+fp8,+fullfp16,+hbc,+hinte,+i8mm,+jsconv,+lse,+lsui,+lut,+mec,+mops,+neon,+occmo,+pauth,+predres,+ras,+rasv2,+rcpc,+rdm,+rme,+sb,+spe-eef,+specres2,+ssbs,+sve,+sve2,+sve2p1,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v8.9a,+v8a,+v9.1a,+v9.2a,+v9.3a,+v9.4a,+v9.5a,+v9.6a,+v9a,+wfxt" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055be1284e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055be1284b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055be1284ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe435249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe4352a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe435249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe435231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055be127e424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055be127e4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055be127c8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055be12478176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055be12477e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe435232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe4352330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe4352330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055be12477d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c (1316 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8m4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca # | ... # `---data was truncated (10240/176535) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b032fb457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b032fb1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b032fb4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6f45e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6f45e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6f45e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6f45e03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b032f4a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b032f4a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b032f2ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b032bde176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b032bdde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6f45e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6f45e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6f45e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b032bddd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c (1317 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f32m1x2_tu(target("riscv # | ... # `---data was truncated (10240/295533) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555d7054957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555d70546515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555d70549cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4fb3649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4fb36a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4fb3649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4fb3631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555d704df24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555d704df096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555d704c3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555d70173176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555d70172e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4fb3632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4fb36330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4fb36330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555d70172d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c (1318 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055aa6bfd157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055aa6bfce515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055aa6bfd1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd00c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd00c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd00c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd00c51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aa6bf6724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055aa6bf67096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055aa6bf4bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055aa6bbfb176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055aa6bbfae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd00c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd00c51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd00c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aa6bbfad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c (1319 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = allo # | ... # `---data was truncated (10240/98179) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056295b10557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056295b102515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056295b105cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc76ee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc76eea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc76ee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc76ee31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056295b09b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056295b09b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056295b07ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056295ad2f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056295ad2ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc76ee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc76ee330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc76ee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056295ad2ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c (1320 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_f32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_f32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_i32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_i32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_u32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_u32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_f32mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_f32m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounw # | ... # `---data was truncated (10240/15952) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005611ef96d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005611ef96a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005611ef96dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f905c81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f905c8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f905c81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f905c803507 abort ./stdlib/abort.c:85:3 # | #7 0x00005611ef90324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005611ef903096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005611ef8e7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005611ef597176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005611ef596e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f905c804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f905c8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f905c8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005611ef596d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c (1321 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv32i16.i64( poison, %0, i64 %1) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c (1322 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16mf4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv1f16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv2f16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv4f16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv8f16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv16f16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv32f16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv32f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_i16mf4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv1i16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_i16mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv2i16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_i16m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv4i16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4i16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_i16m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv8i16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vhsubq.c (1323 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vhsubq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhsubq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vhsub.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vhsub.v16i8(<16 x i8>, <16 x i8>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhsubq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vhsub.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vhsub.v8i16(<8 x i16>, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhsubq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vhsub.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vhsub.v4i32(<4 x i32>, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhsubq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.hsub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.hsub.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhsubq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.hsub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.hsub.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhsubq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.hsub.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.hsub.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhsubq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = call <16 x i8> @llvm.arm.mve.vhsub.v16i8(<16 x i8> %0, <16 x i8> %.splat, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhsubq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = call <8 x i16> @llvm.arm.mve.vhsub.v8i16(<8 x i16> %0, <8 x i16> %.splat, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhsubq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = call <4 x i32> @llvm.arm.mve.vhsub.v4i32(<4 x i32> %0, <4 x i32> %.splat, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhsubq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.hsub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhsubq_m_n_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.hsub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, i32 1, <8 x i1> %4, <8 x i # | ... # `---data was truncated (10240/14644) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f1af4fa57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f1af4f7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f1af4facbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa99fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa99fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa99fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa99fb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f1af49024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f1af490096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f1af474f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f1af124176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f1af123e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa99fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa99fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa99fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f1af123d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c (1324 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563ad153b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563ad1538515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563ad153bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f23ed21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f23ed2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f23ed21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f23ed203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563ad14d124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563ad14d1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563ad14b5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563ad1165176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563ad1164e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f23ed204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f23ed2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f23ed2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563ad1164d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c (1325 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559c95d4957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559c95d46515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559c95d49cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f29c8e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f29c8e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f29c8e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f29c8e03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559c95cdf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559c95cdf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559c95cc3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559c95973176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559c95972e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f29c8e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f29c8e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f29c8e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559c95972d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c (1326 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf8x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf4x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf8x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf4x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv8i1(target("riscv.vector.tup # | ... # `---data was truncated (10240/11031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d512bef57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d512bec515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d512befcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f077cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f077cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f077cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f077cf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d512b8524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d512b85096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d512b69f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d512819176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d512818e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f077cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f077cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f077cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d512818d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c (1327 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557b16eef57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557b16eec515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557b16eefcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f882cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f882cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f882cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f882cb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557b16e8524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557b16e85096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557b16e69f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557b16b19176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557b16b18e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f882cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f882cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f882cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557b16b18d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c (1328 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c (1329 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_i64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_u64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_f64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_i64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_u64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_f64m1x5_tumu( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 0, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_i64m1x5_tumu( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tu # | ... # `---data was truncated (10240/16560) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d9ec3d557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d9ec3d2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d9ec3d5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efd73105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efd7315c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efd73105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efd730ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d9ec36b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d9ec36b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d9ec34ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d9ebfff176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d9ebffee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efd730eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efd730ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efd730ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d9ebffed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c (1330 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | ... # `---data was truncated (10240/302389) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cb851fd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cb851fa515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cb851fdcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3831b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3831b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3831b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3831b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cb8519324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cb85193096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cb85177f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cb84e27176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cb84e26e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3831b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3831b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3831b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cb84e26d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c (1331 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f32m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f32m4x2(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c (1332 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_i8mf8x7_tu(target("riscv.vector.tuple", , 7) %m # | ... # `---data was truncated (10240/160133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056199d4dc57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056199d4d9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056199d4dccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5c04f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5c04f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5c04f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5c04f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056199d47224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056199d472096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056199d456f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056199d106176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056199d105e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5c04f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5c04f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5c04f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056199d105d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c (1333 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 # | ... # `---data was truncated (10240/66565) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005596d4d4f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005596d4d4c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005596d4d4fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff24e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff24e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff24e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff24e11b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005596d4ce524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005596d4ce5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005596d4cc9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005596d4979176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005596d4978e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff24e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff24e11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff24e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005596d4978d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c (1334 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_i64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_i64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_u64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_u64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m1x3_tum( %mask, target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c (1335 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = l # | ... # `---data was truncated (10240/23247) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055562f34757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055562f344515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055562f347cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc5cdc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc5cdca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc5cdc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc5cdc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055562f2dd24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055562f2dd096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055562f2c1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055562ef71176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055562ef70e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc5cdc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc5cdc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc5cdc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055562ef70d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c (1336 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f64m1x4(ptr noundef %base, %binde # | ... # `---data was truncated (10240/99754) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558645a0757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558645a04515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558645a07cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2fa8733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2fa878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2fa8733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2fa871b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055864599d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055864599d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558645981f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558645631176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558645630e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2fa871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2fa871d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2fa871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558645630d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c (1337 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwi # | ... # `---data was truncated (10240/44369) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e1c5e6f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e1c5e6c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e1c5e6fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1737d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1737d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1737d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1737d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e1c5e0524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e1c5e05096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e1c5de9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e1c5a99176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e1c5a98e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1737d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1737d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1737d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e1c5a98d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c (1338 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf8( %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf8( %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv1i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf4( %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf4( %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv2i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf2( %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf2( %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv4i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8m1( %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8m1( %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv8i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv8i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8m2( %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca # | ... # `---data was truncated (10240/124506) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561197edc57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561197ed9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561197edccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f704b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f704b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f704b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f704b51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561197e7224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561197e72096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561197e56f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561197b06176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561197b05e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f704b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f704b51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f704b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561197b05d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/builtin-align.c (1339 of 27911) ******************** TEST 'Clang :: CodeGen/builtin-align.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple=x86_64-unknown-unknown -DTEST_VOID_PTR -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -check-prefixes CHECK,CHECK-VOID_PTR -enable-var-scope '-D$PTRTYPE=i8' # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple=x86_64-unknown-unknown -DTEST_VOID_PTR -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-unknown" # | # | @aligned_true = global i8 1, align 1 # | @aligned_false = global i8 0, align 1 # | @down_1 = global i32 992, align 4 # | @down_2 = global i32 256, align 4 # | @up_1 = global i32 1024, align 4 # | @up_2 = global i32 256, align 4 # | # | ; Function Attrs: noinline nounwind # | define dso_local ptr @get_type() #0 { # | entry: # | ret ptr null # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local zeroext i1 @is_aligned(ptr noundef %ptr, i32 noundef %align) #0 { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %align.addr = alloca i32, align 4 # | store ptr %ptr, ptr %ptr.addr, align 8 # | store i32 %align, ptr %align.addr, align 4 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i32, ptr %align.addr, align 4 # | %alignment = zext i32 %1 to i64 # | %mask = sub i64 %alignment, 1 # | %src_addr = ptrtoint ptr %0 to i64 # | %set_bits = and i64 %src_addr, %mask # | %is_aligned = icmp eq i64 %set_bits, 0 # | ret i1 %is_aligned # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local ptr @align_up(ptr noundef %ptr, i32 noundef %align) #0 { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %align.addr = alloca i32, align 4 # | store ptr %ptr, ptr %ptr.addr, align 8 # | store i32 %align, ptr %align.addr, align 4 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i32, ptr %align.addr, align 4 # | %alignment = zext i32 %1 to i64 # | %mask = sub i64 %alignment, 1 # | %over_boundary = getelementptr inbounds i8, ptr %0, i64 %mask # | %inverted_mask = xor i64 %mask, -1 # | %aligned_result = call ptr @llvm.ptrmask.p0.i64(ptr %over_boundary, i64 %inverted_mask) # | ret ptr %aligned_result # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare ptr @llvm.ptrmask.p0.i64(ptr, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local ptr @align_down(ptr noundef %ptr, i32 noundef %align) #0 { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %align.addr = alloca i32, align 4 # | store ptr %ptr, ptr %ptr.addr, align 8 # | store i32 %align, ptr %align.addr, align 4 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i32, ptr %align.addr, align 4 # | %alignment = zext i32 %1 to i64 # | %mask = sub i64 %alignment, 1 # | %inverted_mask = xor i64 %mask, -1 # | %aligned_result = call ptr @llvm.ptrmask.p0.i64(ptr %0, i64 %inverted_mask) # | ret ptr %aligned_result # | } # | # | attributes #0 = { noinline nounwind "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x00005603bb9ab57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005603bb9a8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005603bb9abcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f63cf933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f63cf98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f63cf933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f63cf91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005603bb94124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005603bb941096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005603bb925f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005603bb5d5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005603bb5d4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f63cf91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f63cf91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f63cf91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005603bb5d4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -check-prefixes CHECK,CHECK-VOID_PTR -enable-var-scope '-D$PTRTYPE=i8' # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -check-prefixes CHECK,CHECK-VOID_PTR -enable-var-scope -D$PTRTYPE=i8 # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c (1340 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16mf4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv32f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv32f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16mf4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16i16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | % # | ... # `---data was truncated (10240/33764) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056530442a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000565304427515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056530442acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4829b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4829b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4829b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4829b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005653043c024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005653043c0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005653043a4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000565304054176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000565304053e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4829b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4829b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4829b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565304053d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c (1341 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv1i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv1i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv2i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv2i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv4i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv4i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv8i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv8i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , al # | ... # `---data was truncated (10240/226593) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dbe98fb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055dbe98f8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055dbe98fbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5c5d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5c5d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5c5d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5c5d431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dbe989124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055dbe9891096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055dbe9875f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055dbe9525176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055dbe9524e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5c5d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5c5d4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5c5d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dbe9524d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c (1342 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf8( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf4( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf2( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m1( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m2( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m4( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m8( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv64i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16mf4( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv1i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16mf2( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv2i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16m1( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv4i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16m2( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.add # | ... # `---data was truncated (10240/86739) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557b45bbf57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557b45bbc515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557b45bbfcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fadb4333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fadb438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fadb4333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fadb431b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557b45b5524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557b45b55096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557b45b39f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557b457e9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557b457e8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fadb431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fadb431d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fadb431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557b457e8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c (1343 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_f32mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_f32mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv1f32.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_f32m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_f32m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv2f32.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willret # | ... # `---data was truncated (10240/365423) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056329820f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056329820c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056329820fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0d87933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0d8798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0d87933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0d8791b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005632981a524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005632981a5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563298189f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563297e39176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563297e38e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0d8791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0d8791d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0d8791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563297e38d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c (1344 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_bf16mf4_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_bf16mf4_f32mf2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_bf16mf4_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_bf16_f32mf2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_bf16mf2_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_bf16mf2_f32m1( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_bf16mf2_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_bf16_f32m1( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_bf16m1_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv4f32.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_bf16m1_f32m2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.a # | ... # `---data was truncated (10240/86092) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005626236f357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005626236f0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005626236f3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb1b1333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb1b138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb1b1333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb1b131b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056262368924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562623689096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056262366df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056262331d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056262331ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb1b131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb1b131d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb1b131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056262331cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c (1345 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_i32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_i32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_u32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_u32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32mf2x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, # | ... # `---data was truncated (10240/40726) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563ad912657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563ad9123515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563ad9126cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4df5049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4df50a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4df5049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4df5031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563ad90bc24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563ad90bc096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563ad90a0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563ad8d50176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563ad8d4fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4df5032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4df50330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4df50330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563ad8d4fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c (1346 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1f32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv2f32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv4f32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv8f32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv16f32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1i32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv2i32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv4i32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv8i32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv16i32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_u32mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1i32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_u32m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, a # | ... # `---data was truncated (10240/29450) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055664ad3157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055664ad2e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055664ad31cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9f83333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9f8338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9f83333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9f8331b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055664acc724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055664acc7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055664acabf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055664a95b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055664a95ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9f8331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9f8331d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9f8331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055664a95ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-v8.1a-neon-intrinsics.c (1347 of 27911) ******************** TEST 'Clang :: CodeGen/arm-v8.1a-neon-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.1a-linux-gnu -target-abi apcs-gnu -target-feature +neon -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c --check-prefix=CHECK-ARM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.1a-linux-gnu -target-abi apcs-gnu -target-feature +neon -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c" # | target datalayout = "e-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" # | target triple = "armv8.1a-unknown-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vqrdmlah_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__p2.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | %c.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | store <4 x i16> %c, ptr %c.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | %2 = load <4 x i16>, ptr %c.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | store <4 x i16> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vqrdmlah_s16.i = bitcast <8 x i8> %3 to <4 x i16> # | %vqrdmlah_s161.i = bitcast <8 x i8> %4 to <4 x i16> # | %vqrdmlah_s162.i = bitcast <8 x i8> %5 to <4 x i16> # | %vqrdmlah_s163.i = call <4 x i16> @llvm.arm.neon.vqrdmlah.v4i16(<4 x i16> %vqrdmlah_s16.i, <4 x i16> %vqrdmlah_s161.i, <4 x i16> %vqrdmlah_s162.i) # | %vqrdmlah_s164.i = bitcast <4 x i16> %vqrdmlah_s163.i to <8 x i8> # | store <8 x i8> %vqrdmlah_s164.i, ptr %ref.tmp.i, align 8 # | %6 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %6, ptr %__ret.i, align 8 # | %7 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vqrdmlah_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <2 x i32> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__p2.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <2 x i32>, align 8 # | %c.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <2 x i32> %b, ptr %b.addr, align 8 # | store <2 x i32> %c, ptr %c.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | %1 = load <2 x i32>, ptr %b.addr, align 8 # | %2 = load <2 x i32>, ptr %c.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | store <2 x i32> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vqrdmlah_s32.i = bitcast <8 x i8> %3 to <2 x i32> # | %vqrdmlah_s321.i = bitcast <8 x i8> %4 to <2 x i32> # | %vqrdmlah_s322.i = bitcast <8 x i8> %5 to <2 x i32> # | %vqrdmlah_s323.i = call <2 x i32> @llvm.arm.neon.vqrdmlah.v2i32(<2 x i32> %vqrdmlah_s32.i, <2 x i32> %vqrdmlah_s321.i, <2 x i32> %vqrdmlah_s322.i) # | %vqrdmlah_s324.i = bitcast <2 x i32> %vqrdmlah_s323.i to <8 x i8> # | store <8 x i8> %vqrdmlah_s324.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vqrdmlahq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x i16>, align 16 # | %__p2.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x i16>, align 16 # | %c.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | store <8 x i16> %b, ptr %b.addr, align 16 # | store <8 x i16> %c, ptr %c.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | %1 = load <8 x i16>, ptr %b.addr, align 16 # | %2 = load <8 x i16>, ptr %c.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | store <8 x i16> %1, ptr %__p1.addr.i, align 16 # | store <8 x i16> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vqrdmlahq_s16.i = bitcast <16 x i8> %3 to <8 x i16> # | %vqrdmlahq_s161.i = bitcast <16 x i8> %4 to <8 x i16> # | %vqrdmlahq_s162.i = bitcast <16 x i8> %5 to <8 x i16> # | %vqrdmlahq_s163.i = call <8 x i16> @llvm.arm.neon.vqrdmlah.v8i16(<8 x i16> %vqrdmlahq_s16.i, <8 x i16> %vqrdmlahq_s161.i, <8 x i16> %vqrdmlahq_s162.i) # | %vqrdmlahq_s164.i = bitcast <8 x i16> %vqrdmlahq_s163.i to <16 x i8> # | store <16 x i8> %vqrdmlahq_s164.i, ptr %ref.tmp.i, align 16 # | %6 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %6, ptr %__ret.i, align 16 # | %7 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vqrdmlahq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <4 x i32>, align 16 # | %__p2.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | %b.addr = alloca <4 x i32>, align 16 # | %c.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | store <4 x i32> %b, ptr %b.addr, align 16 # | store <4 x i32> %c, ptr %c.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | %1 = load <4 x i32>, ptr %b.addr, align 16 # | %2 = load <4 x i32>, ptr %c.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | store <4 x i32> %1, ptr %__p1.addr.i, align 16 # | store <4 x i32> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vqrdmlahq_s32.i = bitcast <16 x i8> %3 to <4 x i32> # | %vqrdmlahq_s321.i = bitcast <16 x i8> %4 to <4 x i32> # | %vqrdmlahq_s322.i = bitcast <16 x i8> %5 to <4 x i32> # | %vqrdmlahq_s323.i = call <4 x i32> @llvm.arm.neon.vqrdmlah.v4i32(<4 x i32> %vqrdmlahq_s32.i, <4 x i32> %vqrdmlahq_s321.i, <4 x i32> %vqrdmlahq_s322.i) # | %vqrdmlahq_s324.i = bitcast <4 x i32> %vqrdmlahq_s323.i to <16 x i8> # | store <16 x i8> %vqrdmlahq_s324.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %6, ptr %__ret.i, align 16 # | %7 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vqrdmlah_lane_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__p2.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | %c.addr = alloca <4 x i16>, align 8 # | %__ret_140 = alloca <4 x i16>, align 8 # | %__s0_140 = alloca <4 x i16>, align 8 # | %__s1_140 = alloca <4 x i16>, align 8 # | %__s2_140 = alloca <4 x i16>, align 8 # | %__ret = alloca <4 x i16>, align 8 # | %__s0 = alloca <4 x i16>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x i16>, align 8 # | %tmp1 = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | store <4 x i16> %c, ptr %c.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__s0_140, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %1, ptr %__s1_140, align 8 # | %2 = load <4 x i16>, ptr %c.addr, align 8 # | store <4 x i16> %2, ptr %__s2_140, align 8 # | %3 = load <4 x i16>, ptr %__s0_140, align 8 # | %4 = load <4 x i16>, ptr %__s1_140, align 8 # | %5 = load <4 x i16>, ptr %__s2_140, align 8 # | store <4 x i16> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <4 x i16> # | %lane = shufflevector <4 x i16> %7, <4 x i16> %7, <4 x i32> # | store <4 x i16> %lane, ptr %ref.tmp, align 8 # | %8 = load <4 x i16>, ptr %ref.tmp, align 8 # | store <4 x i16> %8, ptr %__ret, align 8 # | %9 = load <4 x i16>, ptr %__ret, align 8 # | store <4 x i16> %9, ptr %tmp, align 8 # | %10 = load <4 x i16>, ptr %tmp, align 8 # | store <4 x i16> %3, ptr %__p0.addr.i, align 8 # | store <4 x i16> %4, ptr %__p1.addr.i, align 8 # | store <4 x i16> %10, ptr %__p2.addr.i, align 8 # | %11 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %12 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %13 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vqrdmlah_s16.i = bitcast <8 x i8> %11 to <4 x i16> # | %vqrdmlah_s161.i = bitcast <8 x i8> %12 to <4 x i16> # | %vqrdmlah_s162.i = bitcast <8 x i8> %13 to <4 x i16> # | %vqrdmlah_s163.i = call <4 x i16> @llvm.arm.neon.vqrdmlah.v4i16(<4 x i16> %vqrdmlah_s16.i, <4 x i16> %vqrdmlah_s161.i, <4 x i16> %vqrdmlah_s162.i) # | %vqrdmlah_s164.i = bitcast <4 x i16> %vqrdmlah_s163.i to <8 x i8> # | store <8 x i8> %vqrdmlah_s164.i, ptr %ref.tmp.i, align 8 # | %14 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %14, ptr %__ret.i, align 8 # | %15 = load <4 x i16>, ptr %__ret.i, align 8 # | store <4 x i16> %15, ptr %__ret_140, align 8 # | %16 = load <4 x i16>, ptr %__ret_140, align 8 # | store <4 x i16> %16, ptr %tmp1, align 8 # | %17 = load <4 x i16>, ptr %tmp1, align 8 # | ret <4 x i16> %17 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vqrdmlah_lane_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <2 x i32> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__p2.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr # | ... # `---data was truncated (10240/38786) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S # | #0 0x000055c5705ea57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c5705e7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c5705eacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f231ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f231ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f231ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f231ad1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c57058024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c570580096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c570564f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c570214176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c570213e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f231ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f231ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f231ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c570213d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c --check-prefix=CHECK-ARM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c --check-prefix=CHECK-ARM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c (1348 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv1i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv1i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv2i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv2i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv4i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv4i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv8i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv8i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv16i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv16i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function # | ... # `---data was truncated (10240/100281) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055704679657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557046793515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557046796cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbbd1905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbbd195c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbbd1905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbbd18ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055704672c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055704672c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557046710f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005570463c0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005570463bfe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbbd18eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbbd18ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbbd18ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005570463bfd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c (1349 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m8_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32m2_tu( %maskedoff, ptr noundef % # | ... # `---data was truncated (10240/280171) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005606fbca357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005606fbca0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005606fbca3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe295505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe29555c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe295505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe2954ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005606fbc3924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005606fbc39096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005606fbc1df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005606fb8cd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005606fb8cce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe2954eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe2954ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe2954ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005606fb8ccd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c (1350 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m4_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/fp8-cast.c (1351 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-cast.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_f8_f8(<8 x i8> %x) #0 { # | entry: # | %x.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %x, ptr %x.addr, align 8 # | %0 = load <8 x i8>, ptr %x.addr, align 8 # | ret <8 x i8> %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @testq_f8_f8(<16 x i8> %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %x, ptr %x.addr, align 16 # | %0 = load <16 x i8>, ptr %x.addr, align 16 # | ret <16 x i8> %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_f8_s8(<8 x i8> noundef %x) #0 { # | entry: # | %x.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %x, ptr %x.addr, align 8 # | %0 = load <8 x i8>, ptr %x.addr, align 8 # | ret <8 x i8> %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_s8_f8(<8 x i8> %x) #0 { # | entry: # | %x.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %x, ptr %x.addr, align 8 # | %0 = load <8 x i8>, ptr %x.addr, align 8 # | ret <8 x i8> %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @testq_f8_s8(<16 x i8> noundef %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %x, ptr %x.addr, align 16 # | %0 = load <16 x i8>, ptr %x.addr, align 16 # | ret <16 x i8> %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @testq_s8_f8(<16 x i8> %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %x, ptr %x.addr, align 16 # | %0 = load <16 x i8>, ptr %x.addr, align 16 # | ret <16 x i8> %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_f8_f32(<2 x float> noundef %x) #0 { # | entry: # | %x.addr = alloca <2 x float>, align 8 # | store <2 x float> %x, ptr %x.addr, align 8 # | %0 = load <2 x float>, ptr %x.addr, align 8 # | %1 = bitcast <2 x float> %0 to <8 x i8> # | ret <8 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_f32_f8(<8 x i8> %x) #0 { # | entry: # | %x.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %x, ptr %x.addr, align 8 # | %0 = load <8 x i8>, ptr %x.addr, align 8 # | %1 = bitcast <8 x i8> %0 to <2 x float> # | ret <2 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @testq_f8_f32(<4 x float> noundef %x) #0 { # | entry: # | %x.addr = alloca <4 x float>, align 16 # | store <4 x float> %x, ptr %x.addr, align 16 # | %0 = load <4 x float>, ptr %x.addr, align 16 # | %1 = bitcast <4 x float> %0 to <16 x i8> # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @testq_f32_f8(<16 x i8> %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %x, ptr %x.addr, align 16 # | %0 = load <16 x i8>, ptr %x.addr, align 16 # | %1 = bitcast <16 x i8> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @testq_f8_p128(i128 noundef %x) #0 { # | entry: # | %x.addr = alloca i128, align 16 # | store i128 %x, ptr %x.addr, align 16 # | %0 = load i128, ptr %x.addr, align 16 # | %1 = bitcast i128 %0 to <16 x i8> # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @testq_p128_f8(<16 x i8> %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %x, ptr %x.addr, align 16 # | %0 = load <16 x i8>, ptr %x.addr, align 16 # | %1 = bitcast <16 x i8> %0 to i128 # | ret i128 %1 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg # | #0 0x00005635c31cb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005635c31c8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005635c31cbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff82f905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff82f95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff82f905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff82f8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005635c316124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005635c3161096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005635c3145f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005635c2df5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005635c2df4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff82f8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff82f8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff82f8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005635c2df4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c (1352 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test # | ... # `---data was truncated (10240/94993) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559021a1b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559021a18515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559021a1bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbcbfb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbcbfb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbcbfb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbcbfaed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005590219b124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005590219b1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559021995f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559021645176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559021644e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbcbfaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbcbfaef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbcbfaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559021644d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c (1353 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0. # | ... # `---data was truncated (10240/82975) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b18c1e757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b18c1e4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b18c1e7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8a5e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8a5e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8a5e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8a5e631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b18c17d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b18c17d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b18c161f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b18be11176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b18be10e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8a5e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8a5e6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8a5e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b18be10d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c (1354 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, ali # | ... # `---data was truncated (10240/14621) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f36eb2b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f36eb28515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f36eb2bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1cb3c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1cb3c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1cb3c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1cb3c03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f36eac124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f36eac1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f36eaa5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f36e755176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f36e754e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1cb3c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1cb3c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1cb3c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f36e754d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/WebAssembly/builtins-table-externref.c (1355 of 27911) ******************** TEST 'Clang :: CodeGen/WebAssembly/builtins-table-externref.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple wasm32 -target-feature +reference-types -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple wasm32 -target-feature +reference-types -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c" # | target datalayout = "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-i128:128-n32:64-S128-ni:1:10:20" # | target triple = "wasm32" # | # | @table = internal addrspace(1) global [0 x target("wasm.externref")] zeroinitializer, align 1 # | @const_table = internal addrspace(1) constant [0 x target("wasm.externref")] zeroinitializer, align 1 # | @other_table = internal addrspace(1) global [0 x target("wasm.externref")] zeroinitializer, align 1 # | # | ; Function Attrs: noinline nounwind # | define target("wasm.externref") @test_builtin_wasm_table_get(i32 noundef %index) #0 { # | entry: # | %index.addr = alloca i32, align 4 # | store i32 %index, ptr %index.addr, align 4 # | %0 = load i32, ptr %index.addr, align 4 # | %1 = call target("wasm.externref") @llvm.wasm.table.get.externref(ptr addrspace(1) @table, i32 %0) # | ret target("wasm.externref") %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("wasm.externref") @llvm.wasm.table.get.externref(ptr addrspace(1), i32) #1 # | # | ; Function Attrs: noinline nounwind # | define target("wasm.externref") @test_builtin_wasm_table_get_const(i32 noundef %index) #0 { # | entry: # | %index.addr = alloca i32, align 4 # | store i32 %index, ptr %index.addr, align 4 # | %0 = load i32, ptr %index.addr, align 4 # | %1 = call target("wasm.externref") @llvm.wasm.table.get.externref(ptr addrspace(1) @table, i32 %0) # | ret target("wasm.externref") %1 # | } # | # | ; Function Attrs: noinline nounwind # | define void @test_builtin_wasm_table_set(i32 noundef %index, target("wasm.externref") %ref) #0 { # | entry: # | %index.addr = alloca i32, align 4 # | %ref.addr = alloca target("wasm.externref"), align 1 # | store i32 %index, ptr %index.addr, align 4 # | store target("wasm.externref") %ref, ptr %ref.addr, align 1 # | %0 = load i32, ptr %index.addr, align 4 # | %1 = load target("wasm.externref"), ptr %ref.addr, align 1 # | call void @llvm.wasm.table.set.externref(ptr addrspace(1) @const_table, i32 %0, target("wasm.externref") %1) # | %2 = load i32, ptr %index.addr, align 4 # | %3 = load target("wasm.externref"), ptr %ref.addr, align 1 # | call void @llvm.wasm.table.set.externref(ptr addrspace(1) @table, i32 %2, target("wasm.externref") %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.wasm.table.set.externref(ptr addrspace(1), i32, target("wasm.externref")) #2 # | # | ; Function Attrs: noinline nounwind # | define void @test_builtin_wasm_table_set_const(i32 noundef %index, target("wasm.externref") %ref) #0 { # | entry: # | %index.addr = alloca i32, align 4 # | %ref.addr = alloca target("wasm.externref"), align 1 # | store i32 %index, ptr %index.addr, align 4 # | store target("wasm.externref") %ref, ptr %ref.addr, align 1 # | %0 = load i32, ptr %index.addr, align 4 # | %1 = load target("wasm.externref"), ptr %ref.addr, align 1 # | call void @llvm.wasm.table.set.externref(ptr addrspace(1) @table, i32 %0, target("wasm.externref") %1) # | %2 = load i32, ptr %index.addr, align 4 # | %3 = load target("wasm.externref"), ptr %ref.addr, align 1 # | call void @llvm.wasm.table.set.externref(ptr addrspace(1) @const_table, i32 %2, target("wasm.externref") %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define i32 @test_builtin_wasm_table_size() #0 { # | entry: # | %0 = call i32 @llvm.wasm.table.size(ptr addrspace(1) @table) # | ret i32 %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare i32 @llvm.wasm.table.size(ptr addrspace(1)) #1 # | # | ; Function Attrs: noinline nounwind # | define i32 @test_builtin_wasm_table_grow(target("wasm.externref") %ref, i32 noundef %nelem) #0 { # | entry: # | %ref.addr = alloca target("wasm.externref"), align 1 # | %nelem.addr = alloca i32, align 4 # | store target("wasm.externref") %ref, ptr %ref.addr, align 1 # | store i32 %nelem, ptr %nelem.addr, align 4 # | %0 = load target("wasm.externref"), ptr %ref.addr, align 1 # | %1 = load i32, ptr %nelem.addr, align 4 # | %2 = call i32 @llvm.wasm.table.grow.externref(ptr addrspace(1) @table, target("wasm.externref") %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare i32 @llvm.wasm.table.grow.externref(ptr addrspace(1), target("wasm.externref"), i32) #3 # | # | ; Function Attrs: noinline nounwind # | define void @test_builtin_wasm_table_fill(i32 noundef %index, target("wasm.externref") %ref, i32 noundef %nelem) #0 { # | entry: # | %index.addr = alloca i32, align 4 # | %ref.addr = alloca target("wasm.externref"), align 1 # | %nelem.addr = alloca i32, align 4 # | store i32 %index, ptr %index.addr, align 4 # | store target("wasm.externref") %ref, ptr %ref.addr, align 1 # | store i32 %nelem, ptr %nelem.addr, align 4 # | %0 = load i32, ptr %index.addr, align 4 # | %1 = load target("wasm.externref"), ptr %ref.addr, align 1 # | %2 = load i32, ptr %nelem.addr, align 4 # | call void @llvm.wasm.table.fill.externref(ptr addrspace(1) @table, i32 %0, target("wasm.externref") %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.wasm.table.fill.externref(ptr addrspace(1), i32, target("wasm.externref"), i32) #3 # | # | ; Function Attrs: noinline nounwind # | define void @test_table_copy(i32 noundef %dst_idx, i32 noundef %src_idx, i32 noundef %nelem) #0 { # | entry: # | %dst_idx.addr = alloca i32, align 4 # | %src_idx.addr = alloca i32, align 4 # | %nelem.addr = alloca i32, align 4 # | store i32 %dst_idx, ptr %dst_idx.addr, align 4 # | store i32 %src_idx, ptr %src_idx.addr, align 4 # | store i32 %nelem, ptr %nelem.addr, align 4 # | %0 = load i32, ptr %dst_idx.addr, align 4 # | %1 = load i32, ptr %src_idx.addr, align 4 # | %2 = load i32, ptr %nelem.addr, align 4 # | call void @llvm.wasm.table.copy(ptr addrspace(1) @table, ptr addrspace(1) @other_table, i32 %1, i32 %0, i32 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.wasm.table.copy(ptr addrspace(1), ptr addrspace(1), i32, i32, i32) #3 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+reference-types" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(write) } # | attributes #3 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a68e63f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a68e63c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a68e63fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0d32449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0d324a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0d32449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0d32431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a68e5d524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a68e5d5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a68e5b9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a68e269176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a68e268e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0d32432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0d324330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0d324330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a68e268d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c (1356 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16m1x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563f5f76757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563f5f764515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563f5f767cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fec4aa1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fec4aa725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fec4aa1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fec4aa03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563f5f6fd24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563f5f6fd096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563f5f6e1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563f5f391176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563f5f390e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fec4aa04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fec4aa050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fec4aa050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563f5f390d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c (1357 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_i64m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_i64m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_u64m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_u64m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_i64m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_i64m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_u64m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.t # | ... # `---data was truncated (10240/12089) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e47138557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e471382515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e471385cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5fe201bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5fe20725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5fe201ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5fe2003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e47131b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e47131b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e4712fff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e470faf176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e470faee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5fe2004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5fe20050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5fe20050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e470faed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c (1358 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_v # | ... # `---data was truncated (10240/216258) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bb3ba8a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bb3ba87515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bb3ba8acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7d50933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7d5098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7d50933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7d5091b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bb3ba2024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bb3ba20096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bb3ba04f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bb3b6b4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bb3b6b3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7d5091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7d5091d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7d5091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bb3b6b3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c (1359 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055823ea3d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055823ea3a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055823ea3dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5b51505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5b5155c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5b51505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5b514ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055823e9d324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055823e9d3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055823e9b7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055823e667176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055823e666e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5b514eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5b514ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5b514ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055823e666d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c (1360 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory( # | ... # `---data was truncated (10240/40661) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056020931857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560209315515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560209318cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc161c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc161ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc161c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc161c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005602092ae24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005602092ae096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560209292f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560208f42176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560208f41e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc161c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc161c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc161c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560208f41d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c (1361 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8m2_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c (1362 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), p # | ... # `---data was truncated (10240/87316) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b72732857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b727325515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b727328cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff426f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff426f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff426f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff426f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b7272be24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b7272be096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b7272a2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b726f52176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b726f51e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff426f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff426f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff426f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b726f51d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-neon-shifts.c (1363 of 27911) ******************** TEST 'Clang :: CodeGen/arm-neon-shifts.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-apple-darwin -disable-O0-optnone -target-cpu cortex-a8 -ffreestanding -emit-llvm -w -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-apple-darwin -disable-O0-optnone -target-cpu cortex-a8 -ffreestanding -emit-llvm -w -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c" # | target datalayout = "e-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" # | target triple = "thumbv7-apple-darwin" # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @test_shift_vshr(<8 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | %vshr_n = lshr <8 x i8> %1, splat (i8 5) # | store <8 x i8> %vshr_n, ptr %ref.tmp, align 8 # | %2 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %2, ptr %__ret, align 8 # | %3 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %3, ptr %tmp, align 8 # | %4 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @test_shift_vshr_smax(<8 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | %vshr_n = ashr <8 x i8> %1, splat (i8 7) # | store <8 x i8> %vshr_n, ptr %ref.tmp, align 8 # | %2 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %2, ptr %__ret, align 8 # | %3 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %3, ptr %tmp, align 8 # | %4 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @test_shift_vshr_umax(<8 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | store <8 x i8> zeroinitializer, ptr %ref.tmp, align 8 # | %2 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %2, ptr %__ret, align 8 # | %3 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %3, ptr %tmp, align 8 # | %4 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @test_shift_vsra(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = load <8 x i8>, ptr %__s1, align 8 # | %vsra_n = lshr <8 x i8> %3, splat (i8 5) # | %4 = add <8 x i8> %2, %vsra_n # | store <8 x i8> %4, ptr %ref.tmp, align 8 # | %5 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %5, ptr %__ret, align 8 # | %6 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %6, ptr %tmp, align 8 # | %7 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @test_shift_vsra_smax(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = load <8 x i8>, ptr %__s1, align 8 # | %vsra_n = ashr <8 x i8> %3, splat (i8 7) # | %4 = add <8 x i8> %2, %vsra_n # | store <8 x i8> %4, ptr %ref.tmp, align 8 # | %5 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %5, ptr %__ret, align 8 # | %6 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %6, ptr %tmp, align 8 # | %7 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @test_shift_vsra_umax(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = load <8 x i8>, ptr %__s1, align 8 # | %4 = add <8 x i8> %2, zeroinitializer # | store <8 x i8> %4, ptr %ref.tmp, align 8 # | %5 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %5, ptr %__ret, align 8 # | %6 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %6, ptr %tmp, align 8 # | %7 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %7 # | } # | # | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a8" "target-features"="+armv7-a,+d32,+dsp,+fp64,+neon,+thumb-mode,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp" } # | # | !llvm.module.flags = !{!0, !1} # | !llvm.ident = !{!2} # | # | !0 = !{i32 1, !"target-abi", !"apcs-gnu"} # | !1 = !{i32 1, !"min_enum_size", i32 4} # | !2 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005614a1ba957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005614a1ba6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005614a1ba9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007effc1333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007effc138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007effc1333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007effc131b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005614a1b3f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005614a1b3f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005614a1b23f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005614a17d3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005614a17d2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007effc131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007effc131d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007effc131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005614a17d2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c (1364 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vreinterpret_p8_mf8(<8 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %v.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %v, ptr %v.addr, align 8 # | %0 = load <8 x i8>, ptr %v.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__ret.i, align 8 # | %2 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vreinterpret_p64_mf8(<8 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %v.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %v, ptr %v.addr, align 8 # | %0 = load <8 x i8>, ptr %v.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <1 x i64>, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__ret.i, align 8 # | %2 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vreinterpret_p16_mf8(<8 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %v.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %v, ptr %v.addr, align 8 # | %0 = load <8 x i8>, ptr %v.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__ret.i, align 8 # | %2 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vreinterpretq_p8_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__ret.i, align 16 # | %2 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca i128, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load i128, ptr %__p0.addr.i, align 16 # | store i128 %1, ptr %__ret.i, align 16 # | %2 = load i128, ptr %__ret.i, align 16 # | ret i128 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vreinterpretq_p64_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | store <2 x i64> %1, ptr %__ret.i, align 16 # | %2 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vreinterpretq_p16_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | store <8 x i16> %1, ptr %__ret.i, align 16 # | %2 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vreinterpretq_u8_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__ret.i, align 16 # | %2 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vreinterpretq_u32_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | store <4 x i32> %1, ptr %__ret.i, align 16 # | %2 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vreinterpretq_u64_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | store <2 x i64> %1, ptr %__ret.i, align 16 # | %2 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vreinterpretq_u16_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | store <8 x i16> %1, ptr %__ret.i, align 16 # | %2 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vreinterpretq_s8_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__ret.i, align 16 # | %2 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vreinterpretq_f64_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x double>, ptr %__p0.addr.i, align 16 # | store <2 x double> %1, ptr %__ret.i, align 16 # | %2 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vreinterpretq_f32_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <4 x float>, ptr %__p0.addr.i, align 16 # | store <4 x float> %1, ptr %__ret.i, align 16 # | %2 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vreinterpretq_f16_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x half>, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__ret.i, align 16 # | %2 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vreinterpretq_s32_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | store <4 x i32> %1, ptr %__ret.i, align 16 # | %2 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vreinterpretq_s64_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | store <2 x i64> %1, ptr %__ret.i, align 16 # | %2 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vreinterpretq_mf8_p8(<16 x i8> noundef %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__ret.i, align 16 # | %2 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vreinterpretq_mf8_p128(i128 noundef %v) #0 { # | entry: # | # | ... # `---data was truncated (10240/32178) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa # | #0 0x0000564bcb84157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564bcb83e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564bcb841cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdc8ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdc8ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdc8ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdc8ef1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564bcb7d724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564bcb7d7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564bcb7bbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564bcb46b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564bcb46ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fdc8ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdc8ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdc8ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564bcb46ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c (1365 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf8( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf8( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv1i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf4( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf4( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv2i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf2( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf2( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv4i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8m1( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8m1( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv8i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv8i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8m2( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/98589) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c15f95557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c15f952515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c15f955cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6c3b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6c3b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6c3b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6c3b631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c15f8eb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c15f8eb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c15f8cff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c15f57f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c15f57ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6c3b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6c3b6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6c3b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c15f57ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c (1366 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_v # | ... # `---data was truncated (10240/253156) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557dbcc6457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557dbcc61515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557dbcc64cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f17e3533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f17e358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f17e3533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f17e351b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557dbcbfa24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557dbcbfa096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557dbcbdef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557dbc88e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557dbc88de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f17e351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f17e351d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f17e351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557dbc88dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c (1367 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f64m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f64.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f64.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f64m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f64.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f64.p0.nxv2i64.i64(, ptr # | ... # `---data was truncated (10240/91267) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f915b8357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f915b80515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f915b83cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8793533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f879358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8793533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f879351b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f915b1924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f915b19096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f915afdf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f9157ad176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f9157ace93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f879351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f879351d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f879351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f9157acd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c (1368 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5), pt # | ... # `---data was truncated (10240/19484) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d2c87ce57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d2c87cb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d2c87cecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f43bc449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f43bc4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f43bc449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f43bc431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d2c876424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d2c8764096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d2c8748f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d2c83f8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d2c83f7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f43bc432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f43bc4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f43bc4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d2c83f7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c (1369 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf8_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m8_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i16mf4_i32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i16mf2_i32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv2i32.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv2i32.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i16m1_i32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca # | ... # `---data was truncated (10240/43515) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055de3da2957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055de3da26515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055de3da29cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f56d1133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f56d118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f56d1133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f56d111b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055de3d9bf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055de3d9bf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055de3d9a3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055de3d653176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055de3d652e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f56d111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f56d111d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f56d111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055de3d652d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c (1370 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c (1371 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_s32( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sdot.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdot.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_s64( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sdot.nxv2i64( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdot.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_u32( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.udot.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.udot.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_u64( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.udot.nxv2i64( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.udot.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_s32( %op1, %op2, i8 noundef %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca i8, align 1 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store i8 %op3, ptr %op3.addr, align 1 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load i8, ptr %op3.addr, align 1 # | %.splatinsert = insertelement poison, i8 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.sdot.nxv4i32( %0, %1, %.splat) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_s64( %op1, %op2, i16 noundef %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca i16, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store i16 %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load i16, ptr %op3.addr, align 2 # | %.splatinsert = insertelement poison, i16 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.sdot.nxv2i64( %0, %1, %.splat) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_u32( %op1, %op2, i8 noundef %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca i8, align 1 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store i8 %op3, ptr %op3.addr, align 1 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load i8, ptr %op3.addr, align 1 # | %.splatinsert = insertelement poison, i8 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.udot.nxv4i32( %0, %1, %.splat) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_u64( %op1, %op2, i16 noundef %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca i16, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store i16 %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load i16, ptr %op3.addr, align 2 # | %.splatinsert = insertelement poison, i16 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.udot.nxv2i64( %0, %1, %.splat) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_lane_s32( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sdot.lane.nxv4i32( %0, %1, %2, i32 0) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdot.lane.nxv4i32(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_lane_s32_1( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = # | ... # `---data was truncated (10240/15126) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055643c89657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055643c893515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055643c896cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb823849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb8238a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb823849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb823831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055643c82c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055643c82c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055643c810f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055643c4c0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055643c4bfe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb823832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb8238330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb8238330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055643c4bfd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c (1372 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8m4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c (1373 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f64m1x4(ptr noundef %base, %binde # | ... # `---data was truncated (10240/94227) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055644fac857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055644fac5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055644fac8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3c79533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3c7958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3c79533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3c7951b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055644fa5e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055644fa5e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055644fa42f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055644f6f2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055644f6f1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3c7951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3c7951d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3c7951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055644f6f1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/load-store.c (1374 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/load-store.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vld1q_f16(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <8 x half>, ptr %0, align 2 # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vld1q_f32(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <4 x float>, ptr %0, align 4 # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vld1q_s8(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <16 x i8>, ptr %0, align 1 # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vld1q_s16(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <8 x i16>, ptr %0, align 2 # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vld1q_s32(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <4 x i32>, ptr %0, align 4 # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vld1q_u8(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <16 x i8>, ptr %0, align 1 # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vld1q_u16(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <8 x i16>, ptr %0, align 2 # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vld1q_u32(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <4 x i32>, ptr %0, align 4 # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vld1q_z_f16(ptr noundef %base, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = call <8 x half> @llvm.masked.load.v8f16.p0(ptr align 2 %0, <8 x i1> %3, <8 x half> zeroinitializer) # | ret <8 x half> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare <8 x half> @llvm.masked.load.v8f16.p0(ptr captures(none), <8 x i1>, <8 x half>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vld1q_z_f32(ptr noundef %base, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = call <4 x float> @llvm.masked.load.v4f32.p0(ptr align 4 %0, <4 x i1> %3, <4 x float> zeroinitializer) # | ret <4 x float> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare <4 x float> @llvm.masked.load.v4f32.p0(ptr captures(none), <4 x i1>, <4 x float>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vld1q_z_s8(ptr noundef %base, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr align 1 %0, <16 x i1> %3, <16 x i8> zeroinitializer) # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare <16 x i8> @llvm.masked.load.v16i8.p0(ptr captures(none), <16 x i1>, <16 x i8>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vld1q_z_s16(ptr noundef %base, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr align 2 %0, <8 x i1> %3, <8 x i16> zeroinitializer) # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare <8 x i16> @llvm.masked.load.v8i16.p0(ptr captures(none), <8 x i1>, <8 x i16>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vld1q_z_s32(ptr noundef %base, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr align 4 %0, <4 x i1> %3, <4 x i32> zeroinitializer) # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr captures(none), <4 x i1>, <4 x i32>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vld1q_z_u8(ptr noundef %base, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr align 1 %0, <16 x i1> %3, <16 x i8> zeroinitializer) # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vld1q_z_u16(ptr noundef %base, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr align 2 %0, <8 x i1> %3, <8 x i16> zeroinitializer) # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vld1q_z_u32(ptr noundef %base, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr align 4 %0, <4 x i1> %3, <4 x i32> zeroinitializer) # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_s8(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <16 x i8>, ptr %0, align 1 # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_s16(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <8 x i8>, ptr %0, align 1 # | %2 = sext <8 x i8> %1 to <8 x i16> # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_s32(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <4 x i8>, ptr %0, align 1 # | %2 = sext <4 x i8> %1 to <4 x i32> # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_u8(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <16 x i8>, ptr %0, align 1 # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_u16(ptr noundef %base) #0 { # | entry: # | %base.addr = a # | ... # `---data was truncated (10240/50873) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005645a0bea57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005645a0be7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005645a0beacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7016333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f701638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7016333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f701631b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005645a0b8024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005645a0b80096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005645a0b64f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005645a0814176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005645a0813e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f701631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f701631d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f701631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005645a0813d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c (1375 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m1x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_i64m1x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_i64m2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_u64m1x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_u64m2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a167ec857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a167ec5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a167ec8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f25c5f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f25c5f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f25c5f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f25c5f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a167e5e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a167e5e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a167e42f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a167af2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a167af1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f25c5f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f25c5f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f25c5f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a167af1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/neon/vpaddl.c (1376 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon/vpaddl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c --check-prefixes=LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vpaddl_s8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vpaddl.i = call <4 x i16> @llvm.aarch64.neon.saddlp.v4i16.v8i8(<8 x i8> %1) # | store <4 x i16> %vpaddl.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %2, ptr %__ret.i, align 8 # | %3 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vpaddlq_s8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vpaddl.i = call <8 x i16> @llvm.aarch64.neon.saddlp.v8i16.v16i8(<16 x i8> %1) # | store <8 x i16> %vpaddl.i, ptr %ref.tmp.i, align 16 # | %2 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %2, ptr %__ret.i, align 16 # | %3 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vpaddl_s16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vpaddl.i = bitcast <8 x i8> %1 to <4 x i16> # | %vpaddl1.i = call <2 x i32> @llvm.aarch64.neon.saddlp.v2i32.v4i16(<4 x i16> %vpaddl.i) # | store <2 x i32> %vpaddl1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vpaddlq_s16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vpaddl.i = bitcast <16 x i8> %1 to <8 x i16> # | %vpaddl1.i = call <4 x i32> @llvm.aarch64.neon.saddlp.v4i32.v8i16(<8 x i16> %vpaddl.i) # | store <4 x i32> %vpaddl1.i, ptr %ref.tmp.i, align 16 # | %2 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %2, ptr %__ret.i, align 16 # | %3 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vpaddl_s32(<2 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vpaddl.i = bitcast <8 x i8> %1 to <2 x i32> # | %vpaddl1.i = call <1 x i64> @llvm.aarch64.neon.saddlp.v1i64.v2i32(<2 x i32> %vpaddl.i) # | store <1 x i64> %vpaddl1.i, ptr %ref.tmp.i, align 8 # | %2 = load <1 x i64>, ptr %ref.tmp.i, align 8 # | store <1 x i64> %2, ptr %__ret.i, align 8 # | %3 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vpaddlq_s32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vpaddl.i = bitcast <16 x i8> %1 to <4 x i32> # | %vpaddl1.i = call <2 x i64> @llvm.aarch64.neon.saddlp.v2i64.v4i32(<4 x i32> %vpaddl.i) # | store <2 x i64> %vpaddl1.i, ptr %ref.tmp.i, align 16 # | %2 = load <2 x i64>, ptr %ref.tmp.i, align 16 # | store <2 x i64> %2, ptr %__ret.i, align 16 # | %3 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vpaddl_u8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vpaddl.i = call <4 x i16> @llvm.aarch64.neon.uaddlp.v4i16.v8i8(<8 x i8> %1) # | store <4 x i16> %vpaddl.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %2, ptr %__ret.i, align 8 # | %3 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vpaddlq_u8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vpaddl.i = call <8 x i16> @llvm.aarch64.neon.uaddlp.v8i16.v16i8(<16 x i8> %1) # | store <8 x i16> %vpaddl.i, ptr %ref.tmp.i, align 16 # | %2 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %2, ptr %__ret.i, align 16 # | %3 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vpaddl_u16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vpaddl.i = bitcast <8 x i8> %1 to <4 x i16> # | %vpaddl1.i = call <2 x i32> @llvm.aarch64.neon.uaddlp.v2i32.v4i16(<4 x i16> %vpaddl.i) # | store <2 x i32> %vpaddl1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vpaddlq_u16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vpaddl.i = bitcast <16 x i8> %1 to <8 x i16> # | %vpaddl1.i = call <4 x i32> @llvm.aarch64.neon.uaddlp.v4i32.v8i16(<8 x i16> %vpaddl.i) # | store <4 x i32> %vpaddl1.i, ptr %ref.tmp.i, align 16 # | %2 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %2, ptr %__ret.i, align 16 # | %3 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vpaddl_u32(<2 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vpaddl.i = bitcast <8 x i8> %1 to <2 x i32> # | %vpaddl1.i = call <1 x i64> @llvm.aarch64.neon.uaddlp.v1i64.v2i32(<2 x i32> %vpaddl.i) # | store <1 x i64> %vpaddl1.i, ptr %ref.tmp.i, align 8 # | %2 = load <1 x i64>, ptr %ref.tmp.i, align 8 # | store <1 x i64> %2, ptr %__ret.i, align 8 # | %3 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vpaddlq_u32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vpaddl.i = bitcast <16 x i8> %1 to <4 x i32> # | %vpaddl1.i = call <2 x i64> @llvm.aarch64.neon.uaddlp.v2i64.v4i32(<4 x i32> %vpaddl.i) # | store <2 x i64> %vpaddl1.i, ptr %ref.tmp.i, align 16 # | %2 = load <2 x i64>, ptr %ref.tmp.i, align 16 # | store <2 x i64> %2, ptr %__ret.i, align 16 # | %3 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vpadal_s8(<4 x i16> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <8 x i8>, al # | ... # `---data was truncated (10240/26059) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055d578a2457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d578a21515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d578a24cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8bd961bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8bd96725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8bd961ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8bd9603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d5789ba24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d5789ba096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d57899ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d57864e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d57864de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8bd9604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8bd96050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8bd96050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d57864dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c --check-prefixes=LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c --check-prefixes=LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c (1377 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf4_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf2_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.mask.nxv2bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.mask.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m1_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c (1378 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svcreate4_s8( %x0, %x1, %x2, %x4) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | %x4.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | store %x4, ptr %x4.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = load , ptr %x4.addr, align 16 # | %4 = insertvalue { , , , } poison, %0, 0 # | %5 = insertvalue { , , , } %4, %1, 1 # | %6 = insertvalue { , , , } %5, %2, 2 # | %7 = insertvalue { , , , } %6, %3, 3 # | ret { , , , } %7 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svcreate4_s16( %x0, %x1, %x2, %x4) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | %x4.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | store %x4, ptr %x4.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = load , ptr %x4.addr, align 16 # | %4 = insertvalue { , , , } poison, %0, 0 # | %5 = insertvalue { , , , } %4, %1, 1 # | %6 = insertvalue { , , , } %5, %2, 2 # | %7 = insertvalue { , , , } %6, %3, 3 # | ret { , , , } %7 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svcreate4_s32( %x0, %x1, %x2, %x4) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | %x4.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | store %x4, ptr %x4.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = load , ptr %x4.addr, align 16 # | %4 = insertvalue { , , , } poison, %0, 0 # | %5 = insertvalue { , , , } %4, %1, 1 # | %6 = insertvalue { , , , } %5, %2, 2 # | %7 = insertvalue { , , , } %6, %3, 3 # | ret { , , , } %7 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svcreate4_s64( %x0, %x1, %x2, %x4) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | %x4.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | store %x4, ptr %x4.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = load , ptr %x4.addr, align 16 # | %4 = insertvalue { , , , } poison, %0, 0 # | %5 = insertvalue { , , , } %4, %1, 1 # | %6 = insertvalue { , , , } %5, %2, 2 # | %7 = insertvalue { , , , } %6, %3, 3 # | ret { , , , } %7 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svcreate4_u8( %x0, %x1, %x2, %x4) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | %x4.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | store %x4, ptr %x4.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = load , ptr %x4.addr, align 16 # | %4 = insertvalue { , , , } poison, %0, 0 # | %5 = insertvalue { , , , } %4, %1, 1 # | %6 = insertvalue { , , , } %5, %2, 2 # | %7 = insertvalue { , , , } %6, %3, 3 # | ret { , , , } %7 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svcreate4_u16( %x0, %x1, %x2, %x4) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | %x4.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | store %x4, ptr %x4.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = load , ptr %x4.addr, align 16 # | %4 = insertvalue { , , , } poison, %0, 0 # | %5 = insertvalue { , , , } %4, %1, 1 # | %6 = insertvalue { , , , } %5, %2, 2 # | %7 = insertvalue { , , , } %6, %3, 3 # | ret { , , , } %7 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svcreate4_u32( %x0, %x1, %x2, %x4) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | %x4.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c (1379 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf8x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_u8mf8x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_u8mf4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vect # | ... # `---data was truncated (10240/32932) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558f408a657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558f408a3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558f408a6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f19d9733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f19d978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f19d9733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f19d971b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558f4083c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558f4083c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558f40820f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558f404d0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558f404cfe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f19d971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f19d971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f19d971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558f404cfd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c (1380 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv1i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv2i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv4i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv8i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv16i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv16i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsm # | ... # `---data was truncated (10240/99585) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fbad96457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fbad961515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fbad964cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f281e61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f281e6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f281e61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f281e603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fbad8fa24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fbad8fa096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fbad8def49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fbad58e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fbad58de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f281e604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f281e6050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f281e6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fbad58dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c (1381 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16mf4_f8e4m3mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16mf4_f8e4m3mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16mf2_f8e4m3mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16mf2_f8e4m3mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m1_f8e4m3mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m1_f8e4m3mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m2_f8e4m3m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m2_f8e4m3m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m4_f8e4m3m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m4_f8e4m3m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m8_f8e4m3m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv32i8.nxv32bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv32i8.nxv32bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m8_f8e4m3m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c (1382 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f32m2x2(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c (1383 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwin # | ... # `---data was truncated (10240/95437) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564da911257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564da910f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564da9112cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9b90a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9b90aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9b90a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9b90a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564da90a824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564da90a8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564da908cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564da8d3c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564da8d3be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9b90a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9b90a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9b90a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564da8d3bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c (1384 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_u8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { targe # | ... # `---data was truncated (10240/68233) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562c0bc5957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562c0bc56515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562c0bc59cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcfbc61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcfbc6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcfbc61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcfbc603507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562c0bbef24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562c0bbef096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562c0bbd3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562c0b883176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562c0b882e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcfbc604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcfbc6050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcfbc6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562c0b882d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c (1385 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1q.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1q.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1q.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1q.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1q.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1q.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1q.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_bf16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1q.nxv8bf16(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000563b6f2d357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563b6f2d0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563b6f2d3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff656c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff656ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff656c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff656c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563b6f26924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563b6f269096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563b6f24df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563b6eefd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563b6eefce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff656c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff656c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff656c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563b6eefcd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c (1386 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005594ebc4f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005594ebc4c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005594ebc4fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fba00649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fba006a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fba00649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fba00631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005594ebbe524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005594ebbe5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005594ebbc9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005594eb879176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005594eb878e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fba00632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fba006330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fba006330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005594eb878d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c (1387 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32mf2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m1_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr # | ... # `---data was truncated (10240/14461) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056367c37c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056367c379515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056367c37ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc3ecb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc3ecb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc3ecb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc3ecb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056367c31224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056367c312096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056367c2f6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056367bfa6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056367bfa5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc3ecb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc3ecb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc3ecb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056367bfa5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c (1388 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c (1389 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, a # | ... # `---data was truncated (10240/222483) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565399d1357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000565399d10515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000565399d13cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcd37049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcd370a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcd37049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcd37031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565399ca924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000565399ca9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000565399c8df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056539993d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056539993ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcd37032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcd370330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcd370330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056539993cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c (1390 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16m1x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556f8924057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556f8923d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556f89240cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f278521bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f27852725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f278521ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2785203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556f891d624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556f891d6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556f891baf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556f88e6a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556f88e69e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2785204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f27852050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f27852050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556f88e69d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c (1391 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f39d82757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f39d824515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f39d827cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f62db333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f62db38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f62db333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f62db31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f39d7bd24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f39d7bd096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f39d7a1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f39d451176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f39d450e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f62db31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f62db31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f62db31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f39d450d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c (1392 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32mf2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m1( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m4( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c (1393 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i64m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i64.nxv1i64.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i64m1( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv1i64.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i64.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i64m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i64.nxv2i64.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i64m2( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv2i64.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i64.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i64m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i64.nxv4i64.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i64m4( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv4i64.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i64.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i64m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i64.nxv8i64.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i64m8( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv8i64.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i64.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i64m1_m( %mask, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load , ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64.i64(, , , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i64m1_m( %mask, %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | % # | ... # `---data was truncated (10240/18873) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559144bf857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559144bf5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559144bf8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9344933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f934498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9344933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f934491b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559144b8e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559144b8e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559144b72f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559144822176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559144821e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f934491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f934491d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f934491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559144821d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c (1394 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_f16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_f16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_f16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_i16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_i16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_i16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_u16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_u16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_u16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", # | ... # `---data was truncated (10240/23365) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a229dab57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a229da8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a229dabcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f00b8d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f00b8d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f00b8d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f00b8ced507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a229d4124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a229d41096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a229d25f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a2299d5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a2299d4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f00b8ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f00b8cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f00b8cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a2299d4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c (1395 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf4x7(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf2x7(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16m1x7(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16m1x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b42554957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b425546515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b425549cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7878449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f78784a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7878449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7878431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b4254df24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b4254df096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b4254c3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b425173176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b425172e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7878432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f78784330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f78784330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b425172d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c (1396 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005645dd2b657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005645dd2b3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005645dd2b6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4c50e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4c50ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4c50e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4c50e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005645dd24c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005645dd24c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005645dd230f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005645dcee0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005645dcedfe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4c50e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4c50e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4c50e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005645dcedfd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c (1397 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32mf2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32mf2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_u32mf2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_u32m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_u3 # | ... # `---data was truncated (10240/11880) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fe2732e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fe2732b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fe2732ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4c8941bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4c894725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4c8941ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4c89403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fe272c424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fe272c4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fe272a8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fe26f58176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fe26f57e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4c89404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4c894050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4c894050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fe26f57d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c (1398 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_u64m4x2_u64m4(target("riscv.vector.tuple", , 2) %src) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | store target("riscv.vector.tuple", , 2) %src, ptr %src.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %src.addr, align 8 # | %1 = call @llvm.riscv.tuple.extract.nxv4i64.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", , 2) %0, i32 1) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv4i64.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", , 2), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vset_v_u64m4_u64m4x2(target("riscv.vector.tuple", , 2) %dest, %val) #0 { # | entry: # | %dest.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %val.addr = alloca , align 8 # | store target("riscv.vector.tuple", , 2) %dest, ptr %dest.addr, align 8 # | store %val, ptr %val.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %dest.addr, align 8 # | %1 = load , ptr %val.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv32i8_2t.nxv4i64(target("riscv.vector.tuple", , 2) %0, %1, i32 1) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv32i8_2t.nxv4i64(target("riscv.vector.tuple", , 2), , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d54b3cd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d54b3ca515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d54b3cdcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5165c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5165ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5165c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5165c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d54b36324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d54b363096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d54b347f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d54aff7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d54aff6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5165c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5165c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5165c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d54aff6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c (1399 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv2f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv4f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv8f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv16f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv32f16.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv2f32.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv4f32.nxv2f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv8f32.nxv4f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwi # | ... # `---data was truncated (10240/235604) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e6a089257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e6a088f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e6a0892cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcc06f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcc06f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcc06f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcc06f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e6a082824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e6a0828096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e6a080cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e6a04bc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e6a04bbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcc06f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcc06f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcc06f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e6a04bbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c (1400 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16mf4_f8e4m3mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16mf4_f8e4m3mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16mf2_f8e4m3mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16mf2_f8e4m3mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m1_f8e4m3mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m1_f8e4m3mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m2_f8e4m3m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m2_f8e4m3m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m4_f8e4m3m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m4_f8e4m3m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | % # | ... # `---data was truncated (10240/201226) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c4e7c7057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c4e7c6d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c4e7c70cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f447c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f447c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f447c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f447c231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c4e7c0624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c4e7c06096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c4e7beaf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c4e789a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c4e7899e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f447c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f447c2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f447c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c4e7899d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c (1401 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m4( % # | ... # `---data was truncated (10240/149145) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056140101c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561401019515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056140101ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3b44e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3b44ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3b44e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3b44e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561400fb224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561400fb2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561400f96f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561400c46176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561400c45e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3b44e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3b44e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3b44e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561400c45d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c (1402 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_f64m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1f64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_f64m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2f64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_f64m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4f64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_f64m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8f64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_i64m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_i64m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_i64m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_i64m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_u64m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_u64m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_u64m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_u64m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_f64m1_m( %mask, ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align # | ... # `---data was truncated (10240/22890) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055685db5257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055685db4f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055685db52cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7d5b849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7d5b8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7d5b849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7d5b831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055685dae824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055685dae8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055685daccf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055685d77c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055685d77be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7d5b832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7d5b8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7d5b8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055685d77bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c (1403 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_i8mf4x8(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557b4412957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557b44126515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557b44129cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc9e6733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc9e678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc9e6733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc9e671b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557b440bf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557b440bf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557b440a3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557b43d53176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557b43d52e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc9e671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc9e671d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc9e671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557b43d52d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c (1404 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv1i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv2i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv4i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv8i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m1_m( %mask, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.mask.nxv1i64.nxv1i64.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m1_m( %mask, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | # | ... # `---data was truncated (10240/18925) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555ef65af57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555ef65ac515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555ef65afcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6c5d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6c5d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6c5d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6c5d431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555ef654524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555ef6545096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555ef6529f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555ef61d9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555ef61d8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6c5d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6c5d4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6c5d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555ef61d8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c (1405 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt # | ... # `---data was truncated (10240/18668) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ef5550957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ef55506515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ef55509cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efe4bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efe4bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efe4bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efe4bb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ef5549f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ef5549f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ef55483f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ef55133176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ef55132e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efe4bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efe4bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efe4bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ef55132d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c (1406 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32mf2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m1( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m4( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(, ha # | ... # `---data was truncated (10240/90685) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005561cbbce57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005561cbbcb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005561cbbcecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fef96333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fef9638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fef96333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fef9631b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005561cbb6424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005561cbb64096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005561cbb48f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005561cb7f8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005561cb7f7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fef9631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fef9631d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fef9631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005561cb7f7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c (1407 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_i8mf8x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_i8mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_i8mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_i8m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_u8mf8x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_u8mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_u8mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_u8m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_i8mf8x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | # | ... # `---data was truncated (10240/21558) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558797a3357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558797a30515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558797a33cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f61df133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f61df18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f61df133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f61df11b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005587979c924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005587979c9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005587979adf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055879765d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055879765ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f61df11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f61df11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f61df11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055879765cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c (1408 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2e # | ... # `---data was truncated (10240/253148) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055642652557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556426522515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556426525cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1f74933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1f7498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1f74933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1f7491b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005564264bb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005564264bb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055642649ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055642614f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055642614ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1f7491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1f7491d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1f7491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055642614ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c (1409 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | ... # `---data was truncated (10240/302389) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a6bf45457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a6bf451515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a6bf454cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f414ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f414ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f414ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f414ef1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a6bf3ea24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a6bf3ea096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a6bf3cef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a6bf07e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a6bf07de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f414ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f414ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f414ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a6bf07dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c (1410 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4e # | ... # `---data was truncated (10240/228857) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005638df35457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005638df351515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005638df354cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa1e2049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa1e20a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa1e2049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa1e2031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005638df2ea24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005638df2ea096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005638df2cef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005638def7e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005638def7de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa1e2032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa1e20330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa1e20330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005638def7dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c (1411 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f32m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f32m4x2(ptr noundef %base, %binde # | ... # `---data was truncated (10240/110121) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a9a3a7a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a9a3a77515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a9a3a7acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2288f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2288f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2288f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2288f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a9a3a1024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a9a3a10096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a9a39f4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a9a36a4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a9a36a3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2288f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2288f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2288f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a9a36a3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c (1412 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline # | ... # `---data was truncated (10240/95445) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b0fa34257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b0fa33f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b0fa342cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6fdc249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6fdc2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6fdc249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6fdc231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b0fa2d824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b0fa2d8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b0fa2bcf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b0f9f6c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b0f9f6be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6fdc232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6fdc2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6fdc2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b0f9f6bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c (1413 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vx_i16mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wx_i16mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.w.nxv1i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vx_i16mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wx_i16mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.w.nxv2i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c (1414 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv16i8.nxv16i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ... # `---data was truncated (10240/69831) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055951709857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559517095515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559517098cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbe05b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbe05b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbe05b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbe05b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055951702e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055951702e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559517012f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559516cc2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559516cc1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbe05b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbe05b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbe05b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559516cc1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c (1415 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf8( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf4( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf2( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8m1( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8m2( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c (1416 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf4x7_tumu( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2. # | ... # `---data was truncated (10240/18498) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562cefc7d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562cefc7a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562cefc7dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f58f7105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f58f715c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f58f7105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f58f70ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562cefc1324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562cefc13096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562cefbf7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562cef8a7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562cef8a6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f58f70eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f58f70ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f58f70ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562cef8a6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/neon-dot-product.c (1417 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon-dot-product.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +dotprod -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +dotprod -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vdot_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %c.addr = alloca <8 x i8>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | store <8 x i8> %c, ptr %c.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | %2 = load <8 x i8>, ptr %c.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | store <8 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vdot.i = bitcast <8 x i8> %3 to <2 x i32> # | %vdot1.i = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %4, <8 x i8> %5) # | store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vdotq_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | %c.addr = alloca <16 x i8>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | store <16 x i8> %c, ptr %c.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | %1 = load <16 x i8>, ptr %b.addr, align 16 # | %2 = load <16 x i8>, ptr %c.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vdot.i = bitcast <16 x i8> %3 to <4 x i32> # | %vdot1.i = call <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32> %vdot.i, <16 x i8> %4, <16 x i8> %5) # | store <4 x i32> %vdot1.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %6, ptr %__ret.i, align 16 # | %7 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vdot_s32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %c.addr = alloca <8 x i8>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | store <8 x i8> %c, ptr %c.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | %2 = load <8 x i8>, ptr %c.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | store <8 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vdot.i = bitcast <8 x i8> %3 to <2 x i32> # | %vdot1.i = call <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %4, <8 x i8> %5) # | store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vdotq_s32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | %c.addr = alloca <16 x i8>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | store <16 x i8> %c, ptr %c.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | %1 = load <16 x i8>, ptr %b.addr, align 16 # | %2 = load <16 x i8>, ptr %c.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vdot.i = bitcast <16 x i8> %3 to <4 x i32> # | %vdot1.i = call <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32> %vdot.i, <16 x i8> %4, <16 x i8> %5) # | store <4 x i32> %vdot1.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %6, ptr %__ret.i, align 16 # | %7 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vdot_lane_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %c.addr = alloca <8 x i8>, align 8 # | %__ret_831 = alloca <2 x i32>, align 8 # | %__s0_831 = alloca <2 x i32>, align 8 # | %__s1_831 = alloca <8 x i8>, align 8 # | %__s2_831 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <2 x i32>, align 8 # | %__ret = alloca <2 x i32>, align 8 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp1 = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x i32>, align 8 # | %tmp2 = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | store <8 x i8> %c, ptr %c.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__s0_831, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %1, ptr %__s1_831, align 8 # | %2 = load <8 x i8>, ptr %c.addr, align 8 # | store <8 x i8> %2, ptr %__s2_831, align 8 # | %3 = load <2 x i32>, ptr %__s0_831, align 8 # | %4 = load <8 x i8>, ptr %__s1_831, align 8 # | %5 = load <2 x i32>, ptr %__s2_831, align 8 # | store <2 x i32> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x i32> # | %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> # | store <2 x i32> %lane, ptr %ref.tmp1, align 8 # | %8 = load <2 x i32>, ptr %ref.tmp1, align 8 # | store <2 x i32> %8, ptr %__ret, align 8 # | %9 = load <2 x i32>, ptr %__ret, align 8 # | store <2 x i32> %9, ptr %tmp, align 8 # | %10 = load <2 x i32>, ptr %tmp, align 8 # | store <2 x i32> %10, ptr %ref.tmp, align 8 # | %11 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <2 x i32> %3, ptr %__p0.addr.i, align 8 # | store <8 x i8> %4, ptr %__p1.addr.i, align 8 # | store <8 x i8> %11, ptr %__p2.addr.i, align 8 # | %12 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %13 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %14 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vdot.i = bitcast <8 x i8> %12 to <2 x i32> # | %vdot1.i = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %13, <8 x i8> %14) # | store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8 # | %15 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %15, ptr %__ret.i, align 8 # | %16 = load <2 x i32>, ptr %__ret.i, align 8 # | store <2 x i32> %16, ptr %__ret_831, align 8 # | %17 = load <2 x i32>, ptr %__ret_831, align 8 # | store <2 x i32> %17, ptr %tmp2, align 8 # | %18 = load <2 x i32>, ptr %tmp2, align 8 # | ret <2 x i32> %18 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vdotq_lane_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <8 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | %c.addr = alloca <8 x i8>, align 8 # | %__ret_827 = alloca <4 x i32>, align 16 # | %__s0_827 = alloca <4 x i32>, align 16 # | %__s1_827 = alloca <16 x i8>, align 16 # | %__s2_827 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <4 x i32>, align 16 # | %__ret = alloca <4 x i32>, align 16 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp1 = alloca <16 x i8>, align 16 # | %tmp = alloca <4 x i32>, align 16 # | %tmp2 = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | store <8 x i8> %c, ptr %c.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__s0_827, align 16 # | %1 = load <16 x i8>, ptr %b.addr, align 16 # | store <16 x i8> %1, ptr %__s1_827, align 16 # | %2 = load <8 x i8>, ptr %c.addr, align 8 # | store <8 x i8> %2, ptr %__s2_827, align 8 # | %3 = load <4 x i32>, ptr %__s0_827, align 16 # | %4 = load <16 x i8>, ptr %__s1_827, align 16 # | %5 = load <2 x i32>, ptr %__s2_827, align 8 # | store <2 x i32> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__ # | ... # `---data was truncated (10240/29862) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine # | #0 0x000055a37fda857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a37fda5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a37fda8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f69db133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f69db18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f69db133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f69db11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a37fd3e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a37fd3e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a37fd22f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a37f9d2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a37f9d1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f69db11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f69db11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f69db11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a37f9d1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c (1418 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c256aa257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c256a9f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c256aa2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8a28849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8a288a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8a28849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8a28831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c256a3824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c256a38096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c256a1cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c2566cc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c2566cbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8a28832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8a288330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8a288330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c2566cbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c (1419 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f32m1x2_tu(target("riscv.vector. # | ... # `---data was truncated (10240/295525) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561e4b20757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561e4b204515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561e4b207cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4670333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f467038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4670333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f467031b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561e4b19d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561e4b19d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561e4b181f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561e4ae31176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561e4ae30e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f467031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f467031d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f467031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561e4ae30d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/neon/subtraction.c (1420 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon/subtraction.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c --check-prefixes=LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vsub_s8(<8 x i8> noundef %v1, <8 x i8> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %v1.addr = alloca <8 x i8>, align 8 # | %v2.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %v1, ptr %v1.addr, align 8 # | store <8 x i8> %v2, ptr %v2.addr, align 8 # | %0 = load <8 x i8>, ptr %v1.addr, align 8 # | %1 = load <8 x i8>, ptr %v2.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %sub.i = sub <8 x i8> %2, %3 # | store <8 x i8> %sub.i, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vsubq_s8(<16 x i8> noundef %v1, <16 x i8> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %v1.addr = alloca <16 x i8>, align 16 # | %v2.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v1, ptr %v1.addr, align 16 # | store <16 x i8> %v2, ptr %v2.addr, align 16 # | %0 = load <16 x i8>, ptr %v1.addr, align 16 # | %1 = load <16 x i8>, ptr %v2.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %sub.i = sub <16 x i8> %2, %3 # | store <16 x i8> %sub.i, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vsub_s16(<4 x i16> noundef %v1, <4 x i16> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %v1.addr = alloca <4 x i16>, align 8 # | %v2.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %v1, ptr %v1.addr, align 8 # | store <4 x i16> %v2, ptr %v2.addr, align 8 # | %0 = load <4 x i16>, ptr %v1.addr, align 8 # | %1 = load <4 x i16>, ptr %v2.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %sub.i = sub <4 x i16> %2, %3 # | store <4 x i16> %sub.i, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vsubq_s16(<8 x i16> noundef %v1, <8 x i16> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %v1.addr = alloca <8 x i16>, align 16 # | %v2.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %v1, ptr %v1.addr, align 16 # | store <8 x i16> %v2, ptr %v2.addr, align 16 # | %0 = load <8 x i16>, ptr %v1.addr, align 16 # | %1 = load <8 x i16>, ptr %v2.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | store <8 x i16> %1, ptr %__p1.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %3 = load <8 x i16>, ptr %__p1.addr.i, align 16 # | %sub.i = sub <8 x i16> %2, %3 # | store <8 x i16> %sub.i, ptr %__ret.i, align 16 # | %4 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vsub_s32(<2 x i32> noundef %v1, <2 x i32> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %v1.addr = alloca <2 x i32>, align 8 # | %v2.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %v1, ptr %v1.addr, align 8 # | store <2 x i32> %v2, ptr %v2.addr, align 8 # | %0 = load <2 x i32>, ptr %v1.addr, align 8 # | %1 = load <2 x i32>, ptr %v2.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %sub.i = sub <2 x i32> %2, %3 # | store <2 x i32> %sub.i, ptr %__ret.i, align 8 # | %4 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vsubq_s32(<4 x i32> noundef %v1, <4 x i32> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %v1.addr = alloca <4 x i32>, align 16 # | %v2.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %v1, ptr %v1.addr, align 16 # | store <4 x i32> %v2, ptr %v2.addr, align 16 # | %0 = load <4 x i32>, ptr %v1.addr, align 16 # | %1 = load <4 x i32>, ptr %v2.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | store <4 x i32> %1, ptr %__p1.addr.i, align 16 # | %2 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %3 = load <4 x i32>, ptr %__p1.addr.i, align 16 # | %sub.i = sub <4 x i32> %2, %3 # | store <4 x i32> %sub.i, ptr %__ret.i, align 16 # | %4 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vsub_s64(<1 x i64> noundef %v1, <1 x i64> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %v1.addr = alloca <1 x i64>, align 8 # | %v2.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %v1, ptr %v1.addr, align 8 # | store <1 x i64> %v2, ptr %v2.addr, align 8 # | %0 = load <1 x i64>, ptr %v1.addr, align 8 # | %1 = load <1 x i64>, ptr %v2.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <1 x i64>, ptr %__p0.addr.i, align 8 # | %3 = load <1 x i64>, ptr %__p1.addr.i, align 8 # | %sub.i = sub <1 x i64> %2, %3 # | store <1 x i64> %sub.i, ptr %__ret.i, align 8 # | %4 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vsubq_s64(<2 x i64> noundef %v1, <2 x i64> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__p1.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %v1.addr = alloca <2 x i64>, align 16 # | %v2.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %v1, ptr %v1.addr, align 16 # | store <2 x i64> %v2, ptr %v2.addr, align 16 # | %0 = load <2 x i64>, ptr %v1.addr, align 16 # | %1 = load <2 x i64>, ptr %v2.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | store <2 x i64> %1, ptr %__p1.addr.i, align 16 # | %2 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %3 = load <2 x i64>, ptr %__p1.addr.i, align 16 # | %sub.i = sub <2 x i64> %2, %3 # | store <2 x i64> %sub.i, ptr %__ret.i, align 16 # | %4 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vsub_u8(<8 x i8> noundef %v1, <8 x i8> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %v1.addr = alloca <8 x i8>, align 8 # | %v2.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %v1, ptr %v1.addr, align 8 # | store <8 x i8> %v2, ptr %v2.addr, align 8 # | %0 = load <8 x i8>, ptr %v1.addr, align 8 # | %1 = load <8 x i8>, ptr %v2.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %sub.i = sub <8 x i8> %2, %3 # | store <8 x i8> %sub.i, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vsub_u16(<4 x i16> noundef %v1, <4 x i16> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %v1.addr = alloca <4 x i16>, align 8 # | %v2.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %v1, ptr %v1.addr, align 8 # | store <4 x i16> %v2, ptr %v2.addr, align 8 # | %0 = load <4 x i16>, ptr %v1.addr, align 8 # | %1 = load <4 x i16>, ptr %v2.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %sub.i = sub <4 x i16> %2, %3 # | store <4 x i16> %sub.i, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vsub_u32(<2 x i32> noundef %v1, <2 x i32> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %v1.addr = alloca <2 x i32>, align 8 # | %v2.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %v1, ptr %v1.addr, align 8 # | store <2 x i32> %v2, ptr %v2.addr, align 8 # | %0 = load <2 x i32>, ptr %v1.addr, align 8 # | %1 = load <2 x i32>, ptr %v2.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %sub.i = sub <2 x i32> %2, %3 # | store <2 x i32> %sub.i, ptr %__ret.i, align 8 # | %4 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vsub_u64(<1 x i64> noundef %v1, <1 x i64> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %v1.addr = alloca <1 x i64>, align 8 # | %v2.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %v1, ptr %v1.addr, align 8 # | # | ... # `---data was truncated (10240/170019) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine # | #0 0x000055b455b9757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b455b94515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b455b97cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8d40f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8d40f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8d40f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8d40f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b455b2d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b455b2d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b455b11f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b4557c1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b4557c0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8d40f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8d40f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8d40f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b4557c0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c --check-prefixes=LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c --check-prefixes=LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c (1421 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv8bf16.nxv8f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv8bf16.nxv8f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv16bf16.nxv16f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.ris # | ... # `---data was truncated (10240/18562) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559278a6957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559278a66515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559278a69cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdb49a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdb49aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdb49a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdb49a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005592789ff24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005592789ff096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005592789e3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559278693176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559278692e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fdb49a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdb49a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdb49a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559278692d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c (1422 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf4( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf2( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m1( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m2( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m4( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m8( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf4_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf2_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.mask.nxv2bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.mask.nxv2bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m1_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.mask.nxv4bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.mask.nxv4bf16.bf16.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c (1423 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f64m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 # | ... # `---data was truncated (10240/99178) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dd91e4057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055dd91e3d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055dd91e40cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7285f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7285f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7285f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7285f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dd91dd624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055dd91dd6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055dd91dbaf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055dd91a6a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055dd91a69e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7285f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7285f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7285f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dd91a69d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c (1424 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c (1425 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ffbbf0957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ffbbf06515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ffbbf09cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5421533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f542158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5421533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f542151b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ffbbe9f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ffbbe9f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ffbbe83f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ffbbb33176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ffbbb32e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f542151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f542151d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f542151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ffbbb32d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c (1426 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_f16mf4x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_f16mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_f16m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_i16mf4x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_i16mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_i16m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_u16mf4x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_u16mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_u16m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_f16mf4x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsse # | ... # `---data was truncated (10240/20441) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a914efb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a914ef8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a914efbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb03c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb03c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb03c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb03c51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a914e9124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a914e91096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a914e75f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a914b25176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a914b24e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb03c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb03c51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb03c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a914b24d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c (1427 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m1_bf16m2( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv8bf16.nxv4bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m1_bf16m4( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv16bf16.nxv4bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m2_bf16m4( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv16bf16.nxv8bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv8bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m1_bf16m8( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m2_bf16m8( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32bf16.nxv8bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv8bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m4_bf16m8( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32bf16.nxv16bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv16bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vset_v_bf16mf4_bf16mf4x2(target("riscv.vector.tuple", , 2) %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store target("riscv.vector.tuple", , 2) %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load target("riscv.vector.tuple", , 2), ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_2t.nxv1bf16(target("riscv.vector.tuple", , 2) %0, %1, i32 0) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_2t.nxv1bf16(target("riscv.vector.tuple", , 2), , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vset_v_bf16mf4_bf16mf4x3(target("riscv.vector.tuple", , 3) %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store target("riscv.vector.tuple", , 3) %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load target("riscv.vector.tuple", , 3), ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_3t.nxv1bf16(target("riscv.vector.tuple", , 3) %0, %1, i32 0) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_3t.nxv1bf16(target("riscv.vector.tuple", , 3), , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vset_v_bf16mf4_bf16mf4x4(target("riscv.vector.tuple", , 4) %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store target("riscv.vector.tuple", , 4) %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load target("riscv.vector.tuple", , 4), ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c (1428 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 5) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 5) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("risc # | ... # `---data was truncated (10240/21103) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c10f8a757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c10f8a4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c10f8a7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2b38b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2b38b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2b38b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2b38b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c10f83d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c10f83d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c10f821f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c10f4d1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c10f4d0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2b38b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2b38b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2b38b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c10f4d0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c (1429 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m1_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv1i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv2i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m4_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv4i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m8_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv8i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m1_tum( %mask, %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c (1430 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16mf4_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16mf2_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m1_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m2_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m4_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m8_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32mf2_tu( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64( %0, i16 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(, i16, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32m1_tu( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64( %0, i16 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(, i16, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32m2_tu( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.a # | ... # `---data was truncated (10240/73947) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005643192e257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005643192df515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005643192e2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9916933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f991698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9916933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f991691b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056431927824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564319278096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056431925cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564318f0c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564318f0be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f991691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f991691d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f991691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564318f0bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c (1431 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559ce495a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559ce4957515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559ce495acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb6ba21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb6ba2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb6ba21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb6ba203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559ce48f024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559ce48f0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559ce48d4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559ce4584176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559ce4583e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb6ba204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb6ba2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb6ba2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559ce4583d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c (1432 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bad639257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bad638f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bad6392cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa025105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa02515c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa025105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa0250ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bad632824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bad6328096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bad630cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bad5fbc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bad5fbbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa0250eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa0250ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa0250ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bad5fbbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c (1433 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretur # | ... # `---data was truncated (10240/20190) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561082ed257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561082ecf515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561082ed2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1c10505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1c1055c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1c10505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1c104ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561082e6824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561082e68096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561082e4cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561082afc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561082afbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1c104eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1c104ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1c104ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561082afbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c (1434 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16mf4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16mf2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m1_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m8_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f32mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f32m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f32m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv2f32.nxv4f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c (1435 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf4( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf2( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m1( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m2( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m4( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m8( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf4_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf2_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.mask.nxv2bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.mask.nxv2bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m1_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.mask.nxv4bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsli # | ... # `---data was truncated (10240/14908) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055784454b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557844548515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055784454bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3331d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3331d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3331d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3331d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005578444e124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005578444e1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005578444c5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557844175176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557844174e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3331d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3331d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3331d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557844174d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c (1436 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vx_u16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wv_u16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wx_u16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.w.nxv1i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vx_u16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wv_u16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wx_u16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.w.nxv2i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.ad # | ... # `---data was truncated (10240/306619) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ee882b657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ee882b3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ee882b6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f86d9249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f86d92a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f86d9249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f86d9231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ee8824c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ee8824c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ee88230f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ee87ee0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ee87edfe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f86d9232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f86d92330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f86d92330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ee87edfd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c (1437 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8mf8x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8mf4x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_u8mf8x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_u8mf4x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_u8mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_u8m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8mf8x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8mf4x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, pt # | ... # `---data was truncated (10240/18980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b09846757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b098464515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b098467cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f764c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f764c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f764c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f764c11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b0983fd24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b0983fd096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b0983e1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b098091176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b098090e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f764c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f764c11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f764c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b098090d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c (1438 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 # | ... # `---data was truncated (10240/126436) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bca900557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bca9002515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bca9005cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7205533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f720558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7205533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f720551b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bca8f9b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bca8f9b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bca8f7ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bca8c2f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bca8c2ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f720551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f720551d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f720551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bca8c2ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c (1439 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.ad # | ... # `---data was truncated (10240/225647) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005603042c057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005603042bd515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005603042c0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd396733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd39678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd396733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd39671b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056030425624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560304256096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056030423af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560303eea176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560303ee9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd39671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd39671d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd39671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560303ee9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c (1440 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m1_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv1i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv2i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m4_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv4i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m8_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv8i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m1_tum( %mask, %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , alig # | ... # `---data was truncated (10240/41669) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562bcb83a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562bcb837515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562bcb83acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8e1d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8e1d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8e1d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8e1d11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562bcb7d024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562bcb7d0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562bcb7b4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562bcb464176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562bcb463e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8e1d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8e1d11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8e1d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562bcb463d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c (1441 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056099cdc257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056099cdbf515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056099cdc2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3942f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3942f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3942f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3942f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056099cd5824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056099cd58096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056099cd3cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056099c9ec176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056099c9ebe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3942f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3942f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3942f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056099c9ebd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmldav.c (1442 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmldav.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 0, i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.vmldava.v16i8(i32, i32, i32, i32, <16 x i8>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load <8 x i16>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 0, i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.vmldava.v8i16(i32, i32, i32, i32, <8 x i16>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load <4 x i32>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 0, i32 0, i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.vmldava.v4i32(i32, i32, i32, i32, <4 x i32>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_u8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 1, i32 0, i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_u16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load <8 x i16>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 1, i32 0, i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_u32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load <4 x i32>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 1, i32 0, i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaxq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 0, i32 1, i32 %0, <16 x i8> %1, <16 x i8> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaxq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load <8 x i16>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 0, i32 1, i32 %0, <8 x i16> %1, <8 x i16> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaxq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load <4 x i32>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 0, i32 0, i32 1, i32 %0, <4 x i32> %1, <4 x i32> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 1, i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load <8 x i16>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 1, i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load <4 x i32>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 0, i32 1, i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaxq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 1, i32 1, i32 %0, <16 x i8> %1, <16 x i8> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaxq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load <8 x i16>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 1, i32 1, i32 %0, <8 x i16> %1, <8 x i16> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaxq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr # | ... # `---data was truncated (10240/44315) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000561b33f9c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561b33f99515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561b33f9ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f041b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f041b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f041b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f041b11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561b33f3224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561b33f32096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561b33f16f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561b33bc6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561b33bc5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f041b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f041b11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f041b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561b33bc5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c (1443 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16mf4( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv1f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16mf2( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv2f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m1( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv4f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m2( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv8f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv8f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m4( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv16f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv16f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m8( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv32f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv32f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f32mf2( %op1, float noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv1f32.f32.i64( poison, %0, float %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1f32.f32.i64(, , float, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f32m1( %op1, float noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv2f32.f32.i64( poison, %0, float %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv2f32.f32.i64(, , float, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f32m2( %op1, float noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %mask.addr = alloca , align # | ... # `---data was truncated (10240/19041) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557f6794857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557f67945515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557f67948cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f262cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f262cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f262cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f262cd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557f678de24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557f678de096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557f678c2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557f67572176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557f67571e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f262cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f262cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f262cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557f67571d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c (1444 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv16bf16.nxv16bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c (1445 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16mf4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16mf2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m1_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m8_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f32mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f32m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f32m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv2f32.nxv4f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c (1446 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), p # | ... # `---data was truncated (10240/87316) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557890cdc57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557890cd9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557890cdccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa658f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa658f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa658f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa658f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557890c7224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557890c72096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557890c56f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557890906176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557890905e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa658f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa658f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa658f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557890905d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c (1447 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.v.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8mf8_tu( %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i8, ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.x.nxv1i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv1i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.v.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8mf4_tu( %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i8, ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.x.nxv2i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv2i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.v.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8mf2_tu( %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i8, ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.x.nxv4i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv4i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.v.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8m1_tu( %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i8, ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.x.nxv8i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv8i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.v.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8m2_tu( %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i8, ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.x.nxv16i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv16i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = l # | ... # `---data was truncated (10240/134736) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056202a74357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056202a740515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056202a743cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f076b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f076b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f076b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f076b51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056202a6d924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056202a6d9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056202a6bdf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056202a36d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056202a36ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f076b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f076b51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f076b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056202a36cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c (1448 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32mf2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m1( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m4( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m8( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32mf2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m1_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_l # | ... # `---data was truncated (10240/13585) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055807358857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558073585515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558073588cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9883849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f98838a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9883849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9883831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055807351e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055807351e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558073502f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005580731b2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005580731b1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9883832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f98838330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f98838330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005580731b1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c (1449 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c430d4457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c430d41515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c430d44cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f034f41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f034f4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f034f41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f034f403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c430cda24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c430cda096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c430cbef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c43096e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c43096de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f034f404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f034f4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f034f4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c43096dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c (1450 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32m2x3_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c (1451 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | # | ... # `---data was truncated (10240/81507) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005595da9a557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005595da9a2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005595da9a5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f99bc733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f99bc78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f99bc733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f99bc71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005595da93b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005595da93b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005595da91ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005595da5cf176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005595da5cee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f99bc71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f99bc71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f99bc71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005595da5ced81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c (1452 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16mf4x5(ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16mf2x5(ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16m1x5(ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16m1x5_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056442bfd157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056442bfce515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056442bfd1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f49f9733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f49f978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f49f9733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f49f971b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056442bf6724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056442bf67096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056442bf4bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056442bbfb176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056442bbfae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f49f971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f49f971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f49f971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056442bbfad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c (1453 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16mf4_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16mf2_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m1_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m2_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m4_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m8_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32mf2_tu( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64( %0, i16 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(, i16, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32m1_tu( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64( %0, i16 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(, i16, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32m2_tu( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, pt # | ... # `---data was truncated (10240/73955) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055919e1ac57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055919e1a9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055919e1accbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1b7de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1b7dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1b7de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1b7de31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055919e14224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055919e142096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055919e126f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055919ddd6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055919ddd5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1b7de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1b7de330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1b7de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055919ddd5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c (1454 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = # | ... # `---data was truncated (10240/125488) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dc37f5e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055dc37f5b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055dc37f5ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f269cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f269cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f269cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f269cf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dc37ef424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055dc37ef4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055dc37ed8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055dc37b88176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055dc37b87e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f269cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f269cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f269cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dc37b87d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c (1455 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0. # | ... # `---data was truncated (10240/82975) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005619b562657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005619b5623515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005619b5626cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f14fe333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f14fe38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f14fe333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f14fe31b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005619b55bc24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005619b55bc096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005619b55a0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005619b5250176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005619b524fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f14fe31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f14fe31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f14fe31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005619b524fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c (1456 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_u32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_u32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c (1457 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_i64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_u64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_f64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 7) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_i64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 7) %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_u64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple # | ... # `---data was truncated (10240/20903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555ae245957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555ae2456515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555ae2459cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fad6a049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fad6a0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fad6a049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fad6a031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555ae23ef24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555ae23ef096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555ae23d3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555ae2083176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555ae2082e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fad6a032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fad6a0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fad6a0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555ae2082d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c (1458 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_f64m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_f64m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_i64m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_i64m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_u64m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_u64m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_f64m1x4_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_f64m2x4_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_i64m1x4_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_i64m2x4_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tu # | ... # `---data was truncated (10240/14044) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e35b74257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e35b73f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e35b742cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa062849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa0628a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa062849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa062831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e35b6d824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e35b6d8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e35b6bcf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e35b36c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e35b36be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa062832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa0628330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa0628330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e35b36bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/idup.c (1459 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/idup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vidupq_n_u8(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call { <16 x i8>, i32 } @llvm.arm.mve.vidup.v16i8(i32 %0, i32 4) # | %2 = extractvalue { <16 x i8>, i32 } %1, 0 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <16 x i8>, i32 } @llvm.arm.mve.vidup.v16i8(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vidupq_n_u16(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call { <8 x i16>, i32 } @llvm.arm.mve.vidup.v8i16(i32 %0, i32 1) # | %2 = extractvalue { <8 x i16>, i32 } %1, 0 # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <8 x i16>, i32 } @llvm.arm.mve.vidup.v8i16(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vidupq_n_u32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32 %0, i32 4) # | %2 = extractvalue { <4 x i32>, i32 } %1, 0 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vddupq_n_u8(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call { <16 x i8>, i32 } @llvm.arm.mve.vddup.v16i8(i32 %0, i32 2) # | %2 = extractvalue { <16 x i8>, i32 } %1, 0 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <16 x i8>, i32 } @llvm.arm.mve.vddup.v16i8(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vddupq_n_u16(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call { <8 x i16>, i32 } @llvm.arm.mve.vddup.v8i16(i32 %0, i32 4) # | %2 = extractvalue { <8 x i16>, i32 } %1, 0 # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <8 x i16>, i32 } @llvm.arm.mve.vddup.v8i16(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vddupq_n_u32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call { <4 x i32>, i32 } @llvm.arm.mve.vddup.v4i32(i32 %0, i32 2) # | %2 = extractvalue { <4 x i32>, i32 } %1, 0 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <4 x i32>, i32 } @llvm.arm.mve.vddup.v4i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_viwdupq_n_u8(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call { <16 x i8>, i32 } @llvm.arm.mve.viwdup.v16i8(i32 %0, i32 %1, i32 4) # | %3 = extractvalue { <16 x i8>, i32 } %2, 0 # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <16 x i8>, i32 } @llvm.arm.mve.viwdup.v16i8(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_viwdupq_n_u16(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call { <8 x i16>, i32 } @llvm.arm.mve.viwdup.v8i16(i32 %0, i32 %1, i32 2) # | %3 = extractvalue { <8 x i16>, i32 } %2, 0 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <8 x i16>, i32 } @llvm.arm.mve.viwdup.v8i16(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_viwdupq_n_u32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call { <4 x i32>, i32 } @llvm.arm.mve.viwdup.v4i32(i32 %0, i32 %1, i32 8) # | %3 = extractvalue { <4 x i32>, i32 } %2, 0 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <4 x i32>, i32 } @llvm.arm.mve.viwdup.v4i32(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdwdupq_n_u8(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call { <16 x i8>, i32 } @llvm.arm.mve.vdwdup.v16i8(i32 %0, i32 %1, i32 4) # | %3 = extractvalue { <16 x i8>, i32 } %2, 0 # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <16 x i8>, i32 } @llvm.arm.mve.vdwdup.v16i8(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdwdupq_n_u16(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call { <8 x i16>, i32 } @llvm.arm.mve.vdwdup.v8i16(i32 %0, i32 %1, i32 8) # | %3 = extractvalue { <8 x i16>, i32 } %2, 0 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <8 x i16>, i32 } @llvm.arm.mve.vdwdup.v8i16(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vdwdupq_n_u32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vdwdup.v4i32(i32 %0, i32 %1, i32 1) # | %3 = extractvalue { <4 x i32>, i32 } %2, 0 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <4 x i32>, i32 } @llvm.arm.mve.vdwdup.v4i32(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vidupq_wb_u8(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 4 # | store ptr %a, ptr %a.addr, align 4 # | %0 = load ptr, ptr %a.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = call { <16 x i8>, i32 } @llvm.arm.mve.vidup.v16i8(i32 %1, i32 8) # | %3 = extractvalue { <16 x i8>, i32 } %2, 1 # | store i32 %3, ptr %0, align 4 # | %4 = extractvalue { <16 x i8>, i32 } %2, 0 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vidupq_wb_u16(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 4 # | store ptr %a, ptr %a.addr, align 4 # | %0 = load ptr, ptr %a.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = call { <8 x i16>, i32 } @llvm.arm.mve.vidup.v8i16(i32 %1, i32 1) # | %3 = extractvalue { <8 x i16>, i32 } %2, 1 # | store i32 %3, ptr %0, align 4 # | %4 = extractvalue { <8 x i16>, i32 } %2, 0 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vidupq_wb_u32(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 4 # | store ptr %a, ptr %a.addr, align 4 # | %0 = load ptr, ptr %a.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32 %1, i32 4) # | %3 = extractvalue { <4 x i32>, i32 } %2, 1 # | store i32 %3, ptr %0, align 4 # | %4 = extractvalue { <4 x i32>, i32 } %2, 0 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vddupq_wb_u8(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 4 # | store ptr %a, ptr %a.addr, align 4 # | %0 = load ptr, ptr %a.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = call { <16 x i8>, i32 } @llvm.arm.mve.vddup.v16i8(i32 %1, i32 2) # | %3 = extractvalue { <16 x i8>, i32 } %2, 1 # | store i32 %3, ptr %0, align 4 # | %4 = extractvalue { <16 x i8>, i32 } %2, 0 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vddupq_wb_u16(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 4 # | store ptr %a, ptr %a.addr, align 4 # | %0 = load ptr, ptr %a.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = call { <8 x i16>, i32 } @llvm.arm.mve.vddup.v8i16(i32 %1, i32 8) # | %3 = extractvalue { <8 x i16>, i32 } %2, 1 # | store i32 %3, ptr %0, align 4 # | %4 = extractvalue { <8 x i16>, i32 } %2, 0 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vddupq_wb_u32(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 4 # | store ptr %a, ptr %a.addr, align 4 # | %0 = load ptr, ptr %a.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vddup.v4i32(i32 %1, i32 2) # | %3 = extractvalue { <4 x i32>, i32 } %2, 1 # | store i32 %3, ptr %0, align 4 # | %4 = extractvalue { <4 x i32>, i32 } %2, 0 # | ret <4 x i3 # | ... # `---data was truncated (10240/57708) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bd3d16f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bd3d16c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bd3d16fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f97f5933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f97f598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f97f5933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f97f591b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bd3d10524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bd3d105096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bd3d0e9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bd3cd99176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bd3cd98e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f97f591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f97f591d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f97f591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bd3cd98d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c (1460 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf8( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf4( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf2( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m1( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m2( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m4( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m8( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv64i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16mf4( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv1i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16mf2( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv2i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16m1( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv4i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16m2( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c (1461 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretu # | ... # `---data was truncated (10240/113047) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e6bf70857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e6bf705515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e6bf708cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f774cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f774cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f774cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f774cd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e6bf69e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e6bf69e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e6bf682f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e6bf332176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e6bf331e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f774cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f774cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f774cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e6bf331d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c (1462 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16mf4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16mf2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv16f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv32f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv32f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_i16mf4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1i16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_i16mf2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2i16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c (1463 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vx_i16mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wx_i16mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.w.nxv1i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vx_i16mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wx_i16mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.w.nxv2i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c (1464 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c (1465 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_i64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_i64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_u64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_u64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m1x4_tum( %mask, target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", # | ... # `---data was truncated (10240/40860) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005563f0d6e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005563f0d6b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005563f0d6ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe93e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe93e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe93e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe93e11b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005563f0d0424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005563f0d04096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005563f0ce8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005563f0998176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005563f0997e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe93e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe93e11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe93e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005563f0997d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c (1466 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget4_b_0( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3) #0 { # | entry: # | %tuple = alloca { , , , }, align 2 # | %tuple.addr = alloca { , , , }, align 2 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 2 # | %tuple1 = load { , , , }, ptr %tuple, align 2 # | store { , , , } %tuple1, ptr %tuple.addr, align 2 # | %4 = load { , , , }, ptr %tuple.addr, align 2 # | %5 = extractvalue { , , , } %4, 0 # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget4_b_1( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3) #0 { # | entry: # | %tuple = alloca { , , , }, align 2 # | %tuple.addr = alloca { , , , }, align 2 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 2 # | %tuple1 = load { , , , }, ptr %tuple, align 2 # | store { , , , } %tuple1, ptr %tuple.addr, align 2 # | %4 = load { , , , }, ptr %tuple.addr, align 2 # | %5 = extractvalue { , , , } %4, 1 # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget4_b_3( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3) #0 { # | entry: # | %tuple = alloca { , , , }, align 2 # | %tuple.addr = alloca { , , , }, align 2 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 2 # | %tuple1 = load { , , , }, ptr %tuple, align 2 # | store { , , , } %tuple1, ptr %tuple.addr, align 2 # | %4 = load { , , , }, ptr %tuple.addr, align 2 # | %5 = extractvalue { , , , } %4, 3 # | ret %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000556c73cdb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556c73cd8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556c73cdbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbf5b21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbf5b2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbf5b21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbf5b203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556c73c7124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556c73c71096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556c73c55f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556c73905176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556c73904e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbf5b204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbf5b2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbf5b2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556c73904d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c (1467 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055efdb3d757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055efdb3d4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055efdb3d7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa067449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa0674a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa067449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa067431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055efdb36d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055efdb36d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055efdb351f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055efdb001176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055efdb000e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa067432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa0674330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa0674330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055efdb000d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c (1468 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none # | ... # `---data was truncated (10240/61673) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055da76c7857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055da76c75515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055da76c78cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff0bb533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff0bb58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff0bb533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff0bb51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055da76c0e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055da76c0e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055da76bf2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055da768a2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055da768a1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff0bb51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff0bb51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff0bb51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055da768a1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c (1469 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 2) %6 # | # | ... # `---data was truncated (10240/34641) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055889ec9b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055889ec98515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055889ec9bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb389049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb3890a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb389049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb389031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055889ec3124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055889ec31096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055889ec15f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055889e8c5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055889e8c4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb389032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb3890330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb3890330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055889e8c4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c (1470 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor # | ... # `---data was truncated (10240/61929) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d86d17657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d86d173515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d86d176cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb3adf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb3adf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb3adf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb3adf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d86d10c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d86d10c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d86d0f0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d86cda0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d86cd9fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb3adf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb3adf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb3adf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d86cd9fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c (1471 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557ccfa7657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557ccfa73515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557ccfa76cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9807849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f98078a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9807849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9807831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557ccfa0c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557ccfa0c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557ccf9f0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557ccf6a0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557ccf69fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9807832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f98078330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f98078330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557ccf69fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c (1472 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv32i8.nxv32i8.i64( %0, # | ... # `---data was truncated (10240/95081) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056522fd2557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056522fd22515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056522fd25cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4c09649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4c096a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4c09649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4c09631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056522fcbb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056522fcbb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056522fc9ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056522f94f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056522f94ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4c09632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4c096330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4c096330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056522f94ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c (1473 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv1i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv2i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv4i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv8i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m1_m( %mask, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.mask.nxv1i64.nxv1i64.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m1_m( %mask, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, a # | ... # `---data was truncated (10240/18875) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bb9b69457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bb9b691515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bb9b694cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0c8821bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0c882725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0c8821ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0c88203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bb9b62a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bb9b62a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bb9b60ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bb9b2be176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bb9b2bde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0c88204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0c882050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0c882050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bb9b2bdd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c (1474 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv8i8.nxv8i8.i64(, , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c (1475 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_i32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_i32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_u32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_u32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32mf2x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, # | ... # `---data was truncated (10240/40726) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c767d1c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c767d19515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c767d1ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4a1d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4a1d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4a1d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4a1d831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c767cb224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c767cb2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c767c96f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c767946176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c767945e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4a1d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4a1d8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4a1d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c767945d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c (1476 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv1i64.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv2i64.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv4i64.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv8i64.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m8_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m1_tumu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c (1477 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m8_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captur # | ... # `---data was truncated (10240/30617) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b74d55957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b74d556515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b74d559cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe57ea1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe57ea725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe57ea1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe57ea03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b74d4ef24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b74d4ef096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b74d4d3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b74d183176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b74d182e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe57ea04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe57ea050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe57ea050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b74d182d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c (1478 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16mf4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055df40cc357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055df40cc0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055df40cc3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcb26049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcb260a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcb26049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcb26031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055df40c5924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055df40c59096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055df40c3df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055df408ed176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055df408ece93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcb26032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcb260330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcb260330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055df408ecd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c (1479 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv4i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv4i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv8i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv8i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv16i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv16i32.i64(, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d65003c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d650039515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d65003ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0c51049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0c510a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0c51049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0c51031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d64ffd224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d64ffd2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d64ffb6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d64fc66176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d64fc65e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0c51032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0c510330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0c510330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d64fc65d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c (1480 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf8_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf4_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf2_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m1_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m2_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv16i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m4_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv32i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m8_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv64i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16mf4_tu( %maskedoff, %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i16, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv1i16.i16.i64( %0, %1, i16 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16mf2_tu( %maskedoff, %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | # | ... # `---data was truncated (10240/211223) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561ded67a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561ded677515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561ded67acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0b6d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0b6d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0b6d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0b6d51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561ded61024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561ded610096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561ded5f4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561ded2a4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561ded2a3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0b6d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0b6d51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0b6d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561ded2a3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c (1481 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563a5923357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563a59230515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563a59233cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f26ccc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f26ccca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f26ccc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f26ccc31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563a591c924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563a591c9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563a591adf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563a58e5d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563a58e5ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f26ccc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f26ccc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f26ccc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563a58e5cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c (1482 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nx # | ... # `---data was truncated (10240/18660) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e46ebc657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e46ebc3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e46ebc6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa9a2449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa9a24a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa9a2449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa9a2431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e46eb5c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e46eb5c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e46eb40f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e46e7f0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e46e7efe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa9a2432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa9a24330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa9a24330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e46e7efd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c (1483 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056307b40a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056307b407515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056307b40acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc328533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc32858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc328533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc32851b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056307b3a024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056307b3a0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056307b384f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056307b034176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056307b033e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc32851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc32851d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc32851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056307b033d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c (1484 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf8_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf4_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf2_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m1_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m2_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m4_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m8_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u16mf4_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u16mf2_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u16m1_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, pt # | ... # `---data was truncated (10240/52733) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559ab972657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559ab9723515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559ab9726cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fea9eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fea9eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fea9eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fea9eb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559ab96bc24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559ab96bc096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559ab96a0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559ab9350176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559ab934fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fea9eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fea9eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fea9eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559ab934fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c (1485 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_f32mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_f32mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv1f32.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_f32m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_f32m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv2f32.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_f32m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_f32m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, a # | ... # `---data was truncated (10240/151903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bd6d7aa57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bd6d7a7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bd6d7aacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1421249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f14212a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1421249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1421231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bd6d74024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bd6d740096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bd6d724f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bd6d3d4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bd6d3d3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1421232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f14212330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f14212330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bd6d3d3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c (1486 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv1i32.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv2i32.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv4i32.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv8i32.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv16i32.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv1i64.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv2i64.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv4i64.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv8i64.nxv8i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 4 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call # | ... # `---data was truncated (10240/39914) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055de4c7c757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055de4c7c4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055de4c7c7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f749d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f749d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f749d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f749d431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055de4c75d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055de4c75d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055de4c741f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055de4c3f1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055de4c3f0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f749d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f749d4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f749d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055de4c3f0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c (1487 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f64m1x3(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c (1488 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf8x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf4x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m1x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m4x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv32i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv32i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_u8mf8x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_u8mf4x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 nounde # | ... # `---data was truncated (10240/16083) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005620728a357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005620728a0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005620728a3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f737c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f737c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f737c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f737c831507 abort ./stdlib/abort.c:85:3 # | #7 0x000056207283924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562072839096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056207281df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005620724cd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005620724cce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f737c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f737c8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f737c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005620724ccd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c (1489 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m8_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Fu # | ... # `---data was truncated (10240/30423) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c3af86157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c3af85e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c3af861cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f93d0533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f93d058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f93d0533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f93d051b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c3af7f724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c3af7f7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c3af7dbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c3af48b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c3af48ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f93d051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f93d051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f93d051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c3af48ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c (1490 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_f32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_f32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_f32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_i32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_i32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_i32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_u32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_u32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_u32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.v # | ... # `---data was truncated (10240/23413) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556364f7b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556364f78515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556364f7bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff5d7905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff5d795c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff5d7905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff5d78ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556364f1124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556364f11096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556364ef5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556364ba5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556364ba4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff5d78eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff5d78ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff5d78ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556364ba4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c (1491 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_vfmad_lane_f64(double noundef %a, double noundef %b, <1 x double> noundef %c) #0 { # | entry: # | %a.addr = alloca double, align 8 # | %b.addr = alloca double, align 8 # | %c.addr = alloca <1 x double>, align 8 # | %__ret = alloca double, align 8 # | %__s0 = alloca double, align 8 # | %__s1 = alloca double, align 8 # | %__s2 = alloca <1 x double>, align 8 # | %ref.tmp = alloca double, align 8 # | %tmp = alloca double, align 8 # | store double %a, ptr %a.addr, align 8 # | store double %b, ptr %b.addr, align 8 # | store <1 x double> %c, ptr %c.addr, align 8 # | %0 = load double, ptr %a.addr, align 8 # | store double %0, ptr %__s0, align 8 # | %1 = load double, ptr %b.addr, align 8 # | store double %1, ptr %__s1, align 8 # | %2 = load <1 x double>, ptr %c.addr, align 8 # | store <1 x double> %2, ptr %__s2, align 8 # | %3 = load double, ptr %__s0, align 8 # | %4 = load double, ptr %__s1, align 8 # | %5 = load <1 x double>, ptr %__s2, align 8 # | %extract = extractelement <1 x double> %5, i32 0 # | %6 = call double @llvm.fma.f64(double %4, double %extract, double %3) # | store double %6, ptr %ref.tmp, align 8 # | %7 = load double, ptr %ref.tmp, align 8 # | store double %7, ptr %__ret, align 8 # | %8 = load double, ptr %__ret, align 8 # | store double %8, ptr %tmp, align 8 # | %9 = load double, ptr %tmp, align 8 # | ret double %9 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare double @llvm.fma.f64(double, double, double) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_vfmad_laneq_f64(double noundef %a, double noundef %b, <2 x double> noundef %c) #0 { # | entry: # | %a.addr = alloca double, align 8 # | %b.addr = alloca double, align 8 # | %c.addr = alloca <2 x double>, align 16 # | %__ret = alloca double, align 8 # | %__s0 = alloca double, align 8 # | %__s1 = alloca double, align 8 # | %__s2 = alloca <2 x double>, align 16 # | %ref.tmp = alloca double, align 8 # | %tmp = alloca double, align 8 # | store double %a, ptr %a.addr, align 8 # | store double %b, ptr %b.addr, align 8 # | store <2 x double> %c, ptr %c.addr, align 16 # | %0 = load double, ptr %a.addr, align 8 # | store double %0, ptr %__s0, align 8 # | %1 = load double, ptr %b.addr, align 8 # | store double %1, ptr %__s1, align 8 # | %2 = load <2 x double>, ptr %c.addr, align 16 # | store <2 x double> %2, ptr %__s2, align 16 # | %3 = load double, ptr %__s0, align 8 # | %4 = load double, ptr %__s1, align 8 # | %5 = load <2 x double>, ptr %__s2, align 16 # | %extract = extractelement <2 x double> %5, i32 1 # | %6 = call double @llvm.fma.f64(double %4, double %extract, double %3) # | store double %6, ptr %ref.tmp, align 8 # | %7 = load double, ptr %ref.tmp, align 8 # | store double %7, ptr %__ret, align 8 # | %8 = load double, ptr %__ret, align 8 # | store double %8, ptr %tmp, align 8 # | %9 = load double, ptr %tmp, align 8 # | ret double %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vfmss_lane_f32(float noundef %a, float noundef %b, <2 x float> noundef %c) #0 { # | entry: # | %a.addr = alloca float, align 4 # | %b.addr = alloca float, align 4 # | %c.addr = alloca <2 x float>, align 8 # | %__ret_443 = alloca float, align 4 # | %__s0_443 = alloca float, align 4 # | %__s1_443 = alloca float, align 4 # | %__s2_443 = alloca <2 x float>, align 8 # | %__ret = alloca float, align 4 # | %__s0 = alloca float, align 4 # | %__s1 = alloca float, align 4 # | %__s2 = alloca <2 x float>, align 8 # | %ref.tmp = alloca float, align 4 # | %tmp = alloca float, align 4 # | %tmp1 = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | store float %b, ptr %b.addr, align 4 # | store <2 x float> %c, ptr %c.addr, align 8 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__s0_443, align 4 # | %1 = load float, ptr %b.addr, align 4 # | store float %1, ptr %__s1_443, align 4 # | %2 = load <2 x float>, ptr %c.addr, align 8 # | store <2 x float> %2, ptr %__s2_443, align 8 # | %3 = load float, ptr %__s0_443, align 4 # | store float %3, ptr %__s0, align 4 # | %4 = load float, ptr %__s1_443, align 4 # | %fneg = fneg float %4 # | store float %fneg, ptr %__s1, align 4 # | %5 = load <2 x float>, ptr %__s2_443, align 8 # | store <2 x float> %5, ptr %__s2, align 8 # | %6 = load float, ptr %__s0, align 4 # | %7 = load float, ptr %__s1, align 4 # | %8 = load <2 x float>, ptr %__s2, align 8 # | %extract = extractelement <2 x float> %8, i32 1 # | %9 = call float @llvm.fma.f32(float %7, float %extract, float %6) # | store float %9, ptr %ref.tmp, align 4 # | %10 = load float, ptr %ref.tmp, align 4 # | store float %10, ptr %__ret, align 4 # | %11 = load float, ptr %__ret, align 4 # | store float %11, ptr %tmp, align 4 # | %12 = load float, ptr %tmp, align 4 # | store float %12, ptr %__ret_443, align 4 # | %13 = load float, ptr %__ret_443, align 4 # | store float %13, ptr %tmp1, align 4 # | %14 = load float, ptr %tmp1, align 4 # | ret float %14 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare float @llvm.fma.f32(float, float, float) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vfma_lane_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %v) #0 { # | entry: # | %a.addr = alloca <1 x double>, align 8 # | %b.addr = alloca <1 x double>, align 8 # | %v.addr = alloca <1 x double>, align 8 # | %__ret = alloca <1 x double>, align 8 # | %__s0 = alloca <1 x double>, align 8 # | %__s1 = alloca <1 x double>, align 8 # | %__s2 = alloca <1 x double>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | store <1 x double> %b, ptr %b.addr, align 8 # | store <1 x double> %v, ptr %v.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__s0, align 8 # | %1 = load <1 x double>, ptr %b.addr, align 8 # | store <1 x double> %1, ptr %__s1, align 8 # | %2 = load <1 x double>, ptr %v.addr, align 8 # | store <1 x double> %2, ptr %__s2, align 8 # | %3 = load <8 x i8>, ptr %__s0, align 8 # | %4 = load <8 x i8>, ptr %__s1, align 8 # | %5 = load <8 x i8>, ptr %__s2, align 8 # | %6 = bitcast <8 x i8> %5 to <1 x double> # | %lane = shufflevector <1 x double> %6, <1 x double> %6, <1 x i32> zeroinitializer # | %fmla = bitcast <8 x i8> %4 to <1 x double> # | %fmla1 = bitcast <8 x i8> %3 to <1 x double> # | %fmla2 = call <1 x double> @llvm.fma.v1f64(<1 x double> %fmla, <1 x double> %lane, <1 x double> %fmla1) # | store <1 x double> %fmla2, ptr %ref.tmp, align 8 # | %7 = load <1 x double>, ptr %ref.tmp, align 8 # | store <1 x double> %7, ptr %__ret, align 8 # | %8 = load <1 x double>, ptr %__ret, align 8 # | store <1 x double> %8, ptr %tmp, align 8 # | %9 = load <1 x double>, ptr %tmp, align 8 # | ret <1 x double> %9 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <1 x double> @llvm.fma.v1f64(<1 x double>, <1 x double>, <1 x double>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vfms_lane_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %v) #0 { # | entry: # | %a.addr = alloca <1 x double>, align 8 # | %b.addr = alloca <1 x double>, align 8 # | %v.addr = alloca <1 x double>, align 8 # | %__ret_449 = alloca <1 x double>, align 8 # | %__s0_449 = alloca <1 x double>, align 8 # | %__s1_449 = alloca <1 x double>, align 8 # | %__s2_449 = alloca <1 x double>, align 8 # | %__ret = alloca <1 x double>, align 8 # | %__s0 = alloca <1 x double>, align 8 # | %__s1 = alloca <1 x double>, align 8 # | %__s2 = alloca <1 x double>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <1 x double>, align 8 # | %tmp3 = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | store <1 x double> %b, ptr %b.addr, align 8 # | store <1 x double> %v, ptr %v.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__s0_449, align 8 # | %1 = load <1 x double>, ptr %b.addr, align 8 # | store <1 x double> %1, ptr %__s1_449, align 8 # | %2 = load <1 x double>, ptr %v.addr, align 8 # | store <1 x double> %2, ptr %__s2_449, align 8 # | %3 = load <1 x double>, ptr %__s0_449, align 8 # | store <1 x double> %3, ptr %__s0, align 8 # | %4 = load <1 x double>, ptr %__s1_449, align 8 # | %fneg = fneg <1 x double> %4 # | store <1 x double> %fneg, ptr %__s1, align 8 # | %5 = load <1 x double>, ptr %__s2_449, align 8 # | store <1 x double> %5, ptr %__s2, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = load <8 x i8>, ptr %__s1, align 8 # | %8 = load <8 x i8>, ptr %__s2, align 8 # | %9 = bitcast <8 x i8> %8 to <1 x double> # | %lane = shufflevector <1 x double> %9, <1 x double> %9, <1 x i32> zeroinitializer # | %fmla = bitcast <8 x i8> %7 to <1 x double> # | %fmla1 = bitcast <8 x i8> %6 to <1 x double> # | %fmla2 = call <1 x double> @llvm.fma.v1f64(<1 x double> %fmla, <1 x double> %lane, <1 x double> %fmla1) # | store <1 x double> %fmla2, ptr %ref.tmp, align 8 # | %10 = load <1 x double>, ptr %ref.tmp, align 8 # | store <1 x double> %10, ptr %__ret, align 8 # | %11 = load <1 x double>, ptr %__ret, align 8 # | store <1 x double> %11, ptr %tmp, align 8 # | %12 = load <1 x double>, ptr %tmp, align 8 # | store <1 x double> %12, ptr %__ret_449, align 8 # | %13 = load <1 x double>, ptr %__ret_449, align 8 # | store <1 x double> %13, ptr %tmp3, align 8 # | %14 = load <1 x double>, ptr %tmp3, align 8 # | ret <1 x double> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vfms_laneq_f64(<1 x double> noundef %a, <1 x double> noundef %b, <2 x double> noundef %v) #0 { # | entry: # | %a.addr = alloca <1 x double>, align 8 # | %b.addr = alloca <1 x double>, align 8 # | %v.addr = alloca <2 x double>, align 16 # | %__ret_460 = alloca <1 x double>, align 8 # | %__s0_460 = alloca <1 x double>, align 8 # | %__s1_460 = alloca <1 x double>, align 8 # | %__s2_460 = alloca <2 x double>, align 16 # | %__ret = alloca <1 x double>, align 8 # | %_ # | ... # `---data was truncated (10240/12799) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055a2e271f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a2e271c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a2e271fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0e69a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0e69aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0e69a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0e69a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a2e26b524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a2e26b5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a2e2699f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a2e2349176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a2e2348e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0e69a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0e69a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0e69a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a2e2348d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c (1492 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1f32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2f32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4f32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8f32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv16f32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2i32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4i32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8i32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c (1493 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32mf2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1f32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2f32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4f32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8f32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv16f32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32mf2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1i32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2i32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4i32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.risc # | ... # `---data was truncated (10240/78164) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005613634ad57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005613634aa515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005613634adcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0ddf133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0ddf18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0ddf133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0ddf11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056136344324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561363443096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561363427f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005613630d7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005613630d6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0ddf11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0ddf11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0ddf11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005613630d6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c (1494 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf4_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m1_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m4_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m8_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf4_tum( %mask, %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load float, ptr %op2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf2_tum( %mask, %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load float, ptr %op2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64( %1, %2, float %3, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c (1495 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e50f25b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e50f258515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e50f25bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f12da449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f12da4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f12da449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f12da431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e50f1f124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e50f1f1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e50f1d5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e50ee85176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e50ee84e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f12da432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f12da4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f12da4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e50ee84d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem.c (1496 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vmuls_lane_f32(float noundef %a, <2 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca float, align 4 # | %b.addr = alloca <2 x float>, align 8 # | %__ret_571 = alloca float, align 4 # | %__s0_571 = alloca float, align 4 # | %__s1_571 = alloca <2 x float>, align 8 # | %__ret = alloca float, align 4 # | %__s0 = alloca <2 x float>, align 8 # | %ref.tmp = alloca float, align 4 # | %tmp = alloca float, align 4 # | %tmp1 = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | store <2 x float> %b, ptr %b.addr, align 8 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__s0_571, align 4 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | store <2 x float> %1, ptr %__s1_571, align 8 # | %2 = load float, ptr %__s0_571, align 4 # | %3 = load <2 x float>, ptr %__s1_571, align 8 # | store <2 x float> %3, ptr %__s0, align 8 # | %4 = load <2 x float>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x float> %4, i32 1 # | store float %vget_lane, ptr %ref.tmp, align 4 # | %5 = load float, ptr %ref.tmp, align 4 # | store float %5, ptr %__ret, align 4 # | %6 = load float, ptr %__ret, align 4 # | store float %6, ptr %tmp, align 4 # | %7 = load float, ptr %tmp, align 4 # | %mul = fmul float %2, %7 # | store float %mul, ptr %__ret_571, align 4 # | %8 = load float, ptr %__ret_571, align 4 # | store float %8, ptr %tmp1, align 4 # | %9 = load float, ptr %tmp1, align 4 # | ret float %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_vmuld_lane_f64(double noundef %a, <1 x double> noundef %b) #0 { # | entry: # | %a.addr = alloca double, align 8 # | %b.addr = alloca <1 x double>, align 8 # | %__ret_570 = alloca double, align 8 # | %__s0_570 = alloca double, align 8 # | %__s1_570 = alloca <1 x double>, align 8 # | %__ret = alloca double, align 8 # | %__s0 = alloca <1 x double>, align 8 # | %ref.tmp = alloca double, align 8 # | %tmp = alloca double, align 8 # | %tmp1 = alloca double, align 8 # | store double %a, ptr %a.addr, align 8 # | store <1 x double> %b, ptr %b.addr, align 8 # | %0 = load double, ptr %a.addr, align 8 # | store double %0, ptr %__s0_570, align 8 # | %1 = load <1 x double>, ptr %b.addr, align 8 # | store <1 x double> %1, ptr %__s1_570, align 8 # | %2 = load double, ptr %__s0_570, align 8 # | %3 = load <1 x double>, ptr %__s1_570, align 8 # | store <1 x double> %3, ptr %__s0, align 8 # | %4 = load <1 x double>, ptr %__s0, align 8 # | %vget_lane = extractelement <1 x double> %4, i32 0 # | store double %vget_lane, ptr %ref.tmp, align 8 # | %5 = load double, ptr %ref.tmp, align 8 # | store double %5, ptr %__ret, align 8 # | %6 = load double, ptr %__ret, align 8 # | store double %6, ptr %tmp, align 8 # | %7 = load double, ptr %tmp, align 8 # | %mul = fmul double %2, %7 # | store double %mul, ptr %__ret_570, align 8 # | %8 = load double, ptr %__ret_570, align 8 # | store double %8, ptr %tmp1, align 8 # | %9 = load double, ptr %tmp1, align 8 # | ret double %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vmuls_laneq_f32(float noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca float, align 4 # | %b.addr = alloca <4 x float>, align 16 # | %__ret_577 = alloca float, align 4 # | %__s0_577 = alloca float, align 4 # | %__s1_577 = alloca <4 x float>, align 16 # | %__ret = alloca float, align 4 # | %__s0 = alloca <4 x float>, align 16 # | %ref.tmp = alloca float, align 4 # | %tmp = alloca float, align 4 # | %tmp1 = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | store <4 x float> %b, ptr %b.addr, align 16 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__s0_577, align 4 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | store <4 x float> %1, ptr %__s1_577, align 16 # | %2 = load float, ptr %__s0_577, align 4 # | %3 = load <4 x float>, ptr %__s1_577, align 16 # | store <4 x float> %3, ptr %__s0, align 16 # | %4 = load <4 x float>, ptr %__s0, align 16 # | %vgetq_lane = extractelement <4 x float> %4, i32 3 # | store float %vgetq_lane, ptr %ref.tmp, align 4 # | %5 = load float, ptr %ref.tmp, align 4 # | store float %5, ptr %__ret, align 4 # | %6 = load float, ptr %__ret, align 4 # | store float %6, ptr %tmp, align 4 # | %7 = load float, ptr %tmp, align 4 # | %mul = fmul float %2, %7 # | store float %mul, ptr %__ret_577, align 4 # | %8 = load float, ptr %__ret_577, align 4 # | store float %8, ptr %tmp1, align 4 # | %9 = load float, ptr %tmp1, align 4 # | ret float %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_vmuld_laneq_f64(double noundef %a, <2 x double> noundef %b) #0 { # | entry: # | %a.addr = alloca double, align 8 # | %b.addr = alloca <2 x double>, align 16 # | %__ret_575 = alloca double, align 8 # | %__s0_575 = alloca double, align 8 # | %__s1_575 = alloca <2 x double>, align 16 # | %__ret = alloca double, align 8 # | %__s0 = alloca <2 x double>, align 16 # | %ref.tmp = alloca double, align 8 # | %tmp = alloca double, align 8 # | %tmp1 = alloca double, align 8 # | store double %a, ptr %a.addr, align 8 # | store <2 x double> %b, ptr %b.addr, align 16 # | %0 = load double, ptr %a.addr, align 8 # | store double %0, ptr %__s0_575, align 8 # | %1 = load <2 x double>, ptr %b.addr, align 16 # | store <2 x double> %1, ptr %__s1_575, align 16 # | %2 = load double, ptr %__s0_575, align 8 # | %3 = load <2 x double>, ptr %__s1_575, align 16 # | store <2 x double> %3, ptr %__s0, align 16 # | %4 = load <2 x double>, ptr %__s0, align 16 # | %vgetq_lane = extractelement <2 x double> %4, i32 1 # | store double %vgetq_lane, ptr %ref.tmp, align 8 # | %5 = load double, ptr %ref.tmp, align 8 # | store double %5, ptr %__ret, align 8 # | %6 = load double, ptr %__ret, align 8 # | store double %6, ptr %tmp, align 8 # | %7 = load double, ptr %tmp, align 8 # | %mul = fmul double %2, %7 # | store double %mul, ptr %__ret_575, align 8 # | %8 = load double, ptr %__ret_575, align 8 # | store double %8, ptr %tmp1, align 8 # | %9 = load double, ptr %tmp1, align 8 # | ret double %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vmul_n_f64(<1 x double> noundef %a, double noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <1 x double>, align 8 # | %__p1.addr.i = alloca double, align 8 # | %__ret.i = alloca <1 x double>, align 8 # | %ref.tmp.i = alloca <1 x double>, align 8 # | %a.addr = alloca <1 x double>, align 8 # | %b.addr = alloca double, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | store double %b, ptr %b.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | %1 = load double, ptr %b.addr, align 8 # | store <1 x double> %0, ptr %__p0.addr.i, align 8 # | store double %1, ptr %__p1.addr.i, align 8 # | %2 = load <1 x double>, ptr %__p0.addr.i, align 8 # | %3 = load double, ptr %__p1.addr.i, align 8 # | %4 = bitcast <1 x double> %2 to double # | %5 = fmul double %4, %3 # | store double %5, ptr %ref.tmp.i, align 8 # | %6 = load <1 x double>, ptr %ref.tmp.i, align 8 # | store <1 x double> %6, ptr %__ret.i, align 8 # | %7 = load <1 x double>, ptr %__ret.i, align 8 # | ret <1 x double> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vmulxs_lane_f32(float noundef %a, <2 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca float, align 4 # | %__p1.addr.i = alloca float, align 4 # | %__ret.i = alloca float, align 4 # | %ref.tmp.i = alloca float, align 4 # | %a.addr = alloca float, align 4 # | %b.addr = alloca <2 x float>, align 8 # | %__ret_626 = alloca float, align 4 # | %__s0_626 = alloca float, align 4 # | %__s1_626 = alloca <2 x float>, align 8 # | %__ret = alloca float, align 4 # | %__s0 = alloca <2 x float>, align 8 # | %ref.tmp = alloca float, align 4 # | %tmp = alloca float, align 4 # | %tmp1 = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | store <2 x float> %b, ptr %b.addr, align 8 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__s0_626, align 4 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | store <2 x float> %1, ptr %__s1_626, align 8 # | %2 = load float, ptr %__s0_626, align 4 # | %3 = load <2 x float>, ptr %__s1_626, align 8 # | store <2 x float> %3, ptr %__s0, align 8 # | %4 = load <2 x float>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x float> %4, i32 1 # | store float %vget_lane, ptr %ref.tmp, align 4 # | %5 = load float, ptr %ref.tmp, align 4 # | store float %5, ptr %__ret, align 4 # | %6 = load float, ptr %__ret, align 4 # | store float %6, ptr %tmp, align 4 # | %7 = load float, ptr %tmp, align 4 # | store float %2, ptr %__p0.addr.i, align 4 # | store float %7, ptr %__p1.addr.i, align 4 # | %8 = load float, ptr %__p0.addr.i, align 4 # | %9 = load float, ptr %__p1.addr.i, align 4 # | %vmulxs_f32.i = call float @llvm.aarch64.neon.fmulx.f32(float %8, float %9) # | store float %vmulxs_f32.i, ptr %ref.tmp.i, align 4 # | %10 = load float, ptr %ref.tmp.i, align 4 # | store float %10, ptr %__ret.i, align 4 # | %11 = load float, ptr %__ret.i, align 4 # | store float %11, ptr %__ret_626, align 4 # | %12 = load float, ptr %__ret_626, align 4 # | store float %12, ptr %tmp1, align 4 # | %13 = load float, ptr %tmp1, align 4 # | ret float %13 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vmulxs_laneq_f32(float noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca float, align 4 # | %__p1.addr.i = alloca float, align 4 # | %__ret.i = alloca float, align 4 # | %ref.tmp.i = alloca float, align 4 # | %a.addr = alloca float, align 4 # | %b.addr = alloca <4 x float>, align 16 # | %__ret_636 = alloca float, align 4 # | %__s0_636 = alloca float, align 4 # | %__s1_636 = alloca <4 x float>, align 16 # | %__ret = alloca float, align 4 # | %__s0 = alloca <4 x float>, align 16 # | %ref.tmp = alloca float, align 4 # | %tmp = alloca float, align 4 # | %tmp1 = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | store <4 x float> %b, ptr %b.addr, align 16 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__s0_636, align 4 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | store <4 x float> %1, ptr %__s1_636, align 16 # | %2 = load float, ptr %__s0_636, align 4 # | %3 = load <4 x float>, ptr %__s1_636, align 16 # | store <4 x float> %3, ptr % # | ... # `---data was truncated (10240/74804) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000056304760d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056304760a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056304760dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2f55849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2f558a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2f55849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2f55831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005630475a324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005630475a3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563047587f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563047237176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563047236e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2f55832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2f558330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2f558330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563047236d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c (1497 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32mf2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m1x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m4x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32mf2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32m1x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32m2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv. # | ... # `---data was truncated (10240/17879) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561ecb40f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561ecb40c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561ecb40fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff371c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff371ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff371c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff371c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561ecb3a524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561ecb3a5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561ecb389f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561ecb039176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561ecb038e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff371c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff371c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff371c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561ecb038d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c (1498 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16m2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.ad # | ... # `---data was truncated (10240/150649) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556a753e857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556a753e5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556a753e8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f470bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f470bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f470bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f470bf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556a7537e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556a7537e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556a75362f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556a75012176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556a75011e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f470bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f470bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f470bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556a75011d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c (1499 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16mf4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b403e2357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b403e20515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b403e23cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa41e81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa41e8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa41e81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa41e803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b403db924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b403db9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b403d9df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b403a4d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b403a4ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa41e804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa41e8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa41e8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b403a4cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c (1500 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv # | ... # `---data was truncated (10240/53726) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005561f66d957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005561f66d6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005561f66d9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbca3249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbca32a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbca3249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbca3231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005561f666f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005561f666f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005561f6653f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005561f6303176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005561f6302e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbca3232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbca32330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbca32330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005561f6302d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c (1501 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f32m2x2(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c (1502 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf8x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf4x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv16i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv16i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8mf8x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8mf4x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8mf2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl. # | ... # `---data was truncated (10240/13557) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005624d62fb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005624d62f8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005624d62fbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f389e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f389e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f389e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f389e631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005624d629124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005624d6291096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005624d6275f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005624d5f25176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005624d5f24e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f389e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f389e6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f389e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005624d5f24d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c (1503 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretu # | ... # `---data was truncated (10240/113047) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558daf2c257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558daf2bf515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558daf2c2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8bef849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8bef8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8bef849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8bef831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558daf25824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558daf258096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558daf23cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558daeeec176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558daeeebe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8bef832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8bef8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8bef8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558daeeebd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c (1504 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m4_tu( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c (1505 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf8_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf4_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8m1_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %v # | ... # `---data was truncated (10240/222307) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559ecdadc57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559ecdad9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559ecdadccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa9ff41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa9ff4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa9ff41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa9ff403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559ecda7224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559ecda72096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559ecda56f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559ecd706176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559ecd705e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa9ff404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa9ff4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa9ff4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559ecd705d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c (1506 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_s8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.compact.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.compact.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_s16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.compact.nxv8i16( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.compact.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_u8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.compact.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_u16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.compact.nxv8i16( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_mf8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.compact.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_f16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.compact.nxv8f16( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.compact.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_bf16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.compact.nxv8bf16( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.compact.nxv8bf16(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2p2" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055ad78efc57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ad78ef9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ad78efccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6770649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f67706a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6770649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6770631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ad78e9224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ad78e92096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ad78e76f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ad78b26176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ad78b25e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6770632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f67706330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f67706330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ad78b25d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c (1507 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m1( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m8( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf4_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf2_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m1_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.mask.nxv4f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.mask.nxv4f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m2_m( %mask, %op1, fl # | ... # `---data was truncated (10240/25099) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005594fa2f757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005594fa2f4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005594fa2f7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff215533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff21558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff215533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff21551b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005594fa28d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005594fa28d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005594fa271f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005594f9f21176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005594f9f20e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff21551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff21551d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff21551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005594f9f20d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c (1508 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv1i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv1i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv2i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv2i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv4i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv4i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv8i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv8i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/226585) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056037c7bb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056037c7b8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056037c7bbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f64c1849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f64c18a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f64c1849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f64c1831507 abort ./stdlib/abort.c:85:3 # | #7 0x000056037c75124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056037c751096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056037c735f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056037c3e5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056037c3e4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f64c1832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f64c18330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f64c18330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056037c3e4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c (1509 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +v8.5a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +v8.5a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_rint32zf(float noundef %a) #0 { # | entry: # | %__a.addr.i = alloca float, align 4 # | %a.addr = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__a.addr.i, align 4 # | %1 = load float, ptr %__a.addr.i, align 4 # | %frint32z.i = call float @llvm.aarch64.frint32z.f32(float %1) # | ret float %frint32z.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_rint32z(double noundef %a) #0 { # | entry: # | %__a.addr.i = alloca double, align 8 # | %a.addr = alloca double, align 8 # | store double %a, ptr %a.addr, align 8 # | %0 = load double, ptr %a.addr, align 8 # | store double %0, ptr %__a.addr.i, align 8 # | %1 = load double, ptr %__a.addr.i, align 8 # | %frint32z.i = call double @llvm.aarch64.frint32z.f64(double %1) # | ret double %frint32z.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_rint64zf(float noundef %a) #0 { # | entry: # | %__a.addr.i = alloca float, align 4 # | %a.addr = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__a.addr.i, align 4 # | %1 = load float, ptr %__a.addr.i, align 4 # | %frint64z.i = call float @llvm.aarch64.frint64z.f32(float %1) # | ret float %frint64z.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_rint64z(double noundef %a) #0 { # | entry: # | %__a.addr.i = alloca double, align 8 # | %a.addr = alloca double, align 8 # | store double %a, ptr %a.addr, align 8 # | %0 = load double, ptr %a.addr, align 8 # | store double %0, ptr %__a.addr.i, align 8 # | %1 = load double, ptr %__a.addr.i, align 8 # | %frint64z.i = call double @llvm.aarch64.frint64z.f64(double %1) # | ret double %frint64z.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_rint32xf(float noundef %a) #0 { # | entry: # | %__a.addr.i = alloca float, align 4 # | %a.addr = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__a.addr.i, align 4 # | %1 = load float, ptr %__a.addr.i, align 4 # | %frint32x.i = call float @llvm.aarch64.frint32x.f32(float %1) # | ret float %frint32x.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_rint32x(double noundef %a) #0 { # | entry: # | %__a.addr.i = alloca double, align 8 # | %a.addr = alloca double, align 8 # | store double %a, ptr %a.addr, align 8 # | %0 = load double, ptr %a.addr, align 8 # | store double %0, ptr %__a.addr.i, align 8 # | %1 = load double, ptr %__a.addr.i, align 8 # | %frint32x.i = call double @llvm.aarch64.frint32x.f64(double %1) # | ret double %frint32x.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_rint64xf(float noundef %a) #0 { # | entry: # | %__a.addr.i = alloca float, align 4 # | %a.addr = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__a.addr.i, align 4 # | %1 = load float, ptr %__a.addr.i, align 4 # | %frint64x.i = call float @llvm.aarch64.frint64x.f32(float %1) # | ret float %frint64x.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_rint64x(double noundef %a) #0 { # | entry: # | %__a.addr.i = alloca double, align 8 # | %a.addr = alloca double, align 8 # | store double %a, ptr %a.addr, align 8 # | %0 = load double, ptr %a.addr, align 8 # | store double %0, ptr %__a.addr.i, align 8 # | %1 = load double, ptr %__a.addr.i, align 8 # | %frint64x.i = call double @llvm.aarch64.frint64x.f64(double %1) # | ret double %frint64x.i # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.aarch64.frint32z.f32(float) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.aarch64.frint32z.f64(double) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.aarch64.frint64z.f32(float) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.aarch64.frint64z.f64(double) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.aarch64.frint32x.f32(float) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.aarch64.frint32x.f64(double) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.aarch64.frint64x.f32(float) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.aarch64.frint64x.f64(double) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+jsconv,+lse,+neon,+pauth,+predres,+ras,+rcpc,+rdm,+sb,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8a" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005601ca1c357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005601ca1c0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005601ca1c3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2b6d01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2b6d0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2b6d01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2b6d003507 abort ./stdlib/abort.c:85:3 # | #7 0x00005601ca15924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005601ca159096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005601ca13df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005601c9ded176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005601c9dece93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2b6d004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2b6d0050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2b6d0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005601c9decd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c (1510 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, ali # | ... # `---data was truncated (10240/14621) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e8945a157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e89459e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e8945a1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efede533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efede58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efede533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efede51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e89453724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e894537096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e89451bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e8941cb176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e8941cae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efede51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efede51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efede51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e8941cad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c (1511 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svsetffr() #0 { # | entry: # | call void @llvm.aarch64.sve.setffr() # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.sve.setffr() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005642bc59957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005642bc596515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005642bc599cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f814b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f814b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f814b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f814b631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005642bc52f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005642bc52f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005642bc513f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005642bc1c3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005642bc1c2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f814b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f814b6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f814b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005642bc1c2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c (1512 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/284336) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559304c8257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559304c7f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559304c82cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3d54c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3d54ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3d54c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3d54c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559304c1824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559304c18096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559304bfcf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005593048ac176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005593048abe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3d54c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3d54c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3d54c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005593048abd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu (1513 of 27911) ******************** TEST 'Clang :: CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -o - # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu # RUN: at line 6 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple spirv64-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK-SPIRV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple spirv64-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -o - # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK-SPIRV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu # RUN: at line 7 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -disable-O0-optnone -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2 | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu --check-prefixes=OPT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -disable-O0-optnone -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu" # | target datalayout = "e-m:e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-p10:32:32-p11:32:32-p12:32:32-p13:32:32-p14:32:32-p15:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9" # | target triple = "amdgpu-amd-amdhsa" # | # | %struct.S = type { ptr, ptr } # | %struct.T = type { [2 x ptr] } # | %struct.SS = type { ptr } # | # | @__hip_cuid_ = addrspace(1) global i8 0 # | @llvm.compiler.used = appending addrspace(1) global [1 x ptr] [ptr addrspacecast (ptr addrspace(1) @__hip_cuid_ to ptr)], section "llvm.metadata" # | # | ; Function Attrs: convergent mustprogress noinline norecurse nounwind # | define dso_local amdgpu_kernel void @_Z7kernel1Pi(ptr addrspace(1) noundef %x.coerce) #0 { # | entry: # | %x = alloca ptr, align 8, addrspace(5) # | %x.addr = alloca ptr, align 8, addrspace(5) # | %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr # | store ptr addrspace(1) %x.coerce, ptr addrspace(5) %x, align 8 # | %x1 = load ptr, ptr addrspace(5) %x, align 8 # | store ptr %x1, ptr %x.addr.ascast, align 8 # | %0 = load ptr, ptr %x.addr.ascast, align 8 # | %arrayidx = getelementptr inbounds i32, ptr %0, i64 0 # | %1 = load i32, ptr %arrayidx, align 4 # | %inc = add nsw i32 %1, 1 # | store i32 %inc, ptr %arrayidx, align 4 # | ret void # | } # | # | ; Function Attrs: convergent mustprogress noinline norecurse nounwind # | define dso_local amdgpu_kernel void @_Z7kernel2Ri(ptr addrspace(1) noundef nonnull align 4 dereferenceable(4) %x.coerce) #0 { # | entry: # | %x = alloca ptr, align 8, addrspace(5) # | %x.addr = alloca ptr, align 8, addrspace(5) # | %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr # | store ptr addrspace(1) %x.coerce, ptr addrspace(5) %x, align 8 # | %x1 = load ptr, ptr addrspace(5) %x, align 8 # | store ptr %x1, ptr %x.addr.ascast, align 8 # | %0 = load ptr, ptr %x.addr.ascast, align 8, !nonnull !3, !align !4 # | %1 = load i32, ptr %0, align 4 # | %inc = add nsw i32 %1, 1 # | store i32 %inc, ptr %0, align 4 # | ret void # | } # | # | ; Function Attrs: convergent mustprogress noinline norecurse nounwind # | define dso_local amdgpu_kernel void @_Z7kernel3PU3AS2iPU3AS1i(ptr addrspace(2) noundef %x, ptr addrspace(1) noundef %y) #0 { # | entry: # | %x.addr = alloca ptr addrspace(2), align 8, addrspace(5) # | %y.addr = alloca ptr addrspace(1), align 8, addrspace(5) # | %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr # | %y.addr.ascast = addrspacecast ptr addrspace(5) %y.addr to ptr # | store ptr addrspace(2) %x, ptr %x.addr.ascast, align 8 # | store ptr addrspace(1) %y, ptr %y.addr.ascast, align 8 # | %0 = load ptr addrspace(2), ptr %x.addr.ascast, align 8 # | %arrayidx = getelementptr inbounds i32, ptr addrspace(2) %0, i64 0 # | %1 = load i32, ptr addrspace(2) %arrayidx, align 4 # | %2 = load ptr addrspace(1), ptr %y.addr.ascast, align 8 # | %arrayidx1 = getelementptr inbounds i32, ptr addrspace(1) %2, i64 0 # | store i32 %1, ptr addrspace(1) %arrayidx1, align 4 # | ret void # | } # | # | ; Function Attrs: convergent mustprogress noinline nounwind # | define dso_local void @_Z4funcPi(ptr noundef %x) #1 { # | entry: # | %x.addr = alloca ptr, align 8, addrspace(5) # | %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr # | store ptr %x, ptr %x.addr.ascast, align 8 # | %0 = load ptr, ptr %x.addr.ascast, align 8 # | %arrayidx = getelementptr inbounds i32, ptr %0, i64 0 # | %1 = load i32, ptr %arrayidx, align 4 # | %inc = add nsw i32 %1, 1 # | store i32 %inc, ptr %arrayidx, align 4 # | ret void # | } # | # | ; Function Attrs: convergent mustprogress noinline norecurse nounwind # | define dso_local amdgpu_kernel void @_Z7kernel41S(ptr addrspace(4) noundef byref(%struct.S) align 8 %0) #0 { # | entry: # | %s = alloca %struct.S, align 8, addrspace(5) # | call void @llvm.memcpy.p5.p4.i64(ptr addrspace(5) align 8 %s, ptr addrspace(4) align 8 %0, i64 16, i1 false) # | %s.ascast = addrspacecast ptr addrspace(5) %s to ptr # | %x = getelementptr inbounds nuw %struct.S, ptr %s.ascast, i32 0, i32 0 # | %1 = load ptr, ptr %x, align 8 # | %arrayidx = getelementptr inbounds i32, ptr %1, i64 0 # | %2 = load i32, ptr %arrayidx, align 4 # | %inc = add nsw i32 %2, 1 # | store i32 %inc, ptr %arrayidx, align 4 # | %y = getelementptr inbounds nuw %struct.S, ptr %s.ascast, i32 0, i32 1 # | %3 = load ptr, ptr %y, align 8 # | %arrayidx1 = getelementptr inbounds float, ptr %3, i64 0 # | %4 = load float, ptr %arrayidx1, align 4 # | %add = fadd contract float %4, 1.000000e+00 # | store float %add, ptr %arrayidx1, align 4 # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.memcpy.p5.p4.i64(ptr addrspace(5) noalias writeonly captures(none), ptr addrspace(4) noalias readonly captures(none), i64, i1 immarg) #2 # | # | ; Function Attrs: convergent mustprogress noinline norecurse nounwind # | define dso_local amdgpu_kernel void @_Z7kernel5P1S(ptr addrspace(1) noundef %s.coerce) #0 { # | entry: # | %s = alloca ptr, align 8, addrspace(5) # | %s.addr = alloca ptr, align 8, addrspace(5) # | %s.addr.ascast = addrspacecast ptr addrspace(5) %s.addr to ptr # | store ptr addrspace(1) %s.coerce, ptr addrspace(5) %s, align 8 # | %s1 = load ptr, ptr addrspace(5) %s, align 8 # | store ptr %s1, ptr %s.addr.ascast, align 8 # | %0 = load ptr, ptr %s.addr.ascast, align 8 # | %x = getelementptr inbounds nuw %struct.S, ptr %0, i32 0, i32 0 # | %1 = load ptr, ptr %x, align 8 # | %arrayidx = getelementptr inbounds i32, ptr %1, i64 0 # | %2 = load i32, ptr %arrayidx, align 4 # | %inc = add nsw i32 %2, 1 # | store i32 %inc, ptr %arrayidx, align 4 # | %3 = load ptr, ptr %s.addr.ascast, align 8 # | %y = getelementptr inbounds nuw %struct.S, ptr %3, i32 0, i32 1 # | %4 = load ptr, ptr %y, align 8 # | %arrayidx2 = getelementptr inbounds float, ptr %4, i64 0 # | %5 = load float, ptr %arrayidx2, align 4 # | %add = fadd contract float %5, 1.000000e+00 # | store float %add, ptr %arrayidx2, align 4 # | ret void # | } # | # | ; Function Attrs: convergent mustprogress noinline norecurse nounwind # | define dso_local amdgpu_kernel void @_Z7kernel61T(ptr addrspace(4) noundef byref(%struct.T) align 8 %0) #0 { # | entry: # | %t = alloca %struct.T, align 8, addrspace(5) # | call void @llvm.memcpy.p5.p4.i64(ptr addrspace(5) align 8 %t, ptr addrspace(4) align 8 %0, i64 16, i1 false) # | %t.ascast = addrspacecast ptr addrspace(5) %t to ptr # | %x = getelementptr inbounds nuw %struct.T, ptr %t.ascast, i32 0, i32 0 # | %arrayidx = getelementptr inbounds [2 x ptr], ptr %x, i64 0, i64 0 # | %1 = load ptr, ptr %arrayidx, align 8 # | %arrayidx1 = getelementptr inbounds float, ptr %1, i64 0 # | %2 = load float, ptr %arrayidx1, align 4 # | %add = fadd contract float %2, 1.000000e+00 # | store float %add, ptr %arrayidx1, align 4 # | %x2 = getelementptr inbounds nuw %struct.T, ptr %t.ascast, i32 0, i32 0 # | %arrayidx3 = getelementptr inbounds [2 x ptr], ptr %x2, i64 0, i64 1 # | %3 = load ptr, ptr %arrayidx3, align 8 # | %arrayidx4 = getelementptr inbounds float, ptr %3, i64 0 # | %4 = load float, ptr %arrayidx4, align 4 # | %add5 = fadd contract float %4, 2.000000e+00 # | store float %add5, ptr %arrayidx4, align 4 # | ret void # | } # | # | ; Function Attrs: convergent mustprogress noinline norecurse nounwind # | define dso_local amdgpu_kernel void @_Z7kernel7Pi(ptr addrspace(1) noalias noundef %x.coerce) #0 { # | entry: # | %x = alloca ptr, align 8, addrspace(5) # | %x.addr = alloca ptr, align 8, addrspace(5) # | %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr # | store ptr addrspace(1) %x.coerce, ptr addrspace(5) %x, align 8 # | %x1 = load ptr, ptr addrspace(5) %x, align 8 # | store ptr %x1, ptr %x.addr.ascast, align 8 # | %0 = load ptr, ptr %x.addr.ascast, align 8 # | %arrayidx = getelementptr inbounds i32, ptr %0, i64 0 # | %1 = load i32, ptr %arrayidx, align 4 # | %inc = add nsw i32 %1, 1 # | store i32 %inc, ptr %arrayidx, align 4 # | ret void # | } # | # | ; Function Attrs: convergent mustprogress noinline norecurse nounwind # | define dso_local amdgpu_kernel void @_Z7kernel82SS(ptr addrspace(1) %a.coerce) #0 { # | entry: # | %a = alloca %struct.SS, align 8, addrspace(5) # | %coerce.dive = getelementptr inbounds nuw %struct.SS, ptr addrspace(5) %a, i32 0, i32 0 # | store ptr addrspace(1) %a.coerce, ptr addrspace(5) %coerce.dive, align 8 # | %a.ascast = addrspacecast ptr addrspace(5) %a to ptr # | %x = getelementptr inbounds nuw %struct.SS, ptr %a.ascast, i32 0, i32 0 # | %0 = load ptr, ptr %x, align 8 # | %1 = load float, ptr %0, align 4 # | %add = fadd contract float %1, 3.000000e+00 # | store float %add, ptr %0, align 4 # | ret void # | } # | # | attributes #0 = { convergent mustprogress noinline norecurse nounwind "amdgpu-flat-work-group-size"="1,1024" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size" } # | attributes #1 = { convergent mustprogress noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size" } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } # | # | !llvm.module.flags = !{!0, !1} # | !llvm.ident = !{!2} # | # | !0 = !{i32 1, !"amdhsa_code_object_version", i32 600} # | !1 = !{i32 1, !"amdgpu_printf_kind", !"hostcall"} # | !2 = !{!"clang version 24.0.0"} # | !3 = !{} # | !4 = !{i64 4} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2 # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2 # | #0 0x00005592004a757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005592004a4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005592004a7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4306d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4306d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4306d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4306d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055920043d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055920043d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559200421f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005592000d1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005592000d0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4306d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4306d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4306d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005592000d0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu --check-prefixes=OPT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu --check-prefixes=OPT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c (1514 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_i8mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/69980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557b2fe4957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557b2fe46515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557b2fe49cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcac4f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcac4f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcac4f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcac4f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557b2fddf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557b2fddf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557b2fdc3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557b2fa73176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557b2fa72e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcac4f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcac4f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcac4f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557b2fa72d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c (1515 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_i8mf8x7_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c (1516 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettn_e8w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.sf.vsettnt.i64(i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettn_e8w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettn_e8w4(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettn_e16w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettn_e16w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettn_e16w4(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettn_e32w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 2, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettn_e32w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 2, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettn_e64w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 3, i64 1) # | ret i64 %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055667aaef57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055667aaec515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055667aaefcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe3cf61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe3cf6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe3cf61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe3cf603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055667aa8524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055667aa85096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055667aa69f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055667a719176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055667a718e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe3cf604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe3cf6050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe3cf6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055667a718d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c (1517 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_e4m3_e4m3_w4_f8e4m3m8_f8e4m3m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d06b79b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d06b798515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d06b79bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f77bbc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f77bbca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f77bbc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f77bbc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d06b73124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d06b731096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d06b715f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d06b3c5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d06b3c4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f77bbc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f77bbc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f77bbc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d06b3c4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c (1518 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d61b30757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d61b304515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d61b307cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb5baa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb5baaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb5baa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb5baa31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d61b29d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d61b29d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d61b281f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d61af31176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d61af30e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb5baa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb5baa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb5baa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d61af30d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/aapcs-bitfield.c (1519 of 27911) ******************** TEST 'Clang :: CodeGen/aapcs-bitfield.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-eabi -fno-aapcs-bitfield-width -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c -check-prefix=LE # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-eabi -fno-aapcs-bitfield-width -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8-none-linux-eabi" # | # | %struct.st6 = type { i16, i8, i8 } # | %struct.st7b = type { i8, [3 x i8], %struct.st7a } # | %struct.st7a = type { i8, i8, [2 x i8] } # | %struct.st11 = type <{ i8, i16, i8 }> # | %struct.st13 = type <{ i8, i32 }> # | %struct.st16 = type { i32, i16, i32, i16 } # | %struct.st17 = type <{ i32, i8 }> # | %struct.zero_bitfield = type { i8, i8, [2 x i8] } # | %struct.zero_bitfield_ok = type { i16, i32 } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @st0_check_load(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load i8, ptr %0, align 2 # | %bf.shl = shl i8 %bf.load, 1 # | %bf.ashr = ashr i8 %bf.shl, 1 # | %bf.cast = sext i8 %bf.ashr to i16 # | %conv = sext i16 %bf.cast to i32 # | ret i32 %conv # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @st0_check_store(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load i8, ptr %0, align 2 # | %bf.clear = and i8 %bf.load, -128 # | %bf.set = or i8 %bf.clear, 1 # | store i8 %bf.set, ptr %0, align 2 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @st1_check_load(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load i16, ptr %0, align 4 # | %bf.ashr = ashr i16 %bf.load, 10 # | %conv = sext i16 %bf.ashr to i32 # | ret i32 %conv # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @st1_check_store(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load i16, ptr %0, align 4 # | %bf.clear = and i16 %bf.load, 1023 # | %bf.set = or i16 %bf.clear, 1024 # | store i16 %bf.set, ptr %0, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @st2_check_load(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load i32, ptr %0, align 4 # | %bf.shl = shl i32 %bf.load, 9 # | %bf.ashr = ashr i32 %bf.shl, 25 # | %bf.cast = trunc i32 %bf.ashr to i16 # | %conv = sext i16 %bf.cast to i32 # | ret i32 %conv # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @st2_check_store(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load i32, ptr %0, align 4 # | %bf.clear = and i32 %bf.load, -8323073 # | %bf.set = or i32 %bf.clear, 65536 # | store i32 %bf.set, ptr %0, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @st3_check_load(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load volatile i8, ptr %0, align 2 # | %bf.shl = shl i8 %bf.load, 1 # | %bf.ashr = ashr i8 %bf.shl, 1 # | %bf.cast = sext i8 %bf.ashr to i16 # | %conv = sext i16 %bf.cast to i32 # | ret i32 %conv # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @st3_check_store(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load volatile i8, ptr %0, align 2 # | %bf.clear = and i8 %bf.load, -128 # | %bf.set = or i8 %bf.clear, 1 # | store volatile i8 %bf.set, ptr %0, align 2 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @st4_check_load(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load volatile i16, ptr %0, align 4 # | %bf.shl = shl i16 %bf.load, 2 # | %bf.ashr = ashr i16 %bf.shl, 11 # | %bf.cast = trunc i16 %bf.ashr to i8 # | %conv = sext i8 %bf.cast to i32 # | ret i32 %conv # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @st4_check_store(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load volatile i16, ptr %0, align 4 # | %bf.clear = and i16 %bf.load, -15873 # | %bf.set = or i16 %bf.clear, 512 # | store volatile i16 %bf.set, ptr %0, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @st4_check_nonv_store(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load i16, ptr %0, align 4 # | %bf.clear = and i16 %bf.load, -512 # | %bf.set = or i16 %bf.clear, 1 # | store i16 %bf.set, ptr %0, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @st5_check_load(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load volatile i32, ptr %0, align 4 # | %bf.shl = shl i32 %bf.load, 11 # | %bf.ashr = ashr i32 %bf.shl, 27 # | %bf.cast = trunc i32 %bf.ashr to i8 # | %conv = sext i8 %bf.cast to i32 # | ret i32 %conv # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @st5_check_store(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load volatile i32, ptr %0, align 4 # | %bf.clear = and i32 %bf.load, -2031617 # | %bf.set = or i32 %bf.clear, 65536 # | store volatile i32 %bf.set, ptr %0, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @st6_check_load(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | %x = alloca i32, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load volatile i16, ptr %0, align 4 # | %bf.shl = shl i16 %bf.load, 4 # | %bf.ashr = ashr i16 %bf.shl, 4 # | %bf.cast = sext i16 %bf.ashr to i32 # | store i32 %bf.cast, ptr %x, align 4 # | %1 = load ptr, ptr %m.addr, align 4 # | %b = getelementptr inbounds nuw %struct.st6, ptr %1, i32 0, i32 1 # | %2 = load volatile i8, ptr %b, align 2 # | %conv = sext i8 %2 to i32 # | %3 = load i32, ptr %x, align 4 # | %add = add nsw i32 %3, %conv # | store i32 %add, ptr %x, align 4 # | %4 = load ptr, ptr %m.addr, align 4 # | %c = getelementptr inbounds nuw %struct.st6, ptr %4, i32 0, i32 2 # | %bf.load1 = load volatile i8, ptr %c, align 1 # | %bf.shl2 = shl i8 %bf.load1, 3 # | %bf.ashr3 = ashr i8 %bf.shl2, 3 # | %bf.cast4 = sext i8 %bf.ashr3 to i32 # | %5 = load i32, ptr %x, align 4 # | %add5 = add nsw i32 %5, %bf.cast4 # | store i32 %add5, ptr %x, align 4 # | %6 = load i32, ptr %x, align 4 # | ret i32 %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @st6_check_store(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load i16, ptr %0, align 4 # | %bf.clear = and i16 %bf.load, -4096 # | %bf.set = or i16 %bf.clear, 1 # | store i16 %bf.set, ptr %0, align 4 # | %1 = load ptr, ptr %m.addr, align 4 # | %b = getelementptr inbounds nuw %struct.st6, ptr %1, i32 0, i32 1 # | store i8 2, ptr %b, align 2 # | %2 = load ptr, ptr %m.addr, align 4 # | %c = getelementptr inbounds nuw %struct.st6, ptr %2, i32 0, i32 2 # | %bf.load1 = load i8, ptr %c, align 1 # | %bf.clear2 = and i8 %bf.load1, -32 # | %bf.set3 = or i8 %bf.clear2, 3 # | store i8 %bf.set3, ptr %c, align 1 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @st7_check_load(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | %r = alloca i32, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %x = getelementptr inbounds nuw %struct.st7b, ptr %0, i32 0, i32 0 # | %1 = load i8, ptr %x, align 4 # | %conv = sext i8 %1 to i32 # | store i32 %conv, ptr %r, align 4 # | %2 = load ptr, ptr %m.addr, align 4 # | %y = getelementptr inbounds nuw %struct.st7b, ptr %2, i32 0, i32 2 # | %a = getelementptr inbounds nuw %struct.st7a, ptr %y, i32 0, i32 0 # | %3 = load volatile i8, ptr %a, align 4 # | %conv1 = sext i8 %3 to i32 # | %4 = load i32, ptr %r, align 4 # | %add = add nsw i32 %4, %conv1 # | store i32 %add, ptr %r, align 4 # | %5 = load ptr, ptr %m.addr, align 4 # | %y2 = getelementptr inbounds nuw %struct.st7b, ptr %5, i32 0, i32 2 # | %b = getelementptr inbounds nuw %struct.st7a, ptr %y2, i32 0, i32 1 # | %bf.load = load volatile i8, ptr %b, align 1 # | %bf.shl = shl i8 %bf.load, 3 # | %bf.ashr = ashr i8 %bf.shl, 3 # | %bf.cast = sext i8 %bf.ashr to i32 # | %6 = load i32, ptr %r, align 4 # | %add3 = add nsw i32 %6, %bf.cast # | store i32 %add3, ptr %r, align 4 # | %7 = load i32, ptr %r, align 4 # | ret i32 %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @st7_check_store(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %x = getelementptr inbounds nuw %struct.st7b, ptr %0, i32 0, i32 0 # | store i8 1, ptr %x, align 4 # | %1 = load ptr, ptr %m.addr, align 4 # | %y = getelementptr inbounds nuw %struct.st7b, ptr %1, i32 0, i32 2 # | %a = getelementptr inbounds nuw %struct.st7a, ptr %y, i32 0, i32 0 # | store volatile i8 2, ptr %a, align 4 # | %2 = load ptr, ptr %m.addr, align 4 # | %y1 = getelementptr inbounds nuw %struct.st7b, ptr %2, i32 0, i32 2 # | %b = getelementptr inbounds nuw %struct.st7a, ptr %y1, i32 0, i32 1 # | %bf.load = load volatile i8, ptr %b, align 1 # | %bf.clear = and i8 %bf.load, -32 # | %bf.set = or i8 %bf.clear, 3 # | store volatile i8 %bf.set, ptr %b, align 1 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @st8_check_assignment(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | store i16 -1, ptr %0, align 4 # | ret i32 65535 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @read_st9(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load volatile i8, ptr %0, align 4 # | %bf.cast = sext i8 %bf.load to i32 # | r # | ... # `---data was truncated (10240/24998) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055563ceac57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055563cea9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055563ceaccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa70a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa70a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa70a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa70a831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055563ce4224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055563ce42096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055563ce26f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055563cad6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055563cad5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa70a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa70a8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa70a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055563cad5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c -check-prefix=LE # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c -check-prefix=LE # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c (1520 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.v.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8mf8_tu( %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i8, ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.x.nxv1i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv1i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.v.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8mf4_tu( %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i8, ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.x.nxv2i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv2i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.v.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8mf2_tu( %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i8, ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.x.nxv4i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv4i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.v.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8m1_tu( %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i8, ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.x.nxv8i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv8i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.v.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8m2_tu( %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i8, ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.x.nxv16i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv16i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | # | ... # `---data was truncated (10240/134744) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560bb8fe457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560bb8fe1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560bb8fe4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4110133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f411018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4110133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f411011b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560bb8f7a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560bb8f7a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560bb8f5ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560bb8c0e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560bb8c0de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f411011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f411011d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f411011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560bb8c0dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c (1521 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_f64m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_i64m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_u64m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_f64m1x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_i64m1x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_u64m1x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b0cad0157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b0cacfe515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b0cad01cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f747b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f747b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f747b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f747b51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b0cac9724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b0cac97096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b0cac7bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b0ca92b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b0ca92ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f747b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f747b51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f747b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b0ca92ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c (1522 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ebee6d357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ebee6d0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ebee6d3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbd58a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbd58aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbd58a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbd58a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ebee66924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ebee669096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ebee64df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ebee2fd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ebee2fce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbd58a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbd58a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbd58a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ebee2fcd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c (1523 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.ad # | ... # `---data was truncated (10240/225647) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056320a31a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056320a317515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056320a31acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa36a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa36a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa36a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa36a11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056320a2b024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056320a2b0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056320a294f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563209f44176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563209f43e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa36a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa36a11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa36a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563209f43d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c (1524 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bc8345157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bc8344e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bc83451cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc405f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc405f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc405f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc405eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bc833e724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bc833e7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bc833cbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bc8307b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bc8307ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc405eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc405eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc405eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bc8307ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c (1525 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558447e7d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558447e7a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558447e7dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4a3e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4a3e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4a3e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4a3e631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558447e1324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558447e13096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558447df7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558447aa7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558447aa6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4a3e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4a3e6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4a3e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558447aa6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c (1526 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m8_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captur # | ... # `---data was truncated (10240/30617) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005574fbbbd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005574fbbba515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005574fbbbdcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe853c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe853ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe853c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe853c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005574fbb5324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005574fbb53096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005574fbb37f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005574fb7e7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005574fb7e6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe853c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe853c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe853c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005574fb7e6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-neon-vget.c (1527 of 27911) ******************** TEST 'Clang :: CodeGen/arm-neon-vget.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-apple-darwin -target-abi apcs-gnu -target-cpu cortex-a8 -mfloat-abi soft -target-feature +soft-float-abi -ffreestanding -disable-O0-optnone -emit-llvm -w -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-apple-darwin -target-abi apcs-gnu -target-cpu cortex-a8 -mfloat-abi soft -target-feature +soft-float-abi -ffreestanding -disable-O0-optnone -emit-llvm -w -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c" # | target datalayout = "e-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" # | target triple = "thumbv7-apple-darwin" # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @low_s8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @low_u8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <4 x i16> @low_s16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> # | store <4 x i16> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <4 x i16> @low_u16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> # | store <4 x i16> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <2 x i32> @low_s32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <2 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | %1 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %2 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <4 x i32> %1, <4 x i32> %2, <2 x i32> # | store <2 x i32> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <2 x i32> @low_u32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <2 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | %1 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %2 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <4 x i32> %1, <4 x i32> %2, <2 x i32> # | store <2 x i32> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <1 x i64> @low_s64(<2 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <1 x i64>, align 8 # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %2 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> zeroinitializer # | store <1 x i64> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <1 x i64> @low_u64(<2 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <1 x i64>, align 8 # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %2 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> zeroinitializer # | store <1 x i64> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @low_p8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <4 x i16> @low_p16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> # | store <4 x i16> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <2 x float> @low_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <2 x float>, align 8 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %2 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <4 x float> %1, <4 x float> %2, <2 x i32> # | store <2 x float> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @high_s8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @high_u8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <4 x i16> @high_s16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> # | store <4 x i16> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <4 x i16> @high_u16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %2 = load <8 x i16>, ptr # | ... # `---data was truncated (10240/15571) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056262068857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562620685515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562620688cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1dd5a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1dd5aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1dd5a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1dd5a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056262061e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056262061e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562620602f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005626202b2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005626202b1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1dd5a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1dd5a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1dd5a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005626202b1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c (1528 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf8_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf4_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf2_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m1_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m2_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m4_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m8_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u16mf4_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u16mf2_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u16m1_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %sc # | ... # `---data was truncated (10240/52741) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b3e532357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b3e5320515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b3e5323cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efe8f105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efe8f15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efe8f105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efe8f0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b3e52b924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b3e52b9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b3e529df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b3e4f4d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b3e4f4ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efe8f0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efe8f0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efe8f0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b3e4f4cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/neon-misc-constrained.c (1529 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon-misc-constrained.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vrndaq_f64(<2 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrnda.i = bitcast <16 x i8> %1 to <2 x double> # | %vrnda1.i = call <2 x double> @llvm.round.v2f64(<2 x double> %vrnda.i) # | store <2 x double> %vrnda1.i, ptr %ref.tmp.i, align 16 # | %2 = load <2 x double>, ptr %ref.tmp.i, align 16 # | store <2 x double> %2, ptr %__ret.i, align 16 # | %3 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vrndpq_f64(<2 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrndp.i = bitcast <16 x i8> %1 to <2 x double> # | %vrndp1.i = call <2 x double> @llvm.ceil.v2f64(<2 x double> %vrndp.i) # | store <2 x double> %vrndp1.i, ptr %ref.tmp.i, align 16 # | %2 = load <2 x double>, ptr %ref.tmp.i, align 16 # | store <2 x double> %2, ptr %__ret.i, align 16 # | %3 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vsqrtq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <4 x float> # | %vsqrt.i = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %2) # | store <4 x float> %vsqrt.i, ptr %ref.tmp.i, align 16 # | %3 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %3, ptr %__ret.i, align 16 # | %4 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vcvt_f16_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <4 x float> # | %3 = fptrunc <4 x float> %2 to <4 x half> # | store <4 x half> %3, ptr %ref.tmp.i, align 8 # | %4 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %4, ptr %__ret.i, align 8 # | %5 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vcvt_high_f16_f32(<4 x half> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i1 = alloca <4 x half>, align 8 # | %__p1.addr.i2 = alloca <4 x half>, align 8 # | %__ret.i3 = alloca <8 x half>, align 16 # | %__p0.addr.i.i = alloca <4 x float>, align 16 # | %__ret.i.i = alloca <4 x half>, align 8 # | %ref.tmp.i.i = alloca <8 x i8>, align 8 # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x float>, align 16 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 16 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x float> %1, ptr %__p1.addr.i, align 16 # | %2 = load <4 x half>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x float>, ptr %__p1.addr.i, align 16 # | store <4 x float> %3, ptr %__p0.addr.i.i, align 16 # | %4 = load <16 x i8>, ptr %__p0.addr.i.i, align 16 # | %5 = bitcast <16 x i8> %4 to <4 x float> # | %6 = fptrunc <4 x float> %5 to <4 x half> # | store <4 x half> %6, ptr %ref.tmp.i.i, align 8 # | %7 = load <4 x half>, ptr %ref.tmp.i.i, align 8 # | store <4 x half> %7, ptr %__ret.i.i, align 8 # | %8 = load <4 x half>, ptr %__ret.i.i, align 8 # | store <4 x half> %2, ptr %__p0.addr.i1, align 8 # | store <4 x half> %8, ptr %__p1.addr.i2, align 8 # | %9 = load <4 x half>, ptr %__p0.addr.i1, align 8 # | %10 = load <4 x half>, ptr %__p1.addr.i2, align 8 # | %shuffle.i = shufflevector <4 x half> %9, <4 x half> %10, <8 x i32> # | store <8 x half> %shuffle.i, ptr %__ret.i3, align 16 # | %11 = load <8 x half>, ptr %__ret.i3, align 16 # | store <8 x half> %11, ptr %__ret.i, align 16 # | %12 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vcvt_f32_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fpext <4 x half> %2 to <4 x float> # | store <4 x float> %3, ptr %ref.tmp.i, align 16 # | %4 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %4, ptr %__ret.i, align 16 # | %5 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vcvt_high_f32_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i1 = alloca <8 x half>, align 16 # | %__ret.i2 = alloca <4 x half>, align 8 # | %__p0.addr.i.i = alloca <4 x half>, align 8 # | %__ret.i.i = alloca <4 x float>, align 16 # | %ref.tmp.i.i = alloca <16 x i8>, align 16 # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x half>, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p0.addr.i1, align 16 # | %2 = load <8 x half>, ptr %__p0.addr.i1, align 16 # | %3 = load <8 x half>, ptr %__p0.addr.i1, align 16 # | %shuffle.i = shufflevector <8 x half> %2, <8 x half> %3, <4 x i32> # | store <4 x half> %shuffle.i, ptr %__ret.i2, align 8 # | %4 = load <4 x half>, ptr %__ret.i2, align 8 # | store <4 x half> %4, ptr %__p0.addr.i.i, align 8 # | %5 = load <8 x i8>, ptr %__p0.addr.i.i, align 8 # | %6 = bitcast <8 x i8> %5 to <4 x half> # | %7 = fpext <4 x half> %6 to <4 x float> # | store <4 x float> %7, ptr %ref.tmp.i.i, align 16 # | %8 = load <4 x float>, ptr %ref.tmp.i.i, align 16 # | store <4 x float> %8, ptr %__ret.i.i, align 16 # | %9 = load <4 x float>, ptr %__ret.i.i, align 16 # | store <4 x float> %9, ptr %__ret.i, align 16 # | %10 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %10 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <2 x double> @llvm.round.v2f64(<2 x double>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <2 x double> @llvm.ceil.v2f64(<2 x double>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055f5e1ad257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f5e1acf515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f5e1ad2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc0e8c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc0e8ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc0e8c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc0e8c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f5e1a6824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f5e1a68096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f5e1a4cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f5e16fc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f5e16fbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc0e8c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc0e8c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc0e8c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f5e16fbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c (1530 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c (1531 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_i64m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_i64m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_u64m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_u64m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m1x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/16424) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555ed555157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555ed554e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555ed5551cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7433249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f74332a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7433249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7433231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555ed54e724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555ed54e7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555ed54cbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555ed517b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555ed517ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7433232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f74332330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f74332330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555ed517ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c (1532 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f32m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f32m4x2(ptr noundef %base, %binde # | ... # `---data was truncated (10240/110121) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556e6d47657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556e6d473515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556e6d476cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc134105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc13415c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc134105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc1340ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556e6d40c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556e6d40c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556e6d3f0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556e6d0a0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556e6d09fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc1340eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc1340ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc1340ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556e6d09fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c (1533 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556d0679b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556d06798515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556d0679bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9ead933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9ead98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9ead933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9ead91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556d0673124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556d06731096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556d06715f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556d063c5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556d063c4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9ead91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9ead91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9ead91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556d063c4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c (1534 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m2_f16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv8f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv8f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m4_f16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m8_f16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m4_f16m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m8_f16m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m8_f16m4( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv16f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv16f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m2_f32m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv2f32.nxv4f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f32.nxv4f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m4_f32m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv2f32.nxv8f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f32.nxv8f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m8_f32m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv2f32.nxv16f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f32.nxv16f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m4_f32m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv4f32.nxv8f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f32.nxv8f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m8_f32m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv4f32.nxv16f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f32.nxv16f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m8_f32m4( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv8f32.nxv16f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8f32.nxv16f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f64m2_f64m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 8 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = call @llvm.vector.extract.nxv1f64.nxv2f64( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f64.nxv2f64(, i64 immarg) #1 # | # | ; Function Attrs: noinli # | ... # `---data was truncated (10240/246614) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bcceb1a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bcceb17515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bcceb1acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8b9ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8b9ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8b9ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8b9ad1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bcceab024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bcceab0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bccea94f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bcce744176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bcce743e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8b9ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8b9ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8b9ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bcce743d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c (1535 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste64_f64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.sf.vste64.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste64_i64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste64_u64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564e314de57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564e314db515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564e314decbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fed49d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fed49d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fed49d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fed49ced507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564e3147424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564e31474096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564e31458f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564e31108176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564e31107e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fed49ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fed49cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fed49cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564e31107d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c (1536 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple # | ... # `---data was truncated (10240/31938) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005629d1c2257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005629d1c1f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005629d1c22cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f52cea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f52ceaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f52cea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f52cea31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005629d1bb824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005629d1bb8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005629d1b9cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005629d184c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005629d184be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f52cea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f52cea330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f52cea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005629d184bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c (1537 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005642f506d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005642f506a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005642f506dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc7a4933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc7a498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc7a4933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc7a491b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005642f500324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005642f5003096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005642f4fe7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005642f4c97176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005642f4c96e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc7a491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc7a491d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc7a491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005642f4c96d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c (1538 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f64m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 # | ... # `---data was truncated (10240/99178) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056184fea357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056184fea0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056184fea3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4eb9049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4eb90a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4eb9049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4eb9031507 abort ./stdlib/abort.c:85:3 # | #7 0x000056184fe3924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056184fe39096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056184fe1df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056184facd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056184facce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4eb9032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4eb90330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4eb90330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056184faccd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c (1539 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf8_b64( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf4_b32( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf2_b16( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8m1_b8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8m2_b4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.n # | ... # `---data was truncated (10240/95355) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055db79da257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055db79d9f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055db79da2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd6f4133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd6f418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd6f4133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd6f411b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055db79d3824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055db79d38096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055db79d1cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055db799cc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055db799cbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd6f411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd6f411d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd6f411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055db799cbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c (1540 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16mf4_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv1bf16( %0) # | ret bfloat %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare bfloat @llvm.riscv.vfmv.f.s.nxv1bf16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16mf2_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv2bf16( %0) # | ret bfloat %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare bfloat @llvm.riscv.vfmv.f.s.nxv2bf16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16m1_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv4bf16( %0) # | ret bfloat %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare bfloat @llvm.riscv.vfmv.f.s.nxv4bf16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16m2_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv8bf16( %0) # | ret bfloat %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare bfloat @llvm.riscv.vfmv.f.s.nxv8bf16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16m4_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv16bf16( %0) # | ret bfloat %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare bfloat @llvm.riscv.vfmv.f.s.nxv16bf16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16m8_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv32bf16( %0) # | ret bfloat %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare bfloat @llvm.riscv.vfmv.f.s.nxv32bf16() #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562d28f1057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562d28f0d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562d28f10cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f92b6d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f92b6d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f92b6d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f92b6d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562d28ea624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562d28ea6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562d28e8af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562d28b3a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562d28b39e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f92b6d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f92b6d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f92b6d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562d28b39d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c (1541 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv1i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv2i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv4i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv8i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv16i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv32i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv64i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv1i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv2i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv4i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vr # | ... # `---data was truncated (10240/96265) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056200f15f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056200f15c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056200f15fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8189849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f81898a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8189849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8189831507 abort ./stdlib/abort.c:85:3 # | #7 0x000056200f0f524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056200f0f5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056200f0d9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056200ed89176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056200ed88e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8189832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f81898330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f81898330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056200ed88d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c (1542 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_i32mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_i32m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_u32mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_u32m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32mf2x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: # | ... # `---data was truncated (10240/16382) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056235faf957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056235faf6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056235faf9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f10fd333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f10fd38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f10fd333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f10fd31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056235fa8f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056235fa8f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056235fa73f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056235f723176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056235f722e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f10fd31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f10fd31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f10fd31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056235f722d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c (1543 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m4_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c (1544 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff # | ... # `---data was truncated (10240/54702) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055673ffd857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055673ffd5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055673ffd8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f523db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f523db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f523db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f523db1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055673ff6e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055673ff6e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055673ff52f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055673fc02176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055673fc01e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f523db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f523db1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f523db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055673fc01d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c (1545 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv16i8.nxv16i16.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv16i8.nxv16i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv16i8.nxv16i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv16i8.nxv16i16.i64.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/sve/recps.c (1546 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve/recps.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecps_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.frecps.x.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frecps.x.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecps_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.frecps.x.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frecps.x.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecps_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.frecps.x.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frecps.x.nxv2f64(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x000055c51dc7957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c51dc76515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c51dc79cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0d86a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0d86a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0d86a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0d86a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c51dc0f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c51dc0f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c51dbf3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c51d8a3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c51d8a2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0d86a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0d86a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0d86a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c51d8a2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c (1547 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv16i8( %0, %1, i32 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.ext.nxv16i8(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_s8_1( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv16i8( %0, %1, i32 255) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv8i16( %0, %1, i32 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.ext.nxv8i16(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_s16_1( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv8i16( %0, %1, i32 127) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv4i32( %0, %1, i32 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.ext.nxv4i32(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_s32_1( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv4i32( %0, %1, i32 63) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv2i64( %0, %1, i32 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.ext.nxv2i64(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_s64_1( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv2i64( %0, %1, i32 31) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv16i8( %0, %1, i32 255) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv8i16( %0, %1, i32 127) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv4i32( %0, %1, i32 63) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv2i64( %0, %1, i32 31) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv8f16( %0, %1, i32 127) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.ext.nxv8f16(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr # | ... # `---data was truncated (10240/12880) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000557521e0b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557521e08515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557521e0bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efea2333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efea238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efea2333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efea231b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557521da124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557521da1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557521d85f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557521a35176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557521a34e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efea231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efea231d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efea231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557521a34d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c (1548 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_i8mf8x6_tu(target("riscv.vector.tuple", , 6) %m # | ... # `---data was truncated (10240/160133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b74c6a657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b74c6a3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b74c6a6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1244849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f12448a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1244849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1244831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b74c63c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b74c63c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b74c620f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b74c2d0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b74c2cfe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1244832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f12448330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f12448330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b74c2cfd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c (1549 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 # | ... # `---data was truncated (10240/67006) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dbad9ae57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055dbad9ab515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055dbad9aecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0ab8649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0ab86a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0ab8649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0ab8631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dbad94424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055dbad944096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055dbad928f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055dbad5d8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055dbad5d7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0ab8632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0ab86330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0ab86330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dbad5d7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c (1550 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16m8(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i16.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i16.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c (1551 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | de # | ... # `---data was truncated (10240/70971) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563e1556657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563e15563515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563e15566cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6dc781bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6dc78725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6dc781ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6dc7803507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563e154fc24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563e154fc096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563e154e0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563e15190176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563e1518fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6dc7804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6dc78050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6dc78050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563e1518fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqdmlad.c (1552 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqdmlad.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmladhq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %inactive.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 0, i32 0, i32 0) # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8>, <16 x i8>, <16 x i8>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmladhq_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %inactive.addr, align 8 # | %1 = load <8 x i16>, ptr %a.addr, align 8 # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2, i32 0, i32 0, i32 0) # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16>, <8 x i16>, <8 x i16>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmladhq_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %inactive.addr, align 8 # | %1 = load <4 x i32>, ptr %a.addr, align 8 # | %2 = load <4 x i32>, ptr %b.addr, align 8 # | %3 = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 0, i32 0, i32 0) # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32>, <4 x i32>, <4 x i32>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmladhxq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %inactive.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 1, i32 0, i32 0) # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmladhxq_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %inactive.addr, align 8 # | %1 = load <8 x i16>, ptr %a.addr, align 8 # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2, i32 1, i32 0, i32 0) # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmladhxq_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %inactive.addr, align 8 # | %1 = load <4 x i32>, ptr %a.addr, align 8 # | %2 = load <4 x i32>, ptr %b.addr, align 8 # | %3 = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 1, i32 0, i32 0) # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmlsdhq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %inactive.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 0, i32 0, i32 1) # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmlsdhq_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %inactive.addr, align 8 # | %1 = load <8 x i16>, ptr %a.addr, align 8 # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2, i32 0, i32 0, i32 1) # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmlsdhq_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %inactive.addr, align 8 # | %1 = load <4 x i32>, ptr %a.addr, align 8 # | %2 = load <4 x i32>, ptr %b.addr, align 8 # | %3 = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 0, i32 0, i32 1) # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmlsdhxq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %inactive.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 1, i32 0, i32 1) # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmlsdhxq_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %inactive.addr, align 8 # | %1 = load <8 x i16>, ptr %a.addr, align 8 # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2, i32 1, i32 0, i32 1) # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmlsdhxq_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %inactive.addr, align 8 # | %1 = load <4 x i32>, ptr %a.addr, align 8 # | %2 = load <4 x i32>, ptr %b.addr, align 8 # | %3 = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 1, i32 0, i32 1) # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmladhq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %inactive.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 0, i32 1, i32 0) # | r # | ... # `---data was truncated (10240/43005) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055de6612957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055de66126515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055de66129cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7554e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7554ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7554e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7554e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055de660bf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055de660bf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055de660a3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055de65d53176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055de65d52e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7554e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7554e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7554e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055de65d52d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c (1553 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16mf4(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16mf2(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m1(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m2(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m4(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv16bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv16bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m8(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv32bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv32bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16mf4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.mask.nxv1bf16.p0.i64( %3, ptr %1, i64 %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.mask.nxv1bf16.p0.i64(, ptr captures(none), i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16mf2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.mask.nxv2bf16.p0.i64( %3, ptr %1, i64 %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.mask.nxv2bf16.p0.i64(, ptr captures(none), i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m1_m( %vm, ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.mask.nxv4bf16.p0.i64( %3, ptr %1, i64 %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.mask.nxv4bf16.p0.i64(, ptr captures(none), i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c (1554 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf4x6_tumu( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 0, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector. # | ... # `---data was truncated (10240/16808) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005579251f157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005579251ee515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005579251f1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5bf761bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5bf76725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5bf761ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5bf7603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055792518724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557925187096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055792516bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557924e1b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557924e1ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5bf7604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5bf76050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5bf76050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557924e1ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c (1555 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv1i16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv2i16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv4i16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv8i16.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv16i16.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv32i16.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv1i32.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv2i32.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv4i32.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv8i32.nxv8i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: n # | ... # `---data was truncated (10240/66036) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c3ed9c857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c3ed9c5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c3ed9c8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6977d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6977d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6977d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6977d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c3ed95e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c3ed95e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c3ed942f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c3ed5f2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c3ed5f1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6977d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6977d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6977d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c3ed5f1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-neon-endianness.c (1556 of 27911) ******************** TEST 'Clang :: CodeGen/arm-neon-endianness.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8a-arm-none-eabihf -target-cpu generic -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c --check-prefix=LE # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8a-arm-none-eabihf -target-cpu generic -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8a-arm-none-eabihf" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @int32x4_t_lane_0(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %__ret = alloca i32, align 4 # | %__s0 = alloca <4 x i32>, align 8 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | store <4 x i32> %0, ptr %__s0, align 8 # | %1 = load <4 x i32>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x i32> %1, i32 0 # | store i32 %vget_lane, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @int32x4_t_lane_1(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %__ret = alloca i32, align 4 # | %__s0 = alloca <4 x i32>, align 8 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | store <4 x i32> %0, ptr %__s0, align 8 # | %1 = load <4 x i32>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x i32> %1, i32 1 # | store i32 %vget_lane, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @int32x4_t_lane_2(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %__ret = alloca i32, align 4 # | %__s0 = alloca <4 x i32>, align 8 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | store <4 x i32> %0, ptr %__s0, align 8 # | %1 = load <4 x i32>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x i32> %1, i32 2 # | store i32 %vget_lane, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @int32x4_t_lane_3(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %__ret = alloca i32, align 4 # | %__s0 = alloca <4 x i32>, align 8 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | store <4 x i32> %0, ptr %__s0, align 8 # | %1 = load <4 x i32>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x i32> %1, i32 3 # | store i32 %vget_lane, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @int32x2_t_lane_0(<2 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i32>, align 8 # | %__ret = alloca i32, align 4 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__s0, align 8 # | %1 = load <2 x i32>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x i32> %1, i32 0 # | store i32 %vget_lane, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @int32x2_t_lane_1(<2 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i32>, align 8 # | %__ret = alloca i32, align 4 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__s0, align 8 # | %1 = load <2 x i32>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x i32> %1, i32 1 # | store i32 %vget_lane, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @int64x2_t_lane_0(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | %__ret = alloca i64, align 8 # | %__s0 = alloca <2 x i64>, align 8 # | %ref.tmp = alloca i64, align 8 # | %tmp = alloca i64, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | store <2 x i64> %0, ptr %__s0, align 8 # | %1 = load <2 x i64>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x i64> %1, i32 0 # | store i64 %vget_lane, ptr %ref.tmp, align 8 # | %2 = load i64, ptr %ref.tmp, align 8 # | store i64 %2, ptr %__ret, align 8 # | %3 = load i64, ptr %__ret, align 8 # | store i64 %3, ptr %tmp, align 8 # | %4 = load i64, ptr %tmp, align 8 # | ret i64 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @int64x2_t_lane_1(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | %__ret = alloca i64, align 8 # | %__s0 = alloca <2 x i64>, align 8 # | %ref.tmp = alloca i64, align 8 # | %tmp = alloca i64, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | store <2 x i64> %0, ptr %__s0, align 8 # | %1 = load <2 x i64>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x i64> %1, i32 1 # | store i64 %vget_lane, ptr %ref.tmp, align 8 # | %2 = load i64, ptr %ref.tmp, align 8 # | store i64 %2, ptr %__ret, align 8 # | %3 = load i64, ptr %__ret, align 8 # | store i64 %3, ptr %tmp, align 8 # | %4 = load i64, ptr %tmp, align 8 # | ret i64 %4 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+aes,+armv8-a,+crc,+d32,+dsp,+fp-armv8,+fp-armv8d16,+fp-armv8d16sp,+fp-armv8sp,+fp16,+fp64,+hwdiv,+hwdiv-arm,+neon,+sha2,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp,+vfp4,+vfp4d16,+vfp4d16sp,+vfp4sp,-thumb-mode" } # | # | !llvm.module.flags = !{!0, !1, !2, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"aapcs"} # | !1 = !{i32 1, !"min_enum_size", i32 4} # | !2 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !3 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine -o - # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine -o - # | #0 0x000055d08c0c157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d08c0be515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d08c0c1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff160b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff160b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff160b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff160b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d08c05724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d08c057096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d08c03bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d08bceb176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d08bceae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff160b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff160b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff160b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d08bcead81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c --check-prefix=LE # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c --check-prefix=LE # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c (1557 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564bd286d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564bd286a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564bd286dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe444c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe444ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe444c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe444c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564bd280324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564bd2803096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564bd27e7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564bd2497176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564bd2496e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe444c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe444c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe444c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564bd2496d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c (1558 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16mf4x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16mf4x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_u16mf4x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_u16mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_u16m1x8_m(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c (1559 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf4_tum( %mask, %maskedoff, %src, i64 nou # | ... # `---data was truncated (10240/78890) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c63b62f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c63b62c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c63b62fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb0fa849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb0fa8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb0fa849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb0fa831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c63b5c524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c63b5c5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c63b5a9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c63b259176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c63b258e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb0fa832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb0fa8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb0fa8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c63b258d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c (1560 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32m2x3_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c (1561 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a97661c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a976619515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a97661ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f19e0305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f19e035c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f19e0305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f19e02ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a9765b224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a9765b2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a976596f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a976246176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a976245e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f19e02eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f19e02ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f19e02ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a976245d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c (1562 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16mf4x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16mf2x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16m1x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16m2x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16m1x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16m2x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("risc # | ... # `---data was truncated (10240/11912) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563c469f757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563c469f4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563c469f7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcdf6c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcdf6ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcdf6c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcdf6c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563c4698d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563c4698d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563c46971f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563c46621176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563c46620e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcdf6c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcdf6c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcdf6c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563c46620d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c (1563 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_i8mf4x5(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ee93e1857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ee93e15515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ee93e18cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6128849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f61288a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6128849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6128831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ee93dae24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ee93dae096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ee93d92f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ee93a42176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ee93a41e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6128832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f61288330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f61288330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ee93a41d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c (1564 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32mf2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m1_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c (1565 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005558ff82157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005558ff81e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005558ff821cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0c41733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0c4178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0c41733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0c4171b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005558ff7b724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005558ff7b7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005558ff79bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005558ff44b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005558ff44ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0c4171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0c4171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0c4171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005558ff44ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c (1566 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5), pt # | ... # `---data was truncated (10240/19484) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ccc616457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ccc6161515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ccc6164cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0d29e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0d29ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0d29e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0d29e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ccc60fa24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ccc60fa096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ccc60def49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ccc5d8e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ccc5d8de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0d29e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0d29e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0d29e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ccc5d8dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c (1567 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | ... # `---data was truncated (10240/34356) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005580963f057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005580963ed515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005580963f0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa8d1e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa8d1ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa8d1e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa8d1e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055809638624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558096386096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055809636af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055809601a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558096019e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa8d1e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa8d1e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa8d1e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558096019d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c (1568 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16mf4_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16mf4_f32mf2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16mf2_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16mf2_f32m1_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16m1_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16m1_f32m2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16m2_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16m2_f32m4_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac. # | ... # `---data was truncated (10240/101402) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563eb8d3e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563eb8d3b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563eb8d3ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe7c0f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe7c0f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe7c0f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe7c0eed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563eb8cd424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563eb8cd4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563eb8cb8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563eb8968176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563eb8967e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe7c0eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe7c0eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe7c0eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563eb8967d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c (1569 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005606356cf57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005606356cc515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005606356cfcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4355b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4355b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4355b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4355b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056063566524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560635665096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560635649f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005606352f9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005606352f8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4355b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4355b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4355b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005606352f8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c (1570 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f32.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f32.p0.nxv8i16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c (1571 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_u16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_u16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c (1572 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m1x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | s # | ... # `---data was truncated (10240/24381) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005642c035e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005642c035b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005642c035ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0496c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0496ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0496c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0496c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005642c02f424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005642c02f4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005642c02d8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005642bff88176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005642bff87e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0496c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0496c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0496c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005642bff87d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c (1573 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf8_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf4_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf2_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m1_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m2_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m4_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m8_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u16mf4_u32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv2i32.nxv1i # | ... # `---data was truncated (10240/51295) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005561afbf057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005561afbed515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005561afbf0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f559481bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f55948725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f559481ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5594803507 abort ./stdlib/abort.c:85:3 # | #7 0x00005561afb8624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005561afb86096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005561afb6af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005561af81a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005561af819e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5594804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f55948050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f55948050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005561af819d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c (1574 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16mf4_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16mf2_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m1_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m2_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m4_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv16f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv16f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m8_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv32f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv32f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32mf2_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load float, ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv1f32.f32.i64( %0, %1, float %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32m1_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load float, ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv2f32.f32.i64( %0, %1, float %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32m2_tu( %maskedoff, %src, float noundef %value, i64 noundef # | ... # `---data was truncated (10240/78336) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562f54ab257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562f54aaf515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562f54ab2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff5a1133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff5a118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff5a1133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff5a111b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562f54a4824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562f54a48096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562f54a2cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562f546dc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562f546dbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff5a111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff5a111d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff5a111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562f546dbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c (1575 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f16mf4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f16mf2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f16m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f16m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f16m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f16m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f32mf2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f32m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f32m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f32m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f32m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f64m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f64m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f64m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f64m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i8mf8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i8mf4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i8mf2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i8m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i8m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i8m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i8m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i16mf4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i16mf2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i16m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i16m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i16m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i16m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i32mf2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i32m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i32m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i32m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i32m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i64m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i64m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i64m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i64m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u8mf8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u8mf4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u8mf2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u8m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u8m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u8m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u8m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u16mf4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u16mf2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u16m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u16m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u16m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u16m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u32mf2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u32m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u32m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u32m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u32m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u64m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u64m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u64m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u64m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vsca # | ... # `---data was truncated (10240/63140) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559574eb457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559574eb1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559574eb4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f385ec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f385eca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f385ec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f385ec31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559574e4a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559574e4a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559574e2ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559574ade176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559574adde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f385ec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f385ec330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f385ec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559574addd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c (1576 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563fdb58957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563fdb586515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563fdb589cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd622d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd622d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd622d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd622d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563fdb51f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563fdb51f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563fdb503f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563fdb1b3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563fdb1b2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd622d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd622d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd622d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563fdb1b2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c (1577 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16mf4_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16mf2_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16m1_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16m2_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | st # | ... # `---data was truncated (10240/110292) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a1e8d1457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a1e8d11515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a1e8d14cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f02a7049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f02a70a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f02a7049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f02a7031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a1e8caa24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a1e8caa096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a1e8c8ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a1e893e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a1e893de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f02a7032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f02a70330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f02a70330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a1e893dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c (1578 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv32i8.nxv32i8.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c (1579 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, ali # | ... # `---data was truncated (10240/47706) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e92768357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e927680515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e927683cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6d5cb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6d5cb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6d5cb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6d5caed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e92761924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e927619096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e9275fdf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e9272ad176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e9272ace93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6d5caeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6d5caef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6d5caef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e9272acd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c (1580 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16m8(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory # | ... # `---data was truncated (10240/135997) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055560965357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555609650515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555609653cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff2b8533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff2b858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff2b8533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff2b851b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005556095e924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005556095e9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005556095cdf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055560927d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055560927ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff2b851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff2b851d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff2b851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055560927cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c (1581 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf8_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf4_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8m1_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c (1582 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556ead77957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556ead776515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556ead779cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3a3f505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3a3f55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3a3f505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3a3f4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556ead70f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556ead70f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556ead6f3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556ead3a3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556ead3a2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3a3f4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3a3f4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3a3f4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556ead3a2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c (1583 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_f64m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_i64m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_u64m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_f64m1x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_i64m1x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_u64m1x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a42dc1357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a42dc10515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a42dc13cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa8c5a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa8c5aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa8c5a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa8c5a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a42dba924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a42dba9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a42db8df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a42d83d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a42d83ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa8c5a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa8c5a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa8c5a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a42d83cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c (1584 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | # | ... # `---data was truncated (10240/30268) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005616ff62d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005616ff62a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005616ff62dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6533449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f65334a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6533449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6533431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005616ff5c324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005616ff5c3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005616ff5a7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005616ff257176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005616ff256e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6533432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f65334330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f65334330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005616ff256d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c (1585 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16m1x8_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056157ba0f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056157ba0c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056157ba0fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fac68905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fac6895c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fac68905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fac688ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056157b9a524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056157b9a5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056157b989f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056157b639176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056157b638e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fac688eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fac688ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fac688ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056157b638d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c (1586 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: n # | ... # `---data was truncated (10240/66314) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563eb31d857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563eb31d5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563eb31d8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f388441bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f38844725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f388441ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3884403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563eb316e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563eb316e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563eb3152f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563eb2e02176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563eb2e01e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3884404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f38844050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f38844050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563eb2e01d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c (1587 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv16i8.nxv16i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-neon-directed-rounding.c (1588 of 27911) ******************** TEST 'Clang :: CodeGen/arm-neon-directed-rounding.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8-unknown-linux-gnueabihf" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrnda_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrnda_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vrnda_v1.i = call <2 x float> @llvm.round.v2f32(<2 x float> %vrnda_v.i) # | %vrnda_v2.i = bitcast <2 x float> %vrnda_v1.i to <8 x i8> # | store <8 x i8> %vrnda_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrndaq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vrndaq_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vrndaq_v1.i = call <4 x float> @llvm.round.v4f32(<4 x float> %vrndaq_v.i) # | %vrndaq_v2.i = bitcast <4 x float> %vrndaq_v1.i to <16 x i8> # | store <16 x i8> %vrndaq_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %2, ptr %__ret.i, align 8 # | %3 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrndm_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndm_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vrndm_v1.i = call <2 x float> @llvm.floor.v2f32(<2 x float> %vrndm_v.i) # | %vrndm_v2.i = bitcast <2 x float> %vrndm_v1.i to <8 x i8> # | store <8 x i8> %vrndm_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrndmq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vrndmq_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vrndmq_v1.i = call <4 x float> @llvm.floor.v4f32(<4 x float> %vrndmq_v.i) # | %vrndmq_v2.i = bitcast <4 x float> %vrndmq_v1.i to <16 x i8> # | store <16 x i8> %vrndmq_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %2, ptr %__ret.i, align 8 # | %3 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrndn_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndn_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vrndn_v1.i = call <2 x float> @llvm.roundeven.v2f32(<2 x float> %vrndn_v.i) # | %vrndn_v2.i = bitcast <2 x float> %vrndn_v1.i to <8 x i8> # | store <8 x i8> %vrndn_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrndnq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vrndnq_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vrndnq_v1.i = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %vrndnq_v.i) # | %vrndnq_v2.i = bitcast <4 x float> %vrndnq_v1.i to <16 x i8> # | store <16 x i8> %vrndnq_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %2, ptr %__ret.i, align 8 # | %3 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrndp_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndp_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vrndp_v1.i = call <2 x float> @llvm.ceil.v2f32(<2 x float> %vrndp_v.i) # | %vrndp_v2.i = bitcast <2 x float> %vrndp_v1.i to <8 x i8> # | store <8 x i8> %vrndp_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrndpq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vrndpq_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vrndpq_v1.i = call <4 x float> @llvm.ceil.v4f32(<4 x float> %vrndpq_v.i) # | %vrndpq_v2.i = bitcast <4 x float> %vrndpq_v1.i to <16 x i8> # | store <16 x i8> %vrndpq_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %2, ptr %__ret.i, align 8 # | %3 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrndx_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndx_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vrndx_v1.i = call <2 x float> @llvm.rint.v2f32(<2 x float> %vrndx_v.i) # | %vrndx_v2.i = bitcast <2 x float> %vrndx_v1.i to <8 x i8> # | store <8 x i8> %vrndx_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrndxq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vrndxq_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vrndxq_v1.i = call <4 x float> @llvm.rint.v4f32(<4 x float> %vrndxq_v.i) # | %vrndxq_v2.i = bitcast <4 x float> %vrndxq_v1.i to <16 x i8> # | store <16 x i8> %vrndxq_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %2, ptr %__ret.i, align 8 # | %3 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrnd_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrnd_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vrnd_v1.i = call <2 x float> @llvm.trunc.v2f32(<2 x float> %vrnd_v.i) # | %vrnd_v2.i = bitcast <2 x float> %vrnd_v1.i to <8 x i8> # | store <8 x i8> %vrnd_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrndq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x # | ... # `---data was truncated (10240/16447) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x00005654c353157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005654c352e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005654c3531cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7e23a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7e23aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7e23a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7e23a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005654c34c724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005654c34c7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005654c34abf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005654c315b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005654c315ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7e23a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7e23a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7e23a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005654c315ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c (1589 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16mf4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16mf2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m1_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m8_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f32mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f32m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f32m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv2f32.nxv4f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare # | ... # `---data was truncated (10240/68054) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b4fb53657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b4fb533515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b4fb536cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe350733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe35078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe350733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe35071b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b4fb4cc24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b4fb4cc096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b4fb4b0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b4fb160176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b4fb15fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe35071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe35071d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe35071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b4fb15fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c (1590 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f64m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 # | ... # `---data was truncated (10240/99178) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562f077f057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562f077ed515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562f077f0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7785333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f778538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7785333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f778531b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562f0778624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562f07786096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562f0776af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562f0741a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562f07419e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f778531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f778531d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f778531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562f07419d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c (1591 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, a # | ... # `---data was truncated (10240/222483) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c9769ae57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c9769ab515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c9769aecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7d45933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7d4598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7d45933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7d4591b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c97694424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c976944096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c976928f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c9765d8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c9765d7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7d4591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7d4591d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7d4591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c9765d7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c (1592 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | # | ... # `---data was truncated (10240/12216) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005615e3e5557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005615e3e52515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005615e3e55cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f18c2a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f18c2aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f18c2a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f18c2a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005615e3deb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005615e3deb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005615e3dcff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005615e3a7f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005615e3a7ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f18c2a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f18c2a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f18c2a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005615e3a7ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c (1593 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3e # | ... # `---data was truncated (10240/216250) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d9df02f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d9df02c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d9df02fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0912533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f091258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0912533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f091251b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d9defc524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d9defc5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d9defa9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d9dec59176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d9dec58e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f091251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f091251d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f091251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d9dec58d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c (1594 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr # | ... # `---data was truncated (10240/424049) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563bfcce457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563bfcce1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563bfcce4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbfe5933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbfe598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbfe5933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbfe591b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563bfcc7a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563bfcc7a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563bfcc5ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563bfc90e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563bfc90de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbfe591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbfe591d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbfe591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563bfc90dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c (1595 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv1i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv2i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv4i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv8i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, al # | ... # `---data was truncated (10240/225213) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056210227257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056210226f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562102272cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f119e01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f119e0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f119e01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f119e003507 abort ./stdlib/abort.c:85:3 # | #7 0x000056210220824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562102208096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005621021ecf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562101e9c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562101e9be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f119e004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f119e0050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f119e0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562101e9bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c (1596 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005638d23a657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005638d23a3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005638d23a6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa64d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa64d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa64d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa64d631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005638d233c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005638d233c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005638d2320f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005638d1fd0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005638d1fcfe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa64d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa64d6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa64d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005638d1fcfd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c (1597 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv32i8.nxv32i8.i64( %0, # | ... # `---data was truncated (10240/95081) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056374280657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563742803515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563742806cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f805c21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f805c2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f805c21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f805c203507 abort ./stdlib/abort.c:85:3 # | #7 0x000056374279c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056374279c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563742780f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563742430176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056374242fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f805c204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f805c2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f805c2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056374242fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c (1598 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_i32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_i32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_u32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_u32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32mf2x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c (1599 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c (1600 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_f64m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_i64m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_u64m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d0d77c557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d0d77c2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d0d77c5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7e0ae1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7e0ae725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7e0ae1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7e0ae03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d0d775b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d0d775b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d0d773ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d0d73ef176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d0d73eee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7e0ae04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7e0ae050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7e0ae050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d0d73eed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c (1601 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv1i64.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv2i64.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv4i64.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv8i64.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m8_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m1_tumu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c (1602 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | # | ... # `---data was truncated (10240/25616) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056528f4e457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056528f4e1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056528f4e4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7cbac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7cbaca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7cbac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7cbac31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056528f47a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056528f47a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056528f45ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056528f10e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056528f10de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7cbac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7cbac330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7cbac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056528f10dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c (1603 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16mf4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16mf2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m1_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m8_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f32mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f32m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv2f32.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f32m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv2f32.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv2f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define # | ... # `---data was truncated (10240/37564) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005558a125e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005558a125b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005558a125ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe0e6133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe0e618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe0e6133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe0e611b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005558a11f424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005558a11f4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005558a11d8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005558a0e88176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005558a0e87e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe0e611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe0e611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe0e611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005558a0e87d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c (1604 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.add # | ... # `---data was truncated (10240/424041) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ceba55257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ceba54f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ceba552cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f899cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f899cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f899cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f899cf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ceba4e824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ceba4e8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ceba4ccf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ceba17c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ceba17be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f899cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f899cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f899cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ceba17bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c (1605 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svset2_b_0( %tuple.coerce0, %tuple.coerce1, %x) #0 { # | entry: # | %tuple = alloca { , }, align 2 # | %tuple.addr = alloca { , }, align 2 # | %x.addr = alloca , align 2 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 2 # | %tuple1 = load { , }, ptr %tuple, align 2 # | store { , } %tuple1, ptr %tuple.addr, align 2 # | store %x, ptr %x.addr, align 2 # | %2 = load { , }, ptr %tuple.addr, align 2 # | %3 = load , ptr %x.addr, align 2 # | %4 = insertvalue { , } %2, %3, 0 # | ret { , } %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svset2_b_1( %tuple.coerce0, %tuple.coerce1, %x) #0 { # | entry: # | %tuple = alloca { , }, align 2 # | %tuple.addr = alloca { , }, align 2 # | %x.addr = alloca , align 2 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 2 # | %tuple1 = load { , }, ptr %tuple, align 2 # | store { , } %tuple1, ptr %tuple.addr, align 2 # | store %x, ptr %x.addr, align 2 # | %2 = load { , }, ptr %tuple.addr, align 2 # | %3 = load , ptr %x.addr, align 2 # | %4 = insertvalue { , } %2, %3, 1 # | ret { , } %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005636f249157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005636f248e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005636f2491cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7dece49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7decea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7dece49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7dece31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005636f242724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005636f2427096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005636f240bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005636f20bb176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005636f20bae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7dece32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7dece330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7dece330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005636f20bad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c (1606 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_i8mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef # | ... # `---data was truncated (10240/69988) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561aa9bfb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561aa9bf8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561aa9bfbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff8ea21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff8ea2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff8ea21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff8ea203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561aa9b9124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561aa9b91096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561aa9b75f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561aa9825176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561aa9824e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff8ea204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff8ea2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff8ea2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561aa9824d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c (1607 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv8i8.nxv8f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocall # | ... # `---data was truncated (10240/12425) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555d68cbe57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555d68cbb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555d68cbecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f43ac049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f43ac0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f43ac049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f43ac031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555d68c5424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555d68c54096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555d68c38f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555d688e8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555d688e7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f43ac032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f43ac0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f43ac0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555d688e7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm64_vcopy.c (1608 of 27911) ******************** TEST 'Clang :: CodeGen/arm64_vcopy.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c" # | target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-apple-ios7" # | # | ; Function Attrs: noinline nounwind # | define <16 x i8> @test_vcopyq_laneq_s8(<16 x i8> noundef %a1, <16 x i8> noundef %a2) #0 { # | entry: # | %a1.addr = alloca <16 x i8>, align 16 # | %a2.addr = alloca <16 x i8>, align 16 # | %__ret_336 = alloca <16 x i8>, align 16 # | %__s0_336 = alloca <16 x i8>, align 16 # | %__s2_336 = alloca <16 x i8>, align 16 # | %__ret = alloca <16 x i8>, align 16 # | %__s0 = alloca i8, align 1 # | %__ret1 = alloca i8, align 1 # | %__s02 = alloca <16 x i8>, align 16 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | %__s1 = alloca <16 x i8>, align 16 # | %ref.tmp3 = alloca <16 x i8>, align 16 # | %tmp4 = alloca <16 x i8>, align 16 # | %tmp5 = alloca <16 x i8>, align 16 # | store <16 x i8> %a1, ptr %a1.addr, align 16 # | store <16 x i8> %a2, ptr %a2.addr, align 16 # | %0 = load <16 x i8>, ptr %a1.addr, align 16 # | store <16 x i8> %0, ptr %__s0_336, align 16 # | %1 = load <16 x i8>, ptr %a2.addr, align 16 # | store <16 x i8> %1, ptr %__s2_336, align 16 # | %2 = load <16 x i8>, ptr %__s2_336, align 16 # | store <16 x i8> %2, ptr %__s02, align 16 # | %3 = load <16 x i8>, ptr %__s02, align 16 # | %vgetq_lane = extractelement <16 x i8> %3, i32 13 # | store i8 %vgetq_lane, ptr %ref.tmp, align 1 # | %4 = load i8, ptr %ref.tmp, align 1 # | store i8 %4, ptr %__ret1, align 1 # | %5 = load i8, ptr %__ret1, align 1 # | store i8 %5, ptr %tmp, align 1 # | %6 = load i8, ptr %tmp, align 1 # | store i8 %6, ptr %__s0, align 1 # | %7 = load <16 x i8>, ptr %__s0_336, align 16 # | store <16 x i8> %7, ptr %__s1, align 16 # | %8 = load i8, ptr %__s0, align 1 # | %9 = load <16 x i8>, ptr %__s1, align 16 # | %vset_lane = insertelement <16 x i8> %9, i8 %8, i32 3 # | store <16 x i8> %vset_lane, ptr %ref.tmp3, align 16 # | %10 = load <16 x i8>, ptr %ref.tmp3, align 16 # | store <16 x i8> %10, ptr %__ret, align 16 # | %11 = load <16 x i8>, ptr %__ret, align 16 # | store <16 x i8> %11, ptr %tmp4, align 16 # | %12 = load <16 x i8>, ptr %tmp4, align 16 # | store <16 x i8> %12, ptr %__ret_336, align 16 # | %13 = load <16 x i8>, ptr %__ret_336, align 16 # | store <16 x i8> %13, ptr %tmp5, align 16 # | %14 = load <16 x i8>, ptr %tmp5, align 16 # | ret <16 x i8> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define <16 x i8> @test_vcopyq_laneq_u8(<16 x i8> noundef %a1, <16 x i8> noundef %a2) #0 { # | entry: # | %a1.addr = alloca <16 x i8>, align 16 # | %a2.addr = alloca <16 x i8>, align 16 # | %__ret_328 = alloca <16 x i8>, align 16 # | %__s0_328 = alloca <16 x i8>, align 16 # | %__s2_328 = alloca <16 x i8>, align 16 # | %__ret = alloca <16 x i8>, align 16 # | %__s0 = alloca i8, align 1 # | %__ret1 = alloca i8, align 1 # | %__s02 = alloca <16 x i8>, align 16 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | %__s1 = alloca <16 x i8>, align 16 # | %ref.tmp3 = alloca <16 x i8>, align 16 # | %tmp4 = alloca <16 x i8>, align 16 # | %tmp5 = alloca <16 x i8>, align 16 # | store <16 x i8> %a1, ptr %a1.addr, align 16 # | store <16 x i8> %a2, ptr %a2.addr, align 16 # | %0 = load <16 x i8>, ptr %a1.addr, align 16 # | store <16 x i8> %0, ptr %__s0_328, align 16 # | %1 = load <16 x i8>, ptr %a2.addr, align 16 # | store <16 x i8> %1, ptr %__s2_328, align 16 # | %2 = load <16 x i8>, ptr %__s2_328, align 16 # | store <16 x i8> %2, ptr %__s02, align 16 # | %3 = load <16 x i8>, ptr %__s02, align 16 # | %vgetq_lane = extractelement <16 x i8> %3, i32 13 # | store i8 %vgetq_lane, ptr %ref.tmp, align 1 # | %4 = load i8, ptr %ref.tmp, align 1 # | store i8 %4, ptr %__ret1, align 1 # | %5 = load i8, ptr %__ret1, align 1 # | store i8 %5, ptr %tmp, align 1 # | %6 = load i8, ptr %tmp, align 1 # | store i8 %6, ptr %__s0, align 1 # | %7 = load <16 x i8>, ptr %__s0_328, align 16 # | store <16 x i8> %7, ptr %__s1, align 16 # | %8 = load i8, ptr %__s0, align 1 # | %9 = load <16 x i8>, ptr %__s1, align 16 # | %vset_lane = insertelement <16 x i8> %9, i8 %8, i32 3 # | store <16 x i8> %vset_lane, ptr %ref.tmp3, align 16 # | %10 = load <16 x i8>, ptr %ref.tmp3, align 16 # | store <16 x i8> %10, ptr %__ret, align 16 # | %11 = load <16 x i8>, ptr %__ret, align 16 # | store <16 x i8> %11, ptr %tmp4, align 16 # | %12 = load <16 x i8>, ptr %tmp4, align 16 # | store <16 x i8> %12, ptr %__ret_328, align 16 # | %13 = load <16 x i8>, ptr %__ret_328, align 16 # | store <16 x i8> %13, ptr %tmp5, align 16 # | %14 = load <16 x i8>, ptr %tmp5, align 16 # | ret <16 x i8> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i16> @test_vcopyq_laneq_s16(<8 x i16> noundef %a1, <8 x i16> noundef %a2) #0 { # | entry: # | %a1.addr = alloca <8 x i16>, align 16 # | %a2.addr = alloca <8 x i16>, align 16 # | %__ret_346 = alloca <8 x i16>, align 16 # | %__s0_346 = alloca <8 x i16>, align 16 # | %__s2_346 = alloca <8 x i16>, align 16 # | %__ret = alloca <8 x i16>, align 16 # | %__s0 = alloca i16, align 2 # | %__ret1 = alloca i16, align 2 # | %__s02 = alloca <8 x i16>, align 16 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | %__s1 = alloca <8 x i16>, align 16 # | %ref.tmp3 = alloca <8 x i16>, align 16 # | %tmp4 = alloca <8 x i16>, align 16 # | %tmp5 = alloca <8 x i16>, align 16 # | store <8 x i16> %a1, ptr %a1.addr, align 16 # | store <8 x i16> %a2, ptr %a2.addr, align 16 # | %0 = load <8 x i16>, ptr %a1.addr, align 16 # | store <8 x i16> %0, ptr %__s0_346, align 16 # | %1 = load <8 x i16>, ptr %a2.addr, align 16 # | store <8 x i16> %1, ptr %__s2_346, align 16 # | %2 = load <8 x i16>, ptr %__s2_346, align 16 # | store <8 x i16> %2, ptr %__s02, align 16 # | %3 = load <8 x i16>, ptr %__s02, align 16 # | %vgetq_lane = extractelement <8 x i16> %3, i32 7 # | store i16 %vgetq_lane, ptr %ref.tmp, align 2 # | %4 = load i16, ptr %ref.tmp, align 2 # | store i16 %4, ptr %__ret1, align 2 # | %5 = load i16, ptr %__ret1, align 2 # | store i16 %5, ptr %tmp, align 2 # | %6 = load i16, ptr %tmp, align 2 # | store i16 %6, ptr %__s0, align 2 # | %7 = load <8 x i16>, ptr %__s0_346, align 16 # | store <8 x i16> %7, ptr %__s1, align 16 # | %8 = load i16, ptr %__s0, align 2 # | %9 = load <8 x i16>, ptr %__s1, align 16 # | %vset_lane = insertelement <8 x i16> %9, i16 %8, i32 3 # | store <8 x i16> %vset_lane, ptr %ref.tmp3, align 16 # | %10 = load <8 x i16>, ptr %ref.tmp3, align 16 # | store <8 x i16> %10, ptr %__ret, align 16 # | %11 = load <8 x i16>, ptr %__ret, align 16 # | store <8 x i16> %11, ptr %tmp4, align 16 # | %12 = load <8 x i16>, ptr %tmp4, align 16 # | store <8 x i16> %12, ptr %__ret_346, align 16 # | %13 = load <8 x i16>, ptr %__ret_346, align 16 # | store <8 x i16> %13, ptr %tmp5, align 16 # | %14 = load <8 x i16>, ptr %tmp5, align 16 # | ret <8 x i16> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i16> @test_vcopyq_laneq_u16(<8 x i16> noundef %a1, <8 x i16> noundef %a2) #0 { # | entry: # | %a1.addr = alloca <8 x i16>, align 16 # | %a2.addr = alloca <8 x i16>, align 16 # | %__ret_334 = alloca <8 x i16>, align 16 # | %__s0_334 = alloca <8 x i16>, align 16 # | %__s2_334 = alloca <8 x i16>, align 16 # | %__ret = alloca <8 x i16>, align 16 # | %__s0 = alloca i16, align 2 # | %__ret1 = alloca i16, align 2 # | %__s02 = alloca <8 x i16>, align 16 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | %__s1 = alloca <8 x i16>, align 16 # | %ref.tmp3 = alloca <8 x i16>, align 16 # | %tmp4 = alloca <8 x i16>, align 16 # | %tmp5 = alloca <8 x i16>, align 16 # | store <8 x i16> %a1, ptr %a1.addr, align 16 # | store <8 x i16> %a2, ptr %a2.addr, align 16 # | %0 = load <8 x i16>, ptr %a1.addr, align 16 # | store <8 x i16> %0, ptr %__s0_334, align 16 # | %1 = load <8 x i16>, ptr %a2.addr, align 16 # | store <8 x i16> %1, ptr %__s2_334, align 16 # | %2 = load <8 x i16>, ptr %__s2_334, align 16 # | store <8 x i16> %2, ptr %__s02, align 16 # | %3 = load <8 x i16>, ptr %__s02, align 16 # | %vgetq_lane = extractelement <8 x i16> %3, i32 7 # | store i16 %vgetq_lane, ptr %ref.tmp, align 2 # | %4 = load i16, ptr %ref.tmp, align 2 # | store i16 %4, ptr %__ret1, align 2 # | %5 = load i16, ptr %__ret1, align 2 # | store i16 %5, ptr %tmp, align 2 # | %6 = load i16, ptr %tmp, align 2 # | store i16 %6, ptr %__s0, align 2 # | %7 = load <8 x i16>, ptr %__s0_334, align 16 # | store <8 x i16> %7, ptr %__s1, align 16 # | %8 = load i16, ptr %__s0, align 2 # | %9 = load <8 x i16>, ptr %__s1, align 16 # | %vset_lane = insertelement <8 x i16> %9, i16 %8, i32 3 # | store <8 x i16> %vset_lane, ptr %ref.tmp3, align 16 # | %10 = load <8 x i16>, ptr %ref.tmp3, align 16 # | store <8 x i16> %10, ptr %__ret, align 16 # | %11 = load <8 x i16>, ptr %__ret, align 16 # | store <8 x i16> %11, ptr %tmp4, align 16 # | %12 = load <8 x i16>, ptr %tmp4, align 16 # | store <8 x i16> %12, ptr %__ret_334, align 16 # | %13 = load <8 x i16>, ptr %__ret_334, align 16 # | store <8 x i16> %13, ptr %tmp5, align 16 # | %14 = load <8 x i16>, ptr %tmp5, align 16 # | ret <8 x i16> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define <4 x i32> @test_vcopyq_laneq_s32(<4 x i32> noundef %a1, <4 x i32> noundef %a2) #0 { # | entry: # | %a1.addr = alloca <4 x i32>, align 16 # | %a2.addr = alloca <4 x i32>, align 16 # | %__ret_340 = alloca <4 x i32>, align 16 # | %__s0_340 = alloca <4 x i32>, align 16 # | %__s2_340 = alloca <4 x i32>, align 16 # | %__ret = alloca <4 x i32>, align 16 # | %__s0 = alloca i32, align 4 # | %__ret1 = alloca i32, align 4 # | %__s02 = alloca <4 x i32>, align 16 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | %__s1 = alloca <4 x i32>, align 16 # | %ref.tmp3 = alloca <4 x i32>, align 16 # | %tmp4 = alloca <4 x i32>, align 16 # | %tmp5 = alloca <4 x i32>, align 16 # | store <4 x i32> %a1, ptr %a1.addr, align 16 # | store <4 x i32> %a2, ptr %a2.addr, align 16 # | %0 = load <4 x i32>, ptr %a1.addr, align 16 # | store <4 x i32> %0, ptr %__s0_340, align 16 # | %1 = load <4 x i32>, ptr %a2.addr, align 16 # | store <4 x i32> %1, ptr %__s2_340, align 16 # | %2 = load <4 x i32>, ptr %__s2_340, align 16 # | store <4 x i32> %2, ptr %__s02, align 16 # | %3 = load <4 x i32>, ptr %__s02, align 16 # | %vgetq_lane = extractelement <4 x i32> %3, i32 3 # | store i32 %vgetq_lane, ptr %ref.tmp, align 4 # | %4 = load i32, ptr %ref.tmp, align 4 # | store i32 %4, ptr %__ret1, align 4 # | %5 = load i32, ptr %__ret1, align 4 # | store i32 %5, ptr %tmp, align 4 # | %6 = load i32, ptr %tmp, align 4 # | store i32 %6, ptr %__s0, align 4 # | %7 = load <4 x i32> # | ... # `---data was truncated (10240/22011) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b4e2bdd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b4e2bda515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b4e2bddcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f458c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f458c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f458c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f458c11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b4e2b7324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b4e2b73096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b4e2b57f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b4e2807176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b4e2806e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f458c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f458c11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f458c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b4e2806d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c (1609 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_i8mf8x8 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ec16d2857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ec16d25515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ec16d28cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f722dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f722dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f722dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f722dd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ec16cbe24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ec16cbe096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ec16ca2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ec16952176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ec16951e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f722dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f722dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f722dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ec16951d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c (1610 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16mf4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16mf2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m1_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m8_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f32mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f32m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv2f32.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f32m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv2f32.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv2f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_loc # | ... # `---data was truncated (10240/37556) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564929b6757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564929b64515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564929b67cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f35df733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f35df78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f35df733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f35df71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564929afd24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564929afd096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564929ae1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564929791176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564929790e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f35df71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f35df71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f35df71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564929790d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c (1611 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_i8mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef # | ... # `---data was truncated (10240/69988) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560e0588857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560e05885515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560e05888cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f734f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f734f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f734f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f734f231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560e0581e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560e0581e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560e05802f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560e054b2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560e054b1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f734f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f734f2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f734f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560e054b1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c (1612 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bb3267757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bb32674515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bb32677cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f13e601bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f13e60725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f13e601ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f13e6003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bb3260d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bb3260d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bb325f1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bb322a1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bb322a0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f13e6004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f13e60050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f13e60050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bb322a0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vhaddq.c (1613 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vhaddq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhaddq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vhadd.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vhadd.v16i8(<16 x i8>, <16 x i8>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhaddq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vhadd.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vhadd.v8i16(<8 x i16>, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhaddq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vhadd.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vhadd.v4i32(<4 x i32>, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhaddq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.hadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.hadd.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhaddq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.hadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.hadd.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhaddq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.hadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.hadd.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhaddq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.hadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhaddq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.hadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhaddq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.hadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhaddq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = call <16 x i8> @llvm.arm.mve.vhadd.v16i8(<16 x i8> %0, <16 x i8> %.splat, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhaddq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = call <8 x i16> @llvm.arm.mve.vhadd.v8i16(<8 x i16> %0, <8 x i16> %.splat, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhaddq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> # | ... # `---data was truncated (10240/16951) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560f77b6457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560f77b61515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560f77b64cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9083733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f908378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9083733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f908371b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560f77afa24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560f77afa096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560f77adef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560f7778e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560f7778de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f908371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f908371d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f908371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560f7778dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c (1614 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nx # | ... # `---data was truncated (10240/18660) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555fcb8e557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555fcb8e2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555fcb8e5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdbda133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdbda18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdbda133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdbda11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555fcb87b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555fcb87b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555fcb85ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555fcb50f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555fcb50ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fdbda11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdbda11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdbda11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555fcb50ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c (1615 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0. # | ... # `---data was truncated (10240/82975) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fa3eb6257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fa3eb5f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fa3eb62cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f23e1a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f23e1aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f23e1a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f23e1a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fa3eaf824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fa3eaf8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fa3eadcf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fa3e78c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fa3e78be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f23e1a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f23e1a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f23e1a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fa3e78bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c (1616 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d89962357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d899620515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d899623cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8a52b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8a52b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8a52b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8a52aed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d8995b924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d8995b9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d89959df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d89924d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d89924ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8a52aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8a52aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8a52aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d89924cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c (1617 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e9e456257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e9e455f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e9e4562cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1764d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1764d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1764d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1764ced507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e9e44f824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e9e44f8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e9e44dcf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e9e418c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e9e418be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1764ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1764cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1764cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e9e418bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-neon-dot-product.c (1618 of 27911) ******************** TEST 'Clang :: CodeGen/arm-neon-dot-product.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-linux-gnueabihf -target-cpu cortex-a75 -target-feature +dotprod -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-linux-gnueabihf -target-cpu cortex-a75 -target-feature +dotprod -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8-unknown-linux-gnueabihf" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vdot_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %c.addr = alloca <8 x i8>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | store <8 x i8> %c, ptr %c.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | %2 = load <8 x i8>, ptr %c.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | store <8 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vdot.i = bitcast <8 x i8> %3 to <2 x i32> # | %vdot1.i = call <2 x i32> @llvm.arm.neon.udot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %4, <8 x i8> %5) # | store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vdotq_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 8 # | %__p1.addr.i = alloca <16 x i8>, align 8 # | %__p2.addr.i = alloca <16 x i8>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | store <4 x i32> %0, ptr %__p0.addr.i, align 8 # | store <16 x i8> %1, ptr %__p1.addr.i, align 8 # | store <16 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 8 # | %vdot.i = bitcast <16 x i8> %3 to <4 x i32> # | %vdot1.i = call <4 x i32> @llvm.arm.neon.udot.v4i32.v16i8(<4 x i32> %vdot.i, <16 x i8> %4, <16 x i8> %5) # | store <4 x i32> %vdot1.i, ptr %ref.tmp.i, align 8 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 8 # | store <4 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <4 x i32>, ptr %__ret.i, align 8 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vdot_s32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %c.addr = alloca <8 x i8>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | store <8 x i8> %c, ptr %c.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | %2 = load <8 x i8>, ptr %c.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | store <8 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vdot.i = bitcast <8 x i8> %3 to <2 x i32> # | %vdot1.i = call <2 x i32> @llvm.arm.neon.sdot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %4, <8 x i8> %5) # | store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vdotq_s32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 8 # | %__p1.addr.i = alloca <16 x i8>, align 8 # | %__p2.addr.i = alloca <16 x i8>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | store <4 x i32> %0, ptr %__p0.addr.i, align 8 # | store <16 x i8> %1, ptr %__p1.addr.i, align 8 # | store <16 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 8 # | %vdot.i = bitcast <16 x i8> %3 to <4 x i32> # | %vdot1.i = call <4 x i32> @llvm.arm.neon.sdot.v4i32.v16i8(<4 x i32> %vdot.i, <16 x i8> %4, <16 x i8> %5) # | store <4 x i32> %vdot1.i, ptr %ref.tmp.i, align 8 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 8 # | store <4 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <4 x i32>, ptr %__ret.i, align 8 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vdot_lane_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %c.addr = alloca <8 x i8>, align 8 # | %__ret_831 = alloca <2 x i32>, align 8 # | %__s0_831 = alloca <2 x i32>, align 8 # | %__s1_831 = alloca <8 x i8>, align 8 # | %__s2_831 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <2 x i32>, align 8 # | %__ret = alloca <2 x i32>, align 8 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp1 = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x i32>, align 8 # | %tmp2 = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | store <8 x i8> %c, ptr %c.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__s0_831, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %1, ptr %__s1_831, align 8 # | %2 = load <8 x i8>, ptr %c.addr, align 8 # | store <8 x i8> %2, ptr %__s2_831, align 8 # | %3 = load <2 x i32>, ptr %__s0_831, align 8 # | %4 = load <8 x i8>, ptr %__s1_831, align 8 # | %5 = load <2 x i32>, ptr %__s2_831, align 8 # | store <2 x i32> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x i32> # | %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> # | store <2 x i32> %lane, ptr %ref.tmp1, align 8 # | %8 = load <2 x i32>, ptr %ref.tmp1, align 8 # | store <2 x i32> %8, ptr %__ret, align 8 # | %9 = load <2 x i32>, ptr %__ret, align 8 # | store <2 x i32> %9, ptr %tmp, align 8 # | %10 = load <2 x i32>, ptr %tmp, align 8 # | store <2 x i32> %10, ptr %ref.tmp, align 8 # | %11 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <2 x i32> %3, ptr %__p0.addr.i, align 8 # | store <8 x i8> %4, ptr %__p1.addr.i, align 8 # | store <8 x i8> %11, ptr %__p2.addr.i, align 8 # | %12 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %13 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %14 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vdot.i = bitcast <8 x i8> %12 to <2 x i32> # | %vdot1.i = call <2 x i32> @llvm.arm.neon.udot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %13, <8 x i8> %14) # | store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8 # | %15 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %15, ptr %__ret.i, align 8 # | %16 = load <2 x i32>, ptr %__ret.i, align 8 # | store <2 x i32> %16, ptr %__ret_831, align 8 # | %17 = load <2 x i32>, ptr %__ret_831, align 8 # | store <2 x i32> %17, ptr %tmp2, align 8 # | %18 = load <2 x i32>, ptr %tmp2, align 8 # | ret <2 x i32> %18 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vdotq_lane_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <8 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 8 # | %__p1.addr.i = alloca <16 x i8>, align 8 # | %__p2.addr.i = alloca <16 x i8>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <8 x i8>, align 8 # | %__ret_827 = alloca <4 x i32>, align 8 # | %__s0_827 = alloca <4 x i32>, align 8 # | %__s1_827 = alloca <16 x i8>, align 8 # | %__s2_827 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <4 x i32>, align 8 # | %__ret = alloca <4 x i32>, align 8 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp1 = alloca <16 x i8>, align 8 # | %tmp = alloca <4 x i32>, align 8 # | %tmp2 = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <8 x i8> %c, ptr %c.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | store <4 x i32> %0, ptr %__s0_827, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | store <16 x i8> %1, ptr %__s1_827, align 8 # | %2 = load <8 x i8>, ptr %c.addr, align 8 # | store <8 x i8> %2, ptr %__s2_827, align 8 # | %3 = load <4 x i32>, ptr %__s0_827, align 8 # | %4 = load <16 x i8>, ptr %__s1_827, align 8 # | %5 = load <2 x i32>, ptr %__s2_827, align 8 # | store <2 x i32> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x i32> # | %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <4 x i32> ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c (1619 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv32i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv32i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vx_u8m4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics.c (1620 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vcgezh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %2 = fcmp oge half %1, 0.000000e+00 # | %vcgez = sext i1 %2 to i16 # | store i16 %vcgez, ptr %ref.tmp, align 2 # | %3 = load i16, ptr %ref.tmp, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | ret i16 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vcgtzh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %2 = fcmp ogt half %1, 0.000000e+00 # | %vcgtz = sext i1 %2 to i16 # | store i16 %vcgtz, ptr %ref.tmp, align 2 # | %3 = load i16, ptr %ref.tmp, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | ret i16 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vclezh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %2 = fcmp ole half %1, 0.000000e+00 # | %vclez = sext i1 %2 to i16 # | store i16 %vclez, ptr %ref.tmp, align 2 # | %3 = load i16, ptr %ref.tmp, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | ret i16 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vcltzh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %2 = fcmp olt half %1, 0.000000e+00 # | %vcltz = sext i1 %2 to i16 # | store i16 %vcltz, ptr %ref.tmp, align 2 # | %3 = load i16, ptr %ref.tmp, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | ret i16 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_s16(i16 noundef %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca i16, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | store i16 %0, ptr %__s0, align 2 # | %1 = load i16, ptr %__s0, align 2 # | %2 = sitofp i16 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_s32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %__ret = alloca half, align 2 # | %__s0 = alloca i32, align 4 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__s0, align 4 # | %1 = load i32, ptr %__s0, align 4 # | %2 = sitofp i32 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_s64(i64 noundef %a) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %__ret = alloca half, align 2 # | %__s0 = alloca i64, align 8 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i64 %a, ptr %a.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | store i64 %0, ptr %__s0, align 8 # | %1 = load i64, ptr %__s0, align 8 # | %2 = sitofp i64 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_u16(i16 noundef %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca i16, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | store i16 %0, ptr %__s0, align 2 # | %1 = load i16, ptr %__s0, align 2 # | %2 = uitofp i16 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_u32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %__ret = alloca half, align 2 # | %__s0 = alloca i32, align 4 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__s0, align 4 # | %1 = load i32, ptr %__s0, align 4 # | %2 = uitofp i32 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_u64(i64 noundef %a) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %__ret = alloca half, align 2 # | %__s0 = alloca i64, align 8 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i64 %a, ptr %a.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | store i64 %0, ptr %__s0, align 8 # | %1 = load i64, ptr %__s0, align 8 # | %2 = uitofp i64 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vcvth_s16_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %vcvth_s16_f16 = call i16 @llvm.fptosi.sat.i16.f16(half %1) # | store i16 %vcvth_s16_f16, ptr %ref.tmp, align 2 # | %2 = load i16, ptr %ref.tmp, align 2 # | store i16 %2, ptr %__ret, align 2 # | %3 = load i16, ptr %__ret, align 2 # | store i16 %3, ptr %tmp, align 2 # | %4 = load i16, ptr %tmp, align 2 # | ret i16 %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.fptosi.sat.i16.f16(half) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_vcvth_s32_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i32, align 4 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %vcvth_s32_f16 = call i32 @llvm.fptosi.sat.i32.f16(half %1) # | store i32 %vcvth_s32_f16, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.fptosi.sat.i32.f16(half) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_vcvth_s64_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i64, align 8 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i64, align 8 # | %tmp = alloca i64, align 8 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %vcvth_s64_f16 = call i64 @llvm.fptosi.sat.i64.f16(half %1) # | store i64 %vcvth_s64_f16, ptr %ref.tmp, align 8 # | %2 = load i64, ptr %ref.tmp, align 8 # | store i64 %2, ptr %__ret, align 8 # | %3 = load i64, ptr %__ret, align 8 # | store i64 %3, ptr %tmp, align 8 # | %4 = load i64, ptr %tmp, align 8 # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.fptosi.sat.i64.f16(half) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vcvth_u16_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | st # | ... # `---data was truncated (10240/53064) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559ef60f457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559ef60f1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559ef60f4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8d5f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8d5f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8d5f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8d5f71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559ef608a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559ef608a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559ef606ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559ef5d1e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559ef5d1de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8d5f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8d5f71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8d5f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559ef5d1dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c (1621 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m4_tu( %maskedoff, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c (1622 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv2f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv4f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv8f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv16f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv32f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv2f32.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv4f32.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv8f32.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv16f32.nxv8f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv16f32.nxv8f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f64m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align # | ... # `---data was truncated (10240/102872) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055777f07557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055777f072515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055777f075cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9af8f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9af8f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9af8f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9af8eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055777f00b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055777f00b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055777efeff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055777ec9f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055777ec9ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9af8eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9af8eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9af8eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055777ec9ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c (1623 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1f64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2f64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4f64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8f64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,10 # | ... # `---data was truncated (10240/48393) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e9e5eba57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e9e5eb7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e9e5ebacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f568eb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f568eb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f568eb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f568eaed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e9e5e5024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e9e5e50096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e9e5e34f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e9e5ae4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e9e5ae3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f568eaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f568eaef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f568eaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e9e5ae3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c (1624 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_f64m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_i64m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_u64m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_f64m1x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_i64m1x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_u64m1x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055904363c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559043639515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055904363ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb804c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb804c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb804c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb804c03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005590435d224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005590435d2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005590435b6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559043266176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559043265e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb804c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb804c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb804c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559043265d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c (1625 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, a # | ... # `---data was truncated (10240/222483) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056019cf0b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056019cf08515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056019cf0bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f08dc449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f08dc4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f08dc449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f08dc431507 abort ./stdlib/abort.c:85:3 # | #7 0x000056019cea124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056019cea1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056019ce85f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056019cb35176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056019cb34e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f08dc432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f08dc4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f08dc4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056019cb34d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c (1626 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16mf4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv32f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv32f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16mf4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16i16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, ali # | ... # `---data was truncated (10240/33772) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055571e5b257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055571e5af515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055571e5b2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd0f8849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd0f88a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd0f8849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd0f8831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055571e54824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055571e548096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055571e52cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055571e1dc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055571e1dbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd0f8832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd0f88330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd0f88330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055571e1dbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c (1627 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_u8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv # | ... # `---data was truncated (10240/68225) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056480079f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056480079c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056480079fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff05bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff05bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff05bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff05bf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056480073524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564800735096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564800719f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005648003c9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005648003c8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff05bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff05bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff05bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005648003c8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c (1628 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.ris # | ... # `---data was truncated (10240/60220) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005590090f757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005590090f4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005590090f7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4c21e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4c21ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4c21e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4c21e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055900908d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055900908d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559009071f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559008d21176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559008d20e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4c21e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4c21e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4c21e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559008d20d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c (1629 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf8_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = loa # | ... # `---data was truncated (10240/415311) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055887ce5f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055887ce5c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055887ce5fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f395bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f395bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f395bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f395bb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055887cdf524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055887cdf5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055887cdd9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055887ca89176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055887ca88e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f395bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f395bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f395bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055887ca88d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c (1630 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_i8mf8x6 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056529ca9f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056529ca9c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056529ca9fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1738933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f173898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1738933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f173891b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056529ca3524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056529ca35096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056529ca19f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056529c6c9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056529c6c8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f173891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f173891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f173891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056529c6c8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c (1631 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m4( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c (1632 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_i64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_i64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_u64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_u64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m1x4_tum( %mask, target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m2x4_tum( %mask, target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, # | ... # `---data was truncated (10240/32133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556e219b657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556e219b3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556e219b6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f14b9533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f14b958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f14b9533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f14b951b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556e2194c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556e2194c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556e21930f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556e215e0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556e215dfe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f14b951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f14b951d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f14b951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556e215dfd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/neon-3v.c (1633 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon-3v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vand_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %and.i = and <8 x i8> %2, %3 # | store <8 x i8> %and.i, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vandq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | %1 = load <16 x i8>, ptr %b.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %and.i = and <16 x i8> %2, %3 # | store <16 x i8> %and.i, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vand_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %and.i = and <4 x i16> %2, %3 # | store <4 x i16> %and.i, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vandq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | store <8 x i16> %b, ptr %b.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | %1 = load <8 x i16>, ptr %b.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | store <8 x i16> %1, ptr %__p1.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %3 = load <8 x i16>, ptr %__p1.addr.i, align 16 # | %and.i = and <8 x i16> %2, %3 # | store <8 x i16> %and.i, ptr %__ret.i, align 16 # | %4 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vand_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <2 x i32> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | %1 = load <2 x i32>, ptr %b.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %and.i = and <2 x i32> %2, %3 # | store <2 x i32> %and.i, ptr %__ret.i, align 8 # | %4 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vandq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | %b.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | store <4 x i32> %b, ptr %b.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | %1 = load <4 x i32>, ptr %b.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | store <4 x i32> %1, ptr %__p1.addr.i, align 16 # | %2 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %3 = load <4 x i32>, ptr %__p1.addr.i, align 16 # | %and.i = and <4 x i32> %2, %3 # | store <4 x i32> %and.i, ptr %__ret.i, align 16 # | %4 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vand_s64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | %1 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <1 x i64>, ptr %__p0.addr.i, align 8 # | %3 = load <1 x i64>, ptr %__p1.addr.i, align 8 # | %and.i = and <1 x i64> %2, %3 # | store <1 x i64> %and.i, ptr %__ret.i, align 8 # | %4 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vandq_s64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__p1.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %a.addr = alloca <2 x i64>, align 16 # | %b.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | store <2 x i64> %1, ptr %__p1.addr.i, align 16 # | %2 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %3 = load <2 x i64>, ptr %__p1.addr.i, align 16 # | %and.i = and <2 x i64> %2, %3 # | store <2 x i64> %and.i, ptr %__ret.i, align 16 # | %4 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vand_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %and.i = and <8 x i8> %2, %3 # | store <8 x i8> %and.i, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vandq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | %1 = load <16 x i8>, ptr %b.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %and.i = and <16 x i8> %2, %3 # | store <16 x i8> %and.i, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vand_u16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %and.i = and <4 x i16> %2, %3 # | store <4 x i16> %and.i, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vandq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | store <8 x i16> %b, ptr %b.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | %1 = load <8 x i16>, ptr %b.addr, al # | ... # `---data was truncated (10240/70553) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560b3150e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560b3150b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560b3150ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe724249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe7242a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe724249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe724231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560b314a424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560b314a4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560b31488f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560b31138176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560b31137e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe724232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe7242330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe7242330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560b31137d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c (1634 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e1b882157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e1b881e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e1b8821cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe5cbc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe5cbca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe5cbc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe5cbc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e1b87b724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e1b87b7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e1b879bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e1b844b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e1b844ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe5cbc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe5cbc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe5cbc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e1b844ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c (1635 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16mf4x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16mf2x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16m1x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16m1x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005626c032157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005626c031e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005626c0321cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f477701bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f47770725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f477701ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4777003507 abort ./stdlib/abort.c:85:3 # | #7 0x00005626c02b724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005626c02b7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005626c029bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005626bff4b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005626bff4ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4777004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f47770050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f47770050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005626bff4ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c (1636 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16m2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op # | ... # `---data was truncated (10240/154517) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563a1deb057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563a1dead515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563a1deb0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc7c0449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc7c04a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc7c0449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc7c0431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563a1de4624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563a1de46096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563a1de2af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563a1dada176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563a1dad9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc7c0432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc7c04330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc7c04330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563a1dad9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c (1637 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/225655) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564be716557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564be7162515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564be7165cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f59bc533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f59bc58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f59bc533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f59bc51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564be70fb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564be70fb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564be70dff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564be6d8f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564be6d8ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f59bc51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f59bc51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f59bc51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564be6d8ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c (1638 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_f16mf4x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_f16mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_f16m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_i16mf4x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_i16mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_i16m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_u16mf4x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_u16mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_u16m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_f16mf4x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.ri # | ... # `---data was truncated (10240/20449) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555ebfb1157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555ebfb0e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555ebfb11cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6ed5b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6ed5b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6ed5b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6ed5b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555ebfaa724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555ebfaa7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555ebfa8bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555ebf73b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555ebf73ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6ed5b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6ed5b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6ed5b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555ebf73ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c (1639 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv64i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv64i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv32i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv32i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv16i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv16i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv8i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv8i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b16(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv4i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv4i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b32(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv2i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv2i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b64(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv1i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv1i1.p0.i64(, ptr captures(none), i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bc1985657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bc19853515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bc19856cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4be1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4be178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4be1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4be171b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bc197ec24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bc197ec096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bc197d0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bc19480176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bc1947fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4be171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4be171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4be171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bc1947fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c (1640 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv16f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv32f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv32f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8i16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, pt # | ... # `---data was truncated (10240/71947) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ae69e5a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ae69e57515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ae69e5acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9ed361bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9ed36725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9ed361ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9ed3603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ae69df024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ae69df0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ae69dd4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ae69a84176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ae69a83e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9ed3604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9ed36050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9ed36050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ae69a83d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c (1641 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | # | ... # `---data was truncated (10240/424835) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562c9006f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562c9006c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562c9006fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb2f541bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb2f54725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb2f541ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb2f5403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562c9000524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562c90005096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562c8ffe9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562c8fc99176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562c8fc98e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb2f5404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb2f54050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb2f54050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562c8fc98d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c (1642 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv64i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv32i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv16i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv8i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv4i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv2i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv1i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fdca14f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fdca14c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fdca14fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fddbec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fddbeca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fddbec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fddbec31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fdca0e524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fdca0e5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fdca0c9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fdc9d79176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fdc9d78e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fddbec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fddbec330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fddbec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fdc9d78d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c (1643 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005638b835a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005638b8357515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005638b835acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9ba5305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9ba535c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9ba5305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9ba52ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005638b82f024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005638b82f0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005638b82d4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005638b7f84176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005638b7f83e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9ba52eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9ba52ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9ba52ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005638b7f83d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c (1644 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16mf4_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16mf4_f32mf2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16mf2_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16mf2_f32m1_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16m1_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16m1_f32m2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16m2_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16m2_f32m4_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llv # | ... # `---data was truncated (10240/101576) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055893dd9d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055893dd9a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055893dd9dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f20a1133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f20a118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f20a1133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f20a111b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055893dd3324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055893dd33096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055893dd17f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055893d9c7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055893d9c6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f20a111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f20a111d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f20a111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055893d9c6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c (1645 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv16f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv16f16.f16.i64( poison, %0, ha # | ... # `---data was truncated (10240/125649) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e20f94a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e20f947515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e20f94acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd2d121bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd2d12725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd2d121ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd2d1203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e20f8e024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e20f8e0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e20f8c4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e20f574176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e20f573e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd2d1204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd2d12050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd2d12050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e20f573d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c (1646 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_i64m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_i64m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_u64m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_u64m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_i64m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_i64m2x4_m(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c (1647 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16mf4x7(ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16mf2x7(ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16m1x7(ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16m1x7_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b628fbe57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b628fbb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b628fbecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7bbbd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7bbbd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7bbbd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7bbbd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b628f5424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b628f54096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b628f38f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b628be8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b628be7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7bbbd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7bbbd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7bbbd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b628be7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c (1648 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e1 # | ... # `---data was truncated (10240/63053) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c1ae52857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c1ae525515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c1ae528cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9689133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f968918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9689133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f968911b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c1ae4be24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c1ae4be096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c1ae4a2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c1ae152176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c1ae151e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f968911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f968911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f968911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c1ae151d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c (1649 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_i8mf8x7_tu(target("riscv.vector.tuple", , 7) %m # | ... # `---data was truncated (10240/160133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562cf7fac57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562cf7fa9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562cf7faccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f130f449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f130f4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f130f449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f130f431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562cf7f4224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562cf7f42096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562cf7f26f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562cf7bd6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562cf7bd5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f130f432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f130f4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f130f4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562cf7bd5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c (1650 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32m2x3_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c (1651 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_f64m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_i64m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_u64m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_f64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_i64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_u64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005565d1f2557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005565d1f22515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005565d1f25cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6a7b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6a7b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6a7b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6a7b231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005565d1ebb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005565d1ebb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005565d1e9ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005565d1b4f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005565d1b4ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6a7b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6a7b2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6a7b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005565d1b4ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c (1652 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.r # | ... # `---data was truncated (10240/65582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d9cef1457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d9cef11515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d9cef14cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9c81933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9c8198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9c81933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9c8191b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d9ceeaa24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d9ceeaa096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d9cee8ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d9ceb3e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d9ceb3de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9c8191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9c8191d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9c8191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d9ceb3dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c (1653 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32m2x4_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c (1654 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b1_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv64i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b2_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv32i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b4_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv16i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b8_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv8i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b16_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv4i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv4i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b32_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv2i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv2i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b64_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv1i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv1i1.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c06b93957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c06b936515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c06b939cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb35c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb35c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb35c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb35c11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c06b8cf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c06b8cf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c06b8b3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c06b563176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c06b562e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb35c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb35c11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb35c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c06b562d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c (1655 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv16f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv16f16.f16.i64( poison, %0, ha # | ... # `---data was truncated (10240/125649) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bd92dda57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bd92dd7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bd92ddacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0f71505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0f7155c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0f71505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0f714ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bd92d7024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bd92d70096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bd92d54f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bd92a04176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bd92a03e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0f714eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0f714ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0f714ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bd92a03d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c (1656 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf4_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf2_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m1_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m2_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m4_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m8_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { , i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0( %1, ptr %2, %0, i64 %4, i64 2) # | %6 = extractvalue { , i64 } %5, 0 # | %7 = extractvalue { , i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { , i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c (1657 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16mf4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f64m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/atomic-hint-template.cpp (1658 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/atomic-hint-template.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple aarch64-none-elf -target-feature +v9.4a -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple aarch64-none-elf -target-feature +v9.4a -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-unknown-none-elf" # | # | $_Z37test_atomic_store_hint_template_orderILj3EEvPii = comdat any # | # | $_Z36test_atomic_store_hint_template_hintILj1EEvPii = comdat any # | # | $_Z37test_atomic_fetch_hint_template_orderILj2EEiPii = comdat any # | # | $_Z36test_atomic_fetch_hint_template_hintILj4EEiPii = comdat any # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define weak_odr void @_Z37test_atomic_store_hint_template_orderILj3EEvPii(ptr noundef %ptr, i32 noundef %val) #0 comdat { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %val.addr = alloca i32, align 4 # | store ptr %ptr, ptr %ptr.addr, align 8 # | store i32 %val, ptr %val.addr, align 4 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i32, ptr %val.addr, align 4 # | store atomic i32 %1, ptr %0 release, align 4, !mem.cache_hint !4 # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define weak_odr void @_Z36test_atomic_store_hint_template_hintILj1EEvPii(ptr noundef %ptr, i32 noundef %val) #0 comdat { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %val.addr = alloca i32, align 4 # | store ptr %ptr, ptr %ptr.addr, align 8 # | store i32 %val, ptr %val.addr, align 4 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i32, ptr %val.addr, align 4 # | store atomic i32 %1, ptr %0 seq_cst, align 4, !mem.cache_hint !6 # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local void @_Z43test_atomic_store_hint_array_consexpr_orderPii(ptr noundef %ptr, i32 noundef %value) #0 { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %value.addr = alloca i32, align 4 # | store ptr %ptr, ptr %ptr.addr, align 8 # | store i32 %value, ptr %value.addr, align 4 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i32, ptr %value.addr, align 4 # | store atomic i32 %1, ptr %0 monotonic, align 4, !mem.cache_hint !4 # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local void @_Z42test_atomic_store_hint_array_consexpr_hintPii(ptr noundef %ptr, i32 noundef %value) #0 { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %value.addr = alloca i32, align 4 # | store ptr %ptr, ptr %ptr.addr, align 8 # | store i32 %value, ptr %value.addr, align 4 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i32, ptr %value.addr, align 4 # | store atomic i32 %1, ptr %0 monotonic, align 4, !mem.cache_hint !6 # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define weak_odr noundef i32 @_Z37test_atomic_fetch_hint_template_orderILj2EEiPii(ptr noundef %ptr, i32 noundef %val) #0 comdat { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %val.addr = alloca i32, align 4 # | store ptr %ptr, ptr %ptr.addr, align 8 # | store i32 %val, ptr %val.addr, align 4 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i32, ptr %val.addr, align 4 # | %2 = atomicrmw add ptr %0, i32 %1 acquire, align 4, !mem.cache_hint !8 # | ret i32 %2 # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define weak_odr noundef i32 @_Z36test_atomic_fetch_hint_template_hintILj4EEiPii(ptr noundef %ptr, i32 noundef %val) #0 comdat { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %val.addr = alloca i32, align 4 # | store ptr %ptr, ptr %ptr.addr, align 8 # | store i32 %val, ptr %val.addr, align 4 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i32, ptr %val.addr, align 4 # | %2 = atomicrmw xor ptr %0, i32 %1 seq_cst, align 4, !mem.cache_hint !10 # | ret i32 %2 # | } # | # | attributes #0 = { mustprogress noinline nounwind vscale_range(1,16) "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+bti,+ccidx,+complxnum,+crc,+cssc,+dit,+dotprod,+flagm,+fp-armv8,+fullfp16,+hbc,+i8mm,+jsconv,+lse,+mec,+mops,+neon,+pauth,+predres,+ras,+rasv2,+rcpc,+rdm,+rme,+sb,+spe-eef,+specres2,+ssbs,+sve,+sve2,+sve2p1,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v8.9a,+v8a,+v9.1a,+v9.2a,+v9.3a,+v9.4a,+v9a,+wfxt" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # | !4 = !{i32 1, !5} # | !5 = !{!"aarch64.mem_hint", i32 0} # | !6 = !{i32 1, !7} # | !7 = !{!"aarch64.mem_hint", i32 1} # | !8 = !{i32 0, !9} # | !9 = !{!"aarch64.mem_hint", i32 3} # | !10 = !{i32 0, !11} # | !11 = !{!"aarch64.mem_hint", i32 4} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556e0cd1557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556e0cd12515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556e0cd15cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc9bce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc9bcea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc9bce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc9bce31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556e0ccab24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556e0ccab096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556e0cc8ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556e0c93f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556e0c93ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc9bce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc9bce330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc9bce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556e0c93ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c (1659 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m1x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: n # | ... # `---data was truncated (10240/22107) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561a51ec857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561a51ec5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561a51ec8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa41fb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa41fb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa41fb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa41faed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561a51e5e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561a51e5e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561a51e42f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561a51af2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561a51af1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa41faeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa41faef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa41faef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561a51af1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c (1660 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv32i8.nxv32i8.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c (1661 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/97913) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d52ad5857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d52ad55515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d52ad58cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f98f121bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f98f12725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f98f121ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f98f1203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d52acee24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d52acee096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d52acd2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d52a982176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d52a981e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f98f1204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f98f12050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f98f12050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d52a981d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c (1662 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv16f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv16f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m8_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv32f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv32f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32mf2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv1f32.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv1f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32m1_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv2f32.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv2f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32m2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = all # | ... # `---data was truncated (10240/147390) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559ee83fd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559ee83fa515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559ee83fdcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb85821bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb8582725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb85821ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb858203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559ee839324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559ee8393096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559ee8377f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559ee8027176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559ee8026e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb858204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb8582050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb8582050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559ee8026d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c (1663 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf8x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf8x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf8x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf4x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c (1664 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556b7a0b157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556b7a0ae515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556b7a0b1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5225e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5225ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5225e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5225e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556b7a04724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556b7a047096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556b7a02bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556b79cdb176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556b79cdae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5225e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5225e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5225e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556b79cdad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c (1665 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c (1666 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf4x7(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf2x7(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16m1x7(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16m1x7_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560b5387d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560b5387a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560b5387dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc388133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc38818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc388133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc38811b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560b5381324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560b53813096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560b537f7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560b534a7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560b534a6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc38811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc38811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc38811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560b534a6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c (1667 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m1_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load # | ... # `---data was truncated (10240/26512) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005652cede357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005652cede0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005652cede3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6e5a049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6e5a0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6e5a049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6e5a031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005652ced7924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005652ced79096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005652ced5df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005652cea0d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005652cea0ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6e5a032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6e5a0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6e5a0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005652cea0cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c (1668 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f64m1_tu( %maskedoff, ptr noundef %base, % # | ... # `---data was truncated (10240/215941) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005596dd31657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005596dd313515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005596dd316cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f06d0a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f06d0aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f06d0a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f06d0a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005596dd2ac24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005596dd2ac096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005596dd290f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005596dcf40176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005596dcf3fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f06d0a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f06d0a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f06d0a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005596dcf3fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c (1669 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563679ec057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563679ebd515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563679ec0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f05d7933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f05d798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f05d7933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f05d791b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563679e5624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563679e56096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563679e3af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563679aea176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563679ae9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f05d791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f05d791d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f05d791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563679ae9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c (1670 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m4_tu( %maskedoff, ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c (1671 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16mf4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16mf4_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16mf2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16mf2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16m1_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16m2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca # | ... # `---data was truncated (10240/153805) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dc911bc57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055dc911b9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055dc911bccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff444e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff444e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff444e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff444e03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dc9115224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055dc91152096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055dc91136f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055dc90de6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055dc90de5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff444e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff444e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff444e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dc90de5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c (1672 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005562caa2957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005562caa26515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005562caa29cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2fe5533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2fe558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2fe5533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2fe551b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005562ca9bf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005562ca9bf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005562ca9a3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005562ca653176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005562ca652e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2fe551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2fe551d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2fe551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005562ca652d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmullbq.c (1673 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmullbq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmullbq_int_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8>, <16 x i8>, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmullbq_int_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0, i32 0) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmullbq_int_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1, i32 0) # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32>, <4 x i32>, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmullbq_poly_p16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmullbq_int_m_s8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 0, i32 0, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmullbq_int_m_u16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 1, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmullbq_int_m_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <2 x i64>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <2 x i64> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3) # | %5 = load <2 x i64>, ptr %inactive.addr, align 8 # | %6 = call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %1, i32 0, i32 0, <2 x i1> %4, <2 x i64> %5) # | ret <2 x i64> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v2i1(<4 x i32>, <4 x i32>, i32, i32, <2 x i1>, <2 x i64>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmullbq_poly_m_p8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 0, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmullbq_int_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 1, i32 0, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmullbq_int_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 0, i32 0, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmullbq_int_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | # | ... # `---data was truncated (10240/12050) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005645729be57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005645729bb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005645729becbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2106e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2106ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2106e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2106e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056457295424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564572954096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564572938f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005645725e8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005645725e7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2106e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2106e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2106e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005645725e7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c (1674 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_u8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv # | ... # `---data was truncated (10240/68225) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cc97d7f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cc97d7c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cc97d7fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5958133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f595818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5958133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f595811b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cc97d1524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cc97d15096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cc97cf9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cc979a9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cc979a8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f595811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f595811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f595811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cc979a8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c (1675 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16m4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.i8.i64(, , i8, i64) # | ... # `---data was truncated (10240/68437) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bb87adf57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bb87adc515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bb87adfcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0455c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0455ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0455c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0455c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bb87a7524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bb87a75096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bb87a59f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bb87709176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bb87708e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0455c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0455c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0455c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bb87708d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c (1676 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv1i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv2i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv4i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv8i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv16i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv32i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv64i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv1i16.i16.i64( %0, %1, i16 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv2i16.i16.i64( %0, %1, i16 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv4i16.i16.i64( %0, %1, i16 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i1 # | ... # `---data was truncated (10240/182173) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055571b0d457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055571b0d1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055571b0d4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0164049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f01640a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0164049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0164031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055571b06a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055571b06a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055571b04ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055571acfe176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055571acfde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0164032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f01640330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f01640330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055571acfdd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c (1677 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64V /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local signext i32 @test() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvli.i64(i64 1, i64 0, i64 0) # | %conv = trunc i64 %0 to i32 # | ret i32 %conv # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f60c69b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f60c698515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f60c69bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4d9ee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4d9eea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4d9ee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4d9ee31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f60c63124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f60c631096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f60c615f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f60c2c5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f60c2c4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4d9ee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4d9ee330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4d9ee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f60c2c4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64V /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64V /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c (1678 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_u16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_u16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), # | ... # `---data was truncated (10240/53330) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055800694f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055800694c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055800694fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa591049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa5910a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa591049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa591031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005580068e524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005580068e5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005580068c9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558006579176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558006578e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa591032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa5910330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa5910330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558006578d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c (1679 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf8_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | # | ... # `---data was truncated (10240/415319) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005630aa37f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005630aa37c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005630aa37fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdf82733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdf8278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdf82733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdf8271b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005630aa31524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005630aa315096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005630aa2f9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005630a9fa9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005630a9fa8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fdf8271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdf8271d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdf8271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005630a9fa8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c (1680 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv2i16.nxv2i32.i64.i64( poison, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c (1681 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_f64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_f64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_f64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_i64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_i64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_i64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_u64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_u64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_u64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = loa # | ... # `---data was truncated (10240/23447) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055749f3df57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055749f3dc515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055749f3dfcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff637d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff637d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff637d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff637d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055749f37524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055749f375096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055749f359f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055749f009176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055749f008e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff637d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff637d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff637d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055749f008d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c (1682 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounw # | ... # `---data was truncated (10240/12658) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055af9a46157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055af9a45e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055af9a461cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff68f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff68f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff68f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff68f11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055af9a3f724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055af9a3f7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055af9a3dbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055af9a08b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055af9a08ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff68f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff68f11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff68f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055af9a08ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c (1683 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_i8mf4x6(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d08d3e057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d08d3dd515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d08d3e0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6158049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f61580a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6158049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6158031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d08d37624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d08d376096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d08d35af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d08d00a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d08d009e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6158032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f61580330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f61580330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d08d009d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c (1684 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m8_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32m2_tu( %maskedoff, ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c (1685 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf8_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf4_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf2_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8m1_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv16i8 # | ... # `---data was truncated (10240/215036) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005623ef12d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005623ef12a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005623ef12dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3b4d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3b4d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3b4d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3b4d11b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005623ef0c324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005623ef0c3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005623ef0a7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005623eed57176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005623eed56e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3b4d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3b4d11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3b4d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005623eed56d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c (1686 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv64i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv64i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv32i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv32i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv16i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv16i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv8i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv8i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv4i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv4i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv2i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv2i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv1i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv1i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsof.mask.nxv64i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsof.mask.nxv32i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsof.mask.nxv16i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsof.mask.nxv8i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b16_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsof.mask.nxv4i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback n # | ... # `---data was truncated (10240/13031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d83eb7a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d83eb77515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d83eb7acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9a20f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9a20f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9a20f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9a20eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d83eb1024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d83eb10096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d83eaf4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d83e7a4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d83e7a3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9a20eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9a20eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9a20eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d83e7a3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c (1687 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16mf4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1f16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1f16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16mf2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2f16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2f16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv4f16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4f16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv8f16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv8f16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv16f16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv16f16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv32f16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv32f16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16mf4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1i16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1i16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16mf2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2i16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2i16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv4i16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4i16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv8i16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv8i16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinli # | ... # `---data was truncated (10240/17403) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056418eec557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056418eec2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056418eec5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c4d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c4d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c4d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c4d831507 abort ./stdlib/abort.c:85:3 # | #7 0x000056418ee5b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056418ee5b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056418ee3ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056418eaef176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056418eaeee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2c4d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c4d8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c4d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056418eaeed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c (1688 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_i8mf4x6(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562885ca057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562885c9d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562885ca0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff9ab533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff9ab58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff9ab533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff9ab51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562885c3624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562885c36096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562885c1af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005628858ca176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005628858c9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff9ab51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff9ab51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff9ab51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005628858c9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c (1689 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/97647) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b2c73b057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b2c73ad515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b2c73b0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9d1c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9d1c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9d1c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9d1c031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b2c734624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b2c7346096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b2c732af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b2c6fda176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b2c6fd9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9d1c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9d1c0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9d1c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b2c6fd9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c (1690 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_u64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_u64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca targe # | ... # `---data was truncated (10240/53556) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d11c9df57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d11c9dc515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d11c9dfcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4a7ac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4a7aca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4a7ac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4a7ac31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d11c97524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d11c975096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d11c959f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d11c609176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d11c608e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4a7ac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4a7ac330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4a7ac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d11c608d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c (1691 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("ri # | ... # `---data was truncated (10240/47480) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f5aa5b457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f5aa5b1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f5aa5b4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1878133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f187818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1878133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f187811b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f5aa54a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f5aa54a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f5aa52ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f5aa1de176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f5aa1dde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f187811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f187811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f187811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f5aa1ddd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c (1692 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_i8mf4x7(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562734de257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562734ddf515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562734de2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1b19533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1b1958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1b19533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1b1951b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562734d7824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562734d78096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562734d5cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562734a0c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562734a0be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1b1951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1b1951d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1b1951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562734a0bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c (1693 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv16i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv32i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv32i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv64i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv64i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_u8mf8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_u8mf4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloc # | ... # `---data was truncated (10240/71123) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056247c2d557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056247c2d2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056247c2d5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9087505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f908755c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9087505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f90874ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056247c26b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056247c26b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056247c24ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056247beff176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056247befee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f90874eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f90874ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f90874ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056247befed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c (1694 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv2f32.i64( %0, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c (1695 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4e # | ... # `---data was truncated (10240/228857) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a96a89357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a96a890515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a96a893cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd44a049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd44a0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd44a049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd44a031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a96a82924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a96a829096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a96a80df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a96a4bd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a96a4bce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd44a032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd44a0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd44a0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a96a4bcd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c (1696 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561f2985957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561f29856515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561f29859cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8eb101bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8eb10725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8eb101ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8eb1003507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561f297ef24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561f297ef096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561f297d3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561f29483176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561f29482e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8eb1004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8eb10050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8eb10050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561f29482d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c (1697 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/87892) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564cd577b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564cd5778515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564cd577bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4e7af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4e7af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4e7af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4e7af1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564cd571124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564cd5711096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564cd56f5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564cd53a5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564cd53a4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4e7af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4e7af1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4e7af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564cd53a4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/builtins-arm-exclusive.c (1698 of 27911) ******************** TEST 'Clang :: CodeGen/builtins-arm-exclusive.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Werror -triple thumbv8-linux-gnueabi -fno-signed-char -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Werror -triple thumbv8-linux-gnueabi -fno-signed-char -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8-unknown-linux-gnueabi" # | # | %struct.Simple = type { i8, i8 } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ldrex(ptr noundef %addr, ptr noundef %addr64, ptr noundef %addrfloat) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | %addr64.addr = alloca ptr, align 4 # | %addrfloat.addr = alloca ptr, align 4 # | %sum = alloca i32, align 4 # | store ptr %addr, ptr %addr.addr, align 4 # | store ptr %addr64, ptr %addr64.addr, align 4 # | store ptr %addrfloat, ptr %addrfloat.addr, align 4 # | store i32 0, ptr %sum, align 4 # | %0 = load ptr, ptr %addr.addr, align 4 # | %ldrex = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i8) %0) # | %1 = trunc i32 %ldrex to i8 # | %conv = zext i8 %1 to i32 # | %2 = load i32, ptr %sum, align 4 # | %add = add nsw i32 %2, %conv # | store i32 %add, ptr %sum, align 4 # | %3 = load ptr, ptr %addr.addr, align 4 # | %ldrex1 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i16) %3) # | %4 = trunc i32 %ldrex1 to i16 # | %conv2 = sext i16 %4 to i32 # | %5 = load i32, ptr %sum, align 4 # | %add3 = add nsw i32 %5, %conv2 # | store i32 %add3, ptr %sum, align 4 # | %6 = load ptr, ptr %addr.addr, align 4 # | %ldrex4 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %6) # | %7 = load i32, ptr %sum, align 4 # | %add5 = add nsw i32 %7, %ldrex4 # | store i32 %add5, ptr %sum, align 4 # | %8 = load ptr, ptr %addr.addr, align 4 # | %ldrexd = call { i32, i32 } @llvm.arm.ldrexd(ptr %8) # | %9 = extractvalue { i32, i32 } %ldrexd, 1 # | %10 = extractvalue { i32, i32 } %ldrexd, 0 # | %11 = zext i32 %9 to i64 # | %12 = zext i32 %10 to i64 # | %shl = shl nuw i64 %11, 32 # | %13 = or i64 %shl, %12 # | %14 = load i32, ptr %sum, align 4 # | %conv6 = sext i32 %14 to i64 # | %add7 = add nsw i64 %conv6, %13 # | %conv8 = trunc i64 %add7 to i32 # | store i32 %conv8, ptr %sum, align 4 # | %15 = load ptr, ptr %addr64.addr, align 4 # | %ldrexd9 = call { i32, i32 } @llvm.arm.ldrexd(ptr %15) # | %16 = extractvalue { i32, i32 } %ldrexd9, 1 # | %17 = extractvalue { i32, i32 } %ldrexd9, 0 # | %18 = zext i32 %16 to i64 # | %19 = zext i32 %17 to i64 # | %shl10 = shl nuw i64 %18, 32 # | %20 = or i64 %shl10, %19 # | %21 = load i32, ptr %sum, align 4 # | %conv11 = sext i32 %21 to i64 # | %add12 = add nsw i64 %conv11, %20 # | %conv13 = trunc i64 %add12 to i32 # | store i32 %conv13, ptr %sum, align 4 # | %22 = load ptr, ptr %addrfloat.addr, align 4 # | %ldrex14 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %22) # | %23 = bitcast i32 %ldrex14 to float # | %24 = load i32, ptr %sum, align 4 # | %conv15 = sitofp i32 %24 to float # | %add16 = fadd float %conv15, %23 # | %conv17 = fptosi float %add16 to i32 # | store i32 %conv17, ptr %sum, align 4 # | %25 = load ptr, ptr %addr.addr, align 4 # | %ldrexd18 = call { i32, i32 } @llvm.arm.ldrexd(ptr %25) # | %26 = extractvalue { i32, i32 } %ldrexd18, 1 # | %27 = extractvalue { i32, i32 } %ldrexd18, 0 # | %28 = zext i32 %26 to i64 # | %29 = zext i32 %27 to i64 # | %shl19 = shl nuw i64 %28, 32 # | %30 = or i64 %shl19, %29 # | %31 = bitcast i64 %30 to double # | %32 = load i32, ptr %sum, align 4 # | %conv20 = sitofp i32 %32 to double # | %add21 = fadd double %conv20, %31 # | %conv22 = fptosi double %add21 to i32 # | store i32 %conv22, ptr %sum, align 4 # | %33 = load ptr, ptr %addr.addr, align 4 # | %ldrex23 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %33) # | %34 = inttoptr i32 %ldrex23 to ptr # | %35 = load i32, ptr %34, align 4 # | %36 = load i32, ptr %sum, align 4 # | %add24 = add nsw i32 %36, %35 # | store i32 %add24, ptr %sum, align 4 # | %37 = load ptr, ptr %addr.addr, align 4 # | %ldrex25 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %37) # | %38 = inttoptr i32 %ldrex25 to ptr # | %a = getelementptr inbounds nuw %struct.Simple, ptr %38, i32 0, i32 0 # | %39 = load i8, ptr %a, align 1 # | %conv26 = zext i8 %39 to i32 # | %40 = load i32, ptr %sum, align 4 # | %add27 = add nsw i32 %40, %conv26 # | store i32 %add27, ptr %sum, align 4 # | %41 = load i32, ptr %sum, align 4 # | ret i32 %41 # | } # | # | ; Function Attrs: nounwind # | declare i32 @llvm.arm.ldrex.p0(ptr) #1 # | # | ; Function Attrs: nounwind # | declare { i32, i32 } @llvm.arm.ldrexd(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ldaex(ptr noundef %addr, ptr noundef %addr64, ptr noundef %addrfloat) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | %addr64.addr = alloca ptr, align 4 # | %addrfloat.addr = alloca ptr, align 4 # | %sum = alloca i32, align 4 # | store ptr %addr, ptr %addr.addr, align 4 # | store ptr %addr64, ptr %addr64.addr, align 4 # | store ptr %addrfloat, ptr %addrfloat.addr, align 4 # | store i32 0, ptr %sum, align 4 # | %0 = load ptr, ptr %addr.addr, align 4 # | %ldrex = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i8) %0) # | %1 = trunc i32 %ldrex to i8 # | %conv = zext i8 %1 to i32 # | %2 = load i32, ptr %sum, align 4 # | %add = add nsw i32 %2, %conv # | store i32 %add, ptr %sum, align 4 # | %3 = load ptr, ptr %addr.addr, align 4 # | %ldrex1 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i16) %3) # | %4 = trunc i32 %ldrex1 to i16 # | %conv2 = sext i16 %4 to i32 # | %5 = load i32, ptr %sum, align 4 # | %add3 = add nsw i32 %5, %conv2 # | store i32 %add3, ptr %sum, align 4 # | %6 = load ptr, ptr %addr.addr, align 4 # | %ldrex4 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i32) %6) # | %7 = load i32, ptr %sum, align 4 # | %add5 = add nsw i32 %7, %ldrex4 # | store i32 %add5, ptr %sum, align 4 # | %8 = load ptr, ptr %addr.addr, align 4 # | %ldrexd = call { i32, i32 } @llvm.arm.ldaexd(ptr %8) # | %9 = extractvalue { i32, i32 } %ldrexd, 1 # | %10 = extractvalue { i32, i32 } %ldrexd, 0 # | %11 = zext i32 %9 to i64 # | %12 = zext i32 %10 to i64 # | %shl = shl nuw i64 %11, 32 # | %13 = or i64 %shl, %12 # | %14 = load i32, ptr %sum, align 4 # | %conv6 = sext i32 %14 to i64 # | %add7 = add nsw i64 %conv6, %13 # | %conv8 = trunc i64 %add7 to i32 # | store i32 %conv8, ptr %sum, align 4 # | %15 = load ptr, ptr %addr64.addr, align 4 # | %ldrexd9 = call { i32, i32 } @llvm.arm.ldaexd(ptr %15) # | %16 = extractvalue { i32, i32 } %ldrexd9, 1 # | %17 = extractvalue { i32, i32 } %ldrexd9, 0 # | %18 = zext i32 %16 to i64 # | %19 = zext i32 %17 to i64 # | %shl10 = shl nuw i64 %18, 32 # | %20 = or i64 %shl10, %19 # | %21 = load i32, ptr %sum, align 4 # | %conv11 = sext i32 %21 to i64 # | %add12 = add nsw i64 %conv11, %20 # | %conv13 = trunc i64 %add12 to i32 # | store i32 %conv13, ptr %sum, align 4 # | %22 = load ptr, ptr %addrfloat.addr, align 4 # | %ldrex14 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i32) %22) # | %23 = bitcast i32 %ldrex14 to float # | %24 = load i32, ptr %sum, align 4 # | %conv15 = sitofp i32 %24 to float # | %add16 = fadd float %conv15, %23 # | %conv17 = fptosi float %add16 to i32 # | store i32 %conv17, ptr %sum, align 4 # | %25 = load ptr, ptr %addr.addr, align 4 # | %ldrexd18 = call { i32, i32 } @llvm.arm.ldaexd(ptr %25) # | %26 = extractvalue { i32, i32 } %ldrexd18, 1 # | %27 = extractvalue { i32, i32 } %ldrexd18, 0 # | %28 = zext i32 %26 to i64 # | %29 = zext i32 %27 to i64 # | %shl19 = shl nuw i64 %28, 32 # | %30 = or i64 %shl19, %29 # | %31 = bitcast i64 %30 to double # | %32 = load i32, ptr %sum, align 4 # | %conv20 = sitofp i32 %32 to double # | %add21 = fadd double %conv20, %31 # | %conv22 = fptosi double %add21 to i32 # | store i32 %conv22, ptr %sum, align 4 # | %33 = load ptr, ptr %addr.addr, align 4 # | %ldrex23 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i32) %33) # | %34 = inttoptr i32 %ldrex23 to ptr # | %35 = load i32, ptr %34, align 4 # | %36 = load i32, ptr %sum, align 4 # | %add24 = add nsw i32 %36, %35 # | store i32 %add24, ptr %sum, align 4 # | %37 = load ptr, ptr %addr.addr, align 4 # | %ldrex25 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i32) %37) # | %38 = inttoptr i32 %ldrex25 to ptr # | %a = getelementptr inbounds nuw %struct.Simple, ptr %38, i32 0, i32 0 # | %39 = load i8, ptr %a, align 1 # | %conv26 = zext i8 %39 to i32 # | %40 = load i32, ptr %sum, align 4 # | %add27 = add nsw i32 %40, %conv26 # | store i32 %add27, ptr %sum, align 4 # | %41 = load i32, ptr %sum, align 4 # | ret i32 %41 # | } # | # | ; Function Attrs: nounwind # | declare i32 @llvm.arm.ldaex.p0(ptr) #1 # | # | ; Function Attrs: nounwind # | declare { i32, i32 } @llvm.arm.ldaexd(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_strex(ptr noundef %addr) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | %res = alloca i32, align 4 # | %var = alloca %struct.Simple, align 1 # | %tmp = alloca i64, align 8 # | %tmp8 = alloca double, align 8 # | store ptr %addr, ptr %addr.addr, align 4 # | store i32 0, ptr %res, align 4 # | call void @llvm.memset.p0.i32(ptr align 1 %var, i8 0, i32 2, i1 false) # | %0 = load ptr, ptr %addr.addr, align 4 # | %strex = call i32 @llvm.arm.strex.p0(i32 4, ptr elementtype(i8) %0) # | %1 = load i32, ptr %res, align 4 # | %or = or i32 %1, %strex # | store i32 %or, ptr %res, align 4 # | %2 = load ptr, ptr %addr.addr, align 4 # | %strex1 = call i32 @llvm.arm.strex.p0(i32 42, ptr elementtype(i16) %2) # | %3 = load i32, ptr %res, align 4 # | %or2 = or i32 %3, %strex1 # | store i32 %or2, ptr %res, align 4 # | %4 = load ptr, ptr %addr.addr, align 4 # | %strex3 = call i32 @llvm.arm.strex.p0(i32 42, ptr elementtype(i32) %4) # | %5 = load i32, ptr %res, align 4 # | %or4 = or i32 %5, %strex3 # | store i32 %or4, ptr %res, align 4 # | store i64 42, ptr %tmp, align 8 # | %6 = load { i32, i32 }, ptr %tmp, align 8 # | %7 = extractvalue { i32, i32 } %6, 0 # | %8 = extractvalue { i32, i32 } %6, 1 # | %9 = load ptr, ptr %addr.addr, align 4 # | %strexd = call i32 @llvm.arm.strexd(i32 %7, i32 %8, ptr %9) # | %10 = load i32, ptr %res, align 4 # | %or5 = or i32 %10, %strexd # | store i32 %or5, ptr %res, align 4 # | %11 = load ptr, ptr %addr.addr, align 4 # | %strex6 = call i32 @llvm.arm.strex.p0(i32 1076754509, ptr elementtype(i32) %11) # | %12 = load i32, ptr %res, align 4 # | %or7 = or i32 %12, %strex6 # | store i32 %or7, ptr %res, align 4 # | store double 3.141590e+00, ptr %tmp8, align 8 # | %13 = load { i32, i32 }, ptr %tmp8, align 8 # | %14 = extractvalue { i32, i32 } %13, 0 # | %15 = extractvalue { i32, i32 } %13, 1 # | %16 = load ptr, ptr %addr.addr, align 4 # | %strexd9 = call i32 @llvm.arm.strexd(i32 %14, i32 %15, ptr %16) # | %17 = load i32, ptr %res, align 4 # | %or10 = or i32 %17, %strexd9 # | store i32 %or10, ptr %res, align 4 # | %18 = load ptr, ptr %addr.addr, ali # | ... # `---data was truncated (10240/16971) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005564e268757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005564e2684515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005564e2687cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2d79533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2d7958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2d79533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2d7951b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005564e261d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005564e261d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005564e2601f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005564e22b1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005564e22b0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2d7951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2d7951d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2d7951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005564e22b0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c (1699 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte32_f32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vlte32.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte32_i32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte32_u32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563f053f957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563f053f6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563f053f9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc84a81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc84a8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc84a81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc84a803507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563f0538f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563f0538f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563f05373f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563f05023176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563f05022e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc84a804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc84a8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc84a8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563f05022d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c (1700 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055755d90957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055755d906515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055755d909cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f493ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f493cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f493ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f493ce31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055755d89f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055755d89f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055755d883f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055755d533176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055755d532e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f493ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f493ce330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f493ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055755d532d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c (1701 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i6 # | ... # `---data was truncated (10240/67158) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a72f07557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a72f072515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a72f075cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1e6021bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1e602725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1e6021ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1e60203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a72f00b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a72f00b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a72efeff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a72ec9f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a72ec9ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1e60204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1e602050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1e602050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a72ec9ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c (1702 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16mf4_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16mf4_f32mf2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16mf2_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16mf2_f32m1_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16m1_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16m1_f32m2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16m2_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16m2_f32m4_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32. # | ... # `---data was truncated (10240/101394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056399e33057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056399e32d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056399e330cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f674ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f674ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f674ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f674ff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056399e2c624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056399e2c6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056399e2aaf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056399df5a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056399df59e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f674ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f674ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f674ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056399df59d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c (1703 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3e # | ... # `---data was truncated (10240/228857) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559ec548d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559ec548a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559ec548dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3409049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f34090a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3409049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3409031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559ec542324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559ec5423096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559ec5407f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559ec50b7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559ec50b6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3409032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f34090330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f34090330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559ec50b6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c (1704 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), p # | ... # `---data was truncated (10240/87316) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005604db68d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005604db68a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005604db68dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7f36c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7f36ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7f36c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7f36c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005604db62324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005604db623096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005604db607f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005604db2b7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005604db2b6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7f36c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7f36c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7f36c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005604db2b6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-vls-bitwise-ops.c (1705 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-bitwise-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %and = and <32 x i8> %0, %1 # | store <32 x i8> %and, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv8i8.v32i8( poison, <32 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8i8.v32i8(, <32 x i8>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_i16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i16>, align 8 # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca <16 x i16>, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %b.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store <16 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load <16 x i16>, ptr %b.addr, align 8 # | %and = and <16 x i16> %0, %1 # | store <16 x i16> %and, ptr %retval, align 8 # | %2 = load <16 x i16>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv4i16.v16i16( poison, <16 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4i16.v16i16(, <16 x i16>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_i32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i32>, align 8 # | %a.addr = alloca <8 x i32>, align 8 # | %b.addr = alloca <8 x i32>, align 8 # | %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %a.coerce, i64 0) # | %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %b.coerce, i64 0) # | store <8 x i32> %a, ptr %a.addr, align 8 # | store <8 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i32>, ptr %b.addr, align 8 # | %and = and <8 x i32> %0, %1 # | store <8 x i32> %and, ptr %retval, align 8 # | %2 = load <8 x i32>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv2i32.v8i32( poison, <8 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2i32.v8i32(, <8 x i32>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_i64( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <4 x i64>, align 8 # | %a.addr = alloca <4 x i64>, align 8 # | %b.addr = alloca <4 x i64>, align 8 # | %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %a.coerce, i64 0) # | %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %b.coerce, i64 0) # | store <4 x i64> %a, ptr %a.addr, align 8 # | store <4 x i64> %b, ptr %b.addr, align 8 # | %0 = load <4 x i64>, ptr %a.addr, align 8 # | %1 = load <4 x i64>, ptr %b.addr, align 8 # | %and = and <4 x i64> %0, %1 # | store <4 x i64> %and, ptr %retval, align 8 # | %2 = load <4 x i64>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv1i64.v4i64( poison, <4 x i64> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv1i64.v4i64(, <4 x i64>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_u8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %and = and <32 x i8> %0, %1 # | store <32 x i8> %and, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv8i8.v32i8( poison, <32 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_u16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i16>, align 8 # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca <16 x i16>, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %b.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store <16 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load <16 x i16>, ptr %b.addr, align 8 # | %and = and <16 x i16> %0, %1 # | store <16 x i16> %and, ptr %retval, align 8 # | %2 = load <16 x i16>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv4i16.v16i16( poison, <16 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_u32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i32>, align 8 # | %a.addr = alloca <8 x i32>, align 8 # | %b.addr = alloca <8 x i32>, align 8 # | %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %a.coerce, i64 0) # | %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %b.coerce, i64 0) # | store <8 x i32> %a, ptr %a.addr, align 8 # | store <8 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i32>, ptr %b.addr, align 8 # | %and = and <8 x i32> %0, %1 # | store <8 x i32> %and, ptr %retval, align 8 # | %2 = load <8 x i32>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv2i32.v8i32( poison, <8 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_u64( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <4 x i64>, align 8 # | %a.addr = alloca <4 x i64>, align 8 # | %b.addr = alloca <4 x i64>, align 8 # | %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %a.coerce, i64 0) # | %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %b.coerce, i64 0) # | store <4 x i64> %a, ptr %a.addr, align 8 # | store <4 x i64> %b, ptr %b.addr, align 8 # | %0 = load <4 x i64>, ptr %a.addr, align 8 # | %1 = load <4 x i64>, ptr %b.addr, align 8 # | %and = and <4 x i64> %0, %1 # | store <4 x i64> %and, ptr %retval, align 8 # | %2 = load <4 x i64>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv1i64.v4i64( poison, <4 x i64> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @or_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %or = or <32 x i8> %0, %1 # | store <32 x i8> %or, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c (1706 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.r # | ... # `---data was truncated (10240/65582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056495146d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056495146a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056495146dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7e48b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7e48b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7e48b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7e48b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056495140324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564951403096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005649513e7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564951097176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564951096e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7e48b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7e48b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7e48b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564951096d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c (1707 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/87892) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d12c35057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d12c34d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d12c350cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f98eeb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f98eeb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f98eeb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f98eeb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d12c2e624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d12c2e6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d12c2caf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d12bf7a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d12bf79e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f98eeb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f98eeb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f98eeb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d12bf79d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c (1708 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16mf4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f64m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f64m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv2f64.nxv4f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2f64.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f64m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv4f64.nxv8f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4f64.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c (1709 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_i8mf4x6(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005640baef357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005640baef0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005640baef3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f636eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f636eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f636eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f636eb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005640bae8924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005640bae89096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005640bae6df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005640bab1d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005640bab1ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f636eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f636eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f636eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005640bab1cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c (1710 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_u16mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_u16mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_u16m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, pt # | ... # `---data was truncated (10240/24016) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f98904b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f989048515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f98904bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2aced33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2aced8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2aced33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2aced1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f988fe124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f988fe1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f988fc5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f988c75176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f988c74e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2aced1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2aced1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2aced1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f988c74d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c (1711 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32mf2x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_i32mf2x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_i32m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_u32mf2x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_u32m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_i32mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_i32m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_u32mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8 # | ... # `---data was truncated (10240/12059) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e17691f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e17691c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e17691fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f968a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f968a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f968a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f968a31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e1768b524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e1768b5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e176899f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e176549176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e176548e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f968a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f968a31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f968a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e176548d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbkb.c (1712 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbkb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c -check-prefix=RV32ZBKB # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @brev8_32(i32 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.brev8.i32(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @zip(i32 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.zip.i32(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @unzip(i32 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.unzip.i32(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.brev8.i32(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.zip.i32(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.unzip.i32(i32) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbkb" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_zbkb1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005586c470b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005586c4708515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005586c470bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1a95849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1a958a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1a95849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1a95831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005586c46a124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005586c46a1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005586c4685f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005586c4335176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005586c4334e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1a95832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1a958330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1a958330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005586c4334d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c -check-prefix=RV32ZBKB # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c -check-prefix=RV32ZBKB # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c (1713 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_i8mf8x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_i8mf4x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_i8mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_i8m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_i8m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_u8mf8x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_u8mf4x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_u8mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_u8m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_u8m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | cal # | ... # `---data was truncated (10240/23487) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005582b77fd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005582b77fa515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005582b77fdcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f52fcb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f52fcb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f52fcb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f52fcaed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005582b779324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005582b7793096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005582b7777f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005582b7427176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005582b7426e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f52fcaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f52fcaef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f52fcaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005582b7426d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c (1714 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_i8mf4x6(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056292335657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562923353515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562923356cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3351249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f33512a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3351249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3351231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005629232ec24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005629232ec096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005629232d0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562922f80176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562922f7fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3351232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f33512330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f33512330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562922f7fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c (1715 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16mf4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560bd5e0057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560bd5dfd515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560bd5e00cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1039505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f103955c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1039505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f10394ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560bd5d9624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560bd5d96096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560bd5d7af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560bd5a2a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560bd5a29e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f10394eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f10394ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f10394ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560bd5a29d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c (1716 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e55bc0f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e55bc0c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e55bc0fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9075933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f907598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9075933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f907591b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e55bba524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e55bba5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e55bb89f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e55b839176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e55b838e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f907591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f907591d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f907591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e55b838d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c (1717 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m1_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv1f64.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1f64.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv2f64.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv2f64.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv4f64.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv4f64.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv8f64.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv8f64.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m1_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv1i64.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1i64.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv2i64.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv2i64.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv4i64.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv4i64.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv8i64.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 # | ... # `---data was truncated (10240/15508) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563b26bdb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563b26bd8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563b26bdbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fad85849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fad858a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fad85849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fad85831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563b26b7124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563b26b71096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563b26b55f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563b26805176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563b26804e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fad85832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fad858330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fad858330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563b26804d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c (1718 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosy # | ... # `---data was truncated (10240/12666) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055910484157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055910483e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559104841cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fac8db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fac8db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fac8db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fac8db1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005591047d724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005591047d7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005591047bbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055910446b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055910446ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fac8db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fac8db1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fac8db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055910446ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c (1719 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv1i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv2i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv4i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv8i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m1_m( %mask, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.mask.nxv1i64.nxv1i64.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m1_m( %mask, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = loa # | ... # `---data was truncated (10240/18917) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557b81ef657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557b81ef3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557b81ef6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efc06c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efc06ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efc06c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efc06c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557b81e8c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557b81e8c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557b81e70f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557b81b20176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557b81b1fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efc06c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efc06c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efc06c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557b81b1fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c (1720 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16mf4_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m4_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m8_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f32mf2_f64m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f32m1_f64m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, ali # | ... # `---data was truncated (10240/60334) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056250021a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562500217515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056250021acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4ec1649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4ec16a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4ec1649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4ec1631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005625001b024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005625001b0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562500194f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005624ffe44176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005624ffe43e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4ec1632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4ec16330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4ec16330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005624ffe43d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c (1721 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0. # | ... # `---data was truncated (10240/87884) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055da9398057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055da9397d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055da93980cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff10f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff10f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff10f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff10f11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055da9391624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055da93916096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055da938faf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055da935aa176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055da935a9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff10f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff10f11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff10f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055da935a9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c (1722 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv16bf16.nxv16bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | stor # | ... # `---data was truncated (10240/29518) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557949a6d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557949a6a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557949a6dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8c83c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8c83ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8c83c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8c83c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557949a0324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557949a03096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005579499e7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557949697176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557949696e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8c83c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8c83c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8c83c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557949696d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c (1723 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16mf4x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16mf2x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16mf4x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16mf2x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_u16mf4x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("ri # | ... # `---data was truncated (10240/13634) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056452bab857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056452bab5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056452bab8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f577e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f577e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f577e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f577e431507 abort ./stdlib/abort.c:85:3 # | #7 0x000056452ba4e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056452ba4e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056452ba32f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056452b6e2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056452b6e1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f577e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f577e4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f577e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056452b6e1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c (1724 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c (1725 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055789b87157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055789b86e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055789b871cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f30c5533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f30c558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f30c5533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f30c551b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055789b80724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055789b807096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055789b7ebf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055789b49b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055789b49ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f30c551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f30c551d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f30c551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055789b49ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c (1726 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_f64m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_i64m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_u64m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f2c126857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f2c1265515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f2c1268cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1313e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1313ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1313e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1313e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f2c11fe24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f2c11fe096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f2c11e2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f2c0e92176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f2c0e91e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1313e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1313e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1313e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f2c0e91d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c (1727 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c (1728 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_i64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_u64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_f64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_i64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_u64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_f64m1x8_tumu( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 0, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_i64m1x8_tumu( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-neon-vst.c (1729 of 27911) ******************** TEST 'Clang :: CodeGen/arm-neon-vst.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-gnueabi -target-feature +neon -target-feature +fp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-gnueabi -target-feature +neon -target-feature +fp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8-none-linux-gnueabi" # | # | %struct.float16x4x2_t = type { [2 x <4 x half>] } # | %struct.float16x4x3_t = type { [3 x <4 x half>] } # | %struct.float16x4x4_t = type { [4 x <4 x half>] } # | %struct.float32x2x2_t = type { [2 x <2 x float>] } # | %struct.float32x2x3_t = type { [3 x <2 x float>] } # | %struct.float32x2x4_t = type { [4 x <2 x float>] } # | %struct.poly16x4x2_t = type { [2 x <4 x i16>] } # | %struct.poly16x4x3_t = type { [3 x <4 x i16>] } # | %struct.poly16x4x4_t = type { [4 x <4 x i16>] } # | %struct.poly8x8x2_t = type { [2 x <8 x i8>] } # | %struct.poly8x8x3_t = type { [3 x <8 x i8>] } # | %struct.poly8x8x4_t = type { [4 x <8 x i8>] } # | %struct.int16x4x2_t = type { [2 x <4 x i16>] } # | %struct.int16x4x3_t = type { [3 x <4 x i16>] } # | %struct.int16x4x4_t = type { [4 x <4 x i16>] } # | %struct.int32x2x2_t = type { [2 x <2 x i32>] } # | %struct.int32x2x3_t = type { [3 x <2 x i32>] } # | %struct.int32x2x4_t = type { [4 x <2 x i32>] } # | %struct.int64x1x2_t = type { [2 x <1 x i64>] } # | %struct.int64x1x3_t = type { [3 x <1 x i64>] } # | %struct.int64x1x4_t = type { [4 x <1 x i64>] } # | %struct.int8x8x2_t = type { [2 x <8 x i8>] } # | %struct.int8x8x3_t = type { [3 x <8 x i8>] } # | %struct.int8x8x4_t = type { [4 x <8 x i8>] } # | %struct.uint16x4x2_t = type { [2 x <4 x i16>] } # | %struct.uint16x4x3_t = type { [3 x <4 x i16>] } # | %struct.uint16x4x4_t = type { [4 x <4 x i16>] } # | %struct.uint32x2x2_t = type { [2 x <2 x i32>] } # | %struct.uint32x2x3_t = type { [3 x <2 x i32>] } # | %struct.uint32x2x4_t = type { [4 x <2 x i32>] } # | %struct.uint64x1x2_t = type { [2 x <1 x i64>] } # | %struct.uint64x1x3_t = type { [3 x <1 x i64>] } # | %struct.uint64x1x4_t = type { [4 x <1 x i64>] } # | %struct.uint8x8x2_t = type { [2 x <8 x i8>] } # | %struct.uint8x8x3_t = type { [3 x <8 x i8>] } # | %struct.uint8x8x4_t = type { [4 x <8 x i8>] } # | %struct.float16x8x2_t = type { [2 x <8 x half>] } # | %struct.float16x8x3_t = type { [3 x <8 x half>] } # | %struct.float16x8x4_t = type { [4 x <8 x half>] } # | %struct.float32x4x2_t = type { [2 x <4 x float>] } # | %struct.float32x4x3_t = type { [3 x <4 x float>] } # | %struct.float32x4x4_t = type { [4 x <4 x float>] } # | %struct.poly16x8x2_t = type { [2 x <8 x i16>] } # | %struct.poly16x8x3_t = type { [3 x <8 x i16>] } # | %struct.poly16x8x4_t = type { [4 x <8 x i16>] } # | %struct.poly8x16x2_t = type { [2 x <16 x i8>] } # | %struct.poly8x16x3_t = type { [3 x <16 x i8>] } # | %struct.poly8x16x4_t = type { [4 x <16 x i8>] } # | %struct.int16x8x2_t = type { [2 x <8 x i16>] } # | %struct.int16x8x3_t = type { [3 x <8 x i16>] } # | %struct.int16x8x4_t = type { [4 x <8 x i16>] } # | %struct.int32x4x2_t = type { [2 x <4 x i32>] } # | %struct.int32x4x3_t = type { [3 x <4 x i32>] } # | %struct.int32x4x4_t = type { [4 x <4 x i32>] } # | %struct.int64x2x2_t = type { [2 x <2 x i64>] } # | %struct.int64x2x3_t = type { [3 x <2 x i64>] } # | %struct.int64x2x4_t = type { [4 x <2 x i64>] } # | %struct.int8x16x2_t = type { [2 x <16 x i8>] } # | %struct.int8x16x3_t = type { [3 x <16 x i8>] } # | %struct.int8x16x4_t = type { [4 x <16 x i8>] } # | %struct.uint16x8x2_t = type { [2 x <8 x i16>] } # | %struct.uint16x8x3_t = type { [3 x <8 x i16>] } # | %struct.uint16x8x4_t = type { [4 x <8 x i16>] } # | %struct.uint32x4x2_t = type { [2 x <4 x i32>] } # | %struct.uint32x4x3_t = type { [3 x <4 x i32>] } # | %struct.uint32x4x4_t = type { [4 x <4 x i32>] } # | %struct.uint64x2x2_t = type { [2 x <2 x i64>] } # | %struct.uint64x2x3_t = type { [3 x <2 x i64>] } # | %struct.uint64x2x4_t = type { [4 x <2 x i64>] } # | %struct.uint8x16x2_t = type { [2 x <16 x i8>] } # | %struct.uint8x16x3_t = type { [3 x <16 x i8>] } # | %struct.uint8x16x4_t = type { [4 x <16 x i8>] } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_f16_x2(ptr noundef %a, [2 x i64] %b.coerce) #0 { # | entry: # | %b = alloca %struct.float16x4x2_t, align 8 # | %a.addr = alloca ptr, align 4 # | %__s1 = alloca %struct.float16x4x2_t, align 8 # | %coerce.dive = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %b, i32 0, i32 0 # | store [2 x i64] %b.coerce, ptr %coerce.dive, align 8 # | store ptr %a, ptr %a.addr, align 4 # | call void @llvm.memcpy.p0.p0.i32(ptr align 8 %__s1, ptr align 8 %b, i32 16, i1 false) # | %0 = load ptr, ptr %a.addr, align 4 # | %val = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %__s1, i32 0, i32 0 # | %arrayidx = getelementptr inbounds [2 x <4 x half>], ptr %val, i32 0, i32 0 # | %1 = load <8 x i8>, ptr %arrayidx, align 8 # | %val1 = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %__s1, i32 0, i32 0 # | %arrayidx2 = getelementptr inbounds [2 x <4 x half>], ptr %val1, i32 0, i32 1 # | %2 = load <8 x i8>, ptr %arrayidx2, align 8 # | %3 = bitcast <8 x i8> %1 to <4 x i16> # | %4 = bitcast <8 x i8> %2 to <4 x i16> # | call void @llvm.arm.neon.vst1x2.p0.v4i16(ptr %0, <4 x i16> %3, <4 x i16> %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.memcpy.p0.p0.i32(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i32, i1 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.arm.neon.vst1x2.p0.v4i16(ptr captures(none), <4 x i16>, <4 x i16>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_f16_x3(ptr noundef %a, [3 x i64] %b.coerce) #0 { # | entry: # | %b = alloca %struct.float16x4x3_t, align 8 # | %a.addr = alloca ptr, align 4 # | %__s1 = alloca %struct.float16x4x3_t, align 8 # | %coerce.dive = getelementptr inbounds nuw %struct.float16x4x3_t, ptr %b, i32 0, i32 0 # | store [3 x i64] %b.coerce, ptr %coerce.dive, align 8 # | store ptr %a, ptr %a.addr, align 4 # | call void @llvm.memcpy.p0.p0.i32(ptr align 8 %__s1, ptr align 8 %b, i32 24, i1 false) # | %0 = load ptr, ptr %a.addr, align 4 # | %val = getelementptr inbounds nuw %struct.float16x4x3_t, ptr %__s1, i32 0, i32 0 # | %arrayidx = getelementptr inbounds [3 x <4 x half>], ptr %val, i32 0, i32 0 # | %1 = load <8 x i8>, ptr %arrayidx, align 8 # | %val1 = getelementptr inbounds nuw %struct.float16x4x3_t, ptr %__s1, i32 0, i32 0 # | %arrayidx2 = getelementptr inbounds [3 x <4 x half>], ptr %val1, i32 0, i32 1 # | %2 = load <8 x i8>, ptr %arrayidx2, align 8 # | %val3 = getelementptr inbounds nuw %struct.float16x4x3_t, ptr %__s1, i32 0, i32 0 # | %arrayidx4 = getelementptr inbounds [3 x <4 x half>], ptr %val3, i32 0, i32 2 # | %3 = load <8 x i8>, ptr %arrayidx4, align 8 # | %4 = bitcast <8 x i8> %1 to <4 x i16> # | %5 = bitcast <8 x i8> %2 to <4 x i16> # | %6 = bitcast <8 x i8> %3 to <4 x i16> # | call void @llvm.arm.neon.vst1x3.p0.v4i16(ptr %0, <4 x i16> %4, <4 x i16> %5, <4 x i16> %6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.arm.neon.vst1x3.p0.v4i16(ptr captures(none), <4 x i16>, <4 x i16>, <4 x i16>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_f16_x4(ptr noundef %a, [4 x i64] %b.coerce) #0 { # | entry: # | %b = alloca %struct.float16x4x4_t, align 8 # | %a.addr = alloca ptr, align 4 # | %__s1 = alloca %struct.float16x4x4_t, align 8 # | %coerce.dive = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %b, i32 0, i32 0 # | store [4 x i64] %b.coerce, ptr %coerce.dive, align 8 # | store ptr %a, ptr %a.addr, align 4 # | call void @llvm.memcpy.p0.p0.i32(ptr align 8 %__s1, ptr align 8 %b, i32 32, i1 false) # | %0 = load ptr, ptr %a.addr, align 4 # | %val = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %__s1, i32 0, i32 0 # | %arrayidx = getelementptr inbounds [4 x <4 x half>], ptr %val, i32 0, i32 0 # | %1 = load <8 x i8>, ptr %arrayidx, align 8 # | %val1 = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %__s1, i32 0, i32 0 # | %arrayidx2 = getelementptr inbounds [4 x <4 x half>], ptr %val1, i32 0, i32 1 # | %2 = load <8 x i8>, ptr %arrayidx2, align 8 # | %val3 = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %__s1, i32 0, i32 0 # | %arrayidx4 = getelementptr inbounds [4 x <4 x half>], ptr %val3, i32 0, i32 2 # | %3 = load <8 x i8>, ptr %arrayidx4, align 8 # | %val5 = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %__s1, i32 0, i32 0 # | %arrayidx6 = getelementptr inbounds [4 x <4 x half>], ptr %val5, i32 0, i32 3 # | %4 = load <8 x i8>, ptr %arrayidx6, align 8 # | %5 = bitcast <8 x i8> %1 to <4 x i16> # | %6 = bitcast <8 x i8> %2 to <4 x i16> # | %7 = bitcast <8 x i8> %3 to <4 x i16> # | %8 = bitcast <8 x i8> %4 to <4 x i16> # | call void @llvm.arm.neon.vst1x4.p0.v4i16(ptr %0, <4 x i16> %5, <4 x i16> %6, <4 x i16> %7, <4 x i16> %8) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.arm.neon.vst1x4.p0.v4i16(ptr captures(none), <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_f32_x2(ptr noundef %a, [2 x i64] %b.coerce) #0 { # | entry: # | %b = alloca %struct.float32x2x2_t, align 8 # | %a.addr = alloca ptr, align 4 # | %__s1 = alloca %struct.float32x2x2_t, align 8 # | %coerce.dive = getelementptr inbounds nuw %struct.float32x2x2_t, ptr %b, i32 0, i32 0 # | store [2 x i64] %b.coerce, ptr %coerce.dive, align 8 # | store ptr %a, ptr %a.addr, align 4 # | call void @llvm.memcpy.p0.p0.i32(ptr align 8 %__s1, ptr align 8 %b, i32 16, i1 false) # | %0 = load ptr, ptr %a.addr, align 4 # | %val = getelementptr inbounds nuw %struct.float32x2x2_t, ptr %__s1, i32 0, i32 0 # | %arrayidx = getelementptr inbounds [2 x <2 x float>], ptr %val, i32 0, i32 0 # | %1 = load <8 x i8>, ptr %arrayidx, align 8 # | %val1 = getelementptr inbounds nuw %struct.float32x2x2_t, ptr %__s1, i32 0, i32 0 # | %arrayidx2 = getelementptr inbounds [2 x <2 x float>], ptr %val1, i32 0, i32 1 # | %2 = load <8 x i8>, ptr %arrayidx2, align 8 # | %3 = bitcast <8 x i8> %1 to <2 x float> # | %4 = bitcast <8 x i8> %2 to <2 x float> # | call void @llvm.arm.neon.vst1x2.p0.v2f32(ptr %0, <2 x float> %3, <2 x float> %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.arm.neon.vst1x2.p0.v2f32(ptr captures(none), <2 x float>, <2 x float>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_f32_x3(ptr noundef %a, [3 x i64] %b.coerce) #0 { # | entry: # | %b = alloca %s # | ... # `---data was truncated (10240/108866) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055b42afd757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b42afd4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b42afd7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9c1d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9c1d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9c1d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9c1d631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b42af6d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b42af6d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b42af51f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b42ac01176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b42ac00e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9c1d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9c1d6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9c1d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b42ac00d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c (1730 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8mf8_u8mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8mf4_u8mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8mf2_u8mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8m1_u8m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8m2_u8m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8m4_u8m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8m8_u8m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf8_i8mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf4_i8mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf2_i8mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m1_i8m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m2_i8m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m4_i8m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m8_i8m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16mf4_f16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16mf2_f16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16m1_f16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16m2_f16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16m4_f16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16m8_f16m8( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16mf4_f16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16mf2_f16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16m1_f16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16m2_f16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16m4_f16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16m8_f16m8( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bi # | ... # `---data was truncated (10240/136481) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005616216ce57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005616216cb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005616216cecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb262733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb26278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb262733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb26271b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056162166424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561621664096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561621648f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005616212f8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005616212f7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb26271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb26271d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb26271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005616212f7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c (1731 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c (1732 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_u64m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_u64m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_u64m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m1x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llv # | ... # `---data was truncated (10240/20513) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558816a7657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558816a73515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558816a76cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbb2f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbb2f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbb2f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbb2f71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558816a0c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558816a0c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005588169f0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005588166a0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055881669fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbb2f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbb2f71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbb2f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055881669fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c (1733 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_i8mf4x5(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563b114af57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563b114ac515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563b114afcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffa4b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffa4b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffa4b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffa4b51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563b1144524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563b11445096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563b11429f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563b110d9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563b110d8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ffa4b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffa4b51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffa4b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563b110d8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqmovn.c (1734 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqmovn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 0, i32 0, i32 0) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8>, <8 x i16>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 0, i32 0, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16>, <4 x i32>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 1, i32 0) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 1, i32 1, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovntq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 0, i32 0, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovntq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 0, i32 0, i32 1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovntq_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 1, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovntq_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 1, i32 1, i32 1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovunbq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 0, i32 0) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovunbq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 1, i32 0, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovuntq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 0, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovuntq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 1, i32 0, i32 1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_m_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vqmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 0, i32 0, i32 0, <8 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vqmovn.predicated.v16i8.v8i16.v8i1(<16 x i8>, <8 x i16>, i32, i32, i32, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_m_s32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vqmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 0, i32 0, i32 0, <4 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vqmovn.predicated.v8i16.v4i32.v4i1(<8 x i16>, <4 x i32>, i32, i32, i32, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_m_u16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vqmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 1, i32 1, i32 0, <8 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_m_u32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | # | ... # `---data was truncated (10240/17536) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f534d9f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f534d9c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f534d9fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f69bc649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f69bc6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f69bc649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f69bc631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f534d3524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f534d35096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f534d19f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f5349c9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f5349c8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f69bc632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f69bc6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f69bc6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f5349c8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c (1735 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf8_b64( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf4_b32( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf2_b16( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8m1_b8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8m2_b4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv32i8.n # | ... # `---data was truncated (10240/95347) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562c6c7f557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562c6c7f2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562c6c7f5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f967ab05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f967ab5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f967ab05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f967aaed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562c6c78b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562c6c78b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562c6c76ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562c6c41f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562c6c41ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f967aaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f967aaef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f967aaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562c6c41ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c (1736 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv16i16.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv16i16.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16m4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv16i16.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | ... # `---data was truncated (10240/68247) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055969c9dd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055969c9da515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055969c9ddcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f15ca333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f15ca38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f15ca333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f15ca31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055969c97324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055969c973096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055969c957f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055969c607176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055969c606e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f15ca31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f15ca31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f15ca31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055969c606d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c (1737 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8mf8_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv1i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv1i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8mf4_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv2i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv2i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8mf2_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv4i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv4i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m1_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv8i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv8i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m2_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv16i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv16i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m4_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv32i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv32i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m8_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv64i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv64i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16mf4_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv1i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv1i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16mf2_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv2i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv2i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m1_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv4i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv4i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m2_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv8i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv8i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m4_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv16i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv16i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m8_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv32i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv32i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u32mf2_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c (1738 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf8( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, a # | ... # `---data was truncated (10240/207757) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559570a6257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559570a5f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559570a62cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0be2733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0be278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0be2733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0be271b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005595709f824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005595709f8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005595709dcf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055957068c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055957068be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0be271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0be271d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0be271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055957068bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/sve/rsqrte.c (1739 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve/rsqrte.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrsqrte_f16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.frsqrte.x.nxv8f16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frsqrte.x.nxv8f16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrsqrte_f32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.frsqrte.x.nxv4f32( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frsqrte.x.nxv4f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrsqrte_f64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.frsqrte.x.nxv2f64( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frsqrte.x.nxv2f64() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x000056109d01b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056109d018515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056109d01bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8ae5049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8ae50a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8ae5049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8ae5031507 abort ./stdlib/abort.c:85:3 # | #7 0x000056109cfb124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056109cfb1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056109cf95f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056109cc45176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056109cc44e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8ae5032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8ae50330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8ae50330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056109cc44d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c (1740 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_i8mf4x6(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005642f201657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005642f2013515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005642f2016cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6f1cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6f1cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6f1cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6f1cc31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005642f1fac24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005642f1fac096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005642f1f90f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005642f1c40176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005642f1c3fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6f1cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6f1cc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6f1cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005642f1c3fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c (1741 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf8_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = loa # | ... # `---data was truncated (10240/415311) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559d9157d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559d9157a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559d9157dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6aaf249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6aaf2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6aaf249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6aaf231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559d9151324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559d91513096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559d914f7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559d911a7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559d911a6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6aaf232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6aaf2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6aaf2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559d911a6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c (1742 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c2c94da57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c2c94d7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c2c94dacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc4e0c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc4e0ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc4e0c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc4e0c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c2c947024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c2c9470096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c2c9454f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c2c9104176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c2c9103e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc4e0c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc4e0c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc4e0c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c2c9103d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c (1743 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_i8mf8x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_i8mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_i8mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_i8m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_u8mf8x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_u8mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_u8mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_u8m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_i8mf8x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | # | ... # `---data was truncated (10240/21558) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b99319157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b99318e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b993191cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3d00905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3d0095c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3d00905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3d008ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b99312724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b993127096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b99310bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b992dbb176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b992dbae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3d008eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3d008ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3d008ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b992dbad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c (1744 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr # | ... # `---data was truncated (10240/97905) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555bc4c5e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555bc4c5b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555bc4c5ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f73d7849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f73d78a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f73d7849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f73d7831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555bc4bf424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555bc4bf4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555bc4bd8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555bc4888176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555bc4887e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f73d7832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f73d78330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f73d78330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555bc4887d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c (1745 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_i8mf8x6_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c (1746 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16mf4( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16mf2( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m1( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m2( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m4( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv16f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m8( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv32f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv32f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32mf2( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv1f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32m1( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv2f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32m2( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv4f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv4f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32m4( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv8f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv8f32.f32.i64(, , flo # | ... # `---data was truncated (10240/34773) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564383b7b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564383b78515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564383b7bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc914a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc914aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc914a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc914a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564383b1124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564383b11096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564383af5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005643837a5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005643837a4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc914a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc914a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc914a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005643837a4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c (1747 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv1bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv2bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv4bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv4bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv8bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv8bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv16bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv16bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv32bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv32bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf4_m( %vm, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.mask.nxv1bf16.i64( poison, %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.mask.nxv1bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf2_m( %vm, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.mask.nxv2bf16.i64( poison, %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.mask.nxv2bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m1_m( %vm, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.mask.nxv4bf16.i64( poison, %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.mask.nxv4bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m2_m( %vm, %vs2, i64 noundef # | ... # `---data was truncated (10240/14333) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a2f6d3c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a2f6d39515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a2f6d3ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2bfe049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2bfe0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2bfe049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2bfe031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a2f6cd224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a2f6cd2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a2f6cb6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a2f6966176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a2f6965e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2bfe032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2bfe0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2bfe0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a2f6965d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/neon/perm.c (1748 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon/perm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -disable-O0-optnone -flax-vector-conversions=none -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c --check-prefixes=LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -disable-O0-optnone -flax-vector-conversions=none -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | %struct.int8x8x2_t = type { [2 x <8 x i8>] } # | %struct.int16x4x2_t = type { [2 x <4 x i16>] } # | %struct.uint8x8x2_t = type { [2 x <8 x i8>] } # | %struct.uint16x4x2_t = type { [2 x <4 x i16>] } # | %struct.poly8x8x2_t = type { [2 x <8 x i8>] } # | %struct.poly16x4x2_t = type { [2 x <4 x i16>] } # | %struct.mfloat8x8x2_t = type { [2 x <8 x i8>] } # | %struct.int32x2x2_t = type { [2 x <2 x i32>] } # | %struct.float32x2x2_t = type { [2 x <2 x float>] } # | %struct.uint32x2x2_t = type { [2 x <2 x i32>] } # | %struct.int8x16x2_t = type { [2 x <16 x i8>] } # | %struct.int16x8x2_t = type { [2 x <8 x i16>] } # | %struct.int32x4x2_t = type { [2 x <4 x i32>] } # | %struct.float32x4x2_t = type { [2 x <4 x float>] } # | %struct.uint8x16x2_t = type { [2 x <16 x i8>] } # | %struct.uint16x8x2_t = type { [2 x <8 x i16>] } # | %struct.uint32x4x2_t = type { [2 x <4 x i32>] } # | %struct.poly8x16x2_t = type { [2 x <16 x i8>] } # | %struct.poly16x8x2_t = type { [2 x <8 x i16>] } # | %struct.mfloat8x16x2_t = type { [2 x <16 x i8>] } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vzip1_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <8 x i8> %2, <8 x i8> %3, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vzip1q_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | %1 = load <16 x i8>, ptr %b.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %2, <16 x i8> %3, <16 x i32> # | store <16 x i8> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vzip1_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <4 x i16> %2, <4 x i16> %3, <4 x i32> # | store <4 x i16> %shuffle.i, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vzip1q_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | store <8 x i16> %b, ptr %b.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | %1 = load <8 x i16>, ptr %b.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | store <8 x i16> %1, ptr %__p1.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %3 = load <8 x i16>, ptr %__p1.addr.i, align 16 # | %shuffle.i = shufflevector <8 x i16> %2, <8 x i16> %3, <8 x i32> # | store <8 x i16> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vzip1_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <2 x i32> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | %1 = load <2 x i32>, ptr %b.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <2 x i32> %2, <2 x i32> %3, <2 x i32> # | store <2 x i32> %shuffle.i, ptr %__ret.i, align 8 # | %4 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vzip1q_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | %b.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | store <4 x i32> %b, ptr %b.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | %1 = load <4 x i32>, ptr %b.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | store <4 x i32> %1, ptr %__p1.addr.i, align 16 # | %2 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %3 = load <4 x i32>, ptr %__p1.addr.i, align 16 # | %shuffle.i = shufflevector <4 x i32> %2, <4 x i32> %3, <4 x i32> # | store <4 x i32> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vzip1q_s64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__p1.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %a.addr = alloca <2 x i64>, align 16 # | %b.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | store <2 x i64> %1, ptr %__p1.addr.i, align 16 # | %2 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %3 = load <2 x i64>, ptr %__p1.addr.i, align 16 # | %shuffle.i = shufflevector <2 x i64> %2, <2 x i64> %3, <2 x i32> # | store <2 x i64> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vzip1_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <8 x i8> %2, <8 x i8> %3, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vzip1q_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | %1 = load <16 x i8>, ptr %b.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %2, <16 x i8> %3, <16 x i32> # | store <16 x i8> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vzip1_u16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, # | ... # `---data was truncated (10240/231562) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine # | #0 0x00005644ddcad57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005644ddcaa515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005644ddcadcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdea1449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdea14a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdea1449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdea1431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005644ddc4324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005644ddc43096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005644ddc27f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005644dd8d7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005644dd8d6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fdea1432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdea14330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdea14330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005644dd8d6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c --check-prefixes=LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c --check-prefixes=LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c (1749 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_f16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_f16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_f16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_i16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_i16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_i16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_u16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_u16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_u16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", # | ... # `---data was truncated (10240/23365) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005599033d057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005599033cd515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005599033d0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f85ead33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f85ead8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f85ead33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f85ead1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055990336624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559903366096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055990334af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559902ffa176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559902ff9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f85ead1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f85ead1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f85ead1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559902ff9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c (1750 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_f64m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_f64m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_i64m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_i64m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_u64m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_u64m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_f64m1x3_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_f64m2x3_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_i64m1x3_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_i64m2x3_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tu # | ... # `---data was truncated (10240/14044) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005579056cb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005579056c8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005579056cbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c2a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c2a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c2a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c2a71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055790566124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557905661096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557905645f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005579052f5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005579052f4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2c2a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c2a71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c2a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005579052f4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c (1751 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16mf4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561faba2757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561faba24515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561faba27cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc1c3f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc1c3f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc1c3f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc1c3eed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561fab9bd24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561fab9bd096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561fab9a1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561fab651176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561fab650e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc1c3eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc1c3eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc1c3eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561fab650d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c (1752 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf8( %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf8( %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv1i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf4( %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf4( %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv2i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf2( %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf2( %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv4i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8m1( %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8m1( %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv8i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv8i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8m2( %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = # | ... # `---data was truncated (10240/124514) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bd6111c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bd61119515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bd6111ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6aa2b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6aa2b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6aa2b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6aa2b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bd610b224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bd610b2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bd61096f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bd60d46176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bd60d45e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6aa2b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6aa2b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6aa2b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bd60d45d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c (1753 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_i8mf4x8(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558ec564657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558ec5643515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558ec5646cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc458933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc45898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc458933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc45891b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558ec55dc24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558ec55dc096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558ec55c0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558ec5270176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558ec526fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc45891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc45891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc45891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558ec526fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c (1754 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055959b84d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055959b84a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055959b84dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3beca1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3beca725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3beca1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3beca03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055959b7e324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055959b7e3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055959b7c7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055959b477176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055959b476e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3beca04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3beca050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3beca050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055959b476d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c (1755 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32mf2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m1_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m4_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f3 # | ... # `---data was truncated (10240/179503) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555e0085957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555e00856515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555e00859cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd725e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd725ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd725e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd725e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555e007ef24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555e007ef096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555e007d3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555e00483176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555e00482e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd725e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd725e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd725e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555e00482d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c (1756 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b75074157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b75073e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b750741cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3726449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f37264a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3726449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3726431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b7506d724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b7506d7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b7506bbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b75036b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b75036ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3726432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f37264330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f37264330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b75036ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c (1757 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf8x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8mf8x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | # | ... # `---data was truncated (10240/64349) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005559866c757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005559866c4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005559866c7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6761333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f676138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6761333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f676131b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055598665d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055598665d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555986641f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005559862f1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005559862f0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f676131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f676131d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f676131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005559862f0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/poly128.c (1758 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/poly128.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -ffp-contract=fast -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -ffp-contract=fast -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vldrq_p128(ptr noundef %ptr) #0 { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %__ret = alloca i128, align 16 # | %ref.tmp = alloca i128, align 16 # | %tmp = alloca i128, align 16 # | store ptr %ptr, ptr %ptr.addr, align 8 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i128, ptr %0, align 16 # | store i128 %1, ptr %ref.tmp, align 16 # | %2 = load i128, ptr %ref.tmp, align 16 # | store i128 %2, ptr %__ret, align 16 # | %3 = load i128, ptr %__ret, align 16 # | store i128 %3, ptr %tmp, align 16 # | %4 = load i128, ptr %tmp, align 16 # | ret i128 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_ld_st_p128(ptr noundef %ptr) #0 { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %__s1 = alloca i128, align 16 # | %__ret = alloca i128, align 16 # | %ref.tmp = alloca i128, align 16 # | %tmp = alloca i128, align 16 # | store ptr %ptr, ptr %ptr.addr, align 8 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i128, ptr %0, align 16 # | store i128 %1, ptr %ref.tmp, align 16 # | %2 = load i128, ptr %ref.tmp, align 16 # | store i128 %2, ptr %__ret, align 16 # | %3 = load i128, ptr %__ret, align 16 # | store i128 %3, ptr %tmp, align 16 # | %4 = load i128, ptr %tmp, align 16 # | store i128 %4, ptr %__s1, align 16 # | %5 = load ptr, ptr %ptr.addr, align 8 # | %add.ptr = getelementptr inbounds i128, ptr %5, i64 1 # | %6 = load i128, ptr %__s1, align 16 # | store i128 %6, ptr %add.ptr, align 16 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vmull_p64(i64 noundef %a, i64 noundef %b) #1 { # | entry: # | %__p0.addr.i = alloca i64, align 8 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca i128, align 16 # | %ref.tmp.i = alloca i128, align 16 # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | store i64 %0, ptr %__p0.addr.i, align 8 # | store i64 %1, ptr %__p1.addr.i, align 8 # | %2 = load i64, ptr %__p0.addr.i, align 8 # | %3 = load i64, ptr %__p1.addr.i, align 8 # | %vmull_p64.i = call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %2, i64 %3) # | %vmull_p641.i = bitcast <16 x i8> %vmull_p64.i to i128 # | store i128 %vmull_p641.i, ptr %ref.tmp.i, align 16 # | %4 = load i128, ptr %ref.tmp.i, align 16 # | store i128 %4, ptr %__ret.i, align 16 # | %5 = load i128, ptr %__ret.i, align 16 # | ret i128 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vmull_high_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 { # | entry: # | %__p0.addr.i3 = alloca <2 x i64>, align 16 # | %__ret.i4 = alloca <1 x i64>, align 8 # | %__p0.addr.i1 = alloca <2 x i64>, align 16 # | %__ret.i2 = alloca <1 x i64>, align 8 # | %__p0.addr.i.i = alloca i64, align 8 # | %__p1.addr.i.i = alloca i64, align 8 # | %__ret.i.i = alloca i128, align 16 # | %ref.tmp.i.i = alloca i128, align 16 # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__p1.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca i128, align 16 # | %ref.tmp.i = alloca <1 x i64>, align 8 # | %ref.tmp1.i = alloca <1 x i64>, align 8 # | %a.addr = alloca <2 x i64>, align 16 # | %b.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | store <2 x i64> %1, ptr %__p1.addr.i, align 16 # | %2 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | store <2 x i64> %2, ptr %__p0.addr.i3, align 16 # | %3 = load <2 x i64>, ptr %__p0.addr.i3, align 16 # | %4 = load <2 x i64>, ptr %__p0.addr.i3, align 16 # | %shuffle.i5 = shufflevector <2 x i64> %3, <2 x i64> %4, <1 x i32> # | store <1 x i64> %shuffle.i5, ptr %__ret.i4, align 8 # | %5 = load <1 x i64>, ptr %__ret.i4, align 8 # | store <1 x i64> %5, ptr %ref.tmp.i, align 8 # | %6 = load i64, ptr %ref.tmp.i, align 8 # | %7 = load <2 x i64>, ptr %__p1.addr.i, align 16 # | store <2 x i64> %7, ptr %__p0.addr.i1, align 16 # | %8 = load <2 x i64>, ptr %__p0.addr.i1, align 16 # | %9 = load <2 x i64>, ptr %__p0.addr.i1, align 16 # | %shuffle.i = shufflevector <2 x i64> %8, <2 x i64> %9, <1 x i32> # | store <1 x i64> %shuffle.i, ptr %__ret.i2, align 8 # | %10 = load <1 x i64>, ptr %__ret.i2, align 8 # | store <1 x i64> %10, ptr %ref.tmp1.i, align 8 # | %11 = load i64, ptr %ref.tmp1.i, align 8 # | store i64 %6, ptr %__p0.addr.i.i, align 8 # | store i64 %11, ptr %__p1.addr.i.i, align 8 # | %12 = load i64, ptr %__p0.addr.i.i, align 8 # | %13 = load i64, ptr %__p1.addr.i.i, align 8 # | %vmull_p64.i.i = call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %12, i64 %13) # | %vmull_p641.i.i = bitcast <16 x i8> %vmull_p64.i.i to i128 # | store i128 %vmull_p641.i.i, ptr %ref.tmp.i.i, align 16 # | %14 = load i128, ptr %ref.tmp.i.i, align 16 # | store i128 %14, ptr %__ret.i.i, align 16 # | %15 = load i128, ptr %__ret.i.i, align 16 # | store i128 %15, ptr %__ret.i, align 16 # | %16 = load i128, ptr %__ret.i, align 16 # | ret i128 %16 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_s8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca i128, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load i128, ptr %__p0.addr.i, align 16 # | store i128 %1, ptr %__ret.i, align 16 # | %2 = load i128, ptr %__ret.i, align 16 # | ret i128 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_s16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca i128, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load i128, ptr %__p0.addr.i, align 16 # | store i128 %1, ptr %__ret.i, align 16 # | %2 = load i128, ptr %__ret.i, align 16 # | ret i128 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_s32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca i128, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | %1 = load i128, ptr %__p0.addr.i, align 16 # | store i128 %1, ptr %__ret.i, align 16 # | %2 = load i128, ptr %__ret.i, align 16 # | ret i128 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_s64(<2 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca i128, align 16 # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | %1 = load i128, ptr %__p0.addr.i, align 16 # | store i128 %1, ptr %__ret.i, align 16 # | %2 = load i128, ptr %__ret.i, align 16 # | ret i128 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_u8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca i128, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load i128, ptr %__p0.addr.i, align 16 # | store i128 %1, ptr %__ret.i, align 16 # | %2 = load i128, ptr %__ret.i, align 16 # | ret i128 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_u16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca i128, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load i128, ptr %__p0.addr.i, align 16 # | store i128 %1, ptr %__ret.i, align 16 # | %2 = load i128, ptr %__ret.i, align 16 # | ret i128 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_u32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca i128, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | %1 = load i128, ptr %__p0.addr.i, align 16 # | store i128 %1, ptr %__ret.i, align 16 # | %2 = load i128, ptr %__ret.i, align 16 # | ret i128 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_u64(<2 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca i128, align 16 # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | %1 = load i128, ptr %__p0.addr.i, align 16 # | store i128 %1, ptr %__ret.i, align 16 # | %2 = load i128, ptr %__ret.i, align 16 # | ret i128 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca i128, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load i128, ptr %__p0.addr.i, align 16 # | store i128 %1, ptr %__ret.i, align 16 # | %2 = load i128, ptr %__ret.i, align 16 # | ret i128 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_f64(<2 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca i128, align 16 # | %a.ad # | ... # `---data was truncated (10240/19795) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000056292b4a057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056292b49d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056292b4a0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5481133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f548118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5481133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f548111b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056292b43624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056292b436096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056292b41af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056292b0ca176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056292b0c9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f548111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f548111d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f548111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056292b0c9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c (1759 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svaclt_f16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.facgt.nxv8f16( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facgt.nxv8f16(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svaclt_f32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.facgt.nxv4f32( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facgt.nxv4f32(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svaclt_f64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.facgt.nxv2f64( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facgt.nxv2f64(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svaclt_n_f32( %pg, %op1, float noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca float, align 4 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store float %op2, ptr %op2.addr, align 4 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %.splatinsert = insertelement poison, float %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.facgt.nxv4f32( %3, %.splat, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svaclt_n_f64( %pg, %op1, double noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca double, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store double %op2, ptr %op2.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load double, ptr %op2.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %.splatinsert = insertelement poison, double %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.facgt.nxv2f64( %3, %.splat, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000555b8cd2557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555b8cd22515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555b8cd25cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f80f5a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f80f5aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f80f5a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f80f5a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555b8ccbb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555b8ccbb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555b8cc9ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555b8c94f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555b8c94ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f80f5a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f80f5a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f80f5a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555b8c94ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c (1760 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005564c724957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005564c7246515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005564c7249cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb52a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb52a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb52a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb52a631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005564c71df24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005564c71df096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005564c71c3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005564c6e73176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005564c6e72e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb52a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb52a6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb52a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005564c6e72d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c (1761 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f32.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f32.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vsc # | ... # `---data was truncated (10240/121179) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055774e5be57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055774e5bb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055774e5becbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f35bbf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f35bbf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f35bbf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f35bbf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055774e55424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055774e554096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055774e538f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055774e1e8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055774e1e7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f35bbf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f35bbf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f35bbf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055774e1e7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm64-crc32.c (1762 of 27911) ******************** TEST 'Clang :: CodeGen/arm64-crc32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +crc -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +crc -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32b(i32 noundef %a, i8 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i8, align 1 # | store i32 %a, ptr %a.addr, align 4 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i8, ptr %b.addr, align 1 # | %2 = zext i8 %1 to i32 # | %3 = call i32 @llvm.aarch64.crc32b(i32 %0, i32 %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.crc32b(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32cb(i32 noundef %a, i8 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i8, align 1 # | store i32 %a, ptr %a.addr, align 4 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i8, ptr %b.addr, align 1 # | %2 = zext i8 %1 to i32 # | %3 = call i32 @llvm.aarch64.crc32cb(i32 %0, i32 %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.crc32cb(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32h(i32 noundef %a, i16 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i16, ptr %b.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call i32 @llvm.aarch64.crc32h(i32 %0, i32 %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.crc32h(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32ch(i32 noundef %a, i16 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i16, ptr %b.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call i32 @llvm.aarch64.crc32ch(i32 %0, i32 %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.crc32ch(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32w(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.aarch64.crc32w(i32 %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.crc32w(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32cw(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.aarch64.crc32cw(i32 %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.crc32cw(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32d(i32 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i64, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i64, ptr %b.addr, align 8 # | %2 = call i32 @llvm.aarch64.crc32x(i32 %0, i64 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.crc32x(i32, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32cd(i32 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i64, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i64, ptr %b.addr, align 8 # | %2 = call i32 @llvm.aarch64.crc32cx(i32 %0, i64 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.crc32cx(i32, i64) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056429b80e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056429b80b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056429b80ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa043733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa04378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa043733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa04371b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056429b7a424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056429b7a4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056429b788f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056429b438176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056429b437e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa04371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa04371d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa04371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056429b437d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c (1763 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, ali # | ... # `---data was truncated (10240/223367) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558c14f3f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558c14f3c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558c14f3fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb783305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb78335c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb783305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb7832ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558c14ed524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558c14ed5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558c14eb9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558c14b69176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558c14b68e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb7832eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb7832ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb7832ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558c14b68d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vabavq.c (1764 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vabavq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vabav.v16i8(i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.vabav.v16i8(i32, i32, <16 x i8>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load <8 x i16>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vabav.v8i16(i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.vabav.v8i16(i32, i32, <8 x i16>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load <4 x i32>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vabav.v4i32(i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.vabav.v4i32(i32, i32, <4 x i32>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_u8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vabav.v16i8(i32 1, i32 %0, <16 x i8> %1, <16 x i8> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_u16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load <8 x i16>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vabav.v8i16(i32 1, i32 %0, <8 x i16> %1, <8 x i16> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_u32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load <4 x i32>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vabav.v4i32(i32 1, i32 %0, <4 x i32> %1, <4 x i32> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4) # | %6 = call i32 @llvm.arm.mve.vabav.predicated.v16i8.v16i1(i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2, <16 x i1> %5) # | ret i32 %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.vabav.predicated.v16i8.v16i1(i32, i32, <16 x i8>, <16 x i8>, <16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load <8 x i16>, ptr %c.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4) # | %6 = call i32 @llvm.arm.mve.vabav.predicated.v8i16.v8i1(i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2, <8 x i1> %5) # | ret i32 %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.vabav.predicated.v8i16.v8i1(i32, i32, <8 x i16>, <8 x i16>, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load <4 x i32>, ptr %c.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4) # | %6 = call i32 @llvm.arm.mve.vabav.predicated.v4i32.v4i1(i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2, <4 x i1> %5) # | ret i32 %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.vabav.predicated.v4i32.v4i1(i32, i32, <4 x i32>, <4 x i32>, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_u8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4) # | %6 = call i32 @llvm.arm.mve.vabav.predicated.v16i8.v16i1(i32 1, i32 %0, <16 x i8> %1, <16 x i8> %2, <16 x i1> %5) # | ret i32 %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_u16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load <8 x i16>, ptr %c.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4) # | %6 = call i32 @llvm.arm.mve.vabav.predicated.v8i16.v8i1(i32 1, i32 %0, <8 x i16> %1, <8 x i16> %2, <8 x i1> %5) # | ret i32 %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_u32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | store i16 %p, ptr % # | ... # `---data was truncated (10240/11173) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000563ceb2db57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563ceb2d8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563ceb2dbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcd90133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcd9018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcd90133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcd9011b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563ceb27124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563ceb271096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563ceb255f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563ceaf05176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563ceaf04e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcd9011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcd9011d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcd9011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563ceaf04d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c (1765 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16mf4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562e132ee57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562e132eb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562e132eecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7e04533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7e0458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7e04533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7e0451b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562e1328424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562e13284096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562e13268f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562e12f18176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562e12f17e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7e0451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7e0451d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7e0451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562e12f17d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c (1766 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback n # | ... # `---data was truncated (10240/40795) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558a9f65b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558a9f658515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558a9f65bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1630a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1630a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1630a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1630a03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558a9f5f124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558a9f5f1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558a9f5d5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558a9f285176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558a9f284e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1630a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1630a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1630a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558a9f284d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c (1767 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c (1768 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m8_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = a # | ... # `---data was truncated (10240/288050) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f5efc6c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f5efc69515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f5efc6ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1c1e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1c1e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1c1e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1c1e831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f5efc0224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f5efc02096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f5efbe6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f5ef896176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f5ef895e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1c1e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1c1e8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1c1e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f5ef895d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c (1769 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558b3ec2c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558b3ec29515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558b3ec2ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f99c9733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f99c978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f99c9733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f99c971b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558b3ebc224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558b3ebc2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558b3eba6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558b3e856176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558b3e855e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f99c971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f99c971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f99c971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558b3e855d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c (1770 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = ca # | ... # `---data was truncated (10240/67474) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055979e3d957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055979e3d6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055979e3d9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f69f0733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f69f078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f69f0733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f69f071b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055979e36f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055979e36f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055979e353f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055979e003176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055979e002e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f69f071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f69f071d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f69f071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055979e002d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c (1771 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_i64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_u64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_f64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 8) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_i64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 8) %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_u64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c (1772 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr # | ... # `---data was truncated (10240/97905) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005626ef52e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005626ef52b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005626ef52ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f19fcc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f19fcca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f19fcc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f19fcc31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005626ef4c424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005626ef4c4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005626ef4a8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005626ef158176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005626ef157e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f19fcc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f19fcc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f19fcc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005626ef157d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c (1773 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | # | ... # `---data was truncated (10240/222475) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056231956157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056231955e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562319561cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f847d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f847d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f847d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f847d831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005623194f724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005623194f7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005623194dbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056231918b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056231918ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f847d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f847d8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f847d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056231918ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c (1774 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_i64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_u64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_f64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_i64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_u64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_f64m1x8_tumu( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target(" # | ... # `---data was truncated (10240/18506) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561a9415457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561a94151515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561a94154cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1d4c61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1d4c6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1d4c61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1d4c603507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561a940ea24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561a940ea096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561a940cef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561a93d7e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561a93d7de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1d4c604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1d4c6050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1d4c6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561a93d7dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c (1775 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_f64m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_i64m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_u64m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_f64m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_i64m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_u64m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561283b2a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561283b27515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561283b2acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbe3a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbe3a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbe3a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbe3a31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561283ac024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561283ac0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561283aa4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561283754176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561283753e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbe3a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbe3a31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbe3a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561283753d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c (1776 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560a6113c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560a61139515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560a6113ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbb5bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbb5bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbb5bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbb5bd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560a610d224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560a610d2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560a610b6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560a60d66176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560a60d65e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbb5bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbb5bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbb5bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560a60d65d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c (1777 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | d # | ... # `---data was truncated (10240/95223) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561eceab157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561eceaae515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561eceab1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff388933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff38898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff388933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff38891b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561ecea4724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561ecea47096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561ecea2bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561ece6db176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561ece6dae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff38891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff38891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff38891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561ece6dad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c (1778 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", # | ... # `---data was truncated (10240/19492) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563f5ae3957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563f5ae36515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563f5ae39cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3161733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f316178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3161733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f316171b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563f5adcf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563f5adcf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563f5adb3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563f5aa63176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563f5aa62e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f316171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f316171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f316171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563f5aa62d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c (1779 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005647c0a1a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005647c0a17515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005647c0a1acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3220305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f322035c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3220305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f32202ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005647c09b024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005647c09b0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005647c0994f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005647c0644176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005647c0643e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f32202eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f32202ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f32202ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005647c0643d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c (1780 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16mf4x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16mf4x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16mf4x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_ # | ... # `---data was truncated (10240/10396) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e9c4f3157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e9c4f2e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e9c4f31cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f999441bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f99944725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f999441ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9994403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e9c4ec724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e9c4ec7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e9c4eabf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e9c4b5b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e9c4b5ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9994404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f99944050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f99944050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e9c4b5ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c (1781 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv32i8.nxv32i8.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c (1782 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8mf8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8mf4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv16i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv16i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv32i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv32i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv64i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv64i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_u8mf8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_u8mf4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_u8mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_u8m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %bas # | ... # `---data was truncated (10240/29817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559a7e87457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559a7e871515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559a7e874cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0b86e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0b86e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0b86e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0b86e03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559a7e80a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559a7e80a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559a7e7eef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559a7e49e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559a7e49de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0b86e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0b86e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0b86e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559a7e49dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c (1783 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf8x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf8x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf8x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %m # | ... # `---data was truncated (10240/22258) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dc256ef57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055dc256ec515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055dc256efcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fec68449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fec684a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fec68449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fec68431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dc2568524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055dc25685096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055dc25669f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055dc25319176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055dc25318e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fec68432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fec684330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fec684330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dc25318d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c (1784 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_i8mf4x8(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055990be4a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055990be47515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055990be4acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4f94133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4f9418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4f94133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4f9411b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055990bde024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055990bde0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055990bdc4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055990ba74176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055990ba73e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4f9411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4f9411d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4f9411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055990ba73d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c (1785 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync # | ... # `---data was truncated (10240/183423) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560ec6b0757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560ec6b04515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560ec6b07cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffa8d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffa8d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffa8d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffa8d31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560ec6a9d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560ec6a9d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560ec6a81f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560ec6731176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560ec6730e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ffa8d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffa8d31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffa8d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560ec6730d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c (1786 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_f16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_f16mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_f16m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_f16m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_i16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_i16mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_i16m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_i16m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_u16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | s # | ... # `---data was truncated (10240/30826) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a0d552957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a0d5526515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a0d5529cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fac1ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fac1ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fac1ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fac1ad1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a0d54bf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a0d54bf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a0d54a3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a0d5153176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a0d5152e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fac1ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fac1ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fac1ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a0d5152d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c (1787 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv64i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv64i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv32i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv32i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv16i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv16i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv8i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv8i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv4i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv4i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv2i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv2i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv1i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv1i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbf.mask.nxv64i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbf.mask.nxv32i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbf.mask.nxv16i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbf.mask.nxv8i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b16_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbf.mask.nxv4i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree no # | ... # `---data was truncated (10240/13023) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cbedb9357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cbedb90515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cbedb93cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd89ac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd89aca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd89ac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd89ac31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cbedb2924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cbedb29096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cbedb0df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cbed7bd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cbed7bce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd89ac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd89ac330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd89ac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cbed7bcd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c (1788 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwi # | ... # `---data was truncated (10240/44369) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005620c9d1b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005620c9d18515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005620c9d1bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff71c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff71c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff71c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff71c11b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005620c9cb124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005620c9cb1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005620c9c95f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005620c9945176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005620c9944e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff71c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff71c11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff71c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005620c9944d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c (1789 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c (1790 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4k.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv1i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4k.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv2i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4k.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv4i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4k.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv8i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4k.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv16i32.i64.i64(, , i64 immarg, i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e76379e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e76379b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e76379ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2738533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f273858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2738533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f273851b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e76373424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e763734096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e763718f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e7633c8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e7633c7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f273851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f273851d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f273851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e7633c7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c (1791 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv1i16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv2i16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv4i16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv8i16.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv16i16.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv32i16.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv1i32.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv2i32.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv4i32.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv8i32.nxv8i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallbac # | ... # `---data was truncated (10240/66028) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561ebbfe857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561ebbfe5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561ebbfe8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5144f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5144f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5144f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5144f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561ebbf7e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561ebbf7e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561ebbf62f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561ebbc12176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561ebbc11e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5144f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5144f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5144f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561ebbc11d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c (1792 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf4_rm( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf2_rm( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m1_rm( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m2_rm( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m4_rm( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ed414ea57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ed414e7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ed414eacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1ffe249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1ffe2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1ffe249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1ffe231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ed4148024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ed41480096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ed41464f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ed41114176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ed41113e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1ffe232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1ffe2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1ffe2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ed41113d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c (1793 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste64_f64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.sf.vste64.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste64_i64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste64_u64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e40f98657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e40f983515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e40f986cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc0b0d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc0b0d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc0b0d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc0b0d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e40f91c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e40f91c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e40f900f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e40f5b0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e40f5afe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc0b0d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc0b0d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc0b0d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e40f5afd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c (1794 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056042bb9057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056042bb8d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056042bb90cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2d78f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2d78f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2d78f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2d78f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056042bb2624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056042bb26096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056042bb0af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056042b7ba176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056042b7b9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2d78f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2d78f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2d78f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056042b7b9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c (1795 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32mf2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m1_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m4_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m8_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32mf2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m1_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nou # | ... # `---data was truncated (10240/25034) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560cfee6a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560cfee67515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560cfee6acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f32ae933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f32ae98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f32ae933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f32ae91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560cfee0024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560cfee00096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560cfede4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560cfea94176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560cfea93e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f32ae91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f32ae91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f32ae91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560cfea93d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmulq.c (1796 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmulq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c --check-prefixes=CHECK,CHECK-NONSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = mul <16 x i8> %0, %1 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = mul <8 x i16> %0, %1 # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = mul <4 x i32> %0, %1 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmulq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = fmul <4 x float> %0, %1 # | ret <4 x float> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.mul.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.mul.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.mul.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.mul.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.mul.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.mul.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmulq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x half>, ptr %inactive.addr, align 8 # | %6 = call <8 x half> @llvm.arm.mve.mul.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4, <8 x half> %5) # | ret <8 x half> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.mul.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.mul.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.mul.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.mul.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmulq_x_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x float> @llvm.arm.mve.mul.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4, <4 x float> undef) # | ret <4 x float> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.m # | ... # `---data was truncated (10240/21288) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x0000559e81e2657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559e81e23515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559e81e26cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa4d3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa4d338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa4d3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa4d331b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559e81dbc24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559e81dbc096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559e81da0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559e81a50176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559e81a4fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa4d331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa4d331d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa4d331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559e81a4fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c --check-prefixes=CHECK,CHECK-NONSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c --check-prefixes=CHECK,CHECK-NONSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c (1797 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store # | ... # `---data was truncated (10240/29296) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dd0b77457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055dd0b771515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055dd0b774cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3b20049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3b200a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3b20049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3b20031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dd0b70a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055dd0b70a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055dd0b6eef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055dd0b39e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055dd0b39de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3b20032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3b200330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3b200330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dd0b39dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c (1798 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr # | ... # `---data was truncated (10240/126428) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b60440c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b604409515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b60440ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7e2e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7e2e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7e2e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7e2e91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b6043a224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b6043a2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b604386f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b604036176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b604035e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7e2e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7e2e91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7e2e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b604035d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c (1799 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv16i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_lo # | ... # `---data was truncated (10240/99851) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557323b1957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557323b16515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557323b19cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7b81c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7b81ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7b81c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7b81c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557323aaf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557323aaf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557323a93f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557323743176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557323742e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7b81c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7b81c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7b81c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557323742d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c (1800 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f32.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f32.p0.nxv8i16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c (1801 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf4_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf2_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m1_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m2_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m4_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv16bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m8_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv32bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv32bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vlse.mask.nxv1bf16.p0.i64( %1, ptr %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vlse.mask.nxv2bf16.p0.i64( %1, ptr %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load p # | ... # `---data was truncated (10240/28353) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f34ec9d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f34ec9a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f34ec9dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff3ad333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff3ad38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff3ad333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff3ad31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f34ec3324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f34ec33096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f34ec17f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f34e8c7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f34e8c6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff3ad31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff3ad31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff3ad31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f34e8c6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c (1802 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m4_bf16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv8bf16.nxv8i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv8bf16.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c (1803 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e65510157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e6550fe515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e655101cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fce13249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fce132a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fce13249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fce13231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e65509724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e655097096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e65507bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e654d2b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e654d2ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fce13232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fce132330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fce132330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e654d2ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c (1804 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv1f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c (1805 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_u32mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_u32m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_u32m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 # | ... # `---data was truncated (10240/24072) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563992c0b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563992c08515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563992c0bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5710d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5710d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5710d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5710d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563992ba124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563992ba1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563992b85f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563992835176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563992834e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5710d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5710d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5710d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563992834d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c (1806 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32mf2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m1_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m4_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m8_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32mf2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m1_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | ... # `---data was truncated (10240/24982) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563e1a0a857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563e1a0a5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563e1a0a8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f59b5b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f59b5b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f59b5b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f59b5aed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563e1a03e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563e1a03e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563e1a022f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563e19cd2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563e19cd1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f59b5aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f59b5aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f59b5aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563e19cd1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c (1807 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m4_tu( %maskedoff, %o # | ... # `---data was truncated (10240/70102) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e71147f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e71147c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e71147fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f99d3249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f99d32a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f99d3249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f99d3231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e71141524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e711415096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e7113f9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e7110a9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e7110a8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f99d3232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f99d32330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f99d32330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e7110a8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c (1808 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf4_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv1bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf2_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv2bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m1_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv4bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv4bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m2_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv8bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv8bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m4_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv16bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv16bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m8_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv32bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv32bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslidedown.mask.nxv1bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.mask.nxv1bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslidedown.mask.nxv2bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv. # | ... # `---data was truncated (10240/30759) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005621102e457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005621102e1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005621102e4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4298933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f429898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4298933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f429891b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056211027a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056211027a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056211025ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056210ff0e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056210ff0de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f429891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f429891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f429891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056210ff0dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c (1809 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i64m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i64m1( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv1i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i64m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i64m2( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i64m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i64m4( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i64m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i64m8( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i64m1_m( %mask, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load , ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.mask.nxv1i64.nxv1i64.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i64m1_m( %mask, %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load i64, ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llv # | ... # `---data was truncated (10240/18669) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563b8f56657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563b8f563515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563b8f566cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc8ade49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc8adea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc8ade49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc8ade31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563b8f4fc24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563b8f4fc096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563b8f4e0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563b8f190176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563b8f18fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc8ade32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc8ade330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc8ade330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563b8f18fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c (1810 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf8x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { targe # | ... # `---data was truncated (10240/81756) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d90365657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d903653515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d903656cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8424f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8424f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8424f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8424f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d9035ec24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d9035ec096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d9035d0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d903280176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d90327fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8424f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8424f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8424f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d90327fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c (1811 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf8x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m1x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8mf8x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8mf4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8mf2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8m1x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8m2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8m4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vect # | ... # `---data was truncated (10240/24229) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556ee824e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556ee824b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556ee824ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb336c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb336ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb336c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb336c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556ee81e424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556ee81e4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556ee81c8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556ee7e78176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556ee7e77e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb336c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb336c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb336c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556ee7e77d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c (1812 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e6b644157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e6b643e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e6b6441cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f63d1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f63d178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f63d1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f63d171b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e6b63d724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e6b63d7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e6b63bbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e6b606b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e6b606ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f63d171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f63d171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f63d171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e6b606ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c (1813 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a16f -target-feature +xsfmm32a32f -target-feature +xsfmm64a64f -target-feature +zvfhmin -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a16f -target-feature +xsfmm32a32f -target-feature +xsfmm64a64f -target-feature +zvfhmin -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_mm_f_f_w2_f16m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_mm_f_f_w1_f32m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.f.f.i64.nxv16f32(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.f.f.i64.nxv16f32(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_mm_f_f_w1_f64m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.f.f.i64.nxv8f64(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.f.f.i64.nxv8f64(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+xsfmm32a16f,+xsfmm32a32f,+xsfmm64a64f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvl32b1p0_zvl64b1p0_xsfmm32a16f0p6_xsfmm32a32f0p6_xsfmm64a64f0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b7210f957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b7210f6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b7210f9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f21e9a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f21e9aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f21e9a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f21e9a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b72108f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b72108f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b721073f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b720d23176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b720d22e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f21e9a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f21e9a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f21e9a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b720d22d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c (1814 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64(, , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGenCXX/virtual-base-ctor.cpp (1815 of 27911) ******************** TEST 'Clang :: CodeGenCXX/virtual-base-ctor.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp -emit-llvm -triple x86_64-unknown-linux-gnu -o - -O2 | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp -emit-llvm -triple x86_64-unknown-linux-gnu -o - -O2 # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | %struct.B = type { ptr, ptr, %struct.A } # | %struct.A = type { i32 } # | # | $_ZTV1B = comdat any # | # | $_ZTI1B = comdat any # | # | $_ZTS1B = comdat any # | # | $_ZTI1A = comdat any # | # | $_ZTS1A = comdat any # | # | @y = local_unnamed_addr global i8 2, align 1 # | @x = local_unnamed_addr global %struct.B { ptr getelementptr inbounds inrange(-24, 0) (i8, ptr @_ZTV1B, i64 24), ptr null, %struct.A zeroinitializer }, align 8 # | @_ZTV1B = linkonce_odr constant { [3 x ptr] } { [3 x ptr] [ptr inttoptr (i64 16 to ptr), ptr null, ptr @_ZTI1B] }, comdat, align 8 # | @_ZTI1B = linkonce_odr constant { ptr, ptr, i32, i32, ptr, i64 } { ptr getelementptr inbounds (i8, ptr @_ZTVN10__cxxabiv121__vmi_class_type_infoE, i64 16), ptr @_ZTS1B, i32 0, i32 1, ptr @_ZTI1A, i64 -6141 }, comdat, align 8 # | @_ZTVN10__cxxabiv121__vmi_class_type_infoE = external global [0 x ptr] # | @_ZTS1B = linkonce_odr constant [3 x i8] c"1B\00", comdat, align 1 # | @_ZTI1A = linkonce_odr constant { ptr, ptr } { ptr getelementptr inbounds (i8, ptr @_ZTVN10__cxxabiv117__class_type_infoE, i64 16), ptr @_ZTS1A }, comdat, align 8 # | @_ZTVN10__cxxabiv117__class_type_infoE = external global [0 x ptr] # | @_ZTS1A = linkonce_odr constant [3 x i8] c"1A\00", comdat, align 1 # | @llvm.global_ctors = appending global [0 x { i32, ptr, ptr }] zeroinitializer # | # | !llvm.ident = !{!0} # | !llvm.errno.tbaa = !{!1} # | # | !0 = !{!"clang version 24.0.0"} # | !1 = !{!2, !3, i64 0} # | !2 = !{!"__libc_errno", !3, i64 0} # | !3 = !{!"int", !4, i64 0} # | !4 = !{!"omnipotent char", !5, i64 0} # | !5 = !{!"Simple C++ TBAA"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o - # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o - # | #0 0x0000561727d6457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561727d61515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561727d64cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f58a2049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f58a20a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f58a2049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f58a2031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561727cfa24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561727cfa096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561727cdef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056172798e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056172798de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f58a2032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f58a20330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f58a20330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056172798dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c (1816 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr # | ... # `---data was truncated (10240/97905) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f3e6db557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f3e6db2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f3e6db5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f21bb133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f21bb18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f21bb133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f21bb11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f3e6d4b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f3e6d4b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f3e6d2ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f3e69df176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f3e69dee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f21bb11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f21bb11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f21bb11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f3e69ded81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c (1817 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | # | ... # `---data was truncated (10240/12216) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055759a6a157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055759a69e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055759a6a1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe3d6333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe3d638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe3d6333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe3d631b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055759a63724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055759a637096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055759a61bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055759a2cb176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055759a2cae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe3d631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe3d631d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe3d631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055759a2cad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c (1818 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005619bf0b857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005619bf0b5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005619bf0b8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9f90933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9f9098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9f90933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9f9091b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005619bf04e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005619bf04e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005619bf032f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005619bece2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005619bece1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9f9091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9f9091d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9f9091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005619bece1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c (1819 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32mf2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m1( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m4( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m8( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32mf2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m1_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: # | ... # `---data was truncated (10240/13649) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558434c7857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558434c75515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558434c78cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8f98533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8f9858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8f98533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8f9851b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558434c0e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558434c0e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558434bf2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005584348a2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005584348a1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8f9851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8f9851d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8f9851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005584348a1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c (1820 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv32bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf4_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.mask.nxv1bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf2_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.mask.nxv2bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.mask.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m1_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr # | ... # `---data was truncated (10240/15320) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056122ab9457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056122ab91515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056122ab94cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc101f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc101f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc101f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc101f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056122ab2a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056122ab2a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056122ab0ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056122a7be176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056122a7bde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc101f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc101f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc101f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056122a7bdd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c (1821 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560c2cb4057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560c2cb3d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560c2cb40cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7894533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f789458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7894533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f789451b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560c2cad624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560c2cad6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560c2cabaf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560c2c76a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560c2c769e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f789451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f789451d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f789451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560c2c769d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-cde-vfp.c (1822 of 27911) ******************** TEST 'Clang :: CodeGen/arm-cde-vfp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +cdecp1 -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +cdecp1 -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vcx1_u32() #0 { # | entry: # | %0 = call float @llvm.arm.cde.vcx1.f32(i32 0, i32 11) # | %1 = bitcast float %0 to i32 # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.arm.cde.vcx1.f32(i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vcx1a_u32(i32 noundef %acc) #0 { # | entry: # | %acc.addr = alloca i32, align 4 # | store i32 %acc, ptr %acc.addr, align 4 # | %0 = load i32, ptr %acc.addr, align 4 # | %1 = bitcast i32 %0 to float # | %2 = call float @llvm.arm.cde.vcx1a.f32(i32 1, float %1, i32 12) # | %3 = bitcast float %2 to i32 # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.arm.cde.vcx1a.f32(i32 immarg, float, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vcx2_u32(i32 noundef %n) #0 { # | entry: # | %n.addr = alloca i32, align 4 # | store i32 %n, ptr %n.addr, align 4 # | %0 = load i32, ptr %n.addr, align 4 # | %1 = bitcast i32 %0 to float # | %2 = call float @llvm.arm.cde.vcx2.f32(i32 0, float %1, i32 21) # | %3 = bitcast float %2 to i32 # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.arm.cde.vcx2.f32(i32 immarg, float, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vcx2a_u32(i32 noundef %acc, i32 noundef %n) #0 { # | entry: # | %acc.addr = alloca i32, align 4 # | %n.addr = alloca i32, align 4 # | store i32 %acc, ptr %acc.addr, align 4 # | store i32 %n, ptr %n.addr, align 4 # | %0 = load i32, ptr %acc.addr, align 4 # | %1 = bitcast i32 %0 to float # | %2 = load i32, ptr %n.addr, align 4 # | %3 = bitcast i32 %2 to float # | %4 = call float @llvm.arm.cde.vcx2a.f32(i32 0, float %1, float %3, i32 22) # | %5 = bitcast float %4 to i32 # | ret i32 %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.arm.cde.vcx2a.f32(i32 immarg, float, float, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vcx3_u32(i32 noundef %n, i32 noundef %m) #0 { # | entry: # | %n.addr = alloca i32, align 4 # | %m.addr = alloca i32, align 4 # | store i32 %n, ptr %n.addr, align 4 # | store i32 %m, ptr %m.addr, align 4 # | %0 = load i32, ptr %n.addr, align 4 # | %1 = bitcast i32 %0 to float # | %2 = load i32, ptr %m.addr, align 4 # | %3 = bitcast i32 %2 to float # | %4 = call float @llvm.arm.cde.vcx3.f32(i32 1, float %1, float %3, i32 3) # | %5 = bitcast float %4 to i32 # | ret i32 %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.arm.cde.vcx3.f32(i32 immarg, float, float, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vcx3a_u32(i32 noundef %acc, i32 noundef %n, i32 noundef %m) #0 { # | entry: # | %acc.addr = alloca i32, align 4 # | %n.addr = alloca i32, align 4 # | %m.addr = alloca i32, align 4 # | store i32 %acc, ptr %acc.addr, align 4 # | store i32 %n, ptr %n.addr, align 4 # | store i32 %m, ptr %m.addr, align 4 # | %0 = load i32, ptr %acc.addr, align 4 # | %1 = bitcast i32 %0 to float # | %2 = load i32, ptr %n.addr, align 4 # | %3 = bitcast i32 %2 to float # | %4 = load i32, ptr %m.addr, align 4 # | %5 = bitcast i32 %4 to float # | %6 = call float @llvm.arm.cde.vcx3a.f32(i32 0, float %1, float %3, float %5, i32 5) # | %7 = bitcast float %6 to i32 # | ret i32 %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.arm.cde.vcx3a.f32(i32 immarg, float, float, float, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vcx1d_u64() #0 { # | entry: # | %0 = call double @llvm.arm.cde.vcx1.f64(i32 0, i32 11) # | %1 = bitcast double %0 to i64 # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.arm.cde.vcx1.f64(i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vcx1da_u64(i64 noundef %acc) #0 { # | entry: # | %acc.addr = alloca i64, align 8 # | store i64 %acc, ptr %acc.addr, align 8 # | %0 = load i64, ptr %acc.addr, align 8 # | %1 = bitcast i64 %0 to double # | %2 = call double @llvm.arm.cde.vcx1a.f64(i32 1, double %1, i32 12) # | %3 = bitcast double %2 to i64 # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.arm.cde.vcx1a.f64(i32 immarg, double, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vcx2d_u64(i64 noundef %n) #0 { # | entry: # | %n.addr = alloca i64, align 8 # | store i64 %n, ptr %n.addr, align 8 # | %0 = load i64, ptr %n.addr, align 8 # | %1 = bitcast i64 %0 to double # | %2 = call double @llvm.arm.cde.vcx2.f64(i32 0, double %1, i32 21) # | %3 = bitcast double %2 to i64 # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.arm.cde.vcx2.f64(i32 immarg, double, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vcx2da_u64(i64 noundef %acc, i64 noundef %n) #0 { # | entry: # | %acc.addr = alloca i64, align 8 # | %n.addr = alloca i64, align 8 # | store i64 %acc, ptr %acc.addr, align 8 # | store i64 %n, ptr %n.addr, align 8 # | %0 = load i64, ptr %acc.addr, align 8 # | %1 = bitcast i64 %0 to double # | %2 = load i64, ptr %n.addr, align 8 # | %3 = bitcast i64 %2 to double # | %4 = call double @llvm.arm.cde.vcx2a.f64(i32 0, double %1, double %3, i32 22) # | %5 = bitcast double %4 to i64 # | ret i64 %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.arm.cde.vcx2a.f64(i32 immarg, double, double, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vcx3d_u64(i64 noundef %n, i64 noundef %m) #0 { # | entry: # | %n.addr = alloca i64, align 8 # | %m.addr = alloca i64, align 8 # | store i64 %n, ptr %n.addr, align 8 # | store i64 %m, ptr %m.addr, align 8 # | %0 = load i64, ptr %n.addr, align 8 # | %1 = bitcast i64 %0 to double # | %2 = load i64, ptr %m.addr, align 8 # | %3 = bitcast i64 %2 to double # | %4 = call double @llvm.arm.cde.vcx3.f64(i32 1, double %1, double %3, i32 3) # | %5 = bitcast double %4 to i64 # | ret i64 %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.arm.cde.vcx3.f64(i32 immarg, double, double, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vcx3da_u64(i64 noundef %acc, i64 noundef %n, i64 noundef %m) #0 { # | entry: # | %acc.addr = alloca i64, align 8 # | %n.addr = alloca i64, align 8 # | %m.addr = alloca i64, align 8 # | store i64 %acc, ptr %acc.addr, align 8 # | store i64 %n, ptr %n.addr, align 8 # | store i64 %m, ptr %m.addr, align 8 # | %0 = load i64, ptr %acc.addr, align 8 # | %1 = bitcast i64 %0 to double # | %2 = load i64, ptr %n.addr, align 8 # | %3 = bitcast i64 %2 to double # | %4 = load i64, ptr %m.addr, align 8 # | %5 = bitcast i64 %4 to double # | %6 = call double @llvm.arm.cde.vcx3a.f64(i32 0, double %1, double %3, double %5, i32 5) # | %7 = bitcast double %6 to i64 # | ret i64 %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.arm.cde.vcx3a.f64(i32 immarg, double, double, double, i32 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+cdecp0,+cdecp1,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055707ed2b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055707ed28515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055707ed2bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f86c1049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f86c10a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f86c1049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f86c1031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055707ecc124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055707ecc1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055707eca5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055707e955176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055707e954e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f86c1032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f86c10330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f86c10330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055707e954d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c (1823 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16mf4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_i16mf4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_i16mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_i16m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align # | ... # `---data was truncated (10240/39416) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005574c6a3e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005574c6a3b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005574c6a3ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7ae4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7ae478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7ae4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7ae471b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005574c69d424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005574c69d4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005574c69b8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005574c6668176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005574c6667e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7ae471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7ae471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7ae471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005574c6667d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c (1824 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f32.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c (1825 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i64m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i64m1( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv1i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i64m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i64m2( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i64m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i64m4( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i64m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i64m8( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i64m1_m( %mask, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load , ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i64m1_m( %mask, %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load i64, ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.mask.nxv1i64.i64.i64( poison # | ... # `---data was truncated (10240/18569) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565328b6357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000565328b60515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000565328b63cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff5f881bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff5f88725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff5f881ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff5f8803507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565328af924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000565328af9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000565328addf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056532878d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056532878ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff5f8804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff5f88050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff5f88050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056532878cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vrnd.c (1826 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vrnd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c --check-prefixes=CHECK,CHECK-NOSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndaq_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x half> @llvm.round.v8f16(<8 x half> %0) # | ret <8 x half> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.round.v8f16(<8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndaq_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x float> @llvm.round.v4f32(<4 x float> %0) # | ret <4 x float> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.round.v4f32(<4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndmq_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x half> @llvm.floor.v8f16(<8 x half> %0) # | ret <8 x half> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.floor.v8f16(<8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndmq_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x float> @llvm.floor.v4f32(<4 x float> %0) # | ret <4 x float> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.floor.v4f32(<4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndpq_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x half> @llvm.ceil.v8f16(<8 x half> %0) # | ret <8 x half> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.ceil.v8f16(<8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndpq_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x float> @llvm.ceil.v4f32(<4 x float> %0) # | ret <4 x float> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.ceil.v4f32(<4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndq_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x half> @llvm.trunc.v8f16(<8 x half> %0) # | ret <8 x half> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.trunc.v8f16(<8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndq_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x float> @llvm.trunc.v4f32(<4 x float> %0) # | ret <4 x float> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.trunc.v4f32(<4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndxq_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x half> @llvm.rint.v8f16(<8 x half> %0) # | ret <8 x half> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.rint.v8f16(<8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndxq_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x float> @llvm.rint.v4f32(<4 x float> %0) # | ret <4 x float> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.rint.v4f32(<4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndnq_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x half> @llvm.roundeven.v8f16(<8 x half> %0) # | ret <8 x half> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.roundeven.v8f16(<8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndnq_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %0) # | ret <4 x float> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.roundeven.v4f32(<4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndaq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x half>, ptr %inactive.addr, align 8 # | %5 = call <8 x half> @llvm.arm.mve.vrinta.predicated.v8f16.v8i1(<8 x half> %0, <8 x i1> %3, <8 x half> %4) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vrinta.predicated.v8f16.v8i1(<8 x half>, <8 x i1>, <8 x half>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndaq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x float>, ptr %inactive.addr, align 8 # | %5 = call <4 x float> @llvm.arm.mve.vrinta.predicated.v4f32.v4i1(<4 x float> %0, <4 x i1> %3, <4 x float> %4) # | ret <4 x float> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.vrinta.predicated.v4f32.v4i1(<4 x float>, <4 x i1>, <4 x float>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndmq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x half>, ptr %inactive.addr, align 8 # | %5 = call <8 x half> @llvm.arm.mve.vrintm.predicated.v8f16.v8i1(<8 x half> %0, <8 x i1> %3, <8 x half> %4) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vrintm.predicated.v8f16.v8i1(<8 x half>, <8 x i1>, <8 x half>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndmq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1 # | ... # `---data was truncated (10240/26476) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558624d9457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558624d91515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558624d94cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb1dc049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb1dc0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb1dc049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb1dc031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558624d2a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558624d2a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558624d0ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005586249be176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005586249bde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb1dc032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb1dc0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb1dc0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005586249bdd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c --check-prefixes=CHECK,CHECK-NOSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c --check-prefixes=CHECK,CHECK-NOSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c (1827 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005587eda2557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005587eda22515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005587eda25cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efc2ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efc2ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efc2ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efc2ff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005587ed9bb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005587ed9bb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005587ed99ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005587ed64f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005587ed64ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efc2ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efc2ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efc2ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005587ed64ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c (1828 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nx # | ... # `---data was truncated (10240/78682) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b5188b857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b5188b5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b5188b8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb629333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb62938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb629333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb62931b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b51884e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b51884e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b518832f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b5184e2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b5184e1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb62931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb62931d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb62931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b5184e1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c (1829 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_i8mf8x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_i8mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_i8mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_i8m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_u8mf8x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_u8mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_u8mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_u8m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_i8mf8x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | # | ... # `---data was truncated (10240/21558) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005577bac9d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005577bac9a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005577bac9dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1f51849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1f518a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1f51849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1f51831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005577bac3324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005577bac33096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005577bac17f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005577ba8c7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005577ba8c6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1f51832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1f518330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1f518330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005577ba8c6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c (1830 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vx_i16mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wx_i16mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.w.nxv1i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vx_i16mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wx_i16mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.w.nxv2i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vx_i16m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wv_i16m # | ... # `---data was truncated (10240/134565) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557d5c00f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557d5c00c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557d5c00fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7d5b305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7d5b35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7d5b305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7d5b2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557d5bfa524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557d5bfa5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557d5bf89f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557d5bc39176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557d5bc38e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7d5b2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7d5b2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7d5b2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557d5bc38d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c (1831 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define d # | ... # `---data was truncated (10240/12208) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562fef56d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562fef56a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562fef56dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efcd8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efcd898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efcd8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efcd891b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562fef50324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562fef503096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562fef4e7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562fef197176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562fef196e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efcd891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efcd891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efcd891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562fef196d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c (1832 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , , i64, i64 immarg) # # | ... # `---data was truncated (10240/12075) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f6473e657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f6473e3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f6473e6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0a8dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0a8dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0a8dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0a8dc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f64737c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f64737c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f647360f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f647010176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f64700fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0a8dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0a8dc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0a8dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f64700fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c (1833 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m1x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m1x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m1x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m1x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m4x2_m(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c (1834 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare # | ... # `---data was truncated (10240/20139) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557f68b4557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557f68b42515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557f68b45cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd33f105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd33f15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd33f105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd33f0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557f68adb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557f68adb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557f68abff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557f6876f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557f6876ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd33f0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd33f0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd33f0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557f6876ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/linker-diagnostic.ll (1835 of 27911) ******************** TEST 'Clang :: CodeGen/linker-diagnostic.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 2 mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp # executed command: mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp/foo.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/linker-diagnostic.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp/foo.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/linker-diagnostic.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp/foo.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/linker-diagnostic.ll # | #0 0x000055e6067e857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e6067e5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e6067e8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0f01933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0f0198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0f01933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0f0191b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e60677e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e60677e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e606762f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e606412176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e606411e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0f0191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0f0191d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0f0191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e606411d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c (1836 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559bee84357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559bee840515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559bee843cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f61e6905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f61e695c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f61e6905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f61e68ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559bee7d924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559bee7d9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559bee7bdf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559bee46d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559bee46ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f61e68eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f61e68ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f61e68ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559bee46cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c (1837 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8mf8(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv1i8.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv1i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8mf4(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv2i8.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv2i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8mf2(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv4i8.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv4i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m1(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv8i8.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv8i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m2(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv16i8.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv16i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m4(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv32i8.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv32i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m8(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv64i8.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv64i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16mf4(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv1i16.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv1i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16mf2(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv2i16.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv2i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m1(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv4i16.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv4i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m2(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv8i16.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv8i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m4(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv16i16.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv16i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m8(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv32i16.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv32i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u32mf2(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv1i32.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv1i32.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u32m1(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv2i32.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv2i32.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u32m2(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv4i32.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv4i32.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u32m4(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv8i32.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv8i32.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u32m8(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv16i32.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv16i32.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u64m1(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align # | ... # `---data was truncated (10240/30303) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055611803757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556118034515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556118037cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9a40133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9a4018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9a40133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9a4011b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556117fcd24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556117fcd096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556117fb1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556117c61176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556117c60e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9a4011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9a4011d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9a4011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556117c60d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c (1838 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vvm_i8mf8_b64( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vxm_i8mf8_b64( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbc.borrow.in.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.borrow.in.nxv1i8.i8.i64(, i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbc.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbc.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vvm_i8mf4_b32( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbc.borrow.in.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.borrow.in.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vxm_i8mf4_b32( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbc.borrow.in.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.borrow.in.nxv2i8.i8.i64(, i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbc.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbc.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vvm_i8mf2_b16( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbc.borrow.in.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.borrow.in.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vxm_i8mf2_b16( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , # | ... # `---data was truncated (10240/170497) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005646a83bc57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005646a83b9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005646a83bccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8dbfd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8dbfd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8dbfd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8dbfd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005646a835224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005646a8352096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005646a8336f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005646a7fe6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005646a7fe5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8dbfd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8dbfd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8dbfd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005646a7fe5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c (1839 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv1i64.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv2i64.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv4i64.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv8i64.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m8_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m1_tumu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call # | ... # `---data was truncated (10240/18217) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056083fbba57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056083fbb7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056083fbbacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f08fd333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f08fd38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f08fd333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f08fd31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056083fb5024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056083fb50096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056083fb34f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056083f7e4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056083f7e3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f08fd31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f08fd31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f08fd31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056083f7e3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c (1840 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c (1841 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf4x8(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf2x8(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16m1x8(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf4x8_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf2x8_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16m1x8_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005559592a957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005559592a6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005559592a9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f53a021bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f53a02725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f53a021ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f53a0203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055595923f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055595923f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555959223f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555958ed3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555958ed2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f53a0204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f53a02050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f53a02050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555958ed2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c (1842 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local half @test_vfmv_f_s_f16mf4_f16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call half @llvm.riscv.vfmv.f.s.nxv1f16( %0) # | ret half %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.riscv.vfmv.f.s.nxv1f16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local half @test_vfmv_f_s_f16mf2_f16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call half @llvm.riscv.vfmv.f.s.nxv2f16( %0) # | ret half %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.riscv.vfmv.f.s.nxv2f16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local half @test_vfmv_f_s_f16m1_f16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call half @llvm.riscv.vfmv.f.s.nxv4f16( %0) # | ret half %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.riscv.vfmv.f.s.nxv4f16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local half @test_vfmv_f_s_f16m2_f16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call half @llvm.riscv.vfmv.f.s.nxv8f16( %0) # | ret half %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.riscv.vfmv.f.s.nxv8f16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local half @test_vfmv_f_s_f16m4_f16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call half @llvm.riscv.vfmv.f.s.nxv16f16( %0) # | ret half %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.riscv.vfmv.f.s.nxv16f16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local half @test_vfmv_f_s_f16m8_f16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call half @llvm.riscv.vfmv.f.s.nxv32f16( %0) # | ret half %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.riscv.vfmv.f.s.nxv32f16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local float @test_vfmv_f_s_f32mf2_f32( %src) #0 { # | entry: # | %src.addr = alloca , align 4 # | store %src, ptr %src.addr, align 4 # | %0 = load , ptr %src.addr, align 4 # | %1 = call float @llvm.riscv.vfmv.f.s.nxv1f32( %0) # | ret float %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.riscv.vfmv.f.s.nxv1f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local float @test_vfmv_f_s_f32m1_f32( %src) #0 { # | entry: # | %src.addr = alloca , align 4 # | store %src, ptr %src.addr, align 4 # | %0 = load , ptr %src.addr, align 4 # | %1 = call float @llvm.riscv.vfmv.f.s.nxv2f32( %0) # | ret float %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.riscv.vfmv.f.s.nxv2f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local float @test_vfmv_f_s_f32m2_f32( %src) #0 { # | entry: # | %src.addr = alloca , align 4 # | store %src, ptr %src.addr, align 4 # | %0 = load , ptr %src.addr, align 4 # | %1 = call float @llvm.riscv.vfmv.f.s.nxv4f32( %0) # | ret float %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.riscv.vfmv.f.s.nxv4f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local float @test_vfmv_f_s_f32m4_f32( %src) #0 { # | entry: # | %src.addr = alloca , align 4 # | store %src, ptr %src.addr, align 4 # | %0 = load , ptr %src.addr, align 4 # | %1 = call float @llvm.riscv.vfmv.f.s.nxv8f32( %0) # | ret float %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.riscv.vfmv.f.s.nxv8f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local float @test_vfmv_f_s_f32m8_f32( %src) #0 { # | entry: # | %src.addr = alloca , align 4 # | store %src, ptr %src.addr, align 4 # | %0 = load , ptr %src.addr, align 4 # | %1 = call float @llvm.riscv.vfmv.f.s.nxv16f32( %0) # | ret float %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.riscv.vfmv.f.s.nxv16f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local double @test_vfmv_f_s_f64m1_f64( %src) #0 { # | entry: # | %src.addr = alloca , align 8 # | store %src, ptr %src.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = call double @llvm.riscv.vfmv.f.s.nxv1f64( %0) # | ret double %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.riscv.vfmv.f.s.nxv1f64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local double @test_vfmv_f_s_f64m2_f64( %src) #0 { # | entry: # | %src.addr = alloca , align 8 # | store %src, ptr %src.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = call double @llvm.riscv.vfmv.f.s.nxv2f64( %0) # | ret double %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.riscv.vfmv.f.s.nxv2f64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local double @test_vfmv_f_s_f64m4_f64( %src) #0 { # | entry: # | %src.addr = alloca , align 8 # | store %src, ptr %src.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = call double @llvm.riscv.vfmv.f.s.nxv4f64( %0) # | ret double %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.riscv.vfmv.f.s.nxv4f64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local double @test_vfmv_f_s_f64m8_f64( %src) #0 { # | entry: # | %src.addr = alloca , align 8 # | store %src, ptr %src.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = call double @llvm.riscv.vfmv.f.s.nxv8f64( %0) # | ret double %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.riscv.vfmv.f.s.nxv8f64() #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557fd979f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557fd979c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557fd979fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1ce8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1ce898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1ce8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1ce891b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557fd973524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557fd9735096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557fd9719f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557fd93c9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557fd93c8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1ce891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1ce891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1ce891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557fd93c8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c (1843 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8mf8x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8mf4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_u8mf8x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_u8mf4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_u8mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_u8m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, # | ... # `---data was truncated (10240/27986) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563a1fb0357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563a1fb00515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563a1fb03cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc7cfb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc7cfb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc7cfb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc7cfb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563a1fa9924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563a1fa99096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563a1fa7df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563a1f72d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563a1f72ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc7cfb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc7cfb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc7cfb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563a1f72cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c (1844 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055db338dc57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055db338d9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055db338dccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6428933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f642898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6428933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f642891b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055db3387224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055db33872096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055db33856f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055db33506176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055db33505e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f642891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f642891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f642891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055db33505d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vrev.c (1845 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vrev.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev16q_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev16q_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev32q_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev32q_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrev32q_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <8 x i32> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrev32q_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <8 x i32> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrev32q_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = shufflevector <8 x half> %0, <8 x half> poison, <8 x i32> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev64q_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev64q_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrev64q_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <8 x i32> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrev64q_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <8 x i32> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrev64q_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = shufflevector <8 x half> %0, <8 x half> poison, <8 x i32> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrev64q_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = shufflevector <4 x float> %0, <4 x float> poison, <4 x i32> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrev64q_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = shufflevector <4 x i32> %0, <4 x i32> poison, <4 x i32> # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrev64q_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = shufflevector <4 x i32> %0, <4 x i32> poison, <4 x i32> # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev16q_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = load <16 x i8>, ptr %inactive.addr, align 8 # | %5 = call <16 x i8> @llvm.arm.mve.vrev.predicated.v16i8.v16i1(<16 x i8> %0, i32 16, <16 x i1> %3, <16 x i8> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vrev.predicated.v16i8.v16i1(<16 x i8>, i32, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev16q_m_u8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = load <16 x i8>, ptr %inactive.addr, align 8 # | %5 = call <16 x i8> @llvm.arm.mve.vrev.predicated.v16i8.v16i1(<16 x i8> %0, i32 16, <16 x i1> %3, <16 x i8> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrev32q_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x half>, ptr %inactive.addr, align 8 # | %5 = call <8 x half> @llvm.arm.mve.vrev.predicated.v8f16.v8i1(<8 x half> %0, i32 32, <8 x i1> %3, <8 x half> %4) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vrev.predicated.v8f16.v8i1(<8 x half>, i32, <8 x i1>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev32q_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | # | ... # `---data was truncated (10240/29535) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005645333c857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005645333c5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005645333c8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f42a8049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f42a80a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f42a8049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f42a8031507 abort ./stdlib/abort.c:85:3 # | #7 0x000056453335e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056453335e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564533342f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564532ff2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564532ff1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f42a8032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f42a80330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f42a80330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564532ff1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c (1846 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf8x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_u8mf8x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl. # | ... # `---data was truncated (10240/72143) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560699a0857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560699a05515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560699a08cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efd61133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efd6118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efd61133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efd6111b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056069999e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056069999e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560699982f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560699632176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560699631e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efd6111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efd6111d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efd6111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560699631d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c (1847 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf4x3(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf2x3(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m1x3(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m2x3(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m1x3_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m2x3_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560c4598d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560c4598a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560c4598dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9894533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f989458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9894533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f989451b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560c4592324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560c45923096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560c45907f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560c455b7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560c455b6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f989451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f989451d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f989451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560c455b6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c (1848 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16mf4x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16mf2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16mf4x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16mf2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_u16mf4x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_u16mf2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_u16m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_u16m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16mf4x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = allo # | ... # `---data was truncated (10240/23031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fad421d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fad421a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fad421dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc51de1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc51de725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc51de1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc51de03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fad41b324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fad41b3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fad4197f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fad3e47176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fad3e46e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc51de04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc51de050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc51de050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fad3e46d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c (1849 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv64i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16mf4( %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i16, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv1i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16mf2( %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i16, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv2i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16m1( %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i16, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv4i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16m2( %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i16, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv8i16 # | ... # `---data was truncated (10240/84971) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f9fdddd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f9fddda515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f9fddddcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9c03b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9c03b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9c03b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9c03aed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f9fdd7324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f9fdd73096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f9fdd57f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f9fda07176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f9fda06e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9c03aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9c03aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9c03aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f9fda06d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c (1850 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_f64m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_i64m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_u64m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_f64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_i64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_u64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556400a1857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556400a15515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556400a18cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7923249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f79232a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7923249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7923231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005564009ae24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005564009ae096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556400992f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556400642176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556400641e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7923232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f79232330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f79232330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556400641d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c (1851 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1f32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2f32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4f32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8f32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv16f32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8i32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv16i32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_u32mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %bas # | ... # `---data was truncated (10240/60209) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d8bdd3757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d8bdd34515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d8bdd37cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd89221bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd8922725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd89221ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd892203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d8bdccd24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d8bdccd096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d8bdcb1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d8bd961176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d8bd960e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd892204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd8922050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd8922050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d8bd960d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c (1852 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf8x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv1i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv1i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf4x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m1x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m4x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv32i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv32i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v # | ... # `---data was truncated (10240/18520) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bf2728057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bf2727d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bf27280cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffa58c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffa58c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffa58c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffa58c03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bf2721624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bf27216096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bf271faf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bf26eaa176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bf26ea9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ffa58c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffa58c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffa58c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bf26ea9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c (1853 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f32m2x2(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c (1854 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv64i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv32i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv16i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv8i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv4i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv2i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv1i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ad3741357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ad37410515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ad37413cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4bbb133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4bbb18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4bbb133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4bbb11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ad373a924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ad373a9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ad3738df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ad3703d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ad3703ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4bbb11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4bbb11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4bbb11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ad3703cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c (1855 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf8x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf4x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf8x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf4x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a2d5dd557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a2d5dd2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a2d5dd5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbc22133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbc2218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbc22133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbc2211b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a2d5d6b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a2d5d6b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a2d5d4ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a2d59ff176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a2d59fee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbc2211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbc2211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbc2211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a2d59fed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c (1856 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv4i64.nxv1 # | ... # `---data was truncated (10240/47628) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561f59dd057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561f59dcd515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561f59dd0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0be3649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0be36a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0be3649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0be3631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561f59d6624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561f59d66096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561f59d4af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561f599fa176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561f599f9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0be3632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0be36330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0be36330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561f599f9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c (1857 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16mf4x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16mf2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16mf4x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16mf2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_u16mf4x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_u16mf2x4_m( %mask, ptr nound # | ... # `---data was truncated (10240/13515) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f30d74b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f30d748515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f30d74bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6abbc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6abbca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6abbc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6abbc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f30d6e124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f30d6e1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f30d6c5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f30d375176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f30d374e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6abbc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6abbc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6abbc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f30d374d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c (1858 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m4_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c (1859 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_f32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_f32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_i32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_i32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_u32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_u32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_f32mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_f32m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vsca # | ... # `---data was truncated (10240/15944) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559d9f28157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559d9f27e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559d9f281cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5f8521bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5f852725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5f8521ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5f85203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559d9f21724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559d9f217096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559d9f1fbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559d9eeab176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559d9eeaae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5f85204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5f852050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5f852050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559d9eeaad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c (1860 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561cceecb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561cceec8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561cceecbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f68a1b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f68a1b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f68a1b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f68a1b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561ccee6124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561ccee61096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561ccee45f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561cceaf5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561cceaf4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f68a1b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f68a1b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f68a1b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561cceaf4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c (1861 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f64m1_tu( %maskedoff, ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c (1862 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrnbq_n_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 3, i32 0, i32 0, i32 0, i32 0, i32 0) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8>, <8 x i16>, i32, i32, i32, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrnbq_n_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 9, i32 0, i32 0, i32 0, i32 0, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16>, <4 x i32>, i32, i32, i32, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrnbq_n_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 0, i32 0, i32 1, i32 1, i32 0) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrnbq_n_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 3, i32 0, i32 0, i32 1, i32 1, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrntq_n_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrntq_n_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 10, i32 0, i32 0, i32 0, i32 0, i32 1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrntq_n_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 6, i32 0, i32 0, i32 1, i32 1, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrntq_n_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 10, i32 0, i32 0, i32 1, i32 1, i32 1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrnbq_m_n_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 4, i32 0, i32 0, i32 0, i32 0, i32 0, <8 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8>, <8 x i16>, i32, i32, i32, i32, i32, i32, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrnbq_m_n_s32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 13, i32 0, i32 0, i32 0, i32 0, i32 0, <4 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16>, <4 x i32>, i32, i32, i32, i32, i32, i32, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrnbq_m_n_u16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 7, i32 0, i32 0, i32 1, i32 1, i32 0, <8 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrnbq_m_n_u32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 15, i32 0, i32 0, i32 1, i32 1, i32 0, <4 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrntq_m_n_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 6, i32 0, i32 0, i32 0, i32 0, i32 1, <8 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrntq_m_n_s32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 # | ... # `---data was truncated (10240/73182) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005643f88da57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005643f88d7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005643f88dacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff149105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff14915c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff149105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff1490ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005643f887024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005643f8870096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005643f8854f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005643f8504176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005643f8503e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff1490eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff1490ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff1490ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005643f8503d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c (1863 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback n # | ... # `---data was truncated (10240/40795) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cbcbdf357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cbcbdf0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cbcbdf3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f19c9e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f19c9ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f19c9e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f19c9e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cbcbd8924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cbcbd89096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cbcbd6df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cbcba1d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cbcba1ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f19c9e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f19c9e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f19c9e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cbcba1cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c (1864 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv1bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv2bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv4bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv8bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv16bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv32bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv32bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrec7.mask.nxv1bf16.i64( %1, %2, %0, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrec7.mask.nxv2bf16.i64( %1, %2, %0, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, a # | ... # `---data was truncated (10240/28358) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cb4061957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cb40616515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cb40619cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f987eb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f987eb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f987eb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f987eaed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cb405af24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cb405af096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cb40593f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cb40243176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cb40242e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f987eaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f987eaef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f987eaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cb40242d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c (1865 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f32m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | re # | ... # `---data was truncated (10240/120915) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f09ebd757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f09ebd4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f09ebd7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f581181bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f58118725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f581181ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5811803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f09eb6d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f09eb6d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f09eb51f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f09e801176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f09e800e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5811804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f58118050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f58118050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f09e800d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c (1866 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f64m1_tu( %maskedoff, ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c (1867 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558a5cb5957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558a5cb56515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558a5cb59cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9d6f449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9d6f4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9d6f449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9d6f431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558a5caef24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558a5caef096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558a5cad3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558a5c783176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558a5c782e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9d6f432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9d6f4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9d6f4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558a5c782d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/cx-complex-range.c (1868 of 27911) ******************** TEST 'Clang :: CodeGen/cx-complex-range.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c -O0 -disable-O0-optnone -emit-llvm -triple x86_64-unknown-unknown -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c --check-prefix=FULL # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c -O0 -disable-O0-optnone -emit-llvm -triple x86_64-unknown-unknown -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-unknown" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @divf(<2 x float> noundef %a.coerce, <2 x float> noundef %b.coerce) #0 { # | entry: # | %retval = alloca { float, float }, align 4 # | %a = alloca { float, float }, align 4 # | %b = alloca { float, float }, align 4 # | %coerce = alloca { float, float }, align 4 # | store <2 x float> %a.coerce, ptr %a, align 4 # | store <2 x float> %b.coerce, ptr %b, align 4 # | %a.realp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 0 # | %a.real = load float, ptr %a.realp, align 4 # | %a.imagp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 1 # | %a.imag = load float, ptr %a.imagp, align 4 # | %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0 # | %b.real = load float, ptr %b.realp, align 4 # | %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1 # | %b.imag = load float, ptr %b.imagp, align 4 # | %call = call <2 x float> @__divsc3(float noundef %a.real, float noundef %a.imag, float noundef %b.real, float noundef %b.imag) #2 # | store <2 x float> %call, ptr %coerce, align 4 # | %coerce.realp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 0 # | %coerce.real = load float, ptr %coerce.realp, align 4 # | %coerce.imagp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 1 # | %coerce.imag = load float, ptr %coerce.imagp, align 4 # | %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0 # | %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1 # | store float %coerce.real, ptr %retval.realp, align 4 # | store float %coerce.imag, ptr %retval.imagp, align 4 # | %0 = load <2 x float>, ptr %retval, align 4 # | ret <2 x float> %0 # | } # | # | declare <2 x float> @__divsc3(float, float, float, float) # | # | ; Function Attrs: noinline nounwind # | define dso_local void @divassignf(ptr noundef %a, <2 x float> noundef %b.coerce) #0 { # | entry: # | %b = alloca { float, float }, align 4 # | %a.addr = alloca ptr, align 8 # | %coerce = alloca { float, float }, align 4 # | store <2 x float> %b.coerce, ptr %b, align 4 # | store ptr %a, ptr %a.addr, align 8 # | %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0 # | %b.real = load float, ptr %b.realp, align 4 # | %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1 # | %b.imag = load float, ptr %b.imagp, align 4 # | %0 = load ptr, ptr %a.addr, align 8 # | %.realp = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 0 # | %.real = load float, ptr %.realp, align 4 # | %.imagp = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 1 # | %.imag = load float, ptr %.imagp, align 4 # | %call = call <2 x float> @__divsc3(float noundef %.real, float noundef %.imag, float noundef %b.real, float noundef %b.imag) #2 # | store <2 x float> %call, ptr %coerce, align 4 # | %coerce.realp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 0 # | %coerce.real = load float, ptr %coerce.realp, align 4 # | %coerce.imagp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 1 # | %coerce.imag = load float, ptr %coerce.imagp, align 4 # | %.realp1 = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 0 # | %.imagp2 = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 1 # | store float %coerce.real, ptr %.realp1, align 4 # | store float %coerce.imag, ptr %.imagp2, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @mulf(<2 x float> noundef %a.coerce, <2 x float> noundef %b.coerce) #0 { # | entry: # | %retval = alloca { float, float }, align 4 # | %a = alloca { float, float }, align 4 # | %b = alloca { float, float }, align 4 # | %coerce = alloca { float, float }, align 4 # | store <2 x float> %a.coerce, ptr %a, align 4 # | store <2 x float> %b.coerce, ptr %b, align 4 # | %a.realp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 0 # | %a.real = load float, ptr %a.realp, align 4 # | %a.imagp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 1 # | %a.imag = load float, ptr %a.imagp, align 4 # | %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0 # | %b.real = load float, ptr %b.realp, align 4 # | %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1 # | %b.imag = load float, ptr %b.imagp, align 4 # | %mul_ac = fmul float %a.real, %b.real # | %mul_bd = fmul float %a.imag, %b.imag # | %mul_ad = fmul float %a.real, %b.imag # | %mul_bc = fmul float %a.imag, %b.real # | %mul_r = fsub float %mul_ac, %mul_bd # | %mul_i = fadd float %mul_ad, %mul_bc # | %isnan_cmp = fcmp uno float %mul_r, %mul_r # | br i1 %isnan_cmp, label %complex_mul_imag_nan, label %complex_mul_cont, !prof !2 # | # | complex_mul_imag_nan: ; preds = %entry # | %isnan_cmp1 = fcmp uno float %mul_i, %mul_i # | br i1 %isnan_cmp1, label %complex_mul_libcall, label %complex_mul_cont, !prof !2 # | # | complex_mul_libcall: ; preds = %complex_mul_imag_nan # | %call = call <2 x float> @__mulsc3(float noundef %a.real, float noundef %a.imag, float noundef %b.real, float noundef %b.imag) #2 # | store <2 x float> %call, ptr %coerce, align 4 # | %coerce.realp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 0 # | %coerce.real = load float, ptr %coerce.realp, align 4 # | %coerce.imagp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 1 # | %coerce.imag = load float, ptr %coerce.imagp, align 4 # | br label %complex_mul_cont # | # | complex_mul_cont: ; preds = %complex_mul_libcall, %complex_mul_imag_nan, %entry # | %real_mul_phi = phi float [ %mul_r, %entry ], [ %mul_r, %complex_mul_imag_nan ], [ %coerce.real, %complex_mul_libcall ] # | %imag_mul_phi = phi float [ %mul_i, %entry ], [ %mul_i, %complex_mul_imag_nan ], [ %coerce.imag, %complex_mul_libcall ] # | %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0 # | %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1 # | store float %real_mul_phi, ptr %retval.realp, align 4 # | store float %imag_mul_phi, ptr %retval.imagp, align 4 # | %0 = load <2 x float>, ptr %retval, align 4 # | ret <2 x float> %0 # | } # | # | declare <2 x float> @__mulsc3(float, float, float, float) # | # | ; Function Attrs: noinline nounwind # | define dso_local void @mulassignf(ptr noundef %a, <2 x float> noundef %b.coerce) #0 { # | entry: # | %b = alloca { float, float }, align 4 # | %a.addr = alloca ptr, align 8 # | %coerce = alloca { float, float }, align 4 # | store <2 x float> %b.coerce, ptr %b, align 4 # | store ptr %a, ptr %a.addr, align 8 # | %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0 # | %b.real = load float, ptr %b.realp, align 4 # | %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1 # | %b.imag = load float, ptr %b.imagp, align 4 # | %0 = load ptr, ptr %a.addr, align 8 # | %.realp = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 0 # | %.real = load float, ptr %.realp, align 4 # | %.imagp = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 1 # | %.imag = load float, ptr %.imagp, align 4 # | %mul_ac = fmul float %.real, %b.real # | %mul_bd = fmul float %.imag, %b.imag # | %mul_ad = fmul float %.real, %b.imag # | %mul_bc = fmul float %.imag, %b.real # | %mul_r = fsub float %mul_ac, %mul_bd # | %mul_i = fadd float %mul_ad, %mul_bc # | %isnan_cmp = fcmp uno float %mul_r, %mul_r # | br i1 %isnan_cmp, label %complex_mul_imag_nan, label %complex_mul_cont, !prof !2 # | # | complex_mul_imag_nan: ; preds = %entry # | %isnan_cmp1 = fcmp uno float %mul_i, %mul_i # | br i1 %isnan_cmp1, label %complex_mul_libcall, label %complex_mul_cont, !prof !2 # | # | complex_mul_libcall: ; preds = %complex_mul_imag_nan # | %call = call <2 x float> @__mulsc3(float noundef %.real, float noundef %.imag, float noundef %b.real, float noundef %b.imag) #2 # | store <2 x float> %call, ptr %coerce, align 4 # | %coerce.realp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 0 # | %coerce.real = load float, ptr %coerce.realp, align 4 # | %coerce.imagp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 1 # | %coerce.imag = load float, ptr %coerce.imagp, align 4 # | br label %complex_mul_cont # | # | complex_mul_cont: ; preds = %complex_mul_libcall, %complex_mul_imag_nan, %entry # | %real_mul_phi = phi float [ %mul_r, %entry ], [ %mul_r, %complex_mul_imag_nan ], [ %coerce.real, %complex_mul_libcall ] # | %imag_mul_phi = phi float [ %mul_i, %entry ], [ %mul_i, %complex_mul_imag_nan ], [ %coerce.imag, %complex_mul_libcall ] # | %.realp2 = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 0 # | %.imagp3 = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 1 # | store float %real_mul_phi, ptr %.realp2, align 4 # | store float %imag_mul_phi, ptr %.imagp3, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local { double, double } @divd(double noundef %a.coerce0, double noundef %a.coerce1, double noundef %b.coerce0, double noundef %b.coerce1) #1 { # | entry: # | %retval = alloca { double, double }, align 8 # | %a = alloca { double, double }, align 8 # | %b = alloca { double, double }, align 8 # | %0 = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 0 # | store double %a.coerce0, ptr %0, align 8 # | %1 = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 1 # | store double %a.coerce1, ptr %1, align 8 # | %2 = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 0 # | store double %b.coerce0, ptr %2, align 8 # | %3 = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 1 # | store double %b.coerce1, ptr %3, align 8 # | %a.realp = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 0 # | %a.real = load double, ptr %a.realp, align 8 # | %a.imagp = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 1 # | %a.imag = load doub # | ... # `---data was truncated (10240/29171) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x000056145afaa57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056145afa7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056145afaacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7cc4533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7cc458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7cc4533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7cc451b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056145af4024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056145af40096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056145af24f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056145abd4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056145abd3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7cc451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7cc451d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7cc451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056145abd3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c --check-prefix=FULL # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c --check-prefix=FULL # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c (1869 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv16i32.nxv16i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv16i32.nxv16i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u64m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32.i64( poison, %0, i32 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32.i64(, , i32, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u64 # | ... # `---data was truncated (10240/29259) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f9a30b157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f9a30ae515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f9a30b1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f34a0533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f34a058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f34a0533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f34a051b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f9a304724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f9a3047096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f9a302bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f9a2cdb176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f9a2cdae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f34a051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f34a051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f34a051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f9a2cdad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c (1870 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c -check-prefix=RV64ZKND-ZKNE # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @aes64ks1i(i64 noundef %rs1) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = call i64 @llvm.riscv.aes64ks1i(i64 %0, i32 0) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.aes64ks1i(i64, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @aes64ks2(i64 noundef %rs1, i64 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i64, align 8 # | %__y.addr.i = alloca i64, align 8 # | %rs1.addr = alloca i64, align 8 # | %rs2.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | store i64 %0, ptr %__x.addr.i, align 8 # | store i64 %1, ptr %__y.addr.i, align 8 # | %2 = load i64, ptr %__x.addr.i, align 8 # | %3 = load i64, ptr %__y.addr.i, align 8 # | %4 = call i64 @llvm.riscv.aes64ks2(i64 %2, i64 %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.aes64ks2(i64, i64) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zknd" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zknd1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556c299e757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556c299e4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556c299e7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4e80533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4e8058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4e80533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4e8051b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556c2997d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556c2997d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556c29961f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556c29611176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556c29610e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4e8051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4e8051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4e8051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556c29610d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c -check-prefix=RV64ZKND-ZKNE # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c -check-prefix=RV64ZKND-ZKNE # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c (1871 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005641dce2757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005641dce24515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005641dce27cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4063c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4063ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4063c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4063c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005641dcdbd24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005641dcdbd096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005641dcda1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005641dca51176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005641dca50e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4063c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4063c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4063c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005641dca50d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/builtins-riscv.c (1872 of 27911) ******************** TEST 'Clang :: CodeGen/builtins-riscv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple riscv32 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple riscv32 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_eh_return_data_regno() #0 { # | entry: # | %res = alloca i32, align 4 # | store volatile i32 10, ptr %res, align 4 # | store volatile i32 11, ptr %res, align 4 # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i" } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557adc2f057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557adc2ed515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557adc2f0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7e17d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7e17d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7e17d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7e17d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557adc28624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557adc286096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557adc26af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557adbf1a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557adbf19e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7e17d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7e17d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7e17d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557adbf19d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c (1873 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_bf16mf4_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_bf16mf4_f32mf2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_bf16mf4_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_bf16_f32mf2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_bf16mf2_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_bf16mf2_f32m1_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_bf16mf2_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_bf16_f32m1_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c (1874 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv32i16.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwi # | ... # `---data was truncated (10240/205813) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557d66b6f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557d66b6c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557d66b6fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7772d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7772d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7772d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7772d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557d66b0524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557d66b05096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557d66ae9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557d66799176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557d66798e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7772d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7772d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7772d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557d66798d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c (1875 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op # | ... # `---data was truncated (10240/222917) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f4424bd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f4424ba515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f4424bdcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9550649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f95506a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9550649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9550631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f44245324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f442453096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f442437f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f4420e7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f4420e6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9550632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f95506330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f95506330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f4420e6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c (1876 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv16f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv16f16.f16.i64( poison, %0, ha # | ... # `---data was truncated (10240/125649) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c512fc357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c512fc0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c512fc3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9f72c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9f72ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9f72c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9f72c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c512f5924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c512f59096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c512f3df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c512bed176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c512bece93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9f72c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9f72c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9f72c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c512becd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c (1877 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vx_u16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wv_u16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wx_u16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.w.nxv1i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vx_u16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wv_u16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wx_u16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.w.nxv2i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/306627) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bb9246457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bb92461515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bb92464cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2cca705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2cca75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2cca705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2cca6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bb923fa24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bb923fa096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bb923def49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bb9208e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bb9208de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2cca6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2cca6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2cca6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bb9208dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c (1878 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c (1879 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/48313) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ded49bc57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ded49b9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ded49bccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faf5dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faf5dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faf5dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faf5dd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ded495224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ded4952096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ded4936f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ded45e6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ded45e5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007faf5dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faf5dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faf5dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ded45e5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c (1880 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16mf4_i8mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16mf2_i8mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m1_i8mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m2_i8m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m4_i8m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m8_i8m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16mf4_u8mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16mf2_u8mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m1_u8mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m2_u8m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, # | ... # `---data was truncated (10240/142319) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ac5e89957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ac5e896515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ac5e899cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f719c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f719c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f719c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f719c51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ac5e82f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ac5e82f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ac5e813f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ac5e4c3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ac5e4c2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f719c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f719c51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f719c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ac5e4c2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c (1881 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_f64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_i64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_u64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_f64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_i64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_u64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005632f555157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005632f554e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005632f5551cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4712933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f471298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4712933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f471291b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005632f54e724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005632f54e7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005632f54cbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005632f517b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005632f517ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f471291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f471291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f471291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005632f517ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c (1882 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f64m1x4(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c (1883 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv8f32.nxv8f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f32.nxv8f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv16f32.nxv16f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16f32.nxv16f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1. # | ... # `---data was truncated (10240/30869) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e7908df57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e7908dc515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e7908dfcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5087133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f508718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5087133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f508711b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e79087524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e790875096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e790859f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e790509176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e790508e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f508711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f508711d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f508711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e790508d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c (1884 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | stor # | ... # `---data was truncated (10240/52599) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055752a7fb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055752a7f8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055752a7fbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1712849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f17128a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1712849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1712831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055752a79124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055752a791096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055752a775f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055752a425176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055752a424e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1712832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f17128330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f17128330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055752a424d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c (1885 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f8b880457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f8b8801515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f8b8804cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc450533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc45058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc450533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc45051b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f8b879a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f8b879a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f8b877ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f8b842e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f8b842de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc45051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc45051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc45051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f8b842dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c (1886 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_f16mf4x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_f16mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_f16m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_f16m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_i16mf4x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_i16mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_i16m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_i16m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_u16mf4x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_u16mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_ # | ... # `---data was truncated (10240/26936) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556d5a25c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556d5a259515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556d5a25ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efd4b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efd4b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efd4b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efd4b11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556d5a1f224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556d5a1f2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556d5a1d6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556d59e86176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556d59e85e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efd4b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efd4b11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efd4b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556d59e85d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c (1887 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | ... # `---data was truncated (10240/34356) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555f8112c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555f81129515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555f8112ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb05041bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb0504725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb05041ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb050403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555f810c224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555f810c2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555f810a6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555f80d56176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555f80d55e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb050404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb0504050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb0504050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555f80d55d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c (1888 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf4x7_tumu( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 0, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector. # | ... # `---data was truncated (10240/16808) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c60d41757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c60d414515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c60d417cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f689b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f689b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f689b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f689b11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c60d3ad24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c60d3ad096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c60d391f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c60d041176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c60d040e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f689b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f689b11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f689b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c60d040d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vaddv.c (1889 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vaddv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %0, i32 0) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.addv.v16i8(<16 x i8>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v8i16(<8 x i16> %0, i32 0) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.addv.v8i16(<8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v4i32(<4 x i32> %0, i32 0) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.addv.v4i32(<4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %0, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v8i16(<8 x i16> %0, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v4i32(<4 x i32> %0, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_s8(i32 noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %b.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %0, i32 0) # | %2 = load i32, ptr %a.addr, align 4 # | %3 = add i32 %1, %2 # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_s16(i32 noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %b.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v8i16(<8 x i16> %0, i32 0) # | %2 = load i32, ptr %a.addr, align 4 # | %3 = add i32 %1, %2 # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_s32(i32 noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %b.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v4i32(<4 x i32> %0, i32 0) # | %2 = load i32, ptr %a.addr, align 4 # | %3 = add i32 %1, %2 # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_u8(i32 noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %b.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %0, i32 1) # | %2 = load i32, ptr %a.addr, align 4 # | %3 = add i32 %1, %2 # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_u16(i32 noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %b.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v8i16(<8 x i16> %0, i32 1) # | %2 = load i32, ptr %a.addr, align 4 # | %3 = add i32 %1, %2 # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_u32(i32 noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %b.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v4i32(<4 x i32> %0, i32 1) # | %2 = load i32, ptr %a.addr, align 4 # | %3 = add i32 %1, %2 # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_s8(<16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = call i32 @llvm.arm.mve.addv.predicated.v16i8.v16i1(<16 x i8> %0, i32 0, <16 x i1> %3) # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.addv.predicated.v16i8.v16i1(<16 x i8>, i32, <16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_s16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %0, i32 0, <8 x i1> %3) # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16>, i32, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_s32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %3) # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32>, i32, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_u8(<16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = call i32 @llvm.arm.mve.addv.predicated.v16i8.v16i1(<16 x i8> %0, i32 1, <16 x i1> %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_u16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %0, i32 1, <8 x i1> %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_u32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 1, <4 x i1> %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_p_s8(i32 noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = # | ... # `---data was truncated (10240/19190) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f0e24a957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f0e24a6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f0e24a9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4775b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4775b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4775b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4775aed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f0e243f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f0e243f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f0e2423f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f0e20d3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f0e20d2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4775aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4775aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4775aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f0e20d2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c (1890 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c (1891 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m4_bf16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare # | ... # `---data was truncated (10240/53686) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d998b2457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d998b21515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d998b24cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f68d9249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f68d92a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f68d9249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f68d9231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d998aba24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d998aba096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d998a9ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d99874e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d99874de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f68d9232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f68d92330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f68d92330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d99874dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c (1892 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_s_u_w4_i8m8_u8m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.s.u.i64.nxv64i8.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.s.u.i64.nxv64i8.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555ebc17b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555ebc178515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555ebc17bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4b29333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4b2938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4b29333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4b2931b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555ebc11124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555ebc111096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555ebc0f5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555ebbda5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555ebbda4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4b2931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4b2931d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4b2931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555ebbda4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c (1893 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m4_tu( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c (1894 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcreate_v_f16m1_f16m2( %v0, %v1) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = call @llvm.vector.insert.nxv8f16.nxv4f16( poison, %0, i64 0) # | %3 = call @llvm.vector.insert.nxv8f16.nxv4f16( %2, %1, i64 4) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcreate_v_f16m1_f16m4( %v0, %v1, %v2, %v3) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | %v2.addr = alloca , align 2 # | %v3.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | store %v2, ptr %v2.addr, align 2 # | store %v3, ptr %v3.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = load , ptr %v2.addr, align 2 # | %3 = load , ptr %v3.addr, align 2 # | %4 = call @llvm.vector.insert.nxv16f16.nxv4f16( poison, %0, i64 0) # | %5 = call @llvm.vector.insert.nxv16f16.nxv4f16( %4, %1, i64 4) # | %6 = call @llvm.vector.insert.nxv16f16.nxv4f16( %5, %2, i64 8) # | %7 = call @llvm.vector.insert.nxv16f16.nxv4f16( %6, %3, i64 12) # | ret %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcreate_v_f16m1_f16m8( %v0, %v1, %v2, %v3, %v4, %v5, %v6, %v7) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | %v2.addr = alloca , align 2 # | %v3.addr = alloca , align 2 # | %v4.addr = alloca , align 2 # | %v5.addr = alloca , align 2 # | %v6.addr = alloca , align 2 # | %v7.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | store %v2, ptr %v2.addr, align 2 # | store %v3, ptr %v3.addr, align 2 # | store %v4, ptr %v4.addr, align 2 # | store %v5, ptr %v5.addr, align 2 # | store %v6, ptr %v6.addr, align 2 # | store %v7, ptr %v7.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = load , ptr %v2.addr, align 2 # | %3 = load , ptr %v3.addr, align 2 # | %4 = load , ptr %v4.addr, align 2 # | %5 = load , ptr %v5.addr, align 2 # | %6 = load , ptr %v6.addr, align 2 # | %7 = load , ptr %v7.addr, align 2 # | %8 = call @llvm.vector.insert.nxv32f16.nxv4f16( poison, %0, i64 0) # | %9 = call @llvm.vector.insert.nxv32f16.nxv4f16( %8, %1, i64 4) # | %10 = call @llvm.vector.insert.nxv32f16.nxv4f16( %9, %2, i64 8) # | %11 = call @llvm.vector.insert.nxv32f16.nxv4f16( %10, %3, i64 12) # | %12 = call @llvm.vector.insert.nxv32f16.nxv4f16( %11, %4, i64 16) # | %13 = call @llvm.vector.insert.nxv32f16.nxv4f16( %12, %5, i64 20) # | %14 = call @llvm.vector.insert.nxv32f16.nxv4f16( %13, %6, i64 24) # | %15 = call @llvm.vector.insert.nxv32f16.nxv4f16( %14, %7, i64 28) # | ret %15 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcreate_v_f16m2_f16m4( %v0, %v1) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = call @llvm.vector.insert.nxv16f16.nxv8f16( poison, %0, i64 0) # | %3 = call @llvm.vector.insert.nxv16f16.nxv8f16( %2, %1, i64 8) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv8f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcreate_v_f16m2_f16m8( %v0, %v1, %v2, %v3) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | %v2.addr = alloca , align 2 # | %v3.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | store %v2, ptr %v2.addr, align 2 # | store %v3, ptr %v3.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = load , ptr %v2.addr, align 2 # | %3 = load , ptr %v3.addr, align 2 # | %4 = call @llvm.vector.insert.nxv32f16.nxv8f16( poison, %0, i64 0) # | %5 = call @llvm.vector.insert.nxv32f16.nxv8f16( %4, %1, i64 8) # | %6 = call @llvm.vector.insert.nxv32f16.nxv8f16( %5, %2, i64 16) # | %7 = call @llvm.vector.insert.nxv32f16.nxv8f16( %6, %3, i64 24) # | ret %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv8f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcreate_v_f16m4_f16m8( %v0, %v1) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32f16.nxv16f16( poison, %0, i64 0) # | %3 = call @llvm.vector.insert.nxv32f16.nxv16f16( %2, %1, i64 16) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv16f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcreate_v_f32m1_f32m2( %v0, %v1) #0 { # | entry: # | %v0.addr = alloca , align 4 # | %v1.addr = alloca , align 4 # | store %v0, ptr %v0.addr, align 4 # | store %v1, ptr %v1.addr, align 4 # | %0 = load , ptr %v0.addr, align 4 # | %1 = load , ptr %v1.addr, align 4 # | %2 = call @llvm.vector.insert.nxv4f32.nxv2f32( poison, %0, i64 0) # | %3 = call @llvm. # | ... # `---data was truncated (10240/593252) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005599e1c5457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005599e1c51515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005599e1c54cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f477b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f477b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f477b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f477b031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005599e1bea24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005599e1bea096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005599e1bcef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005599e187e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005599e187de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f477b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f477b0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f477b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005599e187dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c (1895 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_i8mf8x5_tu(target("riscv.vector.tuple", , 5) %m # | ... # `---data was truncated (10240/160133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564b81bce57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564b81bcb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564b81bcecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1092b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1092b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1092b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1092b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564b81b6424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564b81b64096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564b81b48f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564b817f8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564b817f7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1092b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1092b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1092b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564b817f7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c (1896 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 4) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { ta # | ... # `---data was truncated (10240/27858) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055912388157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055912387e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559123881cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f16ca733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f16ca78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f16ca733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f16ca71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055912381724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559123817096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005591237fbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005591234ab176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005591234aae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f16ca71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f16ca71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f16ca71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005591234aad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c (1897 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f32m2x2(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c (1898 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminvq.c (1899 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminvq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc signext i8 @test_vminvq_s8(i8 noundef signext %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | %b.addr = alloca <16 x i8>, align 8 # | store i8 %a, ptr %a.addr, align 1 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load i8, ptr %a.addr, align 1 # | %1 = zext i8 %0 to i32 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.minv.v16i8(i32 %1, <16 x i8> %2, i32 0) # | %4 = trunc i32 %3 to i8 # | ret i8 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.minv.v16i8(i32, <16 x i8>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc signext i16 @test_vminvq_s16(i16 noundef signext %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %b.addr = alloca <8 x i16>, align 8 # | store i16 %a, ptr %a.addr, align 2 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load i16, ptr %a.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.minv.v8i16(i32 %1, <8 x i16> %2, i32 0) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.minv.v8i16(i32, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vminvq_s32(i32 noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call i32 @llvm.arm.mve.minv.v4i32(i32 %0, <4 x i32> %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.minv.v4i32(i32, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vminvq_u8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | %b.addr = alloca <16 x i8>, align 8 # | store i8 %a, ptr %a.addr, align 1 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load i8, ptr %a.addr, align 1 # | %1 = zext i8 %0 to i32 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.minv.v16i8(i32 %1, <16 x i8> %2, i32 1) # | %4 = trunc i32 %3 to i8 # | ret i8 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vminvq_u16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %b.addr = alloca <8 x i16>, align 8 # | store i16 %a, ptr %a.addr, align 2 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load i16, ptr %a.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.minv.v8i16(i32 %1, <8 x i16> %2, i32 1) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vminvq_u32(i32 noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call i32 @llvm.arm.mve.minv.v4i32(i32 %0, <4 x i32> %1, i32 1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc signext i8 @test_vmaxvq_s8(i8 noundef signext %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | %b.addr = alloca <16 x i8>, align 8 # | store i8 %a, ptr %a.addr, align 1 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load i8, ptr %a.addr, align 1 # | %1 = zext i8 %0 to i32 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.maxv.v16i8(i32 %1, <16 x i8> %2, i32 0) # | %4 = trunc i32 %3 to i8 # | ret i8 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.maxv.v16i8(i32, <16 x i8>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc signext i16 @test_vmaxvq_s16(i16 noundef signext %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %b.addr = alloca <8 x i16>, align 8 # | store i16 %a, ptr %a.addr, align 2 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load i16, ptr %a.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.maxv.v8i16(i32 %1, <8 x i16> %2, i32 0) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.maxv.v8i16(i32, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmaxvq_s32(i32 noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call i32 @llvm.arm.mve.maxv.v4i32(i32 %0, <4 x i32> %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.maxv.v4i32(i32, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vmaxvq_u8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | %b.addr = alloca <16 x i8>, align 8 # | store i8 %a, ptr %a.addr, align 1 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load i8, ptr %a.addr, align 1 # | %1 = zext i8 %0 to i32 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.maxv.v16i8(i32 %1, <16 x i8> %2, i32 1) # | %4 = trunc i32 %3 to i8 # | ret i8 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vmaxvq_u16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %b.addr = alloca <8 x i16>, align 8 # | store i16 %a, ptr %a.addr, align 2 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load i16, ptr %a.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.maxv.v8i16(i32 %1, <8 x i16> %2, i32 1) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmaxvq_u32(i32 noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call i32 @llvm.arm.mve.maxv.v4i32(i32 %0, <4 x i32> %1, i32 1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vminavq_s8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | %b.addr = alloca <16 x i8>, align 8 # | store i8 %a, ptr %a.addr, align 1 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load i8, ptr %a.addr, align 1 # | %1 = zext i8 %0 to i32 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.minav.v16i8(i32 %1, <16 x i8> %2) # | %4 = trunc i32 %3 to i8 # | ret i8 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.minav.v16i8(i32, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vminavq_s16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %b.addr = alloca <8 x i16>, align 8 # | store i16 %a, ptr %a.addr, align 2 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load i16, ptr %a.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.minav.v8i16(i32 %1, <8 x i16> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.minav.v8i16(i32, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vminavq_s32(i32 noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call i32 @llvm.arm.mve.minav.v4i32(i32 %0, <4 x i32> %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.minav.v4i32(i32, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vmaxavq_s8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | %b.addr = alloca <16 x i8>, align 8 # | store i8 %a, ptr %a.addr, align 1 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load i8, ptr %a.addr, align 1 # | %1 = zext i8 %0 to i32 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.maxav.v16i8(i32 %1, <16 x i8> %2) # | %4 = trunc i32 %3 to i8 # | ret i8 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.maxav.v16i8(i32, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vmaxavq_s16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %b.addr = alloca <8 x i16>, align 8 # | store i16 %a, ptr %a.addr, align 2 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load i16, ptr %a.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.maxav.v8i16(i32 %1, <8 x i16> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 # | ... # `---data was truncated (10240/39417) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055c4dc4c957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c4dc4c6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c4dc4c9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1618105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f161815c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1618105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f16180ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c4dc45f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c4dc45f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c4dc443f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c4dc0f3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c4dc0f2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f16180eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f16180ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f16180ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c4dc0f2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c (1900 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv1i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv2i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv4i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv8i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, al # | ... # `---data was truncated (10240/225213) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005560cc75757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005560cc754515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005560cc757cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdbbc249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdbbc2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdbbc249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdbbc231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005560cc6ed24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005560cc6ed096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005560cc6d1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005560cc381176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005560cc380e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fdbbc232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdbbc2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdbbc2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005560cc380d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c (1901 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/175163) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ff6a47557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ff6a472515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ff6a475cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa290449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa2904a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa290449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa290431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ff6a40b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ff6a40b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ff6a3eff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ff6a09f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ff6a09ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa290432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa2904330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa2904330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ff6a09ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c (1902 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf4x8_tumu( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | ... # `---data was truncated (10240/18506) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564871a9157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564871a8e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564871a91cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0178849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f01788a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0178849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0178831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564871a2724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564871a27096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564871a0bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005648716bb176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005648716bae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0178832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f01788330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f01788330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005648716bad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c (1903 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_i64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_u64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_f64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 7) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_i64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 7) %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_u64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c (1904 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvfwmaccqqq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvfwmaccqqq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005646d4ff957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005646d4ff6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005646d4ff9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f679c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f679c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f679c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f679c51b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005646d4f8f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005646d4f8f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005646d4f73f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005646d4c23176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005646d4c22e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f679c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f679c51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f679c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005646d4c22d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c (1905 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf8_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | # | ... # `---data was truncated (10240/415319) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557037b2657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557037b23515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557037b26cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fae7721bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fae772725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fae7721ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fae77203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557037abc24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557037abc096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557037aa0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557037750176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055703774fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fae77204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fae772050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fae772050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055703774fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c (1906 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m8_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none) # | ... # `---data was truncated (10240/30609) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056270cca857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056270cca5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056270cca8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f74d4649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f74d46a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f74d4649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f74d4631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056270cc3e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056270cc3e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056270cc22f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056270c8d2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056270c8d1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f74d4632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f74d46330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f74d46330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056270c8d1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c (1907 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_i8mf4x8(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556115bc457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556115bc1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556115bc4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd560449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd5604a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd560449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd560431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556115b5a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556115b5a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556115b3ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005561157ee176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005561157ede93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd560432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd5604330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd5604330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005561157edd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c (1908 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_i8mf8x7 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055920c19857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055920c195515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055920c198cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff2ada49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff2adaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff2ada49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff2ada31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055920c12e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055920c12e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055920c112f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055920bdc2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055920bdc1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff2ada32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff2ada330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff2ada330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055920bdc1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvp-intrinsics.c (1909 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvp-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +experimental-p -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c --check-prefixes=CHECK,RV32 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +experimental-p -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_cls_32(i32 noundef %a) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | %1 = load i32, ptr %__rs1.addr.i, align 4 # | %isneg.i = icmp slt i32 %1, 0 # | %not.i = xor i32 %1, -1 # | %2 = select i1 %isneg.i, i32 %not.i, i32 %1 # | %3 = call i32 @llvm.ctlz.i32(i32 %2, i1 false) # | %4 = sub nuw i32 %3, 1 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_rev_32(i32 noundef %a) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | %1 = load i32, ptr %__rs1.addr.i, align 4 # | %2 = call i32 @llvm.bitreverse.i32(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_slx_32(i32 noundef %rd, i32 noundef %rs1, i32 noundef %shamt) #0 { # | entry: # | %__rd.addr.i = alloca i32, align 4 # | %__rs1.addr.i = alloca i32, align 4 # | %__shamt.addr.i = alloca i32, align 4 # | %rd.addr = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | %shamt.addr = alloca i32, align 4 # | store i32 %rd, ptr %rd.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %shamt, ptr %shamt.addr, align 4 # | %0 = load i32, ptr %rd.addr, align 4 # | %1 = load i32, ptr %rs1.addr, align 4 # | %2 = load i32, ptr %shamt.addr, align 4 # | store i32 %0, ptr %__rd.addr.i, align 4 # | store i32 %1, ptr %__rs1.addr.i, align 4 # | store i32 %2, ptr %__shamt.addr.i, align 4 # | %3 = load i32, ptr %__rd.addr.i, align 4 # | %4 = load i32, ptr %__rs1.addr.i, align 4 # | %5 = load i32, ptr %__shamt.addr.i, align 4 # | %6 = call i32 @llvm.fshl.i32(i32 %3, i32 %4, i32 %5) # | ret i32 %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_srx_32(i32 noundef %rd, i32 noundef %rs1, i32 noundef %shamt) #0 { # | entry: # | %__rd.addr.i = alloca i32, align 4 # | %__rs1.addr.i = alloca i32, align 4 # | %__shamt.addr.i = alloca i32, align 4 # | %rd.addr = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | %shamt.addr = alloca i32, align 4 # | store i32 %rd, ptr %rd.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %shamt, ptr %shamt.addr, align 4 # | %0 = load i32, ptr %rd.addr, align 4 # | %1 = load i32, ptr %rs1.addr, align 4 # | %2 = load i32, ptr %shamt.addr, align 4 # | store i32 %0, ptr %__rd.addr.i, align 4 # | store i32 %1, ptr %__rs1.addr.i, align 4 # | store i32 %2, ptr %__shamt.addr.i, align 4 # | %3 = load i32, ptr %__rs1.addr.i, align 4 # | %4 = load i32, ptr %__rd.addr.i, align 4 # | %5 = load i32, ptr %__shamt.addr.i, align 4 # | %6 = call i32 @llvm.fshr.i32(i32 %3, i32 %4, i32 %5) # | ret i32 %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_aadd_i32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %__rs2.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | store i32 %1, ptr %__rs2.addr.i, align 4 # | %2 = load i32, ptr %__rs1.addr.i, align 4 # | %3 = load i32, ptr %__rs2.addr.i, align 4 # | %4 = call i32 @llvm.riscv.aadd.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_aaddu_u32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %__rs2.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | store i32 %1, ptr %__rs2.addr.i, align 4 # | %2 = load i32, ptr %__rs1.addr.i, align 4 # | %3 = load i32, ptr %__rs2.addr.i, align 4 # | %4 = call i32 @llvm.riscv.aaddu.u32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_asub_i32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %__rs2.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | store i32 %1, ptr %__rs2.addr.i, align 4 # | %2 = load i32, ptr %__rs1.addr.i, align 4 # | %3 = load i32, ptr %__rs2.addr.i, align 4 # | %4 = call i32 @llvm.riscv.asub.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_asubu_u32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %__rs2.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | store i32 %1, ptr %__rs2.addr.i, align 4 # | %2 = load i32, ptr %__rs1.addr.i, align 4 # | %3 = load i32, ptr %__rs2.addr.i, align 4 # | %4 = call i32 @llvm.riscv.asubu.u32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_sadd_i32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %__rs2.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | store i32 %1, ptr %__rs2.addr.i, align 4 # | %2 = load i32, ptr %__rs1.addr.i, align 4 # | %3 = load i32, ptr %__rs2.addr.i, align 4 # | %elt.sat.i = call i32 @llvm.sadd.sat.i32(i32 %2, i32 %3) # | ret i32 %elt.sat.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_saddu_u32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %__rs2.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | store i32 %1, ptr %__rs2.addr.i, align 4 # | %2 = load i32, ptr %__rs1.addr.i, align 4 # | %3 = load i32, ptr %__rs2.addr.i, align 4 # | %elt.sat.i = call i32 @llvm.uadd.sat.i32(i32 %2, i32 %3) # | ret i32 %elt.sat.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ssub_i32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %__rs2.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | store i32 %1, ptr %__rs2.addr.i, align 4 # | %2 = load i32, ptr %__rs1.addr.i, align 4 # | %3 = load i32, ptr %__rs2.addr.i, align 4 # | %elt.sat.i = call i32 @llvm.ssub.sat.i32(i32 %2, i32 %3) # | ret i32 %elt.sat.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ssubu_u32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %__rs2.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | store i32 %1, ptr %__rs2.addr.i, align 4 # | %2 = load i32, ptr %__rs1.addr.i, align 4 # | %3 = load i32, ptr %__rs2.addr.i, align 4 # | %elt.sat.i = call i32 @llvm.usub.sat.i32(i32 %2, i32 %3) # | ret i32 %elt.sat.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_abs_u32(i32 noundef %a) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | %1 = load i32, ptr %__rs1.addr.i, align 4 # | %elt.abs.i = call i32 @llvm.abs.i32(i32 %1, i1 false) # | ret i32 %elt.abs.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_sati_i32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call i32 @llvm.riscv.sati.i32(i32 %0, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sati.i32(i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_usati_u32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call i32 @llvm.riscv.usati.i32(i32 %0, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.usati.i32(i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_mulh_i32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %__rs2.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | store i32 %1, ptr %__rs2.addr.i, align 4 # | %2 = load i32, ptr %__rs1.addr.i, align 4 # | %3 = load i32, ptr %__rs2.addr.i, align 4 # | %4 = call i32 @llvm.smulh.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function At # | ... # `---data was truncated (10240/1228637) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine # | #0 0x000055b60868957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b608686515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b608689cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f418ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f418cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f418ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f418ce31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b60861f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b60861f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b608603f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b6082b3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b6082b2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f418ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f418ce330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f418ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b6082b2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c --check-prefixes=CHECK,RV32 # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c --check-prefixes=CHECK,RV32 # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c (1910 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f50086f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f50086c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f50086fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd5d0b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd5d0b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd5d0b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd5d0b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f50080524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f500805096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f5007e9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f500499176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f500498e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd5d0b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd5d0b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd5d0b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f500498d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c (1911 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv8i8.nxv8f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | ... # `---data was truncated (10240/12457) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557fdc47157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557fdc46e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557fdc471cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff69b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff69b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff69b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff69b431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557fdc40724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557fdc407096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557fdc3ebf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557fdc09b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557fdc09ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff69b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff69b4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff69b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557fdc09ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c (1912 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32mf2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m1_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m4_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m8_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32mf2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m1_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) # | ... # `---data was truncated (10240/25094) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f06005457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f060051515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f060054cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9f75933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9f7598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9f75933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9f7591b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f05ffea24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f05ffea096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f05ffcef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f05fc7e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f05fc7de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9f7591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9f7591d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9f7591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f05fc7dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c (1913 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m1_f16m2( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv8f16.nxv4f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m1_f16m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv16f16.nxv4f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m2_f16m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv16f16.nxv8f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv8f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m1_f16m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32f16.nxv4f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m2_f16m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32f16.nxv8f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv8f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m4_f16m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32f16.nxv16f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv16f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f32m1_f32m2( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 4 # | store %dest, ptr %dest.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 4 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %val.addr, align 4 # | %2 = call @llvm.vector.insert.nxv4f32.nxv2f32( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4f32.nxv2f32(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f32m1_f32m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 4 # | store %dest, ptr %dest.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 4 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %val.addr, align 4 # | %2 = call @llvm.vector.insert.nxv8f32.nxv2f32( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f32.nxv2f32(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f32m2_f32m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 4 # | store %dest, ptr %dest.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 4 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %val.addr, align 4 # | %2 = call @llvm.vector.insert.nxv8f32.nxv4f32( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f32.nxv4f32(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f32m1_f32m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 4 # | store %dest, ptr %dest.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 4 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %val.addr, align 4 # | %2 = call @llvm.vector.insert.nxv16f32.nxv2f32( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c (1914 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_f64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_f64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_i64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_i64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_u64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_u64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_f64m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_f64m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Functi # | ... # `---data was truncated (10240/15986) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005586786e357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005586786e0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005586786e3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5e69d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5e69d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5e69d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5e69d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055867867924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558678679096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055867865df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055867830d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055867830ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5e69d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5e69d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5e69d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055867830cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c (1915 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16mf4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f64m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c (1916 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv1i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv2i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv4i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv8i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv16i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055937787557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559377872515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559377875cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7b4ee1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7b4ee725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7b4ee1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7b4ee03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055937780b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055937780b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005593777eff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055937749f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055937749ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7b4ee04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7b4ee050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7b4ee050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055937749ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c (1917 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-cde-gpr.c (1918 of 27911) ******************** TEST 'Clang :: CodeGen/arm-cde-gpr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +cdecp1 -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +cdecp1 -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_cx1() #0 { # | entry: # | %0 = call i32 @llvm.arm.cde.cx1(i32 0, i32 123) # | ret i32 %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.cde.cx1(i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_cx1a(i32 noundef %acc) #0 { # | entry: # | %acc.addr = alloca i32, align 4 # | store i32 %acc, ptr %acc.addr, align 4 # | %0 = load i32, ptr %acc.addr, align 4 # | %1 = call i32 @llvm.arm.cde.cx1a(i32 0, i32 %0, i32 345) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.cde.cx1a(i32 immarg, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_cx1d() #0 { # | entry: # | %0 = call { i32, i32 } @llvm.arm.cde.cx1d(i32 1, i32 567) # | %1 = extractvalue { i32, i32 } %0, 1 # | %2 = zext i32 %1 to i64 # | %3 = shl i64 %2, 32 # | %4 = extractvalue { i32, i32 } %0, 0 # | %5 = zext i32 %4 to i64 # | %6 = or i64 %3, %5 # | ret i64 %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.cde.cx1d(i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_cx1da(i64 noundef %acc) #0 { # | entry: # | %acc.addr = alloca i64, align 8 # | store i64 %acc, ptr %acc.addr, align 8 # | %0 = load i64, ptr %acc.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = call { i32, i32 } @llvm.arm.cde.cx1da(i32 0, i32 %3, i32 %2, i32 789) # | %5 = extractvalue { i32, i32 } %4, 1 # | %6 = zext i32 %5 to i64 # | %7 = shl i64 %6, 32 # | %8 = extractvalue { i32, i32 } %4, 0 # | %9 = zext i32 %8 to i64 # | %10 = or i64 %7, %9 # | ret i64 %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.cde.cx1da(i32 immarg, i32, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_cx2(i32 noundef %n) #0 { # | entry: # | %n.addr = alloca i32, align 4 # | store i32 %n, ptr %n.addr, align 4 # | %0 = load i32, ptr %n.addr, align 4 # | %1 = call i32 @llvm.arm.cde.cx2(i32 0, i32 %0, i32 11) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.cde.cx2(i32 immarg, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_cx2a(i32 noundef %acc, i32 noundef %n) #0 { # | entry: # | %acc.addr = alloca i32, align 4 # | %n.addr = alloca i32, align 4 # | store i32 %acc, ptr %acc.addr, align 4 # | store i32 %n, ptr %n.addr, align 4 # | %0 = load i32, ptr %acc.addr, align 4 # | %1 = load i32, ptr %n.addr, align 4 # | %2 = call i32 @llvm.arm.cde.cx2a(i32 1, i32 %0, i32 %1, i32 22) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.cde.cx2a(i32 immarg, i32, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_cx2d(i32 noundef %n) #0 { # | entry: # | %n.addr = alloca i32, align 4 # | store i32 %n, ptr %n.addr, align 4 # | %0 = load i32, ptr %n.addr, align 4 # | %1 = call { i32, i32 } @llvm.arm.cde.cx2d(i32 1, i32 %0, i32 33) # | %2 = extractvalue { i32, i32 } %1, 1 # | %3 = zext i32 %2 to i64 # | %4 = shl i64 %3, 32 # | %5 = extractvalue { i32, i32 } %1, 0 # | %6 = zext i32 %5 to i64 # | %7 = or i64 %4, %6 # | ret i64 %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.cde.cx2d(i32 immarg, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_cx2da(i64 noundef %acc, i32 noundef %n) #0 { # | entry: # | %acc.addr = alloca i64, align 8 # | %n.addr = alloca i32, align 4 # | store i64 %acc, ptr %acc.addr, align 8 # | store i32 %n, ptr %n.addr, align 4 # | %0 = load i64, ptr %acc.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load i32, ptr %n.addr, align 4 # | %5 = call { i32, i32 } @llvm.arm.cde.cx2da(i32 0, i32 %3, i32 %2, i32 %4, i32 44) # | %6 = extractvalue { i32, i32 } %5, 1 # | %7 = zext i32 %6 to i64 # | %8 = shl i64 %7, 32 # | %9 = extractvalue { i32, i32 } %5, 0 # | %10 = zext i32 %9 to i64 # | %11 = or i64 %8, %10 # | ret i64 %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.cde.cx2da(i32 immarg, i32, i32, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_cx3(i32 noundef %n, i32 noundef %m) #0 { # | entry: # | %n.addr = alloca i32, align 4 # | %m.addr = alloca i32, align 4 # | store i32 %n, ptr %n.addr, align 4 # | store i32 %m, ptr %m.addr, align 4 # | %0 = load i32, ptr %n.addr, align 4 # | %1 = load i32, ptr %m.addr, align 4 # | %2 = call i32 @llvm.arm.cde.cx3(i32 0, i32 %0, i32 %1, i32 1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.cde.cx3(i32 immarg, i32, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_cx3a(i32 noundef %acc, i32 noundef %n, i32 noundef %m) #0 { # | entry: # | %acc.addr = alloca i32, align 4 # | %n.addr = alloca i32, align 4 # | %m.addr = alloca i32, align 4 # | store i32 %acc, ptr %acc.addr, align 4 # | store i32 %n, ptr %n.addr, align 4 # | store i32 %m, ptr %m.addr, align 4 # | %0 = load i32, ptr %acc.addr, align 4 # | %1 = load i32, ptr %n.addr, align 4 # | %2 = load i32, ptr %m.addr, align 4 # | %3 = call i32 @llvm.arm.cde.cx3a(i32 1, i32 %0, i32 %1, i32 %2, i32 2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.cde.cx3a(i32 immarg, i32, i32, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_cx3d(i32 noundef %n, i32 noundef %m) #0 { # | entry: # | %n.addr = alloca i32, align 4 # | %m.addr = alloca i32, align 4 # | store i32 %n, ptr %n.addr, align 4 # | store i32 %m, ptr %m.addr, align 4 # | %0 = load i32, ptr %n.addr, align 4 # | %1 = load i32, ptr %m.addr, align 4 # | %2 = call { i32, i32 } @llvm.arm.cde.cx3d(i32 1, i32 %0, i32 %1, i32 3) # | %3 = extractvalue { i32, i32 } %2, 1 # | %4 = zext i32 %3 to i64 # | %5 = shl i64 %4, 32 # | %6 = extractvalue { i32, i32 } %2, 0 # | %7 = zext i32 %6 to i64 # | %8 = or i64 %5, %7 # | ret i64 %8 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.cde.cx3d(i32 immarg, i32, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_cx3da(i64 noundef %acc, i32 noundef %n, i32 noundef %m) #0 { # | entry: # | %acc.addr = alloca i64, align 8 # | %n.addr = alloca i32, align 4 # | %m.addr = alloca i32, align 4 # | store i64 %acc, ptr %acc.addr, align 8 # | store i32 %n, ptr %n.addr, align 4 # | store i32 %m, ptr %m.addr, align 4 # | %0 = load i64, ptr %acc.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load i32, ptr %n.addr, align 4 # | %5 = load i32, ptr %m.addr, align 4 # | %6 = call { i32, i32 } @llvm.arm.cde.cx3da(i32 0, i32 %3, i32 %2, i32 %4, i32 %5, i32 4) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.cde.cx3da(i32 immarg, i32, i32, i32, i32, i32 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+cdecp0,+cdecp1,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056233c72957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056233c726515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056233c729cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faa6a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faa6a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faa6a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faa6a31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056233c6bf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056233c6bf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056233c6a3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056233c353176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056233c352e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007faa6a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faa6a31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faa6a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056233c352d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c (1919 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16mf4_i8mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16mf2_i8mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m1_i8mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m2_i8m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m4_i8m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m8_i8m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16mf4_u8mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16mf2_u8mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m1_u8mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m2_u8m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.v # | ... # `---data was truncated (10240/53192) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d05c92157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d05c91e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d05c921cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f722dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f722dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f722dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f722dc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d05c8b724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d05c8b7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d05c89bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d05c54b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d05c54ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f722dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f722dc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f722dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d05c54ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c (1920 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7 # | ... # `---data was truncated (10240/64374) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005558250b357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005558250b0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005558250b3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff007333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff00738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff007333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff00731b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055582504924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555825049096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055582502df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555824cdd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555824cdce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff00731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff00731d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff00731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555824cdcd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c (1921 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv16f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv16f16.f16.i64( poison, %0, half %1, i # | ... # `---data was truncated (10240/125641) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b18a1ab57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b18a1a8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b18a1abcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f371e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f371e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f371e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f371e31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b18a14124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b18a141096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b18a125f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b189dd5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b189dd4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f371e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f371e31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f371e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b189dd4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c (1922 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005562c500457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005562c5001515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005562c5004cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fba56133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fba5618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fba56133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fba5611b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005562c4f9a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005562c4f9a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005562c4f7ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005562c4c2e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005562c4c2de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fba5611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fba5611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fba5611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005562c4c2dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c (1923 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf8x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf4x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf2x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf8x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf4x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf2x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf8x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf4x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = c # | ... # `---data was truncated (10240/16451) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559098cc857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559098cc5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559098cc8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f96e9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f96e9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f96e9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f96e9f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559098c5e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559098c5e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559098c42f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005590988f2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005590988f1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f96e9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f96e9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f96e9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005590988f1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c (1924 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1f64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2f64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4f64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8f64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2i64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4i64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8i64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_u64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c (1925 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, pt # | ... # `---data was truncated (10240/66557) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b0186ff57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b0186fc515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b0186ffcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2e3d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2e3d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2e3d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2e3d51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b01869524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b018695096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b018679f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b018329176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b018328e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2e3d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2e3d51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2e3d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b018328d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c (1926 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m4( %vd, %v # | ... # `---data was truncated (10240/148843) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005593cd6e057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005593cd6dd515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005593cd6e0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5bad933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5bad98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5bad933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5bad91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005593cd67624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005593cd676096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005593cd65af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005593cd30a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005593cd309e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5bad91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5bad91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5bad91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005593cd309d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c (1927 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, ali # | ... # `---data was truncated (10240/14621) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ceca68957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ceca686515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ceca689cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc32d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc32d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc32d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc32d431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ceca61f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ceca61f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ceca603f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ceca2b3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ceca2b2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc32d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc32d4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc32d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ceca2b2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c (1928 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055644b0e657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055644b0e3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055644b0e6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f46f8733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f46f878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f46f8733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f46f871b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055644b07c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055644b07c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055644b060f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055644ad10176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055644ad0fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f46f871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f46f871d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f46f871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055644ad0fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c (1929 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_i8mf4x7(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555df083857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555df0835515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555df0838cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f75dd733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f75dd78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f75dd733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f75dd71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555df07ce24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555df07ce096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555df07b2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555df0462176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555df0461e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f75dd71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f75dd71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f75dd71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555df0461d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c (1930 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a84130857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a841305515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a841308cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc83bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc83bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc83bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc83bb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a84129e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a84129e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a841282f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a840f32176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a840f31e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc83bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc83bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc83bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a840f31d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c (1931 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7), pt # | ... # `---data was truncated (10240/19484) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005624ed81b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005624ed818515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005624ed81bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f82ee933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f82ee98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f82ee933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f82ee91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005624ed7b124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005624ed7b1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005624ed795f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005624ed445176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005624ed444e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f82ee91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f82ee91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f82ee91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005624ed444d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c (1932 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556b6340e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556b6340b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556b6340ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6eabb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6eabb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6eabb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6eabb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556b633a424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556b633a4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556b63388f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556b63038176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556b63037e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6eabb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6eabb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6eabb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556b63037d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c (1933 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f64m1x3(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c (1934 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte16_bf16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vlte16.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte16_f16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte16_i16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte16_u16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvfbfmin,+zvfhmin,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfhmin1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558fcedec57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558fcede9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558fcedeccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3f33733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3f3378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3f33733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3f3371b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558fced8224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558fced82096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558fced66f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558fcea16176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558fcea15e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3f3371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3f3371d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3f3371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558fcea15d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c (1935 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005607a826c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005607a8269515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005607a826ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f576f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f576f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f576f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f576f11b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005607a820224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005607a8202096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005607a81e6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005607a7e96176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005607a7e95e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f576f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f576f11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f576f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005607a7e95d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-v8.2a-neon-intrinsics.c (1936 of 27911) ******************** TEST 'Clang :: CodeGen/arm-v8.2a-neon-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-linux-gnu -target-abi apcs-gnu -target-feature +neon -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-linux-gnu -target-abi apcs-gnu -target-feature +neon -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c" # | target datalayout = "e-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" # | target triple = "armv8.2a-unknown-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vabs_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vabs.i = bitcast <8 x i8> %1 to <4 x half> # | %vabs1.i = call <4 x half> @llvm.fabs.v4f16(<4 x half> %vabs.i) # | store <4 x half> %vabs1.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %2, ptr %__ret.i, align 8 # | %3 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vabsq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vabs.i = bitcast <16 x i8> %1 to <8 x half> # | %vabs1.i = call <8 x half> @llvm.fabs.v8f16(<8 x half> %vabs.i) # | store <8 x half> %vabs1.i, ptr %ref.tmp.i, align 16 # | %2 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %2, ptr %__ret.i, align 16 # | %3 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vceqz_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fcmp oeq <4 x half> %2, zeroinitializer # | %vceqz.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vceqz.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vceqzq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %3 = fcmp oeq <8 x half> %2, zeroinitializer # | %vceqz.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vceqz.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vcgez_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fcmp oge <4 x half> %2, zeroinitializer # | %vcgez.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vcgez.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcgezq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %3 = fcmp oge <8 x half> %2, zeroinitializer # | %vcgez.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vcgez.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vcgtz_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fcmp ogt <4 x half> %2, zeroinitializer # | %vcgtz.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vcgtz.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcgtzq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %3 = fcmp ogt <8 x half> %2, zeroinitializer # | %vcgtz.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vcgtz.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vclez_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fcmp ole <4 x half> %2, zeroinitializer # | %vclez.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vclez.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vclezq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %3 = fcmp ole <8 x half> %2, zeroinitializer # | %vclez.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vclez.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vcltz_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fcmp olt <4 x half> %2, zeroinitializer # | %vcltz.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vcltz.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcltzq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %3 = fcmp olt <8 x half> %2, zeroinitializer # | %vcltz.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vcltz.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vcvt_f16_s16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloc # | ... # `---data was truncated (10240/122004) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000056298e86257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056298e85f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056298e862cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff47d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff47d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff47d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff47d51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056298e7f824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056298e7f8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056298e7dcf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056298e48c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056298e48be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff47d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff47d51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff47d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056298e48bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c (1937 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8mf8_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv1i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv1i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8mf4_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv2i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv2i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8mf2_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv4i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv4i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m1_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv8i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv8i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m2_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv16i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv16i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m4_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv32i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv32i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m8_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv64i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv64i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16mf4_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv1i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv1i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16mf2_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv2i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv2i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m1_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv4i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv4i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m2_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv8i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv8i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m4_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv16i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv16i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m8_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv32i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv32i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u32mf2_tu( %maske # | ... # `---data was truncated (10240/75397) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e4f889257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e4f888f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e4f8892cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f046fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f046faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f046fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f046fa31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e4f882824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e4f8828096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e4f880cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e4f84bc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e4f84bbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f046fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f046fa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f046fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e4f84bbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c (1938 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16m2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c (1939 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16mf4_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m4_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m8_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f32mf2_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f32m1_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f32m2_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv1f64.nxv4f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret # | ... # `---data was truncated (10240/50516) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055957825557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559578252515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559578255cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f39aa733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f39aa78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f39aa733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f39aa71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005595781eb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005595781eb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005595781cff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559577e7f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559577e7ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f39aa71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f39aa71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f39aa71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559577e7ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c (1940 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eeefea257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055eeefe9f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055eeefea2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7fd6449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7fd64a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7fd6449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7fd6431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eeefe3824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055eeefe38096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055eeefe1cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055eeefacc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055eeefacbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7fd6432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7fd64330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7fd64330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eeefacbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c (1941 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16mf4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1f16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16mf2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2f16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4f16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8f16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv16f16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv32f16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv32f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16mf4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1i16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16mf2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2i16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4i16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8i16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv16i16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv32i16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv32i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_u16mf4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1i16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_u16mf2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2i16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_v # | ... # `---data was truncated (10240/29273) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564675b0c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564675b09515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564675b0ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd92b21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd92b2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd92b21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd92b203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564675aa224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564675aa2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564675a86f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564675736176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564675735e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd92b204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd92b2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd92b2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564675735d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c (1942 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32mf2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv1f32.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1f32.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m1_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv2f32.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv2f32.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv4f32.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv4f32.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv8f32.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv8f32.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv16f32.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv16f32.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32mf2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv1i32.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1i32.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32m1_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv2i32.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv2i32.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32m2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv4i32.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | # | ... # `---data was truncated (10240/19123) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055db18a7757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055db18a74515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055db18a77cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f216fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f216faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f216fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f216fa31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055db18a0d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055db18a0d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055db189f1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055db186a1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055db186a0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f216fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f216fa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f216fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055db186a0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c (1943 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fa29f1a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fa29f17515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fa29f1acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbbac249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbbac2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbbac249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbbac231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fa29eb024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fa29eb0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fa29e94f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fa29b44176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fa29b43e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbbac232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbbac2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbbac2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fa29b43d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c (1944 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 8) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 8) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { targ # | ... # `---data was truncated (10240/21111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d44868957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d448686515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d448689cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0272733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f027278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0272733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f027271b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d44861f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d44861f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d448603f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d4482b3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d4482b2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f027271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f027271d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f027271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d4482b2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c (1945 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557b2e5cb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557b2e5c8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557b2e5cbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8953f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8953f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8953f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8953eed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557b2e56124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557b2e561096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557b2e545f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557b2e1f5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557b2e1f4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8953eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8953eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8953eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557b2e1f4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c (1946 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv8i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv8i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv16i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv16i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv32i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv32i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv64i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv64i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xandesvsintload,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xandesvsintload5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056183f17557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056183f172515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056183f175cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff57a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff57a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff57a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff57a71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056183f10b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056183f10b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056183f0eff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056183ed9f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056183ed9ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff57a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff57a71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff57a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056183ed9ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c (1947 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e3ac67357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e3ac670515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e3ac673cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa5bee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa5beea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa5bee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa5bee31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e3ac60924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e3ac609096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e3ac5edf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e3ac29d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e3ac29ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa5bee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa5bee330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa5bee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e3ac29cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c (1948 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f32.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f32.p0.nxv8i16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c (1949 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_i8mf4x5(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f675afe57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f675afb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f675afecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdf6a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdf6a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdf6a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdf6a11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f675a9424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f675a94096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f675a78f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f675728176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f675727e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fdf6a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdf6a11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdf6a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f675727d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c (1950 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16mf2_f16mf4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1f16.nxv2f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f16.nxv2f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m1_f16mf4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1f16.nxv4f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f16.nxv4f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m1_f16mf2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2f16.nxv4f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f16.nxv4f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m2_f16mf4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1f16.nxv8f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f16.nxv8f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m2_f16mf2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2f16.nxv8f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f16.nxv8f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m2_f16m1( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv8f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv8f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m4_f16mf4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m4_f16mf2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m4_f16m1( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m4_f16m2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m8_f16mf4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m8_f16mf2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m8_f16m1( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m8_f16m2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m8_f16m4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv16f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv16f16.nxv32f16(, i64 immarg) #1 # | ... # `---data was truncated (10240/78234) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005558920fb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005558920f8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005558920fbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feb92133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feb9218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feb92133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feb9211b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055589209124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555892091096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555892075f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555891d25176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555891d24e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007feb9211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feb9211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feb9211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555891d24d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c (1951 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple # | ... # `---data was truncated (10240/96919) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a7c776c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a7c7769515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a7c776ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9df9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9df9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9df9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9df9b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a7c770224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a7c7702096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a7c76e6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a7c7396176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a7c7395e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9df9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9df9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9df9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a7c7395d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c (1952 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv8i8.nxv8i8.i64(, , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c (1953 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv1f32.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv2f32.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv4f32.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv8f32.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv16f32.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv1i32.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv2i32.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv4i32.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4i32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv8i32.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8i32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv16i32.i64.p0( poison, ptr %0, i64 %2) # | %4 = # | ... # `---data was truncated (10240/33471) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564a9fde557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564a9fde2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564a9fde5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7181b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7181b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7181b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7181aed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564a9fd7b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564a9fd7b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564a9fd5ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564a9fa0f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564a9fa0ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7181aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7181aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7181aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564a9fa0ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c (1954 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretu # | ... # `---data was truncated (10240/61937) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555f449e657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555f449e3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555f449e6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f632821bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f63282725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f632821ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6328203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555f4497c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555f4497c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555f44960f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555f44610176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555f4460fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6328204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f63282050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f63282050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555f4460fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c (1955 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf8_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf4_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8m1_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %v # | ... # `---data was truncated (10240/222307) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055810397f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055810397c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055810397fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcb5b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcb5b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcb5b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcb5b231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055810391524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558103915096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005581038f9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005581035a9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005581035a8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcb5b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcb5b2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcb5b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005581035a8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c (1956 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv4i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback # | ... # `---data was truncated (10240/15245) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f84f8b357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f84f8b0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f84f8b3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fec21a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fec21aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fec21a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fec21a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f84f84924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f84f849096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f84f82df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f84f4dd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f84f4dce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fec21a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fec21a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fec21a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f84f4dcd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c (1957 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv8f32.nxv8f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f32.nxv8f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv16f32.nxv16f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16f32.nxv16f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, al # | ... # `---data was truncated (10240/30861) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056318a40057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056318a3fd515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056318a400cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f72f0d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f72f0d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f72f0d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f72f0d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056318a39624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056318a396096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056318a37af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056318a02a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056318a029e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f72f0d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f72f0d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f72f0d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056318a029d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c (1958 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_i8mf8x8_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c (1959 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | st # | ... # `---data was truncated (10240/11797) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561d8968e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561d8968b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561d8968ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5a99133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5a9918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5a99133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5a9911b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561d8962424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561d89624096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561d89608f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561d892b8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561d892b7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5a9911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5a9911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5a9911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561d892b7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c (1960 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf4_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m1_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m4_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m8_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf4_tum( %mask, %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load float, ptr %op2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf2_tum( %mask, %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load float, ptr %op2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64( %1, %2, float %3, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c (1961 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf8x8_tum(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c (1962 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv32i8.nxv32i8.i64( %0, # | ... # `---data was truncated (10240/95081) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055daf8cdd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055daf8cda515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055daf8cddcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1086333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f108638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1086333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f108631b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055daf8c7324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055daf8c73096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055daf8c57f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055daf8907176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055daf8906e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f108631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f108631d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f108631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055daf8906d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c (1963 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16mf4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16mf2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m1_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m8_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f32mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f32m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv2f32.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f32m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv2f32.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv2f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_loc # | ... # `---data was truncated (10240/37556) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fe7c4a757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fe7c4a4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fe7c4a7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb67f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb67f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb67f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb67f31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fe7c43d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fe7c43d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fe7c421f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fe7c0d1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fe7c0d0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb67f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb67f31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb67f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fe7c0d0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c (1964 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/82983) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056411213557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564112132515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564112135cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f199cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f199cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f199cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f199cd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005641120cb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005641120cb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005641120aff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564111d5f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564111d5ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f199cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f199cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f199cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564111d5ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c (1965 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8mf8x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_u8mf8x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_u8mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | # | ... # `---data was truncated (10240/31868) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559bb971257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559bb970f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559bb9712cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb1ebc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb1ebca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb1ebc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb1ebc31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559bb96a824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559bb96a8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559bb968cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559bb933c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559bb933be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb1ebc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb1ebc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb1ebc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559bb933bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c (1966 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | ... # `---data was truncated (10240/29304) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556f7563357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556f75630515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556f75633cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f23faa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f23faaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f23faa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f23faa31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556f755c924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556f755c9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556f755adf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556f7525d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556f7525ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f23faa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f23faa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f23faa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556f7525cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c (1967 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m1x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m4x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m1x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m4x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_u64m1x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | % # | ... # `---data was truncated (10240/13690) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558f45ed557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558f45ed2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558f45ed5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6ffda49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6ffdaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6ffda49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6ffda31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558f45e6b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558f45e6b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558f45e4ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558f45aff176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558f45afee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6ffda32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6ffda330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6ffda330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558f45afed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c (1968 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, a # | ... # `---data was truncated (10240/222483) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055abe9ecd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055abe9eca515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055abe9ecdcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd967b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd967b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd967b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd967b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055abe9e6324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055abe9e63096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055abe9e47f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055abe9af7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055abe9af6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd967b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd967b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd967b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055abe9af6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c (1969 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_u16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_u16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), # | ... # `---data was truncated (10240/53330) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561447d8257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561447d7f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561447d82cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7fd9d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7fd9d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7fd9d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7fd9d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561447d1824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561447d18096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561447cfcf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005614479ac176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005614479abe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7fd9d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7fd9d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7fd9d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005614479abd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c (1970 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555da5e0a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555da5e07515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555da5e0acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa1af933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa1af98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa1af933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa1af91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555da5da024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555da5da0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555da5d84f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555da5a34176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555da5a33e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa1af91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa1af91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa1af91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555da5a33d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c (1971 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv16bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv32bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf4_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load , ptr %vs1.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vpairo.mask.nxv1bf16.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c (1972 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f32m2x2(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c (1973 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, pt # | ... # `---data was truncated (10240/135337) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f79ce2e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f79ce2b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f79ce2ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc417449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc4174a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc417449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc417431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f79cdc424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f79cdc4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f79cda8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f79ca58176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f79ca57e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc417432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc4174330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc4174330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f79ca57d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c (1974 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32mf2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555ddb72757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555ddb724515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555ddb727cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1da0249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1da02a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1da0249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1da0231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555ddb6bd24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555ddb6bd096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555ddb6a1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555ddb351176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555ddb350e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1da0232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1da02330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1da02330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555ddb350d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c (1975 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m8_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff. # | ... # `---data was truncated (10240/288058) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564f4b11957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564f4b116515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564f4b119cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7098933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f709898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7098933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f709891b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564f4b0af24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564f4b0af096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564f4b093f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564f4ad43176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564f4ad42e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f709891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f709891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f709891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564f4ad42d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c (1976 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmset_m_b1(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmset.nxv64i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmset.nxv64i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmset_m_b2(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmset.nxv32i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmset.nxv32i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmset_m_b4(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmset.nxv16i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmset.nxv16i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmset_m_b8(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmset.nxv8i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmset.nxv8i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmset_m_b16(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmset.nxv4i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmset.nxv4i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmset_m_b32(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmset.nxv2i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmset.nxv2i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmset_m_b64(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmset.nxv1i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmset.nxv1i1.i64(i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005603e470b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005603e4708515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005603e470bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe80d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe80d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe80d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe80d031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005603e46a124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005603e46a1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005603e4685f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005603e4335176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005603e4334e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe80d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe80d0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe80d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005603e4334d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c (1977 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f64m1_tu( %maskedoff, ptr noundef %base, % # | ... # `---data was truncated (10240/215941) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005607d4c1a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005607d4c17515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005607d4c1acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6fcbb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6fcbb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6fcbb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6fcbaed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005607d4bb024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005607d4bb0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005607d4b94f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005607d4844176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005607d4843e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6fcbaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6fcbaef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6fcbaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005607d4843d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c (1978 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16mf4( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv1bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16mf2( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv2bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m1( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv4bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m2( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv8bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m4( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv16bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m8( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv32bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(, , bfloat, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563e46a2557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563e46a22515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563e46a25cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcb09c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcb09c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcb09c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcb09c03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563e469bb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563e469bb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563e4699ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563e4664f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563e4664ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcb09c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcb09c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcb09c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563e4664ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c (1979 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf8x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv1i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv1i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf4x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf2x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf8x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv1i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf4x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf2x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/12668) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055867ff5257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055867ff4f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055867ff52cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c3a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c3a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c3a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c3a51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055867fee824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055867fee8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055867feccf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055867fb7c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055867fb7be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2c3a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c3a51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c3a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055867fb7bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c (1980 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv16bf16.nxv16bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | stor # | ... # `---data was truncated (10240/29518) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fb6570957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fb65706515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fb65709cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f71f0b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f71f0b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f71f0b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f71f0b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fb6569f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fb6569f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fb65683f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fb65333176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fb65332e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f71f0b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f71f0b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f71f0b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fb65332d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c (1981 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1f64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1f64.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2f64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2f64.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv4f64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4f64.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv8f64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv8f64.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1i64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1i64.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2i64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2i64.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv4i64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4i64.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv8i64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv8i64.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1i64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2i64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , # | ... # `---data was truncated (10240/11969) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005598faf4557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005598faf42515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005598faf45cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3ff7c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3ff7ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3ff7c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3ff7c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005598faedb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005598faedb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005598faebff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005598fab6f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005598fab6ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3ff7c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3ff7c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3ff7c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005598fab6ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c (1982 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f32m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | ... # `---data was truncated (10240/120907) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005574fd6c957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005574fd6c6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005574fd6c9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1021649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f10216a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1021649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1021631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005574fd65f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005574fd65f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005574fd643f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005574fd2f3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005574fd2f2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1021632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f10216330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f10216330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005574fd2f2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c (1983 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16m8(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory # | ... # `---data was truncated (10240/135997) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f79472657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f794723515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f794726cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f02dac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f02daca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f02dac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f02dac31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f7946bc24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f7946bc096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f7946a0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f794350176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f79434fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f02dac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f02dac330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f02dac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f79434fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c (1984 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/thinlto_backend.ll (1985 of 27911) ******************** TEST 'Clang :: CodeGen/thinlto_backend.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend.ll # | #0 0x000056056c65357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056056c650515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056056c653cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4a41649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4a416a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4a41649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4a41631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056056c5e924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056056c5e9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056056c5cdf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056056c27d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056056c27ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4a41632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4a416330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4a416330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056056c27cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c (1986 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_u16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, ali # | ... # `---data was truncated (10240/60543) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fc9296e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fc9296b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fc9296ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc6c3d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc6c3d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc6c3d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc6c3d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fc9290424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fc92904096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fc928e8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fc92598176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fc92597e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc6c3d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc6c3d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc6c3d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fc92597d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c (1987 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local targ # | ... # `---data was truncated (10240/70855) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e988de657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e988de3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e988de6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb7c4a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb7c4aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb7c4a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb7c4a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e988d7c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e988d7c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e988d60f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e988a10176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e988a0fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb7c4a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb7c4a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb7c4a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e988a0fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c (1988 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f32m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f32m4x2(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c (1989 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_i32mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_i32m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_u32mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_u32m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055af6452857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055af64525515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055af64528cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5105705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f510575c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5105705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f51056ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055af644be24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055af644be096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055af644a2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055af64152176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055af64151e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f51056eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f51056ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f51056ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055af64151d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c (1990 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559af689c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559af6899515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559af689ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4b4c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4b4c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4b4c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4b4c11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559af683224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559af6832096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559af6816f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559af64c6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559af64c5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4b4c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4b4c11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4b4c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559af64c5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c (1991 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c (1992 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/97913) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005625df18557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005625df182515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005625df185cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc650b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc650b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc650b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc650b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005625df11b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005625df11b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005625df0fff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005625dedaf176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005625dedaee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc650b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc650b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc650b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005625dedaed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c (1993 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bc8816e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bc8816b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bc8816ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fac8e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fac8e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fac8e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fac8e91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bc8810424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bc88104096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bc880e8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bc87d98176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bc87d97e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fac8e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fac8e91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fac8e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bc87d97d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c (1994 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c (1995 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m1x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m2x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m4x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f97283257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f97282f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f972832cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff4cda49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff4cdaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff4cda49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff4cda31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f9727c824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f9727c8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f9727acf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f97245c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f97245be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff4cda32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff4cda330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff4cda330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f97245bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c (1996 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8m4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c (1997 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16m4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | def # | ... # `---data was truncated (10240/68073) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fbf620657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fbf6203515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fbf6206cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbd03049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbd030a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbd03049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbd03031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fbf619c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fbf619c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fbf6180f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fbf5e30176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fbf5e2fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbd03032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbd030330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbd030330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fbf5e2fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c (1998 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv64i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv64i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv32i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv32i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv16i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv16i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv8i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv8i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b16(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv4i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv4i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b32(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv2i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv2i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b64(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv1i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv1i1.p0.i64(, ptr captures(none), i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005622e655057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005622e654d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005622e6550cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd1fe733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd1fe78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd1fe733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd1fe71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005622e64e624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005622e64e6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005622e64caf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005622e617a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005622e6179e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd1fe71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd1fe71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd1fe71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005622e6179d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-mve-intrinsics/scatter-gather.c (1999 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/scatter-gather.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_gather_offset_s16(ptr noundef %base, <8 x i16> noundef %offset) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <8 x i16>, align 8 # | store ptr %base, ptr %base.addr, align 4 # | store <8 x i16> %offset, ptr %offset.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <8 x i16>, ptr %offset.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.v8i16.p0.v8i16(ptr %0, <8 x i16> %1, i32 8, i32 0, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare <8 x i16> @llvm.arm.mve.vldr.gather.offset.v8i16.p0.v8i16(ptr, <8 x i16>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_gather_offset_s32(ptr noundef %base, <4 x i32> noundef %offset) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <4 x i32>, align 8 # | store ptr %base, ptr %base.addr, align 4 # | store <4 x i32> %offset, ptr %offset.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <4 x i32>, ptr %offset.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0.v4i32(ptr %0, <4 x i32> %1, i32 8, i32 0, i32 0) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0.v4i32(ptr, <4 x i32>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_gather_offset_s8(ptr noundef %base, <16 x i8> noundef %offset) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <16 x i8>, align 8 # | store ptr %base, ptr %base.addr, align 4 # | store <16 x i8> %offset, ptr %offset.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <16 x i8>, ptr %offset.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vldr.gather.offset.v16i8.p0.v16i8(ptr %0, <16 x i8> %1, i32 8, i32 0, i32 0) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare <16 x i8> @llvm.arm.mve.vldr.gather.offset.v16i8.p0.v16i8(ptr, <16 x i8>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_gather_offset_u16(ptr noundef %base, <8 x i16> noundef %offset) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <8 x i16>, align 8 # | store ptr %base, ptr %base.addr, align 4 # | store <8 x i16> %offset, ptr %offset.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <8 x i16>, ptr %offset.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.v8i16.p0.v8i16(ptr %0, <8 x i16> %1, i32 8, i32 0, i32 1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_gather_offset_u32(ptr noundef %base, <4 x i32> noundef %offset) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <4 x i32>, align 8 # | store ptr %base, ptr %base.addr, align 4 # | store <4 x i32> %offset, ptr %offset.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <4 x i32>, ptr %offset.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0.v4i32(ptr %0, <4 x i32> %1, i32 8, i32 0, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_gather_offset_u8(ptr noundef %base, <16 x i8> noundef %offset) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <16 x i8>, align 8 # | store ptr %base, ptr %base.addr, align 4 # | store <16 x i8> %offset, ptr %offset.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <16 x i8>, ptr %offset.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vldr.gather.offset.v16i8.p0.v16i8(ptr %0, <16 x i8> %1, i32 8, i32 0, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_gather_offset_z_s16(ptr noundef %base, <8 x i16> noundef %offset, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store <8 x i16> %offset, ptr %offset.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <8 x i16>, ptr %offset.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.predicated.v8i16.p0.v8i16.v8i1(ptr %0, <8 x i16> %1, i32 8, i32 0, i32 0, <8 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare <8 x i16> @llvm.arm.mve.vldr.gather.offset.predicated.v8i16.p0.v8i16.v8i1(ptr, <8 x i16>, i32, i32, i32, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_gather_offset_z_s32(ptr noundef %base, <4 x i32> noundef %offset, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store <4 x i32> %offset, ptr %offset.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <4 x i32>, ptr %offset.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.predicated.v4i32.p0.v4i32.v4i1(ptr %0, <4 x i32> %1, i32 8, i32 0, i32 0, <4 x i1> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare <4 x i32> @llvm.arm.mve.vldr.gather.offset.predicated.v4i32.p0.v4i32.v4i1(ptr, <4 x i32>, i32, i32, i32, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_gather_offset_z_s8(ptr noundef %base, <16 x i8> noundef %offset, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store <16 x i8> %offset, ptr %offset.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <16 x i8>, ptr %offset.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vldr.gather.offset.predicated.v16i8.p0.v16i8.v16i1(ptr %0, <16 x i8> %1, i32 8, i32 0, i32 0, <16 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare <16 x i8> @llvm.arm.mve.vldr.gather.offset.predicated.v16i8.p0.v16i8.v16i1(ptr, <16 x i8>, i32, i32, i32, <16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_gather_offset_z_u16(ptr noundef %base, <8 x i16> noundef %offset, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store <8 x i16> %offset, ptr %offset.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <8 x i16>, ptr %offset.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.predicated.v8i16.p0.v8i16.v8i1(ptr %0, <8 x i16> %1, i32 8, i32 0, i32 1, <8 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_gather_offset_z_u32(ptr noundef %base, <4 x i32> noundef %offset, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store <4 x i32> %offset, ptr %offset.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <4 x i32>, ptr %offset.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.predicated.v4i32.p0.v4i32.v4i1(ptr %0, <4 x i32> %1, i32 8, i32 0, i32 1, <4 x i1> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_gather_offset_z_u8(ptr noundef %base, <16 x i8> noundef %offset, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store <16 x i8> %offset, ptr %offset.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <16 x i8>, ptr %offset.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vldr.gather.offset.predicated.v16i8.p0.v16i8.v16i1(ptr %0, <16 x i8> %1, i32 8, i32 0, i32 1, <16 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vf # | ... # `---data was truncated (10240/117019) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005644e2bcb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005644e2bc8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005644e2bcbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efde341bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efde34725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efde341ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efde3403507 abort ./stdlib/abort.c:85:3 # | #7 0x00005644e2b6124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005644e2b61096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005644e2b45f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005644e27f5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005644e27f4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efde3404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efde34050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efde34050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005644e27f4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c (2000 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local targ # | ... # `---data was truncated (10240/70855) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f705a5657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f705a53515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f705a56cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff4b5849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff4b58a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff4b5849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff4b5831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f7059ec24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f7059ec096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f7059d0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f705680176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f70567fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff4b5832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff4b58330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff4b58330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f70567fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c (2001 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf8( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | # | ... # `---data was truncated (10240/207749) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bc3f5e457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bc3f5e1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bc3f5e4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd006905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd00695c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd006905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd0068ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bc3f57a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bc3f57a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bc3f55ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bc3f20e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bc3f20de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd0068eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd0068ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd0068ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bc3f20dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c (2002 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv64i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv64i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv32i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv32i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv16i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv16i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv8i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv8i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv4i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv4i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv2i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv2i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv1i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv1i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsof.mask.nxv64i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsof.mask.nxv32i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsof.mask.nxv16i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsof.mask.nxv8i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b16_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsof.mask.nxv4i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree no # | ... # `---data was truncated (10240/13023) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cecf9f157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cecf9ee515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cecf9f1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd8dde1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd8dde725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd8dde1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd8dde03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cecf98724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cecf987096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cecf96bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cecf61b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cecf61ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd8dde04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd8dde050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd8dde050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cecf61ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c (2003 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv2f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32m2_tu # | ... # `---data was truncated (10240/288275) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cdc567657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cdc5673515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cdc5676cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f48b9733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f48b978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f48b9733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f48b971b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cdc560c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cdc560c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cdc55f0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cdc52a0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cdc529fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f48b971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f48b971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f48b971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cdc529fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c (2004 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_f64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_i64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_u64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_f64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_i64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_u64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b45794e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b45794b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b45794ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fead1449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fead14a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fead1449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fead1431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b4578e424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b4578e4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b4578c8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b457578176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b457577e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fead1432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fead14330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fead14330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b457577d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c (2005 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf8x6_tum( %mas # | ... # `---data was truncated (10240/43111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055845fcbd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055845fcba515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055845fcbdcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc632849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc6328a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc632849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc632831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055845fc5324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055845fc53096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055845fc37f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055845f8e7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055845f8e6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc632832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc6328330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc6328330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055845f8e6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c (2006 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv16f32.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv16f32.nxv16f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load # | ... # `---data was truncated (10240/76635) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fa70df857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fa70df5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fa70df8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5926849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f59268a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5926849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5926831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fa70d8e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fa70d8e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fa70d72f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fa70a22176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fa70a21e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5926832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f59268330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f59268330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fa70a21d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c (2007 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv8f32.nxv8f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f32.nxv8f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv16f32.nxv16f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16f32.nxv16f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1. # | ... # `---data was truncated (10240/30869) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a0e49c557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a0e49c2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a0e49c5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007facf2849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007facf28a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007facf2849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007facf2831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a0e495b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a0e495b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a0e493ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a0e45ef176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a0e45eee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007facf2832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007facf28330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007facf28330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a0e45eed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c (2008 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16mf4( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16mf2( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m1( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m2( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m4( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv16f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m8( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv32f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv32f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32mf2( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv1f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32m1( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv2f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32m2( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv4f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv4f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32m4( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv8f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv8f32.f32.i64(, , float, i64) # | ... # `---data was truncated (10240/34765) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560a1a53d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560a1a53a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560a1a53dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f77e8049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f77e80a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f77e8049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f77e8031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560a1a4d324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560a1a4d3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560a1a4b7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560a1a167176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560a1a166e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f77e8032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f77e80330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f77e80330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560a1a166d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c (2009 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/48313) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a4fab3c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a4fab39515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a4fab3ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdac2133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdac218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdac2133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdac211b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a4faad224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a4faad2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a4faab6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a4fa766176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a4fa765e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fdac211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdac211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdac211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a4fa765d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c (2010 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005604c146257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005604c145f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005604c1462cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0e19a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0e19aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0e19a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0e19a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005604c13f824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005604c13f8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005604c13dcf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005604c108c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005604c108be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0e19a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0e19a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0e19a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005604c108bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c (2011 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xtheadbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c -check-prefix=RV64XTHEADBB # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xtheadbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @clz_32(i32 noundef signext %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call i32 @llvm.ctlz.i32(i32 %0, i1 false) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.ctlz.i32(i32, i1 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @clo_32(i32 noundef signext %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %not = xor i32 %0, -1 # | %1 = call i32 @llvm.ctlz.i32(i32 %not, i1 false) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @clz_64(i64 noundef %a) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = call i64 @llvm.ctlz.i64(i64 %0, i1 false) # | %cast = trunc i64 %1 to i32 # | ret i32 %cast # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.ctlz.i64(i64, i1 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @clo_64(i64 noundef %a) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %not = xor i64 %0, -1 # | %1 = call i64 @llvm.ctlz.i64(i64 %not, i1 false) # | %cast = trunc i64 %1 to i32 # | ret i32 %cast # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xtheadbb" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_xtheadbb1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563f210f757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563f210f4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563f210f7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe11b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe11b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe11b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe11b51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563f2108d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563f2108d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563f21071f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563f20d21176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563f20d20e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe11b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe11b51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe11b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563f20d20d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c -check-prefix=RV64XTHEADBB # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c -check-prefix=RV64XTHEADBB # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c (2012 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare # | ... # `---data was truncated (10240/20141) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a69115157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a69114e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a691151cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb105849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb1058a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb105849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb105831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a6910e724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a6910e7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a6910cbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a690d7b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a690d7ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb105832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb1058330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb1058330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a690d7ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c (2013 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosy # | ... # `---data was truncated (10240/12666) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b21871357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b218710515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b218713cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd26b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd26b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd26b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd26b11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b2186a924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b2186a9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b21868df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b21833d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b21833ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd26b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd26b11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd26b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b21833cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c (2014 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv16i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv32i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv64i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16mf4_tu( %maskedoff, %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i16, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv1i16.i16.i64( %0, %1, i16 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16mf2_tu( %maskedoff, %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i16, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c (2015 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , # | ... # `---data was truncated (10240/15607) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cd5d59c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cd5d599515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cd5d59ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff0df733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff0df78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff0df733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff0df71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cd5d53224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cd5d532096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cd5d516f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cd5d1c6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cd5d1c5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff0df71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff0df71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff0df71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cd5d1c5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c (2016 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056284cf2d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056284cf2a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056284cf2dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4b2c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4b2c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4b2c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4b2c71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056284cec324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056284cec3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056284cea7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056284cb57176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056284cb56e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4b2c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4b2c71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4b2c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056284cb56d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c (2017 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c (2018 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16m8(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i16.i64( %2, ptr %0, %1, i6 # | ... # `---data was truncated (10240/132470) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005611145e457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005611145e1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005611145e4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8b36e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8b36ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8b36e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8b36e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056111457a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056111457a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056111455ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056111420e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056111420de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8b36e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8b36e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8b36e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056111420dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c (2019 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_xv_se_u64m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.xv.se.i64.nxv1i64.i64.i64(i64 3, i64 31, %0, i64 %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.xv.se.i64.nxv1i64.i64.i64(i64 immarg, i64 immarg, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_xv_se_u64m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.xv.se.i64.nxv2i64.i64.i64(i64 3, i64 31, %0, i64 %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.xv.se.i64.nxv2i64.i64.i64(i64 immarg, i64 immarg, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_xv_se_u64m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.xv.se.i64.nxv4i64.i64.i64(i64 3, i64 31, %0, i64 %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.xv.se.i64.nxv4i64.i64.i64(i64 immarg, i64 immarg, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_xv_se_u64m8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.xv.se.i64.nxv8i64.i64.i64(i64 3, i64 31, %0, i64 %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.xv.se.i64.nxv8i64.i64.i64(i64 immarg, i64 immarg, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xv_se_u64m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vc.v.xv.se.nxv1i64.i64.nxv1i64.i64.i64(i64 3, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.xv.se.nxv1i64.i64.nxv1i64.i64.i64(i64 immarg, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xv_se_u64m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vc.v.xv.se.nxv2i64.i64.nxv2i64.i64.i64(i64 3, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.xv.se.nxv2i64.i64.nxv2i64.i64.i64(i64 immarg, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xv_se_u64m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vc.v.xv.se.nxv4i64.i64.nxv4i64.i64.i64(i64 3, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.xv.se.nxv4i64.i64.nxv4i64.i64.i64(i64 immarg, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xv_se_u64m8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vc.v.xv.se.nxv8i64.i64.nxv8i64.i64.i64(i64 3, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.xv.se.nxv8i64.i64.nxv8i64.i64.i64(i64 immarg, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xv_u64m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vc.v.xv.nxv1i64.i64.nxv1i64.i64.i64(i64 3, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nounwind memory(none) # | declare @llvm.riscv.sf.vc.v.xv.nxv1i64.i64.nxv1i64.i64.i64(i64 immarg, , i64, i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xv_u64m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vc.v.xv.nxv2i64.i64.nxv2i64.i64.i64(i64 3, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nounwind memory(none) # | declare @llvm.riscv.sf.vc.v.xv.nxv2i64.i64.nxv2i64.i64.i64(i64 immarg, , i64, i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xv_u64m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vc.v.xv.nxv4i64.i64.nxv4i64.i64.i64(i64 3, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nounwind memory(none) # | declare @llvm.riscv.sf.vc.v.xv.nxv4i64.i64.nxv4i64.i64.i64(i64 immarg, , i64, i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xv_u64m8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl. # | ... # `---data was truncated (10240/11504) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f937e1a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f937e17515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f937e1acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f82ba249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f82ba2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f82ba249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f82ba231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f937db024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f937db0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f937d94f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f937a44176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f937a43e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f82ba232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f82ba2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f82ba2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f937a43d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c (2020 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64( %1, %2, float %3, %0, i64 2, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64( %1, %2, float %3, %0, i64 2, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load # | ... # `---data was truncated (10240/26710) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b35ca7357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b35ca70515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b35ca73cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff1d4905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff1d495c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff1d4905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff1d48ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b35ca0924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b35ca09096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b35c9edf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b35c69d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b35c69ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff1d48eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff1d48ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff1d48ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b35c69cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c (2021 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056326327257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056326326f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563263272cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efc16133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efc1618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efc16133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efc1611b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056326320824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563263208096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005632631ecf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563262e9c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563262e9be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efc1611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efc1611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efc1611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563262e9bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c (2022 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align # | ... # `---data was truncated (10240/47596) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fb0331f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fb0331c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fb0331fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1deb533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1deb58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1deb533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1deb51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fb032b524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fb032b5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fb03299f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fb02f49176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fb02f48e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1deb51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1deb51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1deb51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fb02f48d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-mve-intrinsics/reinterpret.c (2023 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/reinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c --check-prefix=BOTH --check-prefix=LE # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = bitcast <8 x i16> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = bitcast <4 x i32> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_s64(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | %1 = bitcast <2 x i64> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = bitcast <8 x i16> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = bitcast <4 x i32> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_u64(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | %1 = bitcast <2 x i64> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = bitcast <8 x half> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = bitcast <8 x i16> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = bitcast <4 x i32> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_s64(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | %1 = bitcast <2 x i64> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = bitcast <8 x i16> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = bitcast <4 x i32> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_u64(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | %1 = bitcast <2 x i64> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = bitcast <8 x half> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = bitcast <4 x i32> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_s64(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | %1 = bitcast <2 x i64> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | ret <8 x i16> %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = bitcast <4 x i32> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_u64(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | %1 = bitcast <2 x i64> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vreinterpretq_s32_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = bitcast <8 x half> %0 to <4 x i32> # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vreinterpretq_s32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vreinterpretq_s32_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align # | ... # `---data was truncated (10240/30281) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>' # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<> # | #0 0x000055a9dae8057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a9dae7d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a9dae80cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5adf849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5adf8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5adf849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5adf831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a9dae1624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a9dae16096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a9dadfaf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a9daaaa176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a9daaa9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5adf832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5adf8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5adf8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a9daaa9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c --check-prefix=BOTH --check-prefix=LE # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c --check-prefix=BOTH --check-prefix=LE # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c (2024 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005571b794d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005571b794a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005571b794dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9421533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f942158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9421533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f942151b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005571b78e324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005571b78e3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005571b78c7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005571b7577176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005571b7576e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f942151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f942151d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f942151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005571b7576d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c (2025 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16mf2_bf16mf4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1bf16.nxv2bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1bf16.nxv2bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m1_bf16mf4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1bf16.nxv4bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1bf16.nxv4bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m1_bf16mf2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2bf16.nxv4bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2bf16.nxv4bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m2_bf16mf4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1bf16.nxv8bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1bf16.nxv8bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m2_bf16mf2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2bf16.nxv8bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2bf16.nxv8bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m2_bf16m1( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv8bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv8bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m4_bf16mf4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m4_bf16mf2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m4_bf16m1( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m4_bf16m2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m8_bf16mf4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m8_bf16mf2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m8_bf16m1( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m8_bf16m2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m8_bf16m4(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c (2026 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_f64m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_i64m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_u64m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562428a5257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562428a4f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562428a52cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7e4961bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7e496725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7e4961ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7e49603507 abort ./stdlib/abort.c:85:3 # | #7 0x00005624289e824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005624289e8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005624289ccf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056242867c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056242867be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7e49604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7e496050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7e496050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056242867bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c (2027 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv1i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv2i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv4i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv8i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv16i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv32i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv64i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv1i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv2i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv4i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv8i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv16i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv16i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c (2028 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16mf4_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16mf4_f32mf2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16mf2_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16mf2_f32m1( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16m1_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16m1_f32m2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16m2_f32m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16m2_f32m4( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16m4_f32m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv16f32.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv16f32.nxv16bf16.nxv16bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16m4_f32m8( %vs2, bflo # | ... # `---data was truncated (10240/43940) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556d8ee6957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556d8ee66515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556d8ee69cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faf28c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faf28ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faf28c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faf28c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556d8edff24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556d8edff096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556d8ede3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556d8ea93176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556d8ea92e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007faf28c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faf28c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faf28c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556d8ea92d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c (2029 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-neon-fma.c (2030 of 27911) ******************** TEST 'Clang :: CodeGen/arm-neon-fma.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-none-linux-gnueabihf -target-abi aapcs -target-cpu cortex-a7 -mfloat-abi hard -ffreestanding -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-none-linux-gnueabihf -target-abi aapcs -target-cpu cortex-a7 -mfloat-abi hard -ffreestanding -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv7-none-linux-gnueabihf" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_fma_order(<2 x float> noundef %accum, <2 x float> noundef %lhs, <2 x float> noundef %rhs) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__p2.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %accum.addr = alloca <2 x float>, align 8 # | %lhs.addr = alloca <2 x float>, align 8 # | %rhs.addr = alloca <2 x float>, align 8 # | store <2 x float> %accum, ptr %accum.addr, align 8 # | store <2 x float> %lhs, ptr %lhs.addr, align 8 # | store <2 x float> %rhs, ptr %rhs.addr, align 8 # | %0 = load <2 x float>, ptr %accum.addr, align 8 # | %1 = load <2 x float>, ptr %lhs.addr, align 8 # | %2 = load <2 x float>, ptr %rhs.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | store <2 x float> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %6 = bitcast <8 x i8> %3 to <2 x float> # | %7 = bitcast <8 x i8> %4 to <2 x float> # | %8 = bitcast <8 x i8> %5 to <2 x float> # | %9 = call <2 x float> @llvm.fma.v2f32(<2 x float> %7, <2 x float> %8, <2 x float> %6) # | store <2 x float> %9, ptr %ref.tmp.i, align 8 # | %10 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %10, ptr %__ret.i, align 8 # | %11 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_fmaq_order(<4 x float> noundef %accum, <4 x float> noundef %lhs, <4 x float> noundef %rhs) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__p1.addr.i = alloca <4 x float>, align 8 # | %__p2.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %accum.addr = alloca <4 x float>, align 8 # | %lhs.addr = alloca <4 x float>, align 8 # | %rhs.addr = alloca <4 x float>, align 8 # | store <4 x float> %accum, ptr %accum.addr, align 8 # | store <4 x float> %lhs, ptr %lhs.addr, align 8 # | store <4 x float> %rhs, ptr %rhs.addr, align 8 # | %0 = load <4 x float>, ptr %accum.addr, align 8 # | %1 = load <4 x float>, ptr %lhs.addr, align 8 # | %2 = load <4 x float>, ptr %rhs.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x float> %1, ptr %__p1.addr.i, align 8 # | store <4 x float> %2, ptr %__p2.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 8 # | %6 = bitcast <16 x i8> %3 to <4 x float> # | %7 = bitcast <16 x i8> %4 to <4 x float> # | %8 = bitcast <16 x i8> %5 to <4 x float> # | %9 = call <4 x float> @llvm.fma.v4f32(<4 x float> %7, <4 x float> %8, <4 x float> %6) # | store <4 x float> %9, ptr %ref.tmp.i, align 8 # | %10 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %10, ptr %__ret.i, align 8 # | %11 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vfma_n_f32(<2 x float> noundef %a, <2 x float> noundef %b, float noundef %n) #0 { # | entry: # | %__p0.addr.i.i = alloca <2 x float>, align 8 # | %__p1.addr.i.i = alloca <2 x float>, align 8 # | %__p2.addr.i.i = alloca <2 x float>, align 8 # | %__ret.i.i = alloca <2 x float>, align 8 # | %ref.tmp.i.i = alloca <8 x i8>, align 8 # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__p2.addr.i = alloca float, align 4 # | %__ret.i = alloca <2 x float>, align 8 # | %.compoundliteral.i = alloca <2 x float>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | %n.addr = alloca float, align 4 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | store float %n, ptr %n.addr, align 4 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | %2 = load float, ptr %n.addr, align 4 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | store float %2, ptr %__p2.addr.i, align 4 # | %3 = load <2 x float>, ptr %__p0.addr.i, align 8 # | %4 = load <2 x float>, ptr %__p1.addr.i, align 8 # | %5 = load float, ptr %__p2.addr.i, align 4 # | %vecinit.i = insertelement <2 x float> poison, float %5, i32 0 # | %6 = load float, ptr %__p2.addr.i, align 4 # | %vecinit1.i = insertelement <2 x float> %vecinit.i, float %6, i32 1 # | store <2 x float> %vecinit1.i, ptr %.compoundliteral.i, align 8 # | %7 = load <2 x float>, ptr %.compoundliteral.i, align 8 # | store <2 x float> %3, ptr %__p0.addr.i.i, align 8 # | store <2 x float> %4, ptr %__p1.addr.i.i, align 8 # | store <2 x float> %7, ptr %__p2.addr.i.i, align 8 # | %8 = load <8 x i8>, ptr %__p0.addr.i.i, align 8 # | %9 = load <8 x i8>, ptr %__p1.addr.i.i, align 8 # | %10 = load <8 x i8>, ptr %__p2.addr.i.i, align 8 # | %11 = bitcast <8 x i8> %8 to <2 x float> # | %12 = bitcast <8 x i8> %9 to <2 x float> # | %13 = bitcast <8 x i8> %10 to <2 x float> # | %14 = call <2 x float> @llvm.fma.v2f32(<2 x float> %12, <2 x float> %13, <2 x float> %11) # | store <2 x float> %14, ptr %ref.tmp.i.i, align 8 # | %15 = load <2 x float>, ptr %ref.tmp.i.i, align 8 # | store <2 x float> %15, ptr %__ret.i.i, align 8 # | %16 = load <2 x float>, ptr %__ret.i.i, align 8 # | store <2 x float> %16, ptr %__ret.i, align 8 # | %17 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %17 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vfmaq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %n) #0 { # | entry: # | %__p0.addr.i.i = alloca <4 x float>, align 8 # | %__p1.addr.i.i = alloca <4 x float>, align 8 # | %__p2.addr.i.i = alloca <4 x float>, align 8 # | %__ret.i.i = alloca <4 x float>, align 8 # | %ref.tmp.i.i = alloca <16 x i8>, align 8 # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__p1.addr.i = alloca <4 x float>, align 8 # | %__p2.addr.i = alloca float, align 4 # | %__ret.i = alloca <4 x float>, align 8 # | %.compoundliteral.i = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %n.addr = alloca float, align 4 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store float %n, ptr %n.addr, align 4 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load float, ptr %n.addr, align 4 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x float> %1, ptr %__p1.addr.i, align 8 # | store float %2, ptr %__p2.addr.i, align 4 # | %3 = load <4 x float>, ptr %__p0.addr.i, align 8 # | %4 = load <4 x float>, ptr %__p1.addr.i, align 8 # | %5 = load float, ptr %__p2.addr.i, align 4 # | %vecinit.i = insertelement <4 x float> poison, float %5, i32 0 # | %6 = load float, ptr %__p2.addr.i, align 4 # | %vecinit1.i = insertelement <4 x float> %vecinit.i, float %6, i32 1 # | %7 = load float, ptr %__p2.addr.i, align 4 # | %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %7, i32 2 # | %8 = load float, ptr %__p2.addr.i, align 4 # | %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %8, i32 3 # | store <4 x float> %vecinit3.i, ptr %.compoundliteral.i, align 8 # | %9 = load <4 x float>, ptr %.compoundliteral.i, align 8 # | store <4 x float> %3, ptr %__p0.addr.i.i, align 8 # | store <4 x float> %4, ptr %__p1.addr.i.i, align 8 # | store <4 x float> %9, ptr %__p2.addr.i.i, align 8 # | %10 = load <16 x i8>, ptr %__p0.addr.i.i, align 8 # | %11 = load <16 x i8>, ptr %__p1.addr.i.i, align 8 # | %12 = load <16 x i8>, ptr %__p2.addr.i.i, align 8 # | %13 = bitcast <16 x i8> %10 to <4 x float> # | %14 = bitcast <16 x i8> %11 to <4 x float> # | %15 = bitcast <16 x i8> %12 to <4 x float> # | %16 = call <4 x float> @llvm.fma.v4f32(<4 x float> %14, <4 x float> %15, <4 x float> %13) # | store <4 x float> %16, ptr %ref.tmp.i.i, align 8 # | %17 = load <4 x float>, ptr %ref.tmp.i.i, align 8 # | store <4 x float> %17, ptr %__ret.i.i, align 8 # | %18 = load <4 x float>, ptr %__ret.i.i, align 8 # | store <4 x float> %18, ptr %__ret.i, align 8 # | %19 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %19 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) #1 # | # | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a7" "target-features"="+armv7-a,+d32,+dsp,+fp16,+fp64,+hwdiv,+hwdiv-arm,+neon,+thumb-mode,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp,+vfp4,+vfp4d16,+vfp4d16sp,+vfp4sp" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1} # | !llvm.ident = !{!2} # | # | !0 = !{i32 1, !"target-abi", !"aapcs"} # | !1 = !{i32 1, !"min_enum_size", i32 4} # | !2 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055b14f47457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b14f471515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b14f474cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb758049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb7580a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb758049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb758031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b14f40a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b14f40a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b14f3eef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b14f09e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b14f09de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb758032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb7580330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb7580330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b14f09dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c (2031 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv32i8.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv. # | ... # `---data was truncated (10240/164791) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056404df2357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056404df20515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056404df23cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6bc7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6bc778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6bc7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6bc771b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056404deb924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056404deb9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056404de9df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056404db4d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056404db4ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6bc771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6bc771d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6bc771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056404db4cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcvt_anpm.c (2032 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcvt_anpm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtaq_s16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.arm.mve.vcvta.v8i16.v8f16(i32 0, <8 x half> %0) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vcvta.v8i16.v8f16(i32, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtaq_s32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.arm.mve.vcvta.v4i32.v4f32(i32 0, <4 x float> %0) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vcvta.v4i32.v4f32(i32, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtaq_u16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.arm.mve.vcvta.v8i16.v8f16(i32 1, <8 x half> %0) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtaq_u32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.arm.mve.vcvta.v4i32.v4f32(i32 1, <4 x float> %0) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtmq_s16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.arm.mve.vcvtm.v8i16.v8f16(i32 0, <8 x half> %0) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vcvtm.v8i16.v8f16(i32, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtmq_s32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.arm.mve.vcvtm.v4i32.v4f32(i32 0, <4 x float> %0) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vcvtm.v4i32.v4f32(i32, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtmq_u16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.arm.mve.vcvtm.v8i16.v8f16(i32 1, <8 x half> %0) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtmq_u32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.arm.mve.vcvtm.v4i32.v4f32(i32 1, <4 x float> %0) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtnq_s16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.arm.mve.vcvtn.v8i16.v8f16(i32 0, <8 x half> %0) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vcvtn.v8i16.v8f16(i32, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtnq_s32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.arm.mve.vcvtn.v4i32.v4f32(i32 0, <4 x float> %0) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vcvtn.v4i32.v4f32(i32, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtnq_u16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.arm.mve.vcvtn.v8i16.v8f16(i32 1, <8 x half> %0) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtnq_u32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.arm.mve.vcvtn.v4i32.v4f32(i32 1, <4 x float> %0) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtpq_s16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.arm.mve.vcvtp.v8i16.v8f16(i32 0, <8 x half> %0) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vcvtp.v8i16.v8f16(i32, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtpq_s32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.arm.mve.vcvtp.v4i32.v4f32(i32 0, <4 x float> %0) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vcvtp.v4i32.v4f32(i32, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtpq_u16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.arm.mve.vcvtp.v8i16.v8f16(i32 1, <8 x half> %0) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtpq_u32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.arm.mve.vcvtp.v4i32.v4f32(i32 1, <4 x float> %0) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtaq_m_s16_f16(<8 x i16> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %inactive.addr, align 8 # | %1 = load <8 x half>, ptr %a.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vcvta.predicated.v8i16.v8f16.v8i1(i32 0, <8 x i16> %0, <8 x half> %1, <8 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vcvta.predicated.v8i16.v8f16.v8i1(i32, <8 x i16>, <8 x half>, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtaq_m_s32_f32(<4 x i32> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %inactive.addr, align 8 # | %1 = load <4 x float>, ptr %a.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.vcvta.predicated.v4i32.v4f32.v4i1(i32 0, <4 x i32> %0, <4 x float> %1, <4 x i1> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vcvta.predicated.v4i32.v4f32.v4i1(i32, <4 x i32>, <4 x float>, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtaq_m_u16_f16(<8 x i16> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %inactive.addr, align 8 # | %1 = load <8 x half>, ptr %a.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1( # | ... # `---data was truncated (10240/32505) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556a4f09e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556a4f09b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556a4f09ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0dc6333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0dc638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0dc6333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0dc631b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556a4f03424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556a4f034096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556a4f018f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556a4ecc8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556a4ecc7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0dc631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0dc631d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0dc631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556a4ecc7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c (2033 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range # | ... # `---data was truncated (10240/302397) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a02f56357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a02f560515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a02f563cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe21b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe21b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe21b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe21b91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a02f4f924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a02f4f9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a02f4ddf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a02f18d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a02f18ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe21b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe21b91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe21b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a02f18cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c (2034 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv16bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m8_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv32bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf4_tum( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(, , bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf2_tum( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , pt # | ... # `---data was truncated (10240/32402) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055983aad657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055983aad3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055983aad6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff722a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff722a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff722a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff722a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055983aa6c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055983aa6c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055983aa50f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055983a700176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055983a6ffe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff722a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff722a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff722a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055983a6ffd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/X86/sse.c (2035 of 27911) ******************** TEST 'Clang :: CodeGen/X86/sse.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple x86_64-- -target-feature +sse4.1 -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple x86_64-- -target-feature +sse4.1 -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-unknown" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_mm_slli_si128(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = bitcast <2 x i64> %0 to <16 x i8> # | %pslldq = shufflevector <16 x i8> zeroinitializer, <16 x i8> %1, <16 x i32> # | %2 = bitcast <16 x i8> %pslldq to <2 x i64> # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_mm_slli_si128_0(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = bitcast <2 x i64> %0 to <16 x i8> # | %pslldq = shufflevector <16 x i8> zeroinitializer, <16 x i8> %1, <16 x i32> # | %2 = bitcast <16 x i8> %pslldq to <2 x i64> # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_mm_slli_si128_16(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = bitcast <2 x i64> %0 to <16 x i8> # | ret <2 x i64> zeroinitializer # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_mm_srli_si128(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = bitcast <2 x i64> %0 to <16 x i8> # | %psrldq = shufflevector <16 x i8> %1, <16 x i8> zeroinitializer, <16 x i32> # | %2 = bitcast <16 x i8> %psrldq to <2 x i64> # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_mm_srli_si128_0(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = bitcast <2 x i64> %0 to <16 x i8> # | %psrldq = shufflevector <16 x i8> %1, <16 x i8> zeroinitializer, <16 x i32> # | %2 = bitcast <16 x i8> %psrldq to <2 x i64> # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_mm_srli_si128_16(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = bitcast <2 x i64> %0 to <16 x i8> # | ret <2 x i64> zeroinitializer # | } # | # | attributes #0 = { noinline nounwind "min-legal-vector-width"="128" "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+sse3,+sse4.1,+ssse3,+x87" } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557329f4e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557329f4b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557329f4ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbd61133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbd6118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbd61133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbd6111b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557329ee424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557329ee4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557329ec8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557329b78176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557329b77e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbd6111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbd6111d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbd6111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557329b77d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c (2036 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a16f -target-feature +xsfmm32a32f -target-feature +xsfmm64a64f -target-feature +zvfhmin -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a16f -target-feature +xsfmm32a32f -target-feature +xsfmm64a64f -target-feature +zvfhmin -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_mm_f_f_w2_f16m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_mm_f_f_w1_f32m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.f.f.i64.nxv16f32(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.f.f.i64.nxv16f32(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_mm_f_f_w1_f64m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.f.f.i64.nxv8f64(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.f.f.i64.nxv8f64(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+xsfmm32a16f,+xsfmm32a32f,+xsfmm64a64f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvl32b1p0_zvl64b1p0_xsfmm32a16f0p6_xsfmm32a32f0p6_xsfmm64a64f0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557eece8a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557eece87515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557eece8acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc831533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc83158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc831533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc83151b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557eece2024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557eece20096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557eece04f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557eecab4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557eecab3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc83151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc83151d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc83151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557eecab3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c (2037 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16m4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_ # | ... # `---data was truncated (10240/68065) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562b0b7ec57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562b0b7e9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562b0b7eccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff9fd533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff9fd58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff9fd533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff9fd51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562b0b78224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562b0b782096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562b0b766f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562b0b416176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562b0b415e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff9fd51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff9fd51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff9fd51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562b0b415d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c (2038 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | s # | ... # `---data was truncated (10240/223359) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055701e73a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055701e737515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055701e73acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa690b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa690b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa690b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa690b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055701e6d024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055701e6d0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055701e6b4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055701e364176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055701e363e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa690b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa690b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa690b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055701e363d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminaq.c (2039 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminaq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminaq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %b.addr, align 8 # | %1 = icmp slt <16 x i8> %0, zeroinitializer # | %2 = sub <16 x i8> zeroinitializer, %0 # | %3 = select <16 x i1> %1, <16 x i8> %2, <16 x i8> %0 # | %4 = load <16 x i8>, ptr %a.addr, align 8 # | %5 = icmp ule <16 x i8> %4, %3 # | %6 = select <16 x i1> %5, <16 x i8> %4, <16 x i8> %3 # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminaq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %b.addr, align 8 # | %1 = icmp slt <8 x i16> %0, zeroinitializer # | %2 = sub <8 x i16> zeroinitializer, %0 # | %3 = select <8 x i1> %1, <8 x i16> %2, <8 x i16> %0 # | %4 = load <8 x i16>, ptr %a.addr, align 8 # | %5 = icmp ule <8 x i16> %4, %3 # | %6 = select <8 x i1> %5, <8 x i16> %4, <8 x i16> %3 # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminaq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %b.addr, align 8 # | %1 = icmp slt <4 x i32> %0, zeroinitializer # | %2 = sub <4 x i32> zeroinitializer, %0 # | %3 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %0 # | %4 = load <4 x i32>, ptr %a.addr, align 8 # | %5 = icmp ule <4 x i32> %4, %3 # | %6 = select <4 x i1> %5, <4 x i32> %4, <4 x i32> %3 # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminaq_m_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vmina.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vmina.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminaq_m_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vmina.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vmina.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminaq_m_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.vmina.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vmina.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bb4d60657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bb4d603515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bb4d606cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6f9f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6f9f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6f9f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6f9f51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bb4d59c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bb4d59c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bb4d580f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bb4d230176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bb4d22fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6f9f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6f9f51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6f9f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bb4d22fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c (2040 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16mf4_tu( %vd, %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv1bf16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv1bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16mf2_tu( %vd, %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv2bf16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv2bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16m1_tu( %vd, %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv4bf16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv4bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16m2_tu( %vd, %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv8bf16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv8bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m4_tu( %vd, %vs2, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c (2041 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_i8mf8x6 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560bd0c9a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560bd0c97515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560bd0c9acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f22a6533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f22a658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f22a6533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f22a651b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560bd0c3024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560bd0c30096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560bd0c14f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560bd08c4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560bd08c3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f22a651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f22a651d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f22a651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560bd08c3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c (2042 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge # | ... # `---data was truncated (10240/18668) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005649065f357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005649065f0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005649065f3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2e8ee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2e8eea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2e8ee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2e8ee31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056490658924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564906589096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056490656df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056490621d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056490621ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2e8ee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2e8ee330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2e8ee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056490621cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c (2043 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor # | ... # `---data was truncated (10240/61929) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dc23f9f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055dc23f9c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055dc23f9fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa37f61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa37f6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa37f61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa37f603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dc23f3524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055dc23f35096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055dc23f19f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055dc23bc9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055dc23bc8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa37f604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa37f6050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa37f6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dc23bc8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c (2044 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f64m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tu # | ... # `---data was truncated (10240/99186) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055baec7d757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055baec7d4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055baec7d7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff363733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff36378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff363733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff36371b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055baec76d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055baec76d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055baec751f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055baec401176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055baec400e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff36371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff36371d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff36371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055baec400d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c (2045 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_f32mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_f32m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_i32mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_i32m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_u32mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_u32m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_f32mf2x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_f32m1x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_i32mf2x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_i32m1x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/14010) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fc71d4e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fc71d4b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fc71d4ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8915849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f89158a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8915849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8915831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fc71ce424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fc71ce4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fc71cc8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fc71978176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fc71977e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8915832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f89158330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f89158330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fc71977d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c (2046 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/48305) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556235ac457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556235ac1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556235ac4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd61b21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd61b2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd61b21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd61b203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556235a5a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556235a5a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556235a3ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005562356ee176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005562356ede93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd61b204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd61b2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd61b2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005562356edd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c (2047 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_u16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, ali # | ... # `---data was truncated (10240/60543) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563bfc68e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563bfc68b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563bfc68ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7d5c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7d5c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7d5c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7d5c71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563bfc62424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563bfc624096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563bfc608f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563bfc2b8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563bfc2b7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7d5c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7d5c71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7d5c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563bfc2b7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c (2048 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16mf4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16mf4_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16mf2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16mf2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16m1_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16m2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c (2049 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055879d7d557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055879d7d2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055879d7d5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f19e1049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f19e10a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f19e1049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f19e1031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055879d76b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055879d76b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055879d74ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055879d3ff176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055879d3fee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f19e1032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f19e10330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f19e10330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055879d3fed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c (2050 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv2i16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv4i16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv8i16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv16i16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv32i16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i32.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv2i32.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv4i32.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv8i32.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i32.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv16i32.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv16i32.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i64.nxv1i32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i64.nxv1i32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , # | ... # `---data was truncated (10240/28571) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ed461bb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ed461b8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ed461bbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efeb0d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efeb0d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efeb0d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efeb0d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ed4615124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ed46151096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ed46135f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ed45de5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ed45de4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efeb0d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efeb0d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efeb0d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ed45de4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c (2051 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005563ce2fb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005563ce2f8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005563ce2fbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5341b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5341b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5341b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5341b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005563ce29124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005563ce291096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005563ce275f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005563cdf25176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005563cdf24e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5341b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5341b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5341b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005563cdf24d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c (2052 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055efac41b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055efac418515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055efac41bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2971849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f29718a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2971849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2971831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055efac3b124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055efac3b1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055efac395f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055efac045176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055efac044e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2971832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f29718330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f29718330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055efac044d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c (2053 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_i64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_i64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_u64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_u64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m1x4_tum( %mask, target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("r # | ... # `---data was truncated (10240/36023) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f977a1157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f977a0e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f977a11cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4e9c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4e9c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4e9c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4e9c631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f9779a724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f9779a7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f97798bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f97763b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f97763ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4e9c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4e9c6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4e9c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f97763ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c (2054 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captu # | ... # `---data was truncated (10240/87308) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005589a980457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005589a9801515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005589a9804cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f568d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f568d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f568d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f568d231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005589a979a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005589a979a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005589a977ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005589a942e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005589a942de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f568d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f568d2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f568d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005589a942dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c (2055 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_f16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_f16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_f16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_i16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_i16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_i16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_u16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_u16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_u16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", # | ... # `---data was truncated (10240/23365) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005606039de57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005606039db515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005606039decbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fde77133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fde7718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fde77133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fde7711b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056060397424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560603974096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560603958f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560603608176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560603607e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fde7711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fde7711d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fde7711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560603607d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c (2056 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16mf4x6(ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16mf2x6(ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16m1x6(ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16m1x6_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558c42f3b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558c42f38515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558c42f3bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f916a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f916a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f916a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f916a71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558c42ed124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558c42ed1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558c42eb5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558c42b65176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558c42b64e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f916a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f916a71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f916a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558c42b64d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c (2057 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32mf2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32m1x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32m2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32mf2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32m1x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32m2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_u32mf2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractval # | ... # `---data was truncated (10240/13669) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005652ff9d957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005652ff9d6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005652ff9d9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6abf533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6abf58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6abf533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6abf51b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005652ff96f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005652ff96f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005652ff953f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005652ff603176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005652ff602e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6abf51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6abf51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6abf51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005652ff602d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c (2058 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055727c4b257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055727c4af515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055727c4b2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1867849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f18678a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1867849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1867831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055727c44824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055727c448096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055727c42cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055727c0dc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055727c0dbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1867832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f18678330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f18678330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055727c0dbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c (2059 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16mf4( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16mf2( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m1( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m2( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m4( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv16f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m8( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv32f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv32f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32mf2( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv1f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32m1( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv2f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32m2( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv4f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv4f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32m4( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv8f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv8f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | de # | ... # `---data was truncated (10240/34581) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005654e8adb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005654e8ad8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005654e8adbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6e9e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6e9e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6e9e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6e9e91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005654e8a7124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005654e8a71096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005654e8a55f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005654e8705176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005654e8704e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6e9e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6e9e91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6e9e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005654e8704d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c (2060 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m1x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 nou # | ... # `---data was truncated (10240/27442) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ae4a07057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ae4a06d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ae4a070cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f27ff249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f27ff2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f27ff249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f27ff231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ae4a00624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ae4a006096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ae49feaf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ae49c9a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ae49c99e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f27ff232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f27ff2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f27ff2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ae49c99d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c (2061 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559442b2c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559442b29515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559442b2ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f795b905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f795b95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f795b905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f795b8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559442ac224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559442ac2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559442aa6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559442756176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559442755e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f795b8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f795b8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f795b8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559442755d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c (2062 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv16i8.nxv16i16.i64.i64( poison, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c (2063 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7 # | ... # `---data was truncated (10240/64374) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ca252d557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ca252d2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ca252d5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa31bc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa31bca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa31bc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa31bc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ca2526b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ca2526b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ca2524ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ca24eff176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ca24efee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa31bc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa31bc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa31bc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ca24efed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c (2064 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf8x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv1i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv1i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf4x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf2x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf8x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv1i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf4x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf2x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/12668) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005653e4a7657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005653e4a73515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005653e4a76cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa71e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa71e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa71e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa71e91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005653e4a0c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005653e4a0c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005653e49f0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005653e46a0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005653e469fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa71e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa71e91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa71e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005653e469fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c (2065 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv8f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv16f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv32f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, al # | ... # `---data was truncated (10240/128416) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555e5ebcf57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555e5ebcc515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555e5ebcfcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb809933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb80998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb809933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb80991b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555e5eb6524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555e5eb65096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555e5eb49f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555e5e7f9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555e5e7f8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb80991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb80991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb80991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555e5e7f8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c (2066 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv1i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv2i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv4i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv8i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv16i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv32i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv64i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv1i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv2i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv4i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , al # | ... # `---data was truncated (10240/92370) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055af9174357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055af91740515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055af91743cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fccbfb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fccbfb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fccbfb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fccbfaed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055af916d924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055af916d9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055af916bdf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055af9136d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055af9136ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fccbfaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fccbfaef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fccbfaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055af9136cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c (2067 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/87892) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055729cfc757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055729cfc4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055729cfc7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f91fef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f91fef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f91fef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f91fef1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055729cf5d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055729cf5d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055729cf41f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055729cbf1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055729cbf0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f91fef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f91fef1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f91fef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055729cbf0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c (2068 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = # | ... # `---data was truncated (10240/14319) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005646671cb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005646671c8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005646671cbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffb81333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffb8138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffb81333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffb8131b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056466716124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564667161096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564667145f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564666df5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564666df4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ffb8131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffb8131d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffb8131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564666df4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/AArch64/neon/rounding.c (2069 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon/rounding.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c --check-prefixes=LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrnd_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndz.i = bitcast <8 x i8> %1 to <2 x float> # | %vrndz1.i = call <2 x float> @llvm.trunc.v2f32(<2 x float> %vrndz.i) # | store <2 x float> %vrndz1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrndq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrndz.i = bitcast <16 x i8> %1 to <4 x float> # | %vrndz1.i = call <4 x float> @llvm.trunc.v4f32(<4 x float> %vrndz.i) # | store <4 x float> %vrndz1.i, ptr %ref.tmp.i, align 16 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %2, ptr %__ret.i, align 16 # | %3 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vrnd_f64(<1 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x double>, align 8 # | %__ret.i = alloca <1 x double>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndz.i = bitcast <8 x i8> %1 to <1 x double> # | %vrndz1.i = call <1 x double> @llvm.trunc.v1f64(<1 x double> %vrndz.i) # | store <1 x double> %vrndz1.i, ptr %ref.tmp.i, align 8 # | %2 = load <1 x double>, ptr %ref.tmp.i, align 8 # | store <1 x double> %2, ptr %__ret.i, align 8 # | %3 = load <1 x double>, ptr %__ret.i, align 8 # | ret <1 x double> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vrndq_f64(<2 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrndz.i = bitcast <16 x i8> %1 to <2 x double> # | %vrndz1.i = call <2 x double> @llvm.trunc.v2f64(<2 x double> %vrndz.i) # | store <2 x double> %vrndz1.i, ptr %ref.tmp.i, align 16 # | %2 = load <2 x double>, ptr %ref.tmp.i, align 16 # | store <2 x double> %2, ptr %__ret.i, align 16 # | %3 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrndn_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndn.i = bitcast <8 x i8> %1 to <2 x float> # | %vrndn1.i = call <2 x float> @llvm.roundeven.v2f32(<2 x float> %vrndn.i) # | store <2 x float> %vrndn1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrndnq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrndn.i = bitcast <16 x i8> %1 to <4 x float> # | %vrndn1.i = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %vrndn.i) # | store <4 x float> %vrndn1.i, ptr %ref.tmp.i, align 16 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %2, ptr %__ret.i, align 16 # | %3 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vrndn_f64(<1 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x double>, align 8 # | %__ret.i = alloca <1 x double>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndn.i = bitcast <8 x i8> %1 to <1 x double> # | %vrndn1.i = call <1 x double> @llvm.roundeven.v1f64(<1 x double> %vrndn.i) # | store <1 x double> %vrndn1.i, ptr %ref.tmp.i, align 8 # | %2 = load <1 x double>, ptr %ref.tmp.i, align 8 # | store <1 x double> %2, ptr %__ret.i, align 8 # | %3 = load <1 x double>, ptr %__ret.i, align 8 # | ret <1 x double> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vrndnq_f64(<2 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrndn.i = bitcast <16 x i8> %1 to <2 x double> # | %vrndn1.i = call <2 x double> @llvm.roundeven.v2f64(<2 x double> %vrndn.i) # | store <2 x double> %vrndn1.i, ptr %ref.tmp.i, align 16 # | %2 = load <2 x double>, ptr %ref.tmp.i, align 16 # | store <2 x double> %2, ptr %__ret.i, align 16 # | %3 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vrndns_f32(float noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca float, align 4 # | %__ret.i = alloca float, align 4 # | %ref.tmp.i = alloca float, align 4 # | %a.addr = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__p0.addr.i, align 4 # | %1 = load float, ptr %__p0.addr.i, align 4 # | %vrndn.i = call float @llvm.roundeven.f32(float %1) # | store float %vrndn.i, ptr %ref.tmp.i, align 4 # | %2 = load float, ptr %ref.tmp.i, align 4 # | store float %2, ptr %__ret.i, align 4 # | %3 = load float, ptr %__ret.i, align 4 # | ret float %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrndm_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndm.i = bitcast <8 x i8> %1 to <2 x float> # | %vrndm1.i = call <2 x float> @llvm.floor.v2f32(<2 x float> %vrndm.i) # | store <2 x float> %vrndm1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrndmq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrndm.i = bitcast <16 x i8> %1 to <4 x float> # | %vrndm1.i = call <4 x float> @llvm.floor.v4f32(<4 x float> %vrndm.i) # | store <4 x float> %vrndm1.i, ptr %ref.tmp.i, align 16 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %2, ptr %__ret.i, align 16 # | %3 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vrndm_f64(<1 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x double>, align 8 # | %__ret.i = alloca <1 x double>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndm.i = bitcast <8 x i8> %1 to <1 x double> # | %vrndm1.i = call <1 x double> @llvm.floor.v1f64(<1 x double> %vrndm.i) # | store <1 x double> %vrndm1.i, ptr %ref.tmp.i, align 8 # | %2 = load <1 x double>, ptr %ref.tmp.i, align 8 # | store <1 x double> %2, ptr %__ret.i, align 8 # | %3 = load <1 x double>, ptr %__ret.i, align 8 # | ret <1 x double> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vrndmq_f64(<2 x double> noundef %a # | ... # `---data was truncated (10240/29785) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055c0cf60257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c0cf5ff515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c0cf602cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fefd9649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fefd96a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fefd9649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fefd9631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c0cf59824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c0cf598096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c0cf57cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c0cf22c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c0cf22be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fefd9632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fefd96330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fefd96330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c0cf22bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c --check-prefixes=LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c --check-prefixes=LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c (2070 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv16f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv32f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv32f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8i16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 # | ... # `---data was truncated (10240/71955) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e78760b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e787608515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e78760bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f72f4133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f72f418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f72f4133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f72f411b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e7875a124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e7875a1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e787585f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e787235176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e787234e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f72f411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f72f411d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f72f411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e787234d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c (2071 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f64m1x3(ptr noundef %base, %binde # | ... # `---data was truncated (10240/94227) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eaba90057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055eaba8fd515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055eaba900cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6ebb61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6ebb6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6ebb61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6ebb603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eaba89624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055eaba896096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055eaba87af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055eaba52a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055eaba529e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6ebb604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6ebb6050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6ebb6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eaba529d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c (2072 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv32bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv32bf16.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eaa932757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055eaa9324515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055eaa9327cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0ab0533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0ab058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0ab0533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0ab051b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eaa92bd24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055eaa92bd096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055eaa92a1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055eaa8f51176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055eaa8f50e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0ab051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0ab051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0ab051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eaa8f50d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c (2073 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557340e1a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557340e17515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557340e1acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbb2f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbb2f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbb2f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbb2f71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557340db024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557340db0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557340d94f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557340a44176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557340a43e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbb2f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbb2f71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbb2f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557340a43d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmulhq.c (2074 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmulhq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulhq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vmulh.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vmulh.v16i8(<16 x i8>, <16 x i8>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulhq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vmulh.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vmulh.v8i16(<8 x i16>, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulhq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vmulh.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vmulh.v4i32(<4 x i32>, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulhq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.mulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.mulh.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulhq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.mulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.mulh.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulhq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.mulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.mulh.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulhq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.mulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulhq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.mulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulhq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.mulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005593e334557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005593e3342515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005593e3345cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f752be49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f752bea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f752be49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f752be31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005593e32db24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005593e32db096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005593e32bff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005593e2f6f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005593e2f6ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f752be32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f752be330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f752be330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005593e2f6ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c (2075 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_f16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_f16mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_f16m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_f16m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_i16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_i16mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_i16m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_i16m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_u16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store tar # | ... # `---data was truncated (10240/30818) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561b2aa6357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561b2aa60515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561b2aa63cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4755533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f475558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4755533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f475551b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561b2a9f924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561b2a9f9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561b2a9ddf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561b2a68d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561b2a68ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f475551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f475551d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f475551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561b2a68cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c (2076 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vx_i16mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wx_i16mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.w.nxv1i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vx_i16mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wx_i16mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.w.nxv2i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c (2077 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559fb1a9557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559fb1a92515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559fb1a95cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5d7b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5d7b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5d7b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5d7b71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559fb1a2b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559fb1a2b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559fb1a0ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559fb16bf176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559fb16bee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5d7b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5d7b71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5d7b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559fb16bed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c (2078 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willr # | ... # `---data was truncated (10240/44361) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562db71ad57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562db71aa515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562db71adcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f54f6249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f54f62a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f54f6249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f54f6231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562db714324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562db7143096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562db7127f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562db6dd7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562db6dd6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f54f6232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f54f62330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f54f62330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562db6dd6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c (2079 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f8a8de857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f8a8de5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f8a8de8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4d47733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4d4778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4d47733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4d4771b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f8a8d7e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f8a8d7e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f8a8d62f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f8a8a12176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f8a8a11e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4d4771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4d4771d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4d4771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f8a8a11d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c (2080 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f64m1x4(ptr noundef %base, %binde # | ... # `---data was truncated (10240/99754) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d8816be57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d8816bb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d8816becbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5fc9449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5fc94a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5fc9449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5fc9431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d88165424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d881654096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d881638f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d8812e8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d8812e7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5fc9432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5fc94330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5fc94330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d8812e7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c (2081 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf8x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue # | ... # `---data was truncated (10240/81764) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ab2aae757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ab2aae4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ab2aae7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa79a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa79a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa79a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa79a71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ab2aa7d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ab2aa7d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ab2aa61f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ab2a711176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ab2a710e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa79a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa79a71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa79a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ab2a710d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c (2082 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_i8mf8x5_tu(target("riscv.vector.tuple", , 5) %m # | ... # `---data was truncated (10240/160133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ebc5dc257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ebc5dbf515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ebc5dc2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f40fb649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f40fb6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f40fb649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f40fb631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ebc5d5824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ebc5d58096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ebc5d3cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ebc59ec176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ebc59ebe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f40fb632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f40fb6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f40fb6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ebc59ebd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c (2083 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv1i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv2i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv4i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv8i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv16i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv32i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv64i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf8_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf4_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf2_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64( %1, ptr %2, %0, i64 %3, # | ... # `---data was truncated (10240/29443) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558f70a0e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558f70a0b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558f70a0ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdef2049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdef20a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdef2049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdef2031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558f709a424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558f709a4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558f70988f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558f70638176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558f70637e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fdef2032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdef20330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdef20330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558f70637d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c (2084 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfa # | ... # `---data was truncated (10240/65574) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055793915457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557939151515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557939154cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3344e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3344ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3344e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3344e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005579390ea24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005579390ea096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005579390cef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557938d7e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557938d7de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3344e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3344e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3344e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557938d7dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c (2085 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-ZVF /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055feac7d357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055feac7d0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055feac7d3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8060533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f806058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8060533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f806051b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055feac76924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055feac769096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055feac74df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055feac3fd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055feac3fce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f806051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f806051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f806051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055feac3fcd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-ZVF /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-ZVF /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-v8.6a-neon-intrinsics.c (2086 of 27911) ******************** TEST 'Clang :: CodeGen/arm-v8.6a-neon-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.6a-arm-none-eabi -target-feature +neon -target-feature +fullfp16 -target-feature +i8mm -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.6a-arm-none-eabi -target-feature +neon -target-feature +fullfp16 -target-feature +i8mm -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8.6a-arm-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vmmlaq_s32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 8 # | %__p1.addr.i = alloca <16 x i8>, align 8 # | %__p2.addr.i = alloca <16 x i8>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %r.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <4 x i32> %r, ptr %r.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %r.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | store <4 x i32> %0, ptr %__p0.addr.i, align 8 # | store <16 x i8> %1, ptr %__p1.addr.i, align 8 # | store <16 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 8 # | %vmmla.i = bitcast <16 x i8> %3 to <4 x i32> # | %vmmla1.i = call <4 x i32> @llvm.arm.neon.smmla.v4i32.v16i8(<4 x i32> %vmmla.i, <16 x i8> %4, <16 x i8> %5) # | store <4 x i32> %vmmla1.i, ptr %ref.tmp.i, align 8 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 8 # | store <4 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <4 x i32>, ptr %__ret.i, align 8 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vmmlaq_u32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 8 # | %__p1.addr.i = alloca <16 x i8>, align 8 # | %__p2.addr.i = alloca <16 x i8>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %r.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <4 x i32> %r, ptr %r.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %r.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | store <4 x i32> %0, ptr %__p0.addr.i, align 8 # | store <16 x i8> %1, ptr %__p1.addr.i, align 8 # | store <16 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 8 # | %vmmla.i = bitcast <16 x i8> %3 to <4 x i32> # | %vmmla1.i = call <4 x i32> @llvm.arm.neon.ummla.v4i32.v16i8(<4 x i32> %vmmla.i, <16 x i8> %4, <16 x i8> %5) # | store <4 x i32> %vmmla1.i, ptr %ref.tmp.i, align 8 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 8 # | store <4 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <4 x i32>, ptr %__ret.i, align 8 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vusmmlaq_s32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 8 # | %__p1.addr.i = alloca <16 x i8>, align 8 # | %__p2.addr.i = alloca <16 x i8>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %r.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <4 x i32> %r, ptr %r.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %r.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | store <4 x i32> %0, ptr %__p0.addr.i, align 8 # | store <16 x i8> %1, ptr %__p1.addr.i, align 8 # | store <16 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 8 # | %vusmmla.i = bitcast <16 x i8> %3 to <4 x i32> # | %vusmmla1.i = call <4 x i32> @llvm.arm.neon.usmmla.v4i32.v16i8(<4 x i32> %vusmmla.i, <16 x i8> %4, <16 x i8> %5) # | store <4 x i32> %vusmmla1.i, ptr %ref.tmp.i, align 8 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 8 # | store <4 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <4 x i32>, ptr %__ret.i, align 8 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vusdot_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x i32>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | store <2 x i32> %r, ptr %r.addr, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %r.addr, align 8 # | %1 = load <8 x i8>, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %b.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | store <8 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vusdot.i = bitcast <8 x i8> %3 to <2 x i32> # | %vusdot1.i = call <2 x i32> @llvm.arm.neon.usdot.v2i32.v8i8(<2 x i32> %vusdot.i, <8 x i8> %4, <8 x i8> %5) # | store <2 x i32> %vusdot1.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vusdot_lane_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x i32>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret_845 = alloca <2 x i32>, align 8 # | %__s0_845 = alloca <2 x i32>, align 8 # | %__s1_845 = alloca <8 x i8>, align 8 # | %__s2_845 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <2 x i32>, align 8 # | %__ret = alloca <2 x i32>, align 8 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp1 = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x i32>, align 8 # | %tmp2 = alloca <2 x i32>, align 8 # | store <2 x i32> %r, ptr %r.addr, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %r.addr, align 8 # | store <2 x i32> %0, ptr %__s0_845, align 8 # | %1 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %1, ptr %__s1_845, align 8 # | %2 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %2, ptr %__s2_845, align 8 # | %3 = load <2 x i32>, ptr %__s0_845, align 8 # | %4 = load <8 x i8>, ptr %__s1_845, align 8 # | %5 = load <2 x i32>, ptr %__s2_845, align 8 # | store <2 x i32> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x i32> # | %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> zeroinitializer # | store <2 x i32> %lane, ptr %ref.tmp1, align 8 # | %8 = load <2 x i32>, ptr %ref.tmp1, align 8 # | store <2 x i32> %8, ptr %__ret, align 8 # | %9 = load <2 x i32>, ptr %__ret, align 8 # | store <2 x i32> %9, ptr %tmp, align 8 # | %10 = load <2 x i32>, ptr %tmp, align 8 # | store <2 x i32> %10, ptr %ref.tmp, align 8 # | %11 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <2 x i32> %3, ptr %__p0.addr.i, align 8 # | store <8 x i8> %4, ptr %__p1.addr.i, align 8 # | store <8 x i8> %11, ptr %__p2.addr.i, align 8 # | %12 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %13 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %14 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vusdot.i = bitcast <8 x i8> %12 to <2 x i32> # | %vusdot1.i = call <2 x i32> @llvm.arm.neon.usdot.v2i32.v8i8(<2 x i32> %vusdot.i, <8 x i8> %13, <8 x i8> %14) # | store <2 x i32> %vusdot1.i, ptr %ref.tmp.i, align 8 # | %15 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %15, ptr %__ret.i, align 8 # | %16 = load <2 x i32>, ptr %__ret.i, align 8 # | store <2 x i32> %16, ptr %__ret_845, align 8 # | %17 = load <2 x i32>, ptr %__ret_845, align 8 # | store <2 x i32> %17, ptr %tmp2, align 8 # | %18 = load <2 x i32>, ptr %tmp2, align 8 # | ret <2 x i32> %18 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vsudot_lane_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x i32>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret_841 = alloca <2 x i32>, align 8 # | %__s0_841 = alloca <2 x i32>, align 8 # | %__s1_841 = alloca <8 x i8>, align 8 # | %__s2_841 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <2 x i32>, align 8 # | %__ret = alloca <2 x i32>, align 8 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp1 = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x i32>, align 8 # | %tmp2 = alloca <2 x i32>, align 8 # | store <2 x i32> %r, ptr %r.addr, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %r.addr, align 8 # | store <2 x i32> %0, ptr %__s0_841, align 8 # | %1 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %1, ptr %__s1_841, align 8 # | %2 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %2, ptr %__s2_841, align 8 # | %3 = load <2 x i32>, ptr %__s0_841, align 8 # | %4 = load <2 x i32>, ptr %__s2_841, align 8 # | store <2 x i32> %4, ptr %__s0, align 8 # | %5 = load <8 x i8>, ptr %__s0, align 8 # | %6 = bitcast <8 x i8> %5 to <2 x i32> # | %lane = shufflevector <2 x i32> %6, <2 x i32> %6, <2 # | ... # `---data was truncated (10240/18482) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055997896457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559978961515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559978964cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4bba649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4bba6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4bba649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4bba631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005599788fa24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005599788fa096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005599788def49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055997858e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055997858de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4bba632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4bba6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4bba6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055997858dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c (2087 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c (2088 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | # | ... # `---data was truncated (10240/25616) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e3f3c8457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e3f3c81515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e3f3c84cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb1f2c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb1f2c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb1f2c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb1f2c03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e3f3c1a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e3f3c1a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e3f3bfef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e3f38ae176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e3f38ade93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb1f2c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb1f2c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb1f2c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e3f38add81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c (2089 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556cdde9157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556cdde8e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556cdde91cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6ff9c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6ff9ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6ff9c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6ff9c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556cdde2724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556cdde27096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556cdde0bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556cddabb176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556cddabae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6ff9c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6ff9c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6ff9c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556cddabad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c (2090 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounw # | ... # `---data was truncated (10240/12658) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560a335de57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560a335db515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560a335decbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f576c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f576c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f576c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f576c91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560a3357424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560a33574096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560a33558f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560a33208176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560a33207e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f576c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f576c91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f576c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560a33207d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcmulq.c (2091 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcmulq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 0, <8 x half> %0, <8 x half> %1) # | ret <8 x half> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32, <8 x half>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 0, <4 x float> %0, <4 x float> %1) # | ret <4 x float> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32, <4 x float>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot90_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 1, <8 x half> %0, <8 x half> %1) # | ret <8 x half> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot90_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 1, <4 x float> %0, <4 x float> %1) # | ret <4 x float> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot180_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 2, <8 x half> %0, <8 x half> %1) # | ret <8 x half> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot180_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 2, <4 x float> %0, <4 x float> %1) # | ret <4 x float> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot270_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 3, <8 x half> %0, <8 x half> %1) # | ret <8 x half> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot270_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 3, <4 x float> %0, <4 x float> %1) # | ret <4 x float> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %inactive.addr, align 8 # | %1 = load <8 x half>, ptr %a.addr, align 8 # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4) # | %6 = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 0, <8 x half> %0, <8 x half> %1, <8 x half> %2, <8 x i1> %5) # | ret <8 x half> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32, <8 x half>, <8 x half>, <8 x half>, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %inactive.addr, align 8 # | %1 = load <4 x float>, ptr %a.addr, align 8 # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4) # | %6 = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 0, <4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x i1> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32, <4 x float>, <4 x float>, <4 x float>, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot90_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %inactive.addr, align 8 # | %1 = load <8 x half>, ptr %a.addr, align 8 # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4) # | %6 = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 1, <8 x half> %0, <8 x half> %1, <8 x half> %2, <8 x i1> %5) # | ret <8 x half> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot90_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %inactive.addr, align 8 # | %1 = load <4 x float>, ptr %a.addr, align 8 # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4) # | %6 = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 1, <4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x i1> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot180_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %inactive.addr, align 8 # | %1 = load <8 x half>, ptr %a.addr, align 8 # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 % # | ... # `---data was truncated (10240/20326) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563fd65b357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563fd65b0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563fd65b3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9281333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f928138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9281333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f928131b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563fd654924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563fd6549096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563fd652df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563fd61dd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563fd61dce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f928131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f928131d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f928131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563fd61dcd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c (2092 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056083db2957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056083db26515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056083db29cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6b2d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6b2d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6b2d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6b2d71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056083dabf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056083dabf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056083daa3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056083d753176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056083d752e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6b2d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6b2d71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6b2d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056083d752d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c (2093 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m8_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Fu # | ... # `---data was truncated (10240/30423) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f43dbed57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f43dbea515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f43dbedcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5cc041bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5cc04725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5cc041ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5cc0403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f43db8324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f43db83096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f43db67f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f43d817176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f43d816e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5cc0404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5cc04050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5cc04050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f43d816d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c (2094 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m4( %vd, %v # | ... # `---data was truncated (10240/148843) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fcd1dd657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fcd1dd3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fcd1dd6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f311e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f311e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f311e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f311e431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fcd1d6c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fcd1d6c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fcd1d50f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fcd1a00176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fcd19ffe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f311e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f311e4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f311e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fcd19ffd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c (2095 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf4x5(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf2x5(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16m1x5(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf4x5_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf2x5_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16m1x5_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bf6f26757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bf6f264515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bf6f267cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f16a2933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f16a298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f16a2933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f16a291b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bf6f1fd24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bf6f1fd096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bf6f1e1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bf6ee91176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bf6ee90e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f16a291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f16a291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f16a291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bf6ee90d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c (2096 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf8( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf4( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf2( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m1( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m2( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m4( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m8( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv64i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16mf4( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv1i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16mf2( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv2i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16m1( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv4i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16m2( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %v # | ... # `---data was truncated (10240/86747) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005613ef2e757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005613ef2e4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005613ef2e7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3944449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f39444a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3944449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3944431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005613ef27d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005613ef27d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005613ef261f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005613eef11176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005613eef10e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3944432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f39444330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f39444330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005613eef10d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c (2097 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_f64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_i64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_u64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ab2382f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ab2382c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ab2382fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f95e7249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f95e72a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f95e7249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f95e7231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ab237c524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ab237c5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ab237a9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ab23459176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ab23458e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f95e7232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f95e72330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f95e72330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ab23458d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c (2098 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32mf2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m1( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m4( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m8( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32mf2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m1_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | defi # | ... # `---data was truncated (10240/13593) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b0c527557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b0c5272515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b0c5275cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa0b3b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa0b3b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa0b3b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa0b3b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b0c520b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b0c520b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b0c51eff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b0c4e9f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b0c4e9ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa0b3b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa0b3b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa0b3b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b0c4e9ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c (2099 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m4( % # | ... # `---data was truncated (10240/149145) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564b129f757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564b129f4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564b129f7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff45f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff45f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff45f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff45f71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564b1298d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564b1298d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564b12971f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564b12621176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564b12620e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff45f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff45f71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff45f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564b12620d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c (2100 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_i32mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_i32m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_u32mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_u32m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056198171957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561981716515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561981719cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c43733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c4378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c43733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c4371b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005619816af24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005619816af096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561981693f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561981343176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561981342e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2c4371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c4371d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c4371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561981342d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c (2101 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d583da857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d583da5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d583da8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3736133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f373618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3736133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f373611b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d583d3e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d583d3e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d583d22f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d5839d2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d5839d1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f373611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f373611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f373611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d5839d1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c (2102 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16mf4_i8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16mf2_i8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m1_i8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m2_i8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m4_i8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m8_i8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16mf4_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16mf2_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m1_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m2_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m4_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m8_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32bf16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c (2103 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560f8b90e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560f8b90b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560f8b90ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5fc0333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5fc038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5fc0333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5fc031b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560f8b8a424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560f8b8a4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560f8b888f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560f8b538176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560f8b537e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5fc031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5fc031d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5fc031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560f8b537d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c (2104 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(targe # | ... # `---data was truncated (10240/53734) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005594e466b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005594e4668515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005594e466bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f21d4d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f21d4d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f21d4d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f21d4d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005594e460124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005594e4601096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005594e45e5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005594e4295176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005594e4294e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f21d4d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f21d4d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f21d4d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005594e4294d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c (2105 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", # | ... # `---data was truncated (10240/80648) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055860f7c557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055860f7c2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055860f7c5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa709449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa7094a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa709449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa709431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055860f75b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055860f75b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055860f73ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055860f3ef176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055860f3eee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa709432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa7094330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa7094330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055860f3eed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c (2106 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff # | ... # `---data was truncated (10240/54702) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f24f19657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f24f193515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f24f196cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f88a3849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f88a38a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f88a3849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f88a3831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f24f12c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f24f12c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f24f110f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f24edc0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f24edbfe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f88a3832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f88a38330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f88a38330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f24edbfd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c (2107 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8mf8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16m2 # | ... # `---data was truncated (10240/94673) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055859786c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558597869515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055859786ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f34f3a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f34f3aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f34f3a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f34f3a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055859780224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558597802096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005585977e6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558597496176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558597495e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f34f3a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f34f3a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f34f3a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558597495d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c (2108 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf4_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f16.nxv1f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f16.nxv1f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf2_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f16.nxv2f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f16.nxv2f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_loca # | ... # `---data was truncated (10240/18587) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055737050557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557370502515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557370505cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0d6ed05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0d6ed5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0d6ed05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0d6eced507 abort ./stdlib/abort.c:85:3 # | #7 0x000055737049b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055737049b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055737047ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055737012f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055737012ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0d6eceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0d6ecef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0d6ecef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055737012ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c (2109 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_i8mf4x5(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055704cb7557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055704cb72515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055704cb75cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc474a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc474a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc474a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc474a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055704cb0b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055704cb0b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055704caeff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055704c79f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055704c79ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc474a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc474a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc474a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055704c79ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c (2110 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16mf4x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16mf4x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16mf4x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_ # | ... # `---data was truncated (10240/10396) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563e5d42057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563e5d41d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563e5d420cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8c06649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8c066a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8c06649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8c06631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563e5d3b624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563e5d3b6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563e5d39af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563e5d04a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563e5d049e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8c06632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8c066330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8c066330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563e5d049d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c (2111 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %o # | ... # `---data was truncated (10240/29054) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563b6438d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563b6438a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563b6438dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f27f0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f27f08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f27f0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f27f0831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563b6432324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563b64323096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563b64307f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563b63fb7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563b63fb6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f27f0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f27f08330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f27f08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563b63fb6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c (2112 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv1i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv2i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv4i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv8i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv16i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv32i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv64i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf8_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf4_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf2_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64( %1, ptr %2, %0, # | ... # `---data was truncated (10240/29451) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055facde6757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055facde64515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055facde67cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2493b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2493b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2493b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2493b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055facddfd24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055facddfd096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055facdde1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055facda91176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055facda90e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2493b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2493b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2493b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055facda90d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c (2113 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv64i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv64i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv32i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv32i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv16i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv16i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv8i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv8i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv4i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv4i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv2i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv2i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv1i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv1i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbf.mask.nxv64i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbf.mask.nxv32i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbf.mask.nxv16i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbf.mask.nxv8i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b16_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbf.mask.nxv4i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback n # | ... # `---data was truncated (10240/13031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005640081c457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005640081c1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005640081c4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f729ae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f729aea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f729ae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f729ae31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056400815a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056400815a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056400813ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564007dee176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564007dede93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f729ae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f729ae330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f729ae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564007dedd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c (2114 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f32m2x2(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c (2115 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m4_tu( %maskedoff, %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c (2116 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005608f016257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005608f015f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005608f0162cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faf42e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faf42ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faf42e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faf42e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005608f00f824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005608f00f8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005608f00dcf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005608efd8c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005608efd8be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007faf42e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faf42e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faf42e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005608efd8bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c (2117 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range( # | ... # `---data was truncated (10240/12227) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c0753e457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c0753e1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c0753e4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff3be449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff3be4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff3be449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff3be431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c07537a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c07537a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c07535ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c07500e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c07500de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff3be432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff3be4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff3be4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c07500dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c (2118 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32mf2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m1_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m4_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f3 # | ... # `---data was truncated (10240/179503) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005612f896757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005612f8964515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005612f8967cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fda62449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fda624a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fda62449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fda62431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005612f88fd24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005612f88fd096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005612f88e1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005612f8591176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005612f8590e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fda62432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fda624330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fda624330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005612f8590d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c (2119 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/296943) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056199a0e457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056199a0e1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056199a0e4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6b50d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6b50d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6b50d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6b50d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056199a07a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056199a07a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056199a05ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561999d0e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561999d0de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6b50d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6b50d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6b50d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561999d0dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c (2120 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/82983) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055791072857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557910725515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557910728cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8ca5e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8ca5ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8ca5e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8ca5e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005579106be24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005579106be096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005579106a2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557910352176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557910351e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8ca5e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8ca5e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8ca5e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557910351d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c (2121 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv1i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv2i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv4i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv8i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv16i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv32i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv64i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv1i16.i16.i64( poison, %0, i16 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv2i16.i16.i64( poison, %0, i16 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv4i16.i16.i64( poison, %0, i16 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv8i16.i16.i64( poison, %0, i16 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv16i16.i16.i64( poison, %0, i16 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv16i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c (2122 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005634ffce957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005634ffce6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005634ffce9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6ac2733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6ac278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6ac2733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6ac271b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005634ffc7f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005634ffc7f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005634ffc63f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005634ff913176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005634ff912e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6ac271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6ac271d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6ac271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005634ff912d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c (2123 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a9b223a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a9b2237515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a9b223acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f331f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f331f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f331f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f331f31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a9b21d024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a9b21d0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a9b21b4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a9b1e64176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a9b1e63e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f331f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f331f31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f331f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a9b1e63d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c (2124 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", # | ... # `---data was truncated (10240/19492) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055958401357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559584010515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559584013cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f67e9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f67e9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f67e9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f67e9f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559583fa924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559583fa9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559583f8df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559583c3d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559583c3ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f67e9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f67e9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f67e9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559583c3cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c (2125 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | # | ... # `---data was truncated (10240/222475) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055be4a1c657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055be4a1c3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055be4a1c6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f508d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f508d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f508d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f508d631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055be4a15c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055be4a15c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055be4a140f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055be49df0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055be49defe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f508d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f508d6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f508d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055be49defd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c (2126 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_u16mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_u16mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_u16m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16mf4x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.v # | ... # `---data was truncated (10240/20439) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d00f55857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d00f555515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d00f558cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2d9fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2d9fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2d9fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2d9fc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d00f4ee24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d00f4ee096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d00f4d2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d00f182176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d00f181e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2d9fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2d9fc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2d9fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d00f181d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c (2127 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_i8mf8x7 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055edda88f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055edda88c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055edda88fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdb43b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdb43b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdb43b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdb43b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055edda82524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055edda825096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055edda809f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055edda4b9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055edda4b8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fdb43b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdb43b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdb43b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055edda4b8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c (2128 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv1bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv2bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv4bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv8bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv16bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv32bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv32bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.mask.nxv1bf16.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.mask.nxv2bf16.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.mask.nxv4bf16.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.mask.nxv8bf16.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, ali # | ... # `---data was truncated (10240/12688) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560c2dda657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560c2dda3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560c2dda6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe51f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe51f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe51f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe51f91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560c2dd3c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560c2dd3c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560c2dd20f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560c2d9d0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560c2d9cfe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe51f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe51f91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe51f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560c2d9cfd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c (2129 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_u16mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | ent # | ... # `---data was truncated (10240/31706) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f1d50d257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f1d50cf515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f1d50d2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fef9061bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fef906725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fef9061ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fef90603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f1d506824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f1d5068096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f1d504cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f1d4cfc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f1d4cfbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fef90604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fef906050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fef906050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f1d4cfbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c (2130 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf8_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf4_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf2_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m1_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m2_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m4_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m8_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u16mf4_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync # | ... # `---data was truncated (10240/62063) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562edfe4457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562edfe41515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562edfe44cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f222b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f222b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f222b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f222b11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562edfdda24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562edfdda096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562edfdbef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562edfa6e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562edfa6de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f222b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f222b11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f222b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562edfa6dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c (2131 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16mf4( %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv1bf16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv1bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16mf2( %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv2bf16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv2bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16m1( %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv4bf16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv4bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16m2( %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv8bf16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv8bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16m4( %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrga # | ... # `---data was truncated (10240/28435) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005569ea44757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005569ea444515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005569ea447cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4e9fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4e9faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4e9fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4e9fa31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005569ea3dd24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005569ea3dd096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005569ea3c1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005569ea071176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005569ea070e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4e9fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4e9fa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4e9fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005569ea070d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c (2132 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f32m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f64m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f64.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret voi # | ... # `---data was truncated (10240/102304) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f8e747d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f8e747a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f8e747dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fae3da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fae3daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fae3da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fae3da31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f8e741324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f8e7413096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f8e73f7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f8e70a7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f8e70a6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fae3da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fae3da330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fae3da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f8e70a6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/distributed-thin-lto/objc-contract-pass.ll (2133 of 27911) ******************** TEST 'Clang :: CodeGen/distributed-thin-lto/objc-contract-pass.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/objc-contract-pass.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/objc-contract-pass.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/objc-contract-pass.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/objc-contract-pass.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/objc-contract-pass.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/objc-contract-pass.ll # | #0 0x0000563296bfb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563296bf8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563296bfbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3dd921bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3dd92725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3dd921ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3dd9203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563296b9124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563296b91096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563296b75f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563296825176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563296824e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3dd9204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3dd92050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3dd92050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563296824d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c (2134 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_u16mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_u16mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_u16m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, pt # | ... # `---data was truncated (10240/24016) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b34cded57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b34cdea515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b34cdedcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7ae5933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7ae598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7ae5933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7ae591b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b34cd8324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b34cd83096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b34cd67f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b34ca17176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b34ca16e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7ae591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7ae591d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7ae591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b34ca16d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c (2135 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ... # `---data was truncated (10240/34438) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005555bc18d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005555bc18a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005555bc18dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f19d6849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f19d68a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f19d6849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f19d6831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005555bc12324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005555bc123096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005555bc107f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005555bbdb7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005555bbdb6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f19d6832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f19d68330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f19d68330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005555bbdb6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c (2136 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f64m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tu # | ... # `---data was truncated (10240/99186) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ee5a8a557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ee5a8a2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ee5a8a5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5592c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5592ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5592c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5592c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ee5a83b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ee5a83b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ee5a81ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ee5a4cf176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ee5a4cee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5592c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5592c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5592c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ee5a4ced81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c (2137 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m1_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv4bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv8bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv8bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv16bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv16bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m8_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv32bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv32bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e7b0c7657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e7b0c73515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e7b0c76cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0f00e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0f00ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0f00e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0f00e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e7b0c0c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e7b0c0c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e7b0bf0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e7b08a0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e7b089fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0f00e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0f00e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0f00e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e7b089fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c (2138 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005560c83db57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005560c83d8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005560c83dbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fddad133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fddad18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fddad133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fddad11b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005560c837124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005560c8371096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005560c8355f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005560c8005176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005560c8004e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fddad11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fddad11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fddad11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005560c8004d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c (2139 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16mf4_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv1bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv1bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16mf2_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv2bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv2bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m1_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv4bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv4bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m2_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv8bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv8bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m4_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv16bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv16bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m8_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv32bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv32bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16mf4_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.s.f.nxv1bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv1bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16mf2_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.s.f.nxv2bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv2bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16m1_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.s.f.nxv4bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv4bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16m2_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.s.f.nxv8bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv8bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16m4_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff. # | ... # `---data was truncated (10240/12648) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055da20cd257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055da20ccf515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055da20cd2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7479049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f74790a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7479049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7479031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055da20c6824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055da20c68096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055da20c4cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055da208fc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055da208fbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7479032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f74790330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f74790330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055da208fbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c (2140 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = al # | ... # `---data was truncated (10240/97675) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556b89b6257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556b89b5f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556b89b62cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f47ab333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f47ab38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f47ab333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f47ab31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556b89af824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556b89af8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556b89adcf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556b8978c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556b8978be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f47ab31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f47ab31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f47ab31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556b8978bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp (2141 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | %class.anon = type { i8 } # | # | $_Z15template_functyIiET_S0_ = comdat any # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local i32 @streaming_caller() #0 { # | entry: # | %call = call i32 @normal_callee() # | ret i32 %call # | } # | # | declare i32 @normal_callee() #1 # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local i32 @streaming_callee() #0 { # | entry: # | %call = call i32 @streaming_decl() #15 # | ret i32 %call # | } # | # | declare i32 @streaming_decl() #2 # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @streaming_compatible_caller() #3 { # | entry: # | %call = call i32 @normal_callee() # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @streaming_compatible_callee() #3 { # | entry: # | %call = call i32 @streaming_compatible_decl() #16 # | ret i32 %call # | } # | # | declare i32 @streaming_compatible_decl() #4 # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local i32 @locally_streaming_caller() #5 { # | entry: # | %call = call i32 @normal_callee() # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local i32 @locally_streaming_callee() #5 { # | entry: # | %call = call i32 @locally_streaming_caller() #17 # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @shared_za_caller() #6 { # | entry: # | %call = call i32 @normal_callee() # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @shared_za_callee() #6 { # | entry: # | %call = call i32 @shared_za_decl() #18 # | ret i32 %call # | } # | # | declare i32 @shared_za_decl() #7 # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @preserves_za_caller() #8 { # | entry: # | %call = call i32 @normal_callee() # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @preserves_za_callee() #8 { # | entry: # | %call = call i32 @preserves_za_decl() #19 # | ret i32 %call # | } # | # | declare i32 @preserves_za_decl() #9 # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @new_za_caller() #10 { # | entry: # | %call = call i32 @normal_callee() # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @new_za_callee() #10 { # | entry: # | %call = call i32 @private_za_decl() # | ret i32 %call # | } # | # | declare i32 @private_za_decl() #1 # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @agnostic_za_caller() #11 { # | entry: # | %call = call i32 @normal_callee() # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @agnostic_za_callee() #12 { # | entry: # | %call = call i32 @agnostic_za_decl() #20 # | ret i32 %call # | } # | # | declare i32 @agnostic_za_decl() #13 # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @agnostic_za_callee_live_za() #6 { # | entry: # | %call = call i32 @agnostic_za_decl() #20 # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @test_streaming_ptrty(ptr noundef %f, i32 noundef %x, i32 noundef %y) #12 { # | entry: # | %f.addr = alloca ptr, align 8 # | %x.addr = alloca i32, align 4 # | %y.addr = alloca i32, align 4 # | store ptr %f, ptr %f.addr, align 8 # | store i32 %x, ptr %x.addr, align 4 # | store i32 %y, ptr %y.addr, align 4 # | %0 = load ptr, ptr %f.addr, align 8 # | %1 = load i32, ptr %x.addr, align 4 # | %2 = load i32, ptr %y.addr, align 4 # | call void %0(i32 noundef %1, i32 noundef %2) #15 # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @test_streaming_compatible_ptrty(ptr noundef %f, i32 noundef %x, i32 noundef %y) #12 { # | entry: # | %f.addr = alloca ptr, align 8 # | %x.addr = alloca i32, align 4 # | %y.addr = alloca i32, align 4 # | store ptr %f, ptr %f.addr, align 8 # | store i32 %x, ptr %x.addr, align 4 # | store i32 %y, ptr %y.addr, align 4 # | %0 = load ptr, ptr %f.addr, align 8 # | %1 = load i32, ptr %x.addr, align 4 # | %2 = load i32, ptr %y.addr, align 4 # | call void %0(i32 noundef %1, i32 noundef %2) #16 # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @test_shared_za(ptr noundef %f, i32 noundef %x, i32 noundef %y) #6 { # | entry: # | %f.addr = alloca ptr, align 8 # | %x.addr = alloca i32, align 4 # | %y.addr = alloca i32, align 4 # | store ptr %f, ptr %f.addr, align 8 # | store i32 %x, ptr %x.addr, align 4 # | store i32 %y, ptr %y.addr, align 4 # | %0 = load ptr, ptr %f.addr, align 8 # | %1 = load i32, ptr %x.addr, align 4 # | %2 = load i32, ptr %y.addr, align 4 # | call void %0(i32 noundef %1, i32 noundef %2) #18 # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @test_preserved_za(ptr noundef %f, i32 noundef %x, i32 noundef %y) #6 { # | entry: # | %f.addr = alloca ptr, align 8 # | %x.addr = alloca i32, align 4 # | %y.addr = alloca i32, align 4 # | store ptr %f, ptr %f.addr, align 8 # | store i32 %x, ptr %x.addr, align 4 # | store i32 %y, ptr %y.addr, align 4 # | %0 = load ptr, ptr %f.addr, align 8 # | %1 = load i32, ptr %x.addr, align 4 # | %2 = load i32, ptr %y.addr, align 4 # | call void %0(i32 noundef %1, i32 noundef %2) #19 # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @test_indirect_streaming_ptrty(ptr noundef %fptr, i32 noundef %x, i32 noundef %y) #12 { # | entry: # | %fptr.addr = alloca ptr, align 8 # | %x.addr = alloca i32, align 4 # | %y.addr = alloca i32, align 4 # | store ptr %fptr, ptr %fptr.addr, align 8 # | store i32 %x, ptr %x.addr, align 4 # | store i32 %y, ptr %y.addr, align 4 # | %0 = load ptr, ptr %fptr.addr, align 8 # | %1 = load ptr, ptr %0, align 8 # | %2 = load ptr, ptr %1, align 8 # | %3 = load i32, ptr %x.addr, align 4 # | %4 = load i32, ptr %y.addr, align 4 # | call void %2(i32 noundef %3, i32 noundef %4) #15 # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @_Z24test_same_type_streamingv() #12 { # | entry: # | call void @_Z10streaming1v() #15 # | call void @_Z10streaming2v() #15 # | call void @_Z20same_type_streaming1v() #15 # | call void @_Z20same_type_streaming2v() #15 # | ret void # | } # | # | declare void @_Z10streaming1v() #2 # | # | declare void @_Z10streaming2v() #2 # | # | declare void @_Z20same_type_streaming1v() #2 # | # | declare void @_Z20same_type_streaming2v() #2 # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local noundef i32 @_Z12overloadedfni(i32 noundef %x) #0 { # | entry: # | %x.addr = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | ret i32 %0 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local noundef float @_Z12overloadedfnf(float noundef %x) #12 { # | entry: # | %x.addr = alloca float, align 4 # | store float %x, ptr %x.addr, align 4 # | %0 = load float, ptr %x.addr, align 4 # | ret float %0 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local noundef i32 @_Z13test_overloadi(i32 noundef %x) #12 { # | entry: # | %x.addr = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %call = call noundef i32 @_Z12overloadedfni(i32 noundef %0) #15 # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local noundef float @_Z13test_overloadf(float noundef %x) #12 { # | entry: # | %x.addr = alloca float, align 4 # | store float %x, ptr %x.addr, align 4 # | %0 = load float, ptr %x.addr, align 4 # | %call = call noundef float @_Z12overloadedfnf(float noundef %0) # | ret float %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local noundef i32 @_Z11test_lambdai(i32 noundef %x) #12 { # | entry: # | %x.addr = alloca i32, align 4 # | %F = alloca %class.anon, align 1 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %call = call noundef i32 @"_ZZ11test_lambdaiENK3$_0clEi"(ptr noundef nonnull align 1 dereferenceable(1) %F, i32 noundef %0) #15 # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define internal noundef i32 @"_ZZ11test_lambdaiENK3$_0clEi"(ptr noundef nonnull align 1 dereferenceable(1) %this, i32 noundef %x) #0 { # | entry: # | %this.addr = alloca ptr, align 8 # | %x.addr = alloca i32, align 4 # | store ptr %this, ptr %this.addr, align 8 # | store i32 %x, ptr %x.addr, align 4 # | %this1 = load ptr, ptr %this.addr, align 8 # | %0 = load i32, ptr %x.addr, align 4 # | ret i32 %0 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local noundef i32 @_Z27test_template_instantiationv() #12 { # | entry: # | %call = call noundef i32 @_Z15template_functyIiET_S0_(i32 noundef 12) #15 # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define linkonce_odr noundef i32 @_Z15template_functyIiET_S0_(i32 noundef %x) #0 comdat { # | entry: # | %x.addr = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | ret i32 %0 # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local void @_Z25locally_streaming_inheritv() #5 { # | entry: # | %call = call i32 @streaming_decl() #15 # | ret void # | } # | # | ; Function Attrs: alwaysinline mustprogress nounwind # | define dso_local noundef i32 @_Z4callv() #14 { # | entry: # | ret i32 0 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local noundef i32 @_Z22test_variadic_templatev() #6 { # | entry: # | %f.addr.i16 = alloca ptr, align 8 # | %f.addr.i12 = alloca ptr, align 8 # | %other.addr.i13 = alloca ptr, align 8 # | %f.addr.i7 = alloca ptr, align 8 # | %other.addr.i8 = alloca ptr, align 8 # | %other.addr2.i9 = alloca ptr, align 8 # | %f.addr.i1 = alloca ptr, align 8 # | %other.addr.i2 = alloca ptr, align 8 # | %other.addr2.i3 = alloca ptr, align 8 # | %other.addr4.i4 = alloca ptr, align 8 # | %f.addr.i = alloca ptr, align 8 # | %other.addr.i = alloca ptr, align 8 # | %other.addr2.i = alloca ptr, align 8 # | %other.addr4.i = alloca ptr, align 8 # | %other.addr6.i = alloca ptr, align 8 # | store ptr @normal_callee, ptr %f.addr.i, align 8 # | store ptr @streaming_decl, ptr %other.addr.i, align 8 # | store ptr @streaming_compatible_decl # | ... # `---data was truncated (10240/15241) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559b2689357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559b26890515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559b26893cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f89a0733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f89a078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f89a0733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f89a071b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559b2682924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559b26829096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559b2680df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559b264bd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559b264bce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f89a071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f89a071d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f89a071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559b264bcd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline # | #0 0x000055bf6d31557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bf6d312515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bf6d315cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa444049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa4440a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa444049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa444031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bf6d2ab24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bf6d2ab096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bf6d28ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bf6cf3f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bf6cf3ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa444032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa4440330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa4440330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bf6cf3ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c (2142 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056418fb4257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056418fb3f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056418fb42cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa3bbf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa3bbf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa3bbf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa3bbf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056418fad824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056418fad8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056418fabcf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056418f76c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056418f76be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa3bbf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa3bbf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa3bbf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056418f76bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c (2143 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.r # | ... # `---data was truncated (10240/65582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555811b2d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555811b2a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555811b2dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f831ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f831eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f831ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f831ea31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555811ac324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555811ac3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555811aa7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555811757176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555811756e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f831ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f831ea330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f831ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555811756d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c (2144 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv8i8.nxv8f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function # | ... # `---data was truncated (10240/12439) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005578272a357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005578272a0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005578272a3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb55bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb55bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb55bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb55bb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055782723924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557827239096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055782721df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557826ecd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557826ecce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb55bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb55bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb55bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557826eccd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c (2145 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m1( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m8( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf4_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf2_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m1_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.mask.nxv4f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.mask.nxv4f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m2_m( %mask, %op1, fl # | ... # `---data was truncated (10240/25099) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560d2f0bd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560d2f0ba515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560d2f0bdcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7ecb733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7ecb78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7ecb733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7ecb71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560d2f05324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560d2f053096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560d2f037f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560d2ece7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560d2ece6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7ecb71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7ecb71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7ecb71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560d2ece6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c (2146 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c (2147 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m1_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c (2148 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_ # | ... # `---data was truncated (10240/63061) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555bd551357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555bd5510515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555bd5513cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4029533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f402958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4029533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f402951b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555bd54a924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555bd54a9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555bd548df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555bd513d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555bd513ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f402951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f402951d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f402951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555bd513cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c (2149 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16mf4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16mf2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m1_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m8_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f32mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f32m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | # | ... # `---data was truncated (10240/81304) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a0a436257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a0a435f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a0a4362cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f310e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f310e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f310e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f310e431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a0a42f824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a0a42f8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a0a42dcf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a0a3f8c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a0a3f8be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f310e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f310e4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f310e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a0a3f8bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c (2150 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_u_u_w4_u8m8_u8m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.u.u.i64.nxv64i8.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.u.u.i64.nxv64i8.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555dd30e757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555dd30e4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555dd30e7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff4e0649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff4e06a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff4e0649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff4e0631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555dd307d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555dd307d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555dd3061f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555dd2d11176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555dd2d10e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff4e0632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff4e06330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff4e06330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555dd2d10d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c (2151 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv1f64.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv2f64.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv4f64.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv8f64.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv1i64.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv2i64.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv4i64.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4i64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv8i64.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8i64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_u64m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv1i64.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_u64m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv2i64.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs # | ... # `---data was truncated (10240/26996) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561f5eae757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561f5eae4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561f5eae7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f89a4a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f89a4aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f89a4a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f89a4a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561f5ea7d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561f5ea7d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561f5ea61f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561f5e711176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561f5e710e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f89a4a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f89a4a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f89a4a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561f5e710d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c (2152 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf8_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf4_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf2_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m1_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m2_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv16i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m4_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv32i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m8_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv64i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16mf4_tu( %maskedoff, %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i16, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv1i16.i16.i64( %0, %1, i16 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16mf2_tu( %maskedoff, %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, # | ... # `---data was truncated (10240/211231) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056050747c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560507479515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056050747ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f684a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f684a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f684a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f684a231507 abort ./stdlib/abort.c:85:3 # | #7 0x000056050741224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560507412096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005605073f6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005605070a6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005605070a5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f684a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f684a2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f684a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005605070a5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c (2153 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind w # | ... # `---data was truncated (10240/20198) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f95eb8757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f95eb84515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f95eb87cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0810449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f08104a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0810449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0810431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f95eb1d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f95eb1d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f95eb01f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f95e7b1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f95e7b0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0810432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f08104330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f08104330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f95e7b0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c (2154 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv8i8.nxv8i8.i64(, , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c (2155 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv8bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | # | ... # `---data was truncated (10240/12381) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cb5abf857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cb5abf5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cb5abf8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcb87f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcb87f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcb87f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcb87f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cb5ab8e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cb5ab8e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cb5ab72f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cb5a822176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cb5a821e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcb87f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcb87f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcb87f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cb5a821d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c (2156 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m4_tu( %maskedoff, # | ... # `---data was truncated (10240/157475) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d45c49257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d45c48f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d45c492cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2aec933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2aec98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2aec933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2aec91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d45c42824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d45c428096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d45c40cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d45c0bc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d45c0bbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2aec91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2aec91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2aec91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d45c0bbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c (2157 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056440f64557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056440f642515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056440f645cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1e5cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1e5cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1e5cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1e5cb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056440f5db24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056440f5db096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056440f5bff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056440f26f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056440f26ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1e5cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1e5cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1e5cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056440f26ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c (2158 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_lo # | ... # `---data was truncated (10240/70863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055687f49957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055687f496515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055687f499cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe0e1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe0e178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe0e1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe0e171b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055687f42f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055687f42f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055687f413f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055687f0c3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055687f0c2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe0e171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe0e171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe0e171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055687f0c2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm64_vdupq_n_f64.c (2159 of 27911) ******************** TEST 'Clang :: CodeGen/arm64_vdupq_n_f64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c" # | target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-apple-ios7" # | # | ; Function Attrs: noinline nounwind # | define <2 x double> @test_vdupq_n_f64(double noundef %w) #0 { # | entry: # | %__p0.addr.i = alloca double, align 8 # | %__ret.i = alloca <2 x double>, align 16 # | %.compoundliteral.i = alloca <2 x double>, align 16 # | %w.addr = alloca double, align 8 # | store double %w, ptr %w.addr, align 8 # | %0 = load double, ptr %w.addr, align 8 # | store double %0, ptr %__p0.addr.i, align 8 # | %1 = load double, ptr %__p0.addr.i, align 8 # | %vecinit.i = insertelement <2 x double> poison, double %1, i32 0 # | %2 = load double, ptr %__p0.addr.i, align 8 # | %vecinit1.i = insertelement <2 x double> %vecinit.i, double %2, i32 1 # | store <2 x double> %vecinit1.i, ptr %.compoundliteral.i, align 16 # | %3 = load <2 x double>, ptr %.compoundliteral.i, align 16 # | store <2 x double> %3, ptr %__ret.i, align 16 # | %4 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define <4 x float> @test_vdupq_n_f32(float noundef %w) #0 { # | entry: # | %__p0.addr.i = alloca float, align 4 # | %__ret.i = alloca <4 x float>, align 16 # | %.compoundliteral.i = alloca <4 x float>, align 16 # | %w.addr = alloca float, align 4 # | store float %w, ptr %w.addr, align 4 # | %0 = load float, ptr %w.addr, align 4 # | store float %0, ptr %__p0.addr.i, align 4 # | %1 = load float, ptr %__p0.addr.i, align 4 # | %vecinit.i = insertelement <4 x float> poison, float %1, i32 0 # | %2 = load float, ptr %__p0.addr.i, align 4 # | %vecinit1.i = insertelement <4 x float> %vecinit.i, float %2, i32 1 # | %3 = load float, ptr %__p0.addr.i, align 4 # | %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %3, i32 2 # | %4 = load float, ptr %__p0.addr.i, align 4 # | %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %4, i32 3 # | store <4 x float> %vecinit3.i, ptr %.compoundliteral.i, align 16 # | %5 = load <4 x float>, ptr %.compoundliteral.i, align 16 # | store <4 x float> %5, ptr %__ret.i, align 16 # | %6 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define <2 x double> @test_vdupq_lane_f64(<1 x double> noundef %V) #0 { # | entry: # | %V.addr = alloca <1 x double>, align 8 # | %__ret_379 = alloca <2 x double>, align 16 # | %__s0_379 = alloca <1 x double>, align 8 # | %__ret = alloca <2 x double>, align 16 # | %__s0 = alloca <1 x double>, align 8 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <2 x double>, align 16 # | %tmp1 = alloca <2 x double>, align 16 # | store <1 x double> %V, ptr %V.addr, align 8 # | %0 = load <1 x double>, ptr %V.addr, align 8 # | store <1 x double> %0, ptr %__s0_379, align 8 # | %1 = load <1 x double>, ptr %__s0_379, align 8 # | store <1 x double> %1, ptr %__s0, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = bitcast <8 x i8> %2 to <1 x double> # | %lane = shufflevector <1 x double> %3, <1 x double> %3, <2 x i32> zeroinitializer # | store <2 x double> %lane, ptr %ref.tmp, align 16 # | %4 = load <2 x double>, ptr %ref.tmp, align 16 # | store <2 x double> %4, ptr %__ret, align 16 # | %5 = load <2 x double>, ptr %__ret, align 16 # | store <2 x double> %5, ptr %tmp, align 16 # | %6 = load <2 x double>, ptr %tmp, align 16 # | store <2 x double> %6, ptr %__ret_379, align 16 # | %7 = load <2 x double>, ptr %__ret_379, align 16 # | store <2 x double> %7, ptr %tmp1, align 16 # | %8 = load <2 x double>, ptr %tmp1, align 16 # | ret <2 x double> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define <2 x double> @test_vmovq_n_f64(double noundef %w) #0 { # | entry: # | %__p0.addr.i = alloca double, align 8 # | %__ret.i = alloca <2 x double>, align 16 # | %.compoundliteral.i = alloca <2 x double>, align 16 # | %w.addr = alloca double, align 8 # | store double %w, ptr %w.addr, align 8 # | %0 = load double, ptr %w.addr, align 8 # | store double %0, ptr %__p0.addr.i, align 8 # | %1 = load double, ptr %__p0.addr.i, align 8 # | %vecinit.i = insertelement <2 x double> poison, double %1, i32 0 # | %2 = load double, ptr %__p0.addr.i, align 8 # | %vecinit1.i = insertelement <2 x double> %vecinit.i, double %2, i32 1 # | store <2 x double> %vecinit1.i, ptr %.compoundliteral.i, align 16 # | %3 = load <2 x double>, ptr %.compoundliteral.i, align 16 # | store <2 x double> %3, ptr %__ret.i, align 16 # | %4 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define <4 x half> @test_vmov_n_f16(ptr noundef %a1) #0 { # | entry: # | %a1.addr = alloca ptr, align 8 # | %__ret = alloca <4 x half>, align 8 # | %__s0 = alloca half, align 2 # | %.compoundliteral = alloca <4 x half>, align 8 # | %tmp = alloca <4 x half>, align 8 # | store ptr %a1, ptr %a1.addr, align 8 # | %0 = load ptr, ptr %a1.addr, align 8 # | %1 = load half, ptr %0, align 2 # | store half %1, ptr %__s0, align 2 # | %2 = load half, ptr %__s0, align 2 # | %vecinit = insertelement <4 x half> poison, half %2, i32 0 # | %3 = load half, ptr %__s0, align 2 # | %vecinit1 = insertelement <4 x half> %vecinit, half %3, i32 1 # | %4 = load half, ptr %__s0, align 2 # | %vecinit2 = insertelement <4 x half> %vecinit1, half %4, i32 2 # | %5 = load half, ptr %__s0, align 2 # | %vecinit3 = insertelement <4 x half> %vecinit2, half %5, i32 3 # | store <4 x half> %vecinit3, ptr %.compoundliteral, align 8 # | %6 = load <4 x half>, ptr %.compoundliteral, align 8 # | store <4 x half> %6, ptr %__ret, align 8 # | %7 = load <4 x half>, ptr %__ret, align 8 # | store <4 x half> %7, ptr %tmp, align 8 # | %8 = load <4 x half>, ptr %tmp, align 8 # | ret <4 x half> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x half> @test_vmovq_n_f16(ptr noundef %a1) #0 { # | entry: # | %a1.addr = alloca ptr, align 8 # | %__ret = alloca <8 x half>, align 16 # | %__s0 = alloca half, align 2 # | %.compoundliteral = alloca <8 x half>, align 16 # | %tmp = alloca <8 x half>, align 16 # | store ptr %a1, ptr %a1.addr, align 8 # | %0 = load ptr, ptr %a1.addr, align 8 # | %1 = load half, ptr %0, align 2 # | store half %1, ptr %__s0, align 2 # | %2 = load half, ptr %__s0, align 2 # | %vecinit = insertelement <8 x half> poison, half %2, i32 0 # | %3 = load half, ptr %__s0, align 2 # | %vecinit1 = insertelement <8 x half> %vecinit, half %3, i32 1 # | %4 = load half, ptr %__s0, align 2 # | %vecinit2 = insertelement <8 x half> %vecinit1, half %4, i32 2 # | %5 = load half, ptr %__s0, align 2 # | %vecinit3 = insertelement <8 x half> %vecinit2, half %5, i32 3 # | %6 = load half, ptr %__s0, align 2 # | %vecinit4 = insertelement <8 x half> %vecinit3, half %6, i32 4 # | %7 = load half, ptr %__s0, align 2 # | %vecinit5 = insertelement <8 x half> %vecinit4, half %7, i32 5 # | %8 = load half, ptr %__s0, align 2 # | %vecinit6 = insertelement <8 x half> %vecinit5, half %8, i32 6 # | %9 = load half, ptr %__s0, align 2 # | %vecinit7 = insertelement <8 x half> %vecinit6, half %9, i32 7 # | store <8 x half> %vecinit7, ptr %.compoundliteral, align 16 # | %10 = load <8 x half>, ptr %.compoundliteral, align 16 # | store <8 x half> %10, ptr %__ret, align 16 # | %11 = load <8 x half>, ptr %__ret, align 16 # | store <8 x half> %11, ptr %tmp, align 16 # | %12 = load <8 x half>, ptr %tmp, align 16 # | ret <8 x half> %12 # | } # | # | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055f6e24b057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f6e24ad515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f6e24b0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f40bf333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f40bf38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f40bf333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f40bf31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f6e244624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f6e2446096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f6e242af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f6e20da176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f6e20d9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f40bf31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f40bf31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f40bf31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f6e20d9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c (2160 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16mf4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16mf2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m1_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m8_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f32mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f32m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | # | ... # `---data was truncated (10240/81304) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dd7e3d657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055dd7e3d3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055dd7e3d6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fca34133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fca3418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fca34133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fca3411b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dd7e36c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055dd7e36c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055dd7e350f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055dd7e000176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055dd7dfffe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fca3411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fca3411d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fca3411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dd7dfffd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c (2161 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_u16mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | ent # | ... # `---data was truncated (10240/31706) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560b7341157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560b7340e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560b73411cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd418933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd41898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd418933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd41891b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560b733a724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560b733a7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560b7338bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560b7303b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560b7303ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd41891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd41891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd41891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560b7303ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c (2162 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c (2163 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv1bf16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv2bf16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m1_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv4bf16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv4bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv8bf16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv8bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv16bf16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv16bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv32bf16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv32bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005558b9b7157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005558b9b6e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005558b9b71cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa9d3449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa9d34a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa9d3449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa9d3431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005558b9b0724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005558b9b07096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005558b9aebf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005558b979b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005558b979ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa9d3432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa9d34330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa9d34330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005558b979ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c (2164 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8mf8(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 5) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8mf4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 6) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8mf2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 7) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8m1(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 0) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8m2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8m4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8m8(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16mf4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 6) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16mf2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 7) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16m1(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 0) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16m2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16m4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16m8(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e32mf2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 7) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e32m1(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 0) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e32m2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e32m4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e32m8(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e64m1(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 0) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e64m2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e64m4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e64m8(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 3) # | ret i64 %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bff20ff57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bff20fc515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bff20ffcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdb58533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdb5858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdb58533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdb5851b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bff209524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bff2095096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bff2079f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bff1d29176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bff1d28e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fdb5851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdb5851d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdb5851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bff1d28d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c (2165 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eebd1cc57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055eebd1c9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055eebd1cccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feaa0333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feaa038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feaa0333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feaa031b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eebd16224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055eebd162096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055eebd146f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055eebcdf6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055eebcdf5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007feaa031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feaa031d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feaa031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eebcdf5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c (2166 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055862620457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558626201515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558626204cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe2b4449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe2b44a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe2b4449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe2b4431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055862619a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055862619a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055862617ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558625e2e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558625e2de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe2b4432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe2b44330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe2b44330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558625e2dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c (2167 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16mf4( %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv1bf16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv1bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16mf2( %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv2bf16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv2bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16m1( %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv4bf16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv4bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16m2( %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv8bf16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv8bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16m4( %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx. # | ... # `---data was truncated (10240/28427) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c6b30cd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c6b30ca515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c6b30cdcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fce73f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fce73f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fce73f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fce73eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c6b306324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c6b3063096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c6b3047f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c6b2cf7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c6b2cf6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fce73eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fce73eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fce73eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c6b2cf6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c (2168 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c (2169 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a32bfd457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a32bfd1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a32bfd4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc97e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc97e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc97e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc97e51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a32bf6a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a32bf6a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a32bf4ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a32bbfe176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a32bbfde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc97e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc97e51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc97e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a32bbfdd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c (2170 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_i8mf4x6(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055704ae3957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055704ae36515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055704ae39cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcda7505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcda755c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcda7505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcda74ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055704adcf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055704adcf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055704adb3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055704aa63176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055704aa62e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcda74eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcda74ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcda74ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055704aa62d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c (2171 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_e5m2_e4m3_w4_f8e5m2m8_f8e4m3m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.e5m2.e4m3.i64.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.e5m2.e4m3.i64.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056492e5ce57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056492e5cb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056492e5cecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9a62049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9a620a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9a62049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9a62031507 abort ./stdlib/abort.c:85:3 # | #7 0x000056492e56424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056492e564096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056492e548f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056492e1f8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056492e1f7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9a62032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9a620330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9a620330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056492e1f7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcaddq.c (2172 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcaddq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 0, <16 x i8> %0, <16 x i8> %1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32, i32, <16 x i8>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot90_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 0, <8 x i16> %0, <8 x i16> %1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32, i32, <8 x i16>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot90_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 0, <4 x i32> %0, <4 x i32> %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32, i32, <4 x i32>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 0, <16 x i8> %0, <16 x i8> %1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot90_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 0, <8 x i16> %0, <8 x i16> %1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot90_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 0, <4 x i32> %0, <4 x i32> %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcaddq_rot90_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = call <8 x half> @llvm.arm.mve.vcaddq.v8f16(i32 1, i32 0, <8 x half> %0, <8 x half> %1) # | ret <8 x half> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vcaddq.v8f16(i32, i32, <8 x half>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcaddq_rot90_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = call <4 x float> @llvm.arm.mve.vcaddq.v4f32(i32 1, i32 0, <4 x float> %0, <4 x float> %1) # | ret <4 x float> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.vcaddq.v4f32(i32, i32, <4 x float>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot270_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 1, <16 x i8> %0, <16 x i8> %1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot270_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 1, <8 x i16> %0, <8 x i16> %1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot270_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 1, <4 x i32> %0, <4 x i32> %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot270_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 1, <16 x i8> %0, <16 x i8> %1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot270_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 1, <8 x i16> %0, <8 x i16> %1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot270_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 1, <4 x i32> %0, <4 x i32> %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcaddq_rot270_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = call <8 x half> @llvm.arm.mve.vcaddq.v8f16(i32 1, i32 1, <8 x half> %0, <8 x half> %1) # | ret <8 x half> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcaddq_rot270_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = call <4 x float> @llvm.arm.mve.vcaddq.v4f32(i32 1, i32 1, <4 x float> %0, <4 x float> %1) # | ret <4 x float> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_m_u8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %inactive.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %b.addr, align # | ... # `---data was truncated (10240/39627) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c1c364357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c1c3640515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c1c3643cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2112f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2112f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2112f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2112eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c1c35d924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c1c35d9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c1c35bdf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c1c326d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c1c326ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2112eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2112eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2112eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c1c326cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c (2173 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16mf4( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16mf2( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m1( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv4f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv4f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m2( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv8f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv8f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m4( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv16f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv16f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m8( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv32f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv32f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32mf2( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1f32.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32m1( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2f32.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32m2( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c (2174 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_i8mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/69980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ea87f2257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ea87f1f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ea87f22cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb9a2249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb9a22a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb9a2249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb9a2231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ea87eb824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ea87eb8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ea87e9cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ea87b4c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ea87b4be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb9a2232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb9a22330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb9a22330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ea87b4bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c (2175 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv4 # | ... # `---data was truncated (10240/47636) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056395106d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056395106a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056395106dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f67db849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f67db8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f67db849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f67db831507 abort ./stdlib/abort.c:85:3 # | #7 0x000056395100324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563951003096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563950fe7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563950c97176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563950c96e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f67db832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f67db8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f67db8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563950c96d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c (2176 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = allo # | ... # `---data was truncated (10240/154609) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055583311357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555833110515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555833113cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff167b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff167b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff167b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff167b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005558330a924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005558330a9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055583308df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555832d3d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555832d3ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff167b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff167b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff167b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555832d3cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c (2177 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vln.nxv1i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vln.nxv2i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vln.nxv4i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vln.nxv8i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vln.nxv16i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vln.nxv32i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vln.nxv64i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv8i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv8i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv16i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.ris # | ... # `---data was truncated (10240/12914) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e01ab0f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e01ab0c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e01ab0fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe733c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe733ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe733c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe733c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e01aaa524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e01aaa5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e01aa89f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e01a739176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e01a738e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe733c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe733c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe733c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e01a738d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c (2178 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_i8mf8x5 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561f9422b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561f94228515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561f9422bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f483af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f483af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f483af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f483af1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561f941c124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561f941c1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561f941a5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561f93e55176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561f93e54e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f483af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f483af1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f483af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561f93e54d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c (2179 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f64m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tu # | ... # `---data was truncated (10240/99186) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055aa2994e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055aa2994b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055aa2994ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f81c1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f81c178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f81c1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f81c171b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aa298e424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055aa298e4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055aa298c8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055aa29578176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055aa29577e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f81c171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f81c171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f81c171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aa29577d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c (2180 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32mf2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32mf2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32mf2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0 # | ... # `---data was truncated (10240/10425) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005584f5d6857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005584f5d65515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005584f5d68cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa1d2905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa1d295c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa1d2905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa1d28ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005584f5cfe24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005584f5cfe096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005584f5ce2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005584f5992176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005584f5991e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa1d28eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa1d28ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa1d28ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005584f5991d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbc.c (2181 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbc -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c -check-prefix=RV32ZBC # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbc -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @clmul_32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.clmul.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @clmulh_32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.clmulh.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @clmulr_32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.clmulr.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.clmul.i32(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.clmulh.i32(i32, i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.clmulr.i32(i32, i32) #2 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbc,+zbkc" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_zbc1p0_zbkc1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556def4ce57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556def4cb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556def4cecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6c83649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6c836a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6c83649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6c83631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556def46424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556def464096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556def448f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556def0f8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556def0f7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6c83632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6c836330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6c836330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556def0f7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c -check-prefix=RV32ZBC # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c -check-prefix=RV32ZBC # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c (2182 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f32m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | ... # `---data was truncated (10240/120907) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562c9a1f957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562c9a1f6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562c9a1f9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f76b3d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f76b3d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f76b3d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f76b3d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562c9a18f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562c9a18f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562c9a173f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562c99e23176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562c99e22e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f76b3d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f76b3d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f76b3d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562c99e22d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c (2183 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f64m1x3(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c (2184 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf4_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf2_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m1_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv4bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv4bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m2_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv8bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv8bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m4_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv16bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv16bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m8_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv32bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv32bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslideup.mask.nxv1bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.mask.nxv1bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslideup.mask.nxv2bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.mask.nxv2bf16.i64(, # | ... # `---data was truncated (10240/30635) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056327819e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056327819b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056327819ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5132933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f513298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5132933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f513291b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056327813424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563278134096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563278118f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563277dc8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563277dc7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f513291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f513291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f513291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563277dc7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c (2185 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m4_tu( %maskedoff, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c (2186 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv16i16.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv16i16.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16m4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv16i16.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline n # | ... # `---data was truncated (10240/68255) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555a5f80a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555a5f807515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555a5f80acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc319f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc319f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc319f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc319f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555a5f7a024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555a5f7a0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555a5f784f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555a5f434176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555a5f433e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc319f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc319f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc319f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555a5f433d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c (2187 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_i8mf4x8(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563583f9f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563583f9c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563583f9fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe6f2649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe6f26a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe6f2649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe6f2631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563583f3524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563583f35096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563583f19f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563583bc9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563583bc8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe6f2632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe6f26330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe6f26330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563583bc8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c (2188 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16mf4_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16mf2_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16m1_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16m2_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %v # | ... # `---data was truncated (10240/110062) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557a0ca7657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557a0ca73515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557a0ca76cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f00aa533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f00aa58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f00aa533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f00aa51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557a0ca0c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557a0ca0c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557a0c9f0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557a0c6a0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557a0c69fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f00aa51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f00aa51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f00aa51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557a0c69fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c (2189 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ed36b3d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ed36b3a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ed36b3dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa708333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa70838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa708333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa70831b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ed36ad324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ed36ad3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ed36ab7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ed36767176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ed36766e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa70831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa70831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa70831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ed36766d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqaddq.c (2190 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqaddq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqaddq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %0, <16 x i8> %1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqaddq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %0, <8 x i16> %1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqaddq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %0, <4 x i32> %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqaddq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.qadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.qadd.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqaddq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.qadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.qadd.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqaddq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.qadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.qadd.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqaddq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %0, <16 x i8> %.splat) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqaddq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %0, <8 x i16> %.splat) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqaddq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %0, <4 x i32> %.splat) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqaddq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.qadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqaddq_m_n_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.qadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, i32 1, <8 x i1> %4, <8 # | ... # `---data was truncated (10240/12015) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055932b38257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055932b37f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055932b382cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3646b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3646b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3646b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3646b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055932b31824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055932b318096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055932b2fcf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055932afac176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055932afabe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3646b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3646b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3646b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055932afabd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c (2191 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("ri # | ... # `---data was truncated (10240/47480) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a54a22f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a54a22c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a54a22fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc210f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc210f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc210f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc210f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a54a1c524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a54a1c5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a54a1a9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a549e59176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a549e58e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc210f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc210f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc210f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a549e58d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c (2192 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32mf2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m1( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m4( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c (2193 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_i32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_i32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_u32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_u32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32mf2x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedof # | ... # `---data was truncated (10240/40734) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005624eeb6057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005624eeb5d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005624eeb60cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f553f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f553f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f553f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f553f631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005624eeaf624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005624eeaf6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005624eeadaf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005624ee78a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005624ee789e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f553f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f553f6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f553f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005624ee789d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c (2194 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32mf2x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_i32mf2x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_i32m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_u32mf2x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_u32m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056133573e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056133573b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056133573ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6c80533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6c8058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6c80533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6c8051b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005613356d424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005613356d4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005613356b8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561335368176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561335367e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6c8051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6c8051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6c8051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561335367d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c (2195 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, p # | ... # `---data was truncated (10240/14521) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056002980f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056002980c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056002980fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5035849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f50358a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5035849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5035831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005600297a524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005600297a5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560029789f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560029439176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560029438e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5035832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f50358330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f50358330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560029438d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c (2196 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32mf2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m1( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m4( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f32.f16.nx # | ... # `---data was truncated (10240/90875) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561cc3d7157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561cc3d6e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561cc3d71cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f708fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f708fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f708fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f708fb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561cc3d0724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561cc3d07096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561cc3cebf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561cc399b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561cc399ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f708fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f708fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f708fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561cc399ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c (2197 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv16bf16.nxv16bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c (2198 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_i8mf8x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_i8mf4x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_i8mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_i8m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_i8m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_u8mf8x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_u8mf4x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_u8mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_u8m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_u8m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @ # | ... # `---data was truncated (10240/23479) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558400c9857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558400c95515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558400c98cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffad6449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffad64a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffad6449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffad6431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558400c2e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558400c2e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558400c12f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005584008c2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005584008c1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ffad6432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffad64330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffad64330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005584008c1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c (2199 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv1f16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv2f16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv4f16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv8f16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv8f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define d # | ... # `---data was truncated (10240/25350) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557dcb40357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557dcb400515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557dcb403cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f190a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f190a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f190a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f190a11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557dcb39924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557dcb399096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557dcb37df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557dcb02d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557dcb02ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f190a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f190a11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f190a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557dcb02cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c (2200 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv4i64.nxv1 # | ... # `---data was truncated (10240/47628) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005565fe2b657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005565fe2b3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005565fe2b6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb96b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb96b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb96b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb96b71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005565fe24c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005565fe24c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005565fe230f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005565fdee0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005565fdedfe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb96b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb96b71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb96b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005565fdedfd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c (2201 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c (2202 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_i64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_u64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_f64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 6) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_i64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 6) %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_u64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple # | ... # `---data was truncated (10240/20903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556f02d0657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556f02d03515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556f02d06cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff8f2f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff8f2f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff8f2f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff8f2f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556f02c9c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556f02c9c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556f02c80f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556f02930176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556f0292fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff8f2f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff8f2f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff8f2f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556f0292fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c (2203 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf4x5(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf2x5(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16m1x5(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16m1x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556c8b00a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556c8b007515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556c8b00acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0c90b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0c90b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0c90b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0c90b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556c8afa024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556c8afa0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556c8af84f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556c8ac34176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556c8ac33e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0c90b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0c90b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0c90b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556c8ac33d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c (2204 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv4i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv8i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv8i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv16i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv16i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv32i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv32i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv64i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv64i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv4i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv8i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c (2205 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m1_bf16m2( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv8bf16.nxv4bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m1_bf16m4( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv16bf16.nxv4bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m2_bf16m4( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv16bf16.nxv8bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv8bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m1_bf16m8( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m2_bf16m8( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32bf16.nxv8bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv8bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m4_bf16m8( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32bf16.nxv16bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv16bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vset_v_bf16mf4_bf16mf4x2(target("riscv.vector.tuple", , 2) %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store target("riscv.vector.tuple", , 2) %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load target("riscv.vector.tuple", , 2), ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_2t.nxv1bf16(target("riscv.vector.tuple", , 2) %0, %1, i32 0) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_2t.nxv1bf16(target("riscv.vector.tuple", , 2), , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vset_v_bf16mf4_bf16mf4x3(target("riscv.vector.tuple", , 3) %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store target("riscv.vector.tuple", , 3) %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load target("riscv.vector.tuple", , 3), ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_3t.nxv1bf16(target("riscv.vector.tuple", , 3) %0, %1, i32 0) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_3t.nxv1bf16(target("riscv.vector.tuple", , 3), , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vset_v_bf16mf4_bf16mf4x4(target("riscv.vector.tuple", , 4) %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store target("riscv.vector.tuple", , 4) %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load target("riscv.vector.tuple", , 4), ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/41659) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556caf7a457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556caf7a1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556caf7a4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa574905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa57495c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa574905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa5748ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556caf73a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556caf73a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556caf71ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556caf3ce176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556caf3cde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa5748eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa5748ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa5748ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556caf3cdd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c (2206 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f32m2x2(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c (2207 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005577d7ccc57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005577d7cc9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005577d7ccccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f523d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f523d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f523d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f523d231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005577d7c6224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005577d7c62096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005577d7c46f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005577d78f6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005577d78f5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f523d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f523d2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f523d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005577d78f5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c (2208 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv1i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv2i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv4i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv8i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv16i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eae4d9857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055eae4d95515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055eae4d98cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3941449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f39414a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3941449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3941431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eae4d2e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055eae4d2e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055eae4d12f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055eae49c2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055eae49c1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3941432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f39414330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f39414330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eae49c1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c (2209 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_f64m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_f64m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_i64m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_i64m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_u64m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_u64m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_f64m1x3_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_f64m2x3_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_i64m1x3_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_i64m2x3_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 # | ... # `---data was truncated (10240/14036) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005601212cf57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005601212cc515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005601212cfcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5a83249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5a832a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5a83249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5a83231507 abort ./stdlib/abort.c:85:3 # | #7 0x000056012126524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560121265096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560121249f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560120ef9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560120ef8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5a83232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5a832330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5a832330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560120ef8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c (2210 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e1b957657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e1b9573515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e1b9576cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7500849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f75008a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7500849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7500831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e1b950c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e1b950c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e1b94f0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e1b91a0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e1b919fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7500832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f75008330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f75008330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e1b919fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c (2211 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16mf4_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16mf4_f32mf2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16mf2_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16mf2_f32m1_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16m1_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16m1_f32m2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16m2_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16m2_f32m4_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc. # | ... # `---data was truncated (10240/101402) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055da2776257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055da2775f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055da27762cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fca48a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fca48aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fca48a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fca48a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055da276f824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055da276f8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055da276dcf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055da2738c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055da2738be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fca48a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fca48a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fca48a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055da2738bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c (2212 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c223b9e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c223b9b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c223b9ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2980d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2980d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2980d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2980d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c223b3424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c223b34096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c223b18f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c2237c8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c2237c7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2980d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2980d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2980d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c2237c7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c (2213 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vtdiscard() #0 { # | entry: # | call void @llvm.riscv.sf.vtdiscard() # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtdiscard() #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564c57bf057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564c57bed515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564c57bf0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8435b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8435b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8435b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8435b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564c57b8624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564c57b86096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564c57b6af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564c5781a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564c57819e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8435b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8435b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8435b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564c57819d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c (2214 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16mf4_bf16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16mf2_bf16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16m1_bf16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16m2_bf16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16m4_bf16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16m8_bf16m8( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16mf4_bf16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16mf2_bf16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16m1_bf16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16m2_bf16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16m4_bf16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16m8_bf16m8( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16mf4_i16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16mf2_i16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m1_i16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m2_i16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m4_i16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m8_i16m8( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16mf4_u16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16mf2_u16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m1_u16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m2_u16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m4_u16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c (2215 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align # | ... # `---data was truncated (10240/94379) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005613f6ac157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005613f6abe515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005613f6ac1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fef9b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fef9b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fef9b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fef9b631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005613f6a5724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005613f6a57096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005613f6a3bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005613f66eb176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005613f66eae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fef9b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fef9b6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fef9b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005613f66ead81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c (2216 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | # | ... # `---data was truncated (10240/63571) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a37c1f157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a37c1ee515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a37c1f1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fea26449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fea264a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fea26449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fea26431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a37c18724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a37c187096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a37c16bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a37be1b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a37be1ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fea26432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fea264330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fea264330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a37be1ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmaxaq.c (2217 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmaxaq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxaq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %b.addr, align 8 # | %1 = icmp slt <16 x i8> %0, zeroinitializer # | %2 = sub <16 x i8> zeroinitializer, %0 # | %3 = select <16 x i1> %1, <16 x i8> %2, <16 x i8> %0 # | %4 = load <16 x i8>, ptr %a.addr, align 8 # | %5 = icmp uge <16 x i8> %4, %3 # | %6 = select <16 x i1> %5, <16 x i8> %4, <16 x i8> %3 # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxaq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %b.addr, align 8 # | %1 = icmp slt <8 x i16> %0, zeroinitializer # | %2 = sub <8 x i16> zeroinitializer, %0 # | %3 = select <8 x i1> %1, <8 x i16> %2, <8 x i16> %0 # | %4 = load <8 x i16>, ptr %a.addr, align 8 # | %5 = icmp uge <8 x i16> %4, %3 # | %6 = select <8 x i1> %5, <8 x i16> %4, <8 x i16> %3 # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxaq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %b.addr, align 8 # | %1 = icmp slt <4 x i32> %0, zeroinitializer # | %2 = sub <4 x i32> zeroinitializer, %0 # | %3 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %0 # | %4 = load <4 x i32>, ptr %a.addr, align 8 # | %5 = icmp uge <4 x i32> %4, %3 # | %6 = select <4 x i1> %5, <4 x i32> %4, <4 x i32> %3 # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxaq_m_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vmaxa.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vmaxa.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxaq_m_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vmaxa.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vmaxa.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxaq_m_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.vmaxa.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vmaxa.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a9d4eae57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a9d4eab515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a9d4eaecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007effe9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007effe998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007effe9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007effe991b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a9d4e4424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a9d4e44096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a9d4e28f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a9d4ad8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a9d4ad7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007effe991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007effe991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007effe991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a9d4ad7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c (2218 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_u32mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_u32m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_u32m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32mf2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg # | ... # `---data was truncated (10240/20483) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fdc1c1657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fdc1c13515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fdc1c16cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faa9be49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faa9bea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faa9be49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faa9be31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fdc1bac24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fdc1bac096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fdc1b90f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fdc1840176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fdc183fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007faa9be32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faa9be330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faa9be330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fdc183fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c (2219 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i64m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i64.nxv1i64.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i64m1( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv1i64.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i64.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i64m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i64.nxv2i64.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i64m2( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv2i64.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i64.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i64m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i64.nxv4i64.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i64m4( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv4i64.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i64.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i64m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i64.nxv8i64.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i64m8( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv8i64.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i64.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i64m1_m( %mask, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load , ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64.i64(, , , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i64m1_m( %mask, %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr # | ... # `---data was truncated (10240/18895) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561aeeb9f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561aeeb9c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561aeeb9fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff714333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff71438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff714333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff71431b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561aeeb3524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561aeeb35096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561aeeb19f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561aee7c9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561aee7c8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff71431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff71431d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff71431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561aee7c8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c (2220 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_f16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_f16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_f16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_i16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_i16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_i16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_u16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_u16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_u16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c (2221 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf4_rm_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf2_rm_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m1_rm_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m2_rm_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m4_rm_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync # | ... # `---data was truncated (10240/10618) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f2790d257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f2790cf515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f2790d2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9ee8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9ee818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9ee8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9ee811b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f27906824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f279068096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f27904cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f278cfc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f278cfbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9ee811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9ee811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9ee811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f278cfbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c (2222 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056072e55d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056072e55a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056072e55dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbc94a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbc94aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbc94a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbc94a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056072e4f324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056072e4f3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056072e4d7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056072e187176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056072e186e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbc94a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbc94a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbc94a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056072e186d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c (2223 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vx_i16mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wx_i16mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.w.nxv1i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vx_i16mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wx_i16mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.w.nxv2i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c (2224 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005570c576e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005570c576b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005570c576ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f255781bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f25578725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f255781ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2557803507 abort ./stdlib/abort.c:85:3 # | #7 0x00005570c570424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005570c5704096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005570c56e8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005570c5398176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005570c5397e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2557804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f25578050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f25578050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005570c5397d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c (2225 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv16f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv16f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv32f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv32f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32mf2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv1f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32m1( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv2f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32m2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv4f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv4f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32m4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv8f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv8f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @ # | ... # `---data was truncated (10240/61058) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d1a6a5757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d1a6a54515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d1a6a57cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb523249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb5232a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb523249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb523231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d1a69ed24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d1a69ed096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d1a69d1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d1a6681176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d1a6680e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb523232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb5232330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb5232330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d1a6680d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/AArch64/neon/conversion-fullfp16.c (2226 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon/conversion-fullfp16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c --check-prefixes=LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vcvt_s16_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %vcvtz.i = call <4 x i16> @llvm.fptosi.sat.v4i16.v4f16(<4 x half> %2) # | store <4 x i16> %vcvtz.i, ptr %ref.tmp.i, align 8 # | %3 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %3, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcvtq_s16_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %vcvtz.i = call <8 x i16> @llvm.fptosi.sat.v8i16.v8f16(<8 x half> %2) # | store <8 x i16> %vcvtz.i, ptr %ref.tmp.i, align 16 # | %3 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %3, ptr %__ret.i, align 16 # | %4 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vcvt_u16_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %vcvtz.i = call <4 x i16> @llvm.fptoui.sat.v4i16.v4f16(<4 x half> %2) # | store <4 x i16> %vcvtz.i, ptr %ref.tmp.i, align 8 # | %3 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %3, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcvtq_u16_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %vcvtz.i = call <8 x i16> @llvm.fptoui.sat.v8i16.v8f16(<8 x half> %2) # | store <8 x i16> %vcvtz.i, ptr %ref.tmp.i, align 16 # | %3 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %3, ptr %__ret.i, align 16 # | %4 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x i16> @llvm.fptosi.sat.v4i16.v4f16(<4 x half>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i16> @llvm.fptosi.sat.v8i16.v8f16(<8 x half>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x i16> @llvm.fptoui.sat.v4i16.v4f16(<4 x half>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i16> @llvm.fptoui.sat.v8i16.v8f16(<8 x half>) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000561a4cbbc57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561a4cbb9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561a4cbbccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1524733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f152478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1524733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f152471b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561a4cb5224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561a4cb52096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561a4cb36f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561a4c7e6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561a4c7e5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f152471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f152471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f152471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561a4c7e5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c --check-prefixes=LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c --check-prefixes=LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c (2227 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m8_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none) # | ... # `---data was truncated (10240/30609) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ba6fa9a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ba6fa97515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ba6fa9acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f890c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f890c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f890c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f890c031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ba6fa3024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ba6fa30096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ba6fa14f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ba6f6c4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ba6f6c3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f890c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f890c0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f890c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ba6f6c3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c (2228 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m1x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 # | ... # `---data was truncated (10240/24373) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a25bcdf57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a25bcdc515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a25bcdfcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcea1e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcea1ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcea1e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcea1e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a25bc7524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a25bc75096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a25bc59f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a25b909176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a25b908e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcea1e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcea1e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcea1e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a25b908d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c (2229 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560a72af957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560a72af6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560a72af9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5295b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5295b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5295b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5295b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560a72a8f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560a72a8f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560a72a73f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560a72723176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560a72722e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5295b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5295b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5295b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560a72722d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c (2230 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor # | ... # `---data was truncated (10240/113039) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559f1a97357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559f1a970515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559f1a973cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd528b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd528b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd528b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd528b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559f1a90924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559f1a909096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559f1a8edf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559f1a59d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559f1a59ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd528b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd528b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd528b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559f1a59cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c (2231 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16mf4x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16mf2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16mf4x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16mf2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_u16mf4x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_u16mf2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_u16m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_u16m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16mf4x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = allo # | ... # `---data was truncated (10240/23031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005596e6e9f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005596e6e9c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005596e6e9fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdb7cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdb7cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdb7cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdb7cf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005596e6e3524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005596e6e35096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005596e6e19f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005596e6ac9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005596e6ac8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fdb7cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdb7cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdb7cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005596e6ac8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c (2232 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c (2233 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv16f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv16f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv32f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv32f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32mf2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv1f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv1f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32m1( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv2f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv2f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32m2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv4f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv4f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32m4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv8f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv8f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @ # | ... # `---data was truncated (10240/61058) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005570840db57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005570840d8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005570840dbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc4da01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc4da0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc4da01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc4da003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055708407124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557084071096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557084055f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557083d05176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557083d04e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc4da004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc4da0050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc4da0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557083d04d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcvt.c (2234 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c --check-prefixes=CHECK,CHECK-NOSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcvtq_f16_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = sitofp <8 x i16> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcvtq_f16_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = uitofp <8 x i16> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcvtq_f32_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = sitofp <4 x i32> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcvtq_f32_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = uitofp <4 x i32> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtq_s16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = fptosi <8 x half> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtq_s32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = fptosi <4 x float> %0 to <4 x i32> # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtq_u16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = fptoui <8 x half> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtq_u32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = fptoui <4 x float> %0 to <4 x i32> # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcvtq_m_f16_s16(<8 x half> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x half>, ptr %inactive.addr, align 8 # | %5 = call <8 x half> @llvm.arm.mve.vcvt.fp.int.predicated.v8f16.v8i16.v8i1(<8 x i16> %0, i32 0, <8 x i1> %3, <8 x half> %4) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vcvt.fp.int.predicated.v8f16.v8i16.v8i1(<8 x i16>, i32, <8 x i1>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcvtq_m_f16_u16(<8 x half> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x half>, ptr %inactive.addr, align 8 # | %5 = call <8 x half> @llvm.arm.mve.vcvt.fp.int.predicated.v8f16.v8i16.v8i1(<8 x i16> %0, i32 1, <8 x i1> %3, <8 x half> %4) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcvtq_m_f32_s32(<4 x float> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x float>, ptr %inactive.addr, align 8 # | %5 = call <4 x float> @llvm.arm.mve.vcvt.fp.int.predicated.v4f32.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %3, <4 x float> %4) # | ret <4 x float> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.vcvt.fp.int.predicated.v4f32.v4i32.v4i1(<4 x i32>, i32, <4 x i1>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcvtq_m_f32_u32(<4 x float> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x float>, ptr %inactive.addr, align 8 # | %5 = call <4 x float> @llvm.arm.mve.vcvt.fp.int.predicated.v4f32.v4i32.v4i1(<4 x i32> %0, i32 1, <4 x i1> %3, <4 x float> %4) # | ret <4 x float> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtq_m_s16_f16(<8 x i16> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.vcvt.fp.int.predicated.v8i16.v8f16.v8i1(<8 x half> %0, i32 0, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vcvt.fp.int.predicated.v8i16.v8f16.v8i1(<8 x half>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtq_m_s32_f32(<4 x i32> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x i32>, ptr %inactive.addr, align 8 # | %5 = call <4 x i32> @llvm.arm.mve.vcvt.fp.int.predicated.v4i32.v4f32.v4i1(<4 x float> %0, i32 0, <4 x i1> %3, <4 x i32> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vcvt.fp.int.predicated.v4i32.v4f32.v4i1(<4 x float>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtq_m_u16_f16(<8 x i16> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.vcvt.fp.int.predicated.v8i16.v8f16.v8i1(<8 x half> %0, i32 1, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtq_m_u32_f32(<4 x i32> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm # | ... # `---data was truncated (10240/37578) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560a65f8c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560a65f89515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560a65f8ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7319705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f731975c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7319705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f73196ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560a65f2224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560a65f22096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560a65f06f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560a65bb6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560a65bb5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f73196eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f73196ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f73196ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560a65bb5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c --check-prefixes=CHECK,CHECK-NOSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c --check-prefixes=CHECK,CHECK-NOSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c (2235 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16mf4x5(ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16mf2x5(ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16m1x5(ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16m1x5_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559b57bc657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559b57bc3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559b57bc6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0a32105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0a3215c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0a32105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0a320ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559b57b5c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559b57b5c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559b57b40f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559b577f0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559b577efe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0a320eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0a320ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0a320ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559b577efd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c (2236 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564ac874c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564ac8749515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564ac874ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f68a6933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f68a698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f68a6933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f68a691b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564ac86e224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564ac86e2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564ac86c6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564ac8376176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564ac8375e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f68a691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f68a691d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f68a691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564ac8375d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c (2237 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 # | ... # `---data was truncated (10240/29136) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e7beccd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e7becca515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e7beccdcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8741533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f874158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8741533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f874151b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e7bec6324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e7bec63096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e7bec47f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e7be8f7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e7be8f6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f874151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f874151d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f874151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e7be8f6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c (2238 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1f32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2f32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4f32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8f32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv16f32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8i32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv16i32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_u32mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, # | ... # `---data was truncated (10240/60217) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055772e5de57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055772e5db515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055772e5decbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fea3c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fea3c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fea3c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fea3c31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055772e57424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055772e574096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055772e558f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055772e208176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055772e207e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fea3c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fea3c31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fea3c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055772e207d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c (2239 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_u_s_w4_u8m8_i8m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.u.s.i64.nxv64i8.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.u.s.i64.nxv64i8.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a1387cc57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a1387c9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a1387cccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd740733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd74078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd740733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd74071b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a13876224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a138762096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a138746f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a1383f6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a1383f5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd74071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd74071d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd74071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a1383f5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c (2240 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c (2241 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c -check-prefix=RV32ZKND # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @aes32dsi(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | %2 = call i32 @llvm.riscv.aes32dsi(i32 %0, i32 %1, i32 3) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.aes32dsi(i32, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @aes32dsmi(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | %2 = call i32 @llvm.riscv.aes32dsmi(i32 %0, i32 %1, i32 3) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.aes32dsmi(i32, i32, i32 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zknd" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_zknd1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562a7ed2057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562a7ed1d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562a7ed20cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff151e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff151ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff151e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff151e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562a7ecb624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562a7ecb6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562a7ec9af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562a7e94a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562a7e949e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff151e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff151e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff151e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562a7e949d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c -check-prefix=RV32ZKND # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c -check-prefix=RV32ZKND # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c (2242 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16mf4_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv1f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv1f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16mf2_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv2f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv2f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m1_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv4f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv4f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m2_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv8f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv8f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m4_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv16f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv16f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m8_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv32f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv32f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32mf2_tu( %maskedoff, float noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load float, ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv1f32.i64( %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv1f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m1_tu( %maskedoff, float noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load float, ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv2f32.i64( %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv2f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m2_tu( %maskedoff, float noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load float, ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv4f32.i64( %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv4f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m4_tu( %maskedoff, float noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load float, ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv8f32.i64( %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv8f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m8_tu( %maskedoff, float noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr # | ... # `---data was truncated (10240/29319) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005641bdb2857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005641bdb25515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005641bdb28cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f857b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f857b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f857b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f857b71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005641bdabe24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005641bdabe096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005641bdaa2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005641bd752176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005641bd751e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f857b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f857b71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f857b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005641bd751d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c (2243 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055908267957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559082676515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559082679cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6d1ba1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6d1ba725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6d1ba1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6d1ba03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055908260f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055908260f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005590825f3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005590822a3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005590822a2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6d1ba04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6d1ba050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6d1ba050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005590822a2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c (2244 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf8x7_tum(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c (2245 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv16f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv16f16.f16.i64( poison, %0, ha # | ... # `---data was truncated (10240/125649) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ce9f28957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ce9f286515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ce9f289cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f81cf61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f81cf6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f81cf61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f81cf603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ce9f21f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ce9f21f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ce9f203f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ce9eeb3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ce9eeb2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f81cf604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f81cf6050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f81cf6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ce9eeb2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c (2246 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16mf4x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16mf2x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16m1x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16m1x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f5f4c0a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f5f4c07515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f5f4c0acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7d5801bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7d580725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7d5801ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7d58003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f5f4ba024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f5f4ba0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f5f4b84f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f5f4834176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f5f4833e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7d58004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7d580050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7d580050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f5f4833d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c (2247 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_f32mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_f32mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv1f32.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_f32m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_f32m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv2f32.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_f32m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_f32m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2 # | ... # `---data was truncated (10240/151911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564cd01b957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564cd01b6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564cd01b9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4e76d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4e76d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4e76d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4e76d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564cd014f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564cd014f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564cd0133f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564ccfde3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564ccfde2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4e76d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4e76d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4e76d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564ccfde2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c (2248 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16mf4_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16mf4_f32mf2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16mf2_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16mf2_f32m1_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16m1_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16m1_f32m2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16m2_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16m2_f32m4_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c (2249 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste32_f32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.sf.vste32.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste32_i32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste32_u32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556b9598557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556b95982515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556b95985cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa889d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa889d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa889d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa889d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556b9591b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556b9591b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556b958fff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556b955af176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556b955aee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa889d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa889d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa889d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556b955aed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c (2250 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16mf4x3(ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16mf2x3(ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16m1x3(ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16m2x3(ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16m1x3_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16m2x3_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale # | ... # `---data was truncated (10240/10790) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f367c3d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f367c3a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f367c3dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1567849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f15678a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1567849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1567831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f367bd324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f367bd3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f367bb7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f367867176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f367866e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1567832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f15678330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f15678330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f367866d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c (2251 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", # | ... # `---data was truncated (10240/19492) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005575e7d8057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005575e7d7d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005575e7d80cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd14e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd14e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd14e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd14e431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005575e7d1624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005575e7d16096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005575e7cfaf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005575e79aa176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005575e79a9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd14e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd14e4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd14e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005575e79a9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c (2252 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_f32mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_f32mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv1f32.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_f32m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_f32m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv2f32.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_f32m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_f32m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, a # | ... # `---data was truncated (10240/151903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055565a6fc57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055565a6f9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055565a6fccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7c29a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7c29aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7c29a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7c29a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055565a69224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055565a692096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055565a676f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055565a326176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055565a325e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7c29a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7c29a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7c29a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055565a325d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c (2253 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv1i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv2i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv4i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv8i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv16i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d64752857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d647525515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d647528cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3e13649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3e136a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3e13649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3e13631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d6474be24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d6474be096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d6474a2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d647152176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d647151e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3e13632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3e136330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3e136330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d647151d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl (2254 of 27911) ******************** TEST 'Clang :: CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O0 -cl-std=CL2.0 -triple amdgpu-amd-amdhsa -fno-ident -DKERNEL_NAME=test_kernel_first -DTYPE=float -DCONST=256.0f -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O0 -cl-std=CL2.0 -triple amdgpu-amd-amdhsa -fno-ident -DKERNEL_NAME=test_kernel_first -DTYPE=float -DCONST=256.0f -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O0 -cl-std=CL2.0 -triple amdgpu-amd-amdhsa -fno-ident -DKERNEL_NAME=test_kernel_second -DTYPE=int -DCONST=128.0f -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.1.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O0 -cl-std=CL2.0 -triple amdgpu-amd-amdhsa -fno-ident -DKERNEL_NAME=test_kernel_second -DTYPE=int -DCONST=128.0f -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.1.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl # RUN: at line 8 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=globalopt -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.opt.0.bc /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=globalopt -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.opt.0.bc /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=globalopt -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.opt.0.bc /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc # | #0 0x0000562aa565757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562aa5654515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562aa5657cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6cd1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6cd178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6cd1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6cd171b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562aa55ed24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562aa55ed096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562aa55d1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562aa5281176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562aa5280e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6cd171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6cd171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6cd171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562aa5280d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c (2255 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557e5468957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557e54686515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557e54689cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1e5a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1e5a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1e5a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1e5a431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557e5461f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557e5461f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557e54603f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557e542b3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557e542b2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1e5a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1e5a4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1e5a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557e542b2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c (2256 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f64m1x4(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c (2257 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a7f748b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a7f7488515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a7f748bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb584105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb58415c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb584105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb5840ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a7f742124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a7f7421096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a7f7405f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a7f70b5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a7f70b4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb5840eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb5840ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb5840ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a7f70b4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c (2258 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | % # | ... # `---data was truncated (10240/14613) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e2a819257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e2a818f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e2a8192cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4890c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4890ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4890c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4890c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e2a812824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e2a8128096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e2a810cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e2a7dbc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e2a7dbbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4890c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4890c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4890c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e2a7dbbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c (2259 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_f64m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_i64m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_u64m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_f64m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_i64m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_u64m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555af8fdd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555af8fda515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555af8fddcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f841cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f841cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f841cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f841cf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555af8f7324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555af8f73096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555af8f57f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555af8c07176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555af8c06e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f841cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f841cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f841cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555af8c06d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c (2260 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32m2x4_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c (2261 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16mf4( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16mf2( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m1( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m2( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m4( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m8( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32mf2( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64( %0, i16 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(, i16, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32m1( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64( %0, i16 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(, i16, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32m2( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.addr, align 2 # | %2 = # | ... # `---data was truncated (10240/39218) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cff8fef57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cff8fec515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cff8fefcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f34ea133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f34ea18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f34ea133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f34ea11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cff8f8524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cff8f85096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cff8f69f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cff8c19176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cff8c18e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f34ea11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f34ea11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f34ea11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cff8c18d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp (2262 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(2,1024) # | define dso_local @_Z21test_vget_v_i8m2_i8m1u14__rvv_int8m2_t( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv8i8.nxv16i8( %0, i64 8) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8i8.nxv16i8(, i64 immarg) #1 # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(2,1024) # | define dso_local @_Z21test_vset_v_i8m1_i8m2u14__rvv_int8m2_tu14__rvv_int8m1_t( %dest, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv16i8.nxv8i8( %0, %1, i64 8) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16i8.nxv8i8(, , i64 immarg) #1 # | # | attributes #0 = { mustprogress noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005609379f557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005609379f2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005609379f5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3779f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3779f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3779f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3779f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056093798b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056093798b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056093796ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056093761f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056093761ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3779f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3779f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3779f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056093761ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c (2263 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16mf4_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv1f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16mf2_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv2f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m1_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv4f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m2_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv8f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv8f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m4_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv16f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv16f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m8_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv32f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv32f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f32mf2_tu( %maskedoff, %op1, float noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv1f32.f32.i64( %0, %1, float %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1f32.f32.i64(, , float, , i64) #1 # | # | ; Function # | ... # `---data was truncated (10240/22375) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055801b2b657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055801b2b3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055801b2b6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2a7f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2a7f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2a7f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2a7f231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055801b24c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055801b24c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055801b230f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055801aee0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055801aedfe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2a7f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2a7f2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2a7f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055801aedfd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c (2264 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m4_tu( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c (2265 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dc81a0457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055dc81a01515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055dc81a04cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff906b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff906b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff906b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff906b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dc8199a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055dc8199a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055dc8197ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055dc8162e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055dc8162de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff906b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff906b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff906b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dc8162dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c (2266 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16mf4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16mf2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m1_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m8_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f32mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f32m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, a # | ... # `---data was truncated (10240/44177) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a17d96457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a17d961515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a17d964cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7537133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f753718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7537133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f753711b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a17d8fa24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a17d8fa096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a17d8def49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a17d58e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a17d58de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f753711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f753711d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f753711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a17d58dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c (2267 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf4_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf2_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m1_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m2_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m4_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m8_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf4_tum( %mask, %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %src.addr, align 2 # | %3 = load bfloat, ptr %value.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf2_tum( %mask, %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c (2268 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vect # | ... # `---data was truncated (10240/113765) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561ea79e757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561ea79e4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561ea79e7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa248905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa24895c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa248905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa2488ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561ea797d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561ea797d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561ea7961f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561ea7611176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561ea7610e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa2488eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa2488ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa2488ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561ea7610d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c (2269 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv16f32.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv16f32.nxv16f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %o # | ... # `---data was truncated (10240/76627) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056069864c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560698649515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056069864ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff662b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff662b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff662b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff662aed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005606985e224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005606985e2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005606985c6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560698276176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560698275e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff662aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff662aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff662aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560698275d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c (2270 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op # | ... # `---data was truncated (10240/222917) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558e7e53957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558e7e536515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558e7e539cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5acaf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5acaf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5acaf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5acaf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558e7e4cf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558e7e4cf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558e7e4b3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558e7e163176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558e7e162e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5acaf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5acaf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5acaf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558e7e162d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c (2271 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64(, , # | ... # `---data was truncated (10240/13290) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e315b4f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e315b4c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e315b4fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb970649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb9706a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb970649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb970631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e315ae524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e315ae5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e315ac9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e315779176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e315778e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb970632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb9706330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb9706330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e315778d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c (2272 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564a6a98057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564a6a97d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564a6a980cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc54bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc54bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc54bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc54bd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564a6a91624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564a6a916096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564a6a8faf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564a6a5aa176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564a6a5a9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc54bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc54bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc54bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564a6a5a9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c (2273 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscal # | ... # `---data was truncated (10240/12235) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f79034057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f79033d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f790340cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff5f1e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff5f1ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff5f1e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff5f1e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f7902d624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f7902d6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f7902baf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f78ff6a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f78ff69e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff5f1e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff5f1e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff5f1e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f78ff69d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c (2274 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055921d4c757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055921d4c4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055921d4c7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd07dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd07dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd07dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd07dc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055921d45d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055921d45d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055921d441f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055921d0f1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055921d0f0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd07dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd07dc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd07dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055921d0f0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c (2275 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nx # | ... # `---data was truncated (10240/18660) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005577a5f7d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005577a5f7a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005577a5f7dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f49a4b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f49a4b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f49a4b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f49a4b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005577a5f1324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005577a5f13096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005577a5ef7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005577a5ba7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005577a5ba6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f49a4b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f49a4b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f49a4b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005577a5ba6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c (2276 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fb24c3857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fb24c35515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fb24c38cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fac97933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fac9798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fac97933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fac9791b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fb24bce24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fb24bce096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fb24bb2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fb24862176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fb24861e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fac9791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fac9791d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fac9791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fb24861d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c (2277 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_bf16mf4_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_bf16mf4_f32mf2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_bf16mf4_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_bf16_f32mf2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_bf16mf2_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_bf16mf2_f32m1_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_bf16mf2_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_bf16_f32m1_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c (2278 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f32.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f32.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16f32.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f32.p0.nxv16i32.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c (2279 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ... # `---data was truncated (10240/34438) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f64a6ea57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f64a6e7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f64a6eacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f53ae21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f53ae2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f53ae21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f53ae203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f64a68024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f64a680096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f64a664f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f64a314176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f64a313e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f53ae204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f53ae2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f53ae2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f64a313d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c (2280 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv1i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv2i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv4i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv8i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv16i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv32i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv64i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv1i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv2i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv4i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv8i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv8i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv16i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv16i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGenCXX/attr-musttail.cpp (2281 of 27911) ******************** TEST 'Clang :: CodeGenCXX/attr-musttail.cpp' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fno-elide-constructors -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp -triple x86_64-unknown-linux-gnu -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fno-elide-constructors -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp -triple x86_64-unknown-linux-gnu -o - # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fno-elide-constructors -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp -triple x86_64-unknown-linux-gnu -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=verify # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fno-elide-constructors -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp -triple x86_64-unknown-linux-gnu -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | %class.Foo = type { i8 } # | %class.HasTrivialDestructor = type { i8 } # | %struct.Data = type { ptr } # | %struct.HasNonTrivialCopyConstructor = type { i8 } # | %struct.HasNonTrivialCopyConstructor2 = type { i8 } # | %struct.LargeWithCopyConstructor = type { [32 x i8] } # | %class.anon = type { i8 } # | # | $_Z12TemplateFuncIiET_S0_ = comdat any # | # | $_Z6Func10IiEii = comdat any # | # | $_Z6Func12IiET_S0_ = comdat any # | # | @pmf = global { i64, i64 } zeroinitializer, align 8 # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z5Func1i(i32 noundef %x) #0 { # | entry: # | %retval = alloca i32, align 4 # | %x.addr = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %tobool = icmp ne i32 %0, 0 # | br i1 %tobool, label %if.then, label %if.else # | # | if.then: ; preds = %entry # | %1 = load i32, ptr %x.addr, align 4 # | %call = musttail call noundef i32 @_Z3Bari(i32 noundef %1) # | ret i32 %call # | # | 2: ; No predecessors! # | store i32 undef, ptr %retval, align 4 # | br label %return # | # | if.else: ; preds = %entry # | %3 = load i32, ptr %x.addr, align 4 # | %call1 = musttail call noundef i32 @_Z3Bazi(i32 noundef %3) # | ret i32 %call1 # | # | 4: ; No predecessors! # | store i32 undef, ptr %retval, align 4 # | br label %return # | # | return: ; preds = %4, %2 # | %5 = load i32, ptr %retval, align 4 # | ret i32 %5 # | } # | # | declare noundef i32 @_Z3Bari(i32 noundef) #1 # | # | declare noundef i32 @_Z3Bazi(i32 noundef) #1 # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z5Func2i(i32 noundef %x) #0 { # | entry: # | %x.addr = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %call = call noundef i32 @_Z3Bari(i32 noundef %0) # | %call1 = musttail call noundef i32 @_Z3Bari(i32 noundef %call) # | ret i32 %call1 # | # | 1: ; No predecessors! # | ret i32 undef # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_ZN3Foo8TailFromEi(ptr noundef nonnull align 1 dereferenceable(1) %this, i32 noundef %x) #0 align 2 { # | entry: # | %this.addr = alloca ptr, align 8 # | %x.addr = alloca i32, align 4 # | store ptr %this, ptr %this.addr, align 8 # | store i32 %x, ptr %x.addr, align 4 # | %this1 = load ptr, ptr %this.addr, align 8 # | %0 = load i32, ptr %x.addr, align 4 # | %call = musttail call noundef i32 @_ZN3Foo14MemberFunctionEi(ptr noundef nonnull align 1 dereferenceable(1) %this1, i32 noundef %0) # | ret i32 %call # | # | 1: ; No predecessors! # | ret i32 undef # | } # | # | declare noundef i32 @_ZN3Foo14MemberFunctionEi(ptr noundef nonnull align 1 dereferenceable(1), i32 noundef) #1 # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z5Func3i(i32 noundef %x) #0 { # | entry: # | %x.addr = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %call = musttail call noundef i32 @_ZN3Foo12StaticMethodEi(i32 noundef %0) # | ret i32 %call # | # | 1: ; No predecessors! # | ret i32 undef # | } # | # | declare noundef i32 @_ZN3Foo12StaticMethodEi(i32 noundef) #1 # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z5Func4i(i32 noundef %x) #0 { # | entry: # | %x.addr = alloca i32, align 4 # | %foo = alloca %class.Foo, align 1 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %call = musttail call noundef i32 @_ZN3Foo12StaticMethodEi(i32 noundef %0) # | ret i32 %call # | # | 1: ; No predecessors! # | ret i32 undef # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_ZN3Foo9TailFrom2Ei(ptr noundef nonnull align 1 dereferenceable(1) %this, i32 noundef %x) #0 align 2 { # | entry: # | %this.addr = alloca ptr, align 8 # | %x.addr = alloca i32, align 4 # | store ptr %this, ptr %this.addr, align 8 # | store i32 %x, ptr %x.addr, align 4 # | %this1 = load ptr, ptr %this.addr, align 8 # | %0 = load { i64, i64 }, ptr @pmf, align 8 # | %memptr.adj = extractvalue { i64, i64 } %0, 1 # | %1 = getelementptr inbounds i8, ptr %this1, i64 %memptr.adj # | %memptr.ptr = extractvalue { i64, i64 } %0, 0 # | %2 = and i64 %memptr.ptr, 1 # | %memptr.isvirtual = icmp ne i64 %2, 0 # | br i1 %memptr.isvirtual, label %memptr.virtual, label %memptr.nonvirtual # | # | memptr.virtual: ; preds = %entry # | %vtable = load ptr, ptr %1, align 8 # | %3 = sub i64 %memptr.ptr, 1 # | %4 = getelementptr i8, ptr %vtable, i64 %3, !nosanitize !1 # | %memptr.virtualfn = load ptr, ptr %4, align 8, !nosanitize !1 # | br label %memptr.end # | # | memptr.nonvirtual: ; preds = %entry # | %memptr.nonvirtualfn = inttoptr i64 %memptr.ptr to ptr # | br label %memptr.end # | # | memptr.end: ; preds = %memptr.nonvirtual, %memptr.virtual # | %5 = phi ptr [ %memptr.virtualfn, %memptr.virtual ], [ %memptr.nonvirtualfn, %memptr.nonvirtual ] # | %6 = load i32, ptr %x.addr, align 4 # | %call = musttail call noundef i32 %5(ptr noundef nonnull align 1 dereferenceable(1) %1, i32 noundef %6) # | ret i32 %call # | # | 7: ; No predecessors! # | ret i32 undef # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_ZN3Foo9TailFrom3Ei(ptr noundef nonnull align 1 dereferenceable(1) %this, i32 noundef %x) #0 align 2 { # | entry: # | %this.addr = alloca ptr, align 8 # | %x.addr = alloca i32, align 4 # | store ptr %this, ptr %this.addr, align 8 # | store i32 %x, ptr %x.addr, align 4 # | %this1 = load ptr, ptr %this.addr, align 8 # | %0 = load { i64, i64 }, ptr @pmf, align 8 # | %memptr.adj = extractvalue { i64, i64 } %0, 1 # | %1 = getelementptr inbounds i8, ptr %this1, i64 %memptr.adj # | %memptr.ptr = extractvalue { i64, i64 } %0, 0 # | %2 = and i64 %memptr.ptr, 1 # | %memptr.isvirtual = icmp ne i64 %2, 0 # | br i1 %memptr.isvirtual, label %memptr.virtual, label %memptr.nonvirtual # | # | memptr.virtual: ; preds = %entry # | %vtable = load ptr, ptr %1, align 8 # | %3 = sub i64 %memptr.ptr, 1 # | %4 = getelementptr i8, ptr %vtable, i64 %3, !nosanitize !1 # | %memptr.virtualfn = load ptr, ptr %4, align 8, !nosanitize !1 # | br label %memptr.end # | # | memptr.nonvirtual: ; preds = %entry # | %memptr.nonvirtualfn = inttoptr i64 %memptr.ptr to ptr # | br label %memptr.end # | # | memptr.end: ; preds = %memptr.nonvirtual, %memptr.virtual # | %5 = phi ptr [ %memptr.virtualfn, %memptr.virtual ], [ %memptr.nonvirtualfn, %memptr.nonvirtual ] # | %6 = load i32, ptr %x.addr, align 4 # | %call = musttail call noundef i32 %5(ptr noundef nonnull align 1 dereferenceable(1) %1, i32 noundef %6) # | ret i32 %call # | # | 7: ; No predecessors! # | ret i32 undef # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local void @_Z5Func5v() #0 { # | entry: # | musttail call void @_Z11ReturnsVoidv() # | ret void # | # | 0: ; No predecessors! # | ret void # | } # | # | declare void @_Z11ReturnsVoidv() #1 # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z5Func6i(i32 noundef %x) #0 { # | entry: # | %x.addr = alloca i32, align 4 # | %foo = alloca %class.HasTrivialDestructor, align 1 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %call = musttail call noundef i32 @_Z10ReturnsInti(i32 noundef %0) # | ret i32 %call # | # | 1: ; No predecessors! # | ret i32 undef # | } # | # | declare noundef i32 @_Z10ReturnsInti(i32 noundef) #1 # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z5Func7P4Data(ptr noundef %data) #0 { # | entry: # | %data.addr = alloca ptr, align 8 # | store ptr %data, ptr %data.addr, align 8 # | %0 = load ptr, ptr %data.addr, align 8 # | %fptr = getelementptr inbounds nuw %struct.Data, ptr %0, i32 0, i32 0 # | %1 = load ptr, ptr %fptr, align 8 # | %2 = load ptr, ptr %data.addr, align 8 # | %call = musttail call noundef i32 %1(ptr noundef %2) # | ret i32 %call # | # | 3: ; No predecessors! # | ret i32 undef # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z5Func9i(i32 noundef %x) #0 { # | entry: # | %x.addr = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %call = musttail call noundef i32 @_Z12TemplateFuncIiET_S0_(i32 noundef %0) # | ret i32 %call # | # | 1: ; No predecessors! # | ret i32 undef # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define linkonce_odr noundef i32 @_Z12TemplateFuncIiET_S0_(i32 noundef %0) #0 comdat { # | entry: # | %.addr = alloca i32, align 4 # | store i32 %0, ptr %.addr, align 4 # | ret i32 5 # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z6Func11i(i32 noundef %x) #0 { # | entry: # | %x.addr = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %call = call noundef i32 @_Z6Func10IiEii(i32 noundef %0) # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define linkonce_odr noundef i32 @_Z6Func10IiEii(i32 noundef %x) #0 comdat { # | entry: # | %x.addr = alloca i32, align 4 # | %t = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %call = musttail call noundef i32 @_Z3Bari(i32 noundef %0) # | ret i32 %call # | # | 1: ; No predecessors! # | ret i32 undef # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z6Func13i(i32 noundef %x) #0 { # | entry: # | %x.ad # | ... # `---data was truncated (10240/18685) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=verify # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=verify # | #0 0x000056419818357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564198180515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564198183cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd751a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd751aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd751a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd751a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056419811924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564198119096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005641980fdf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564197dad176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564197dace93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd751a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd751a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd751a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564197dacd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c (2282 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfs # | ... # `---data was truncated (10240/65574) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557c94df357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557c94df0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557c94df3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2b21933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2b2198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2b21933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2b2191b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557c94d8924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557c94d89096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557c94d6df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557c94a1d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557c94a1ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2b2191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2b2191d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2b2191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557c94a1cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c (2283 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32mf2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32mf2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32mf2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0 # | ... # `---data was truncated (10240/10425) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005569fd8c857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005569fd8c5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005569fd8c8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe72fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe72faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe72fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe72fa31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005569fd85e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005569fd85e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005569fd842f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005569fd4f2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005569fd4f1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe72fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe72fa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe72fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005569fd4f1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c (2284 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noca # | ... # `---data was truncated (10240/40803) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e73080457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e730801515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e730804cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc06e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc06e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc06e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc06e831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e73079a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e73079a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e73077ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e73042e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e73042de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc06e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc06e8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc06e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e73042dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c (2285 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c27081f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c27081c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c27081fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f546f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f546f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f546f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f546f11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c2707b524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c2707b5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c270799f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c270449176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c270448e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f546f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f546f11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f546f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c270448d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c (2286 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willr # | ... # `---data was truncated (10240/44361) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555eea90d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555eea90a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555eea90dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f82e5f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f82e5f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f82e5f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f82e5eed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555eea8a324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555eea8a3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555eea887f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555eea537176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555eea536e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f82e5eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f82e5eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f82e5eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555eea536d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c (2287 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d1f0d0957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d1f0d06515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d1f0d09cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f47eda49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f47edaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f47eda49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f47eda31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d1f0c9f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d1f0c9f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d1f0c83f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d1f0933176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d1f0932e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f47eda32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f47eda330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f47eda330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d1f0932d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c (2288 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16mf4_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m4_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m8_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f32mf2_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f32m1_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f32m2_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv1f64.nxv4f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret # | ... # `---data was truncated (10240/50516) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b43386057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b43385d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b433860cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffad9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffad998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffad9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffad991b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b4337f624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b4337f6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b4337daf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b43348a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b433489e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ffad991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffad991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffad991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b433489d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c (2289 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 2) %6 # | } # | # | ; Fun # | ... # `---data was truncated (10240/34633) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005614a969d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005614a969a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005614a969dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff78e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff78e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff78e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff78e431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005614a963324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005614a9633096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005614a9617f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005614a92c7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005614a92c6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff78e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff78e4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff78e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005614a92c6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c (2290 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op # | ... # `---data was truncated (10240/222917) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555832b7257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555832b6f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555832b72cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f40c9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f40c9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f40c9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f40c9b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555832b0824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555832b08096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555832aecf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055583279c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055583279be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f40c9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f40c9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f40c9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055583279bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c (2291 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin. # | ... # `---data was truncated (10240/69313) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ad8b6c657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ad8b6c3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ad8b6c6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f45c6133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f45c618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f45c6133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f45c611b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ad8b65c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ad8b65c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ad8b640f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ad8b2f0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ad8b2efe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f45c611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f45c611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f45c611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ad8b2efd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c (2292 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562b923b757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562b923b4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562b923b7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f971cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f971cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f971cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f971cc31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562b9234d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562b9234d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562b92331f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562b91fe1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562b91fe0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f971cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f971cc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f971cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562b91fe0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c (2293 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_f32mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1f32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_f32m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2f32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_f32m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4f32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_f32m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8f32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_f32m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16f32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_i32mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_i32m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_i32m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_i32m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_i32m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_u32mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_u32m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i32.p0.i64( %1, ptr %0, # | ... # `---data was truncated (10240/28346) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560fb6a2357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560fb6a20515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560fb6a23cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4b22533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4b2258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4b22533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4b2251b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560fb69b924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560fb69b9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560fb699df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560fb664d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560fb664ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4b2251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4b2251d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4b2251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560fb664cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c (2294 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_i8mf4x7(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005594c549357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005594c5490515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005594c5493cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8d40e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8d40e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8d40e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8d40e03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005594c542924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005594c5429096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005594c540df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005594c50bd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005594c50bce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8d40e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8d40e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8d40e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005594c50bcd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c (2295 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vclz.c (2296 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vclz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclzq_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %0, i1 false) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>, i1 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclzq_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %0, i1 false) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclzq_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %0, i1 false) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclzq_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %0, i1 false) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclzq_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %0, i1 false) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclzq_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %0, i1 false) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclsq_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = call <16 x i8> @llvm.arm.mve.vcls.v16i8(<16 x i8> %0) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vcls.v16i8(<16 x i8>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclsq_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.arm.mve.vcls.v8i16(<8 x i16> %0) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vcls.v8i16(<8 x i16>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclsq_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.arm.mve.vcls.v4i32(<4 x i32> %0) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vcls.v4i32(<4 x i32>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclsq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = load <16 x i8>, ptr %inactive.addr, align 8 # | %5 = call <16 x i8> @llvm.arm.mve.cls.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i1> %3, <16 x i8> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.cls.predicated.v16i8.v16i1(<16 x i8>, <16 x i1>, <16 x i8>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclsq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.cls.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.cls.predicated.v8i16.v8i1(<8 x i16>, <8 x i1>, <8 x i16>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclsq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x i32>, ptr %inactive.addr, align 8 # | %5 = call <4 x i32> @llvm.arm.mve.cls.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i1> %3, <4 x i32> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.cls.predicated.v4i32.v4i1(<4 x i32>, <4 x i1>, <4 x i32>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclzq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = load <16 x i8>, ptr %inactive.addr, align 8 # | %5 = call <16 x i8> @llvm.arm.mve.clz.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i1> %3, <16 x i8> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.clz.predicated.v16i8.v16i1(<16 x i8>, <16 x i1>, <16 x i8>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclzq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.clz.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.clz.predicated.v8i16.v8i1(<8 x i16>, <8 x i1>, <8 x i16>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclzq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x i32>, ptr %inactive.addr, align 8 # | %5 = call <4 x i32> @llvm.arm.mve.clz.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i1> %3, <4 x i32> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x # | ... # `---data was truncated (10240/18674) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e96aafa57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e96aaf7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e96aafacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9ff0b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9ff0b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9ff0b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9ff0b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e96aa9024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e96aa90096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e96aa74f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e96a724176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e96a723e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9ff0b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9ff0b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9ff0b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e96a723d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c (2297 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_u16mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_u16mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_u16m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, pt # | ... # `---data was truncated (10240/24016) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a760a9657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a760a93515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a760a96cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcd6e705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcd6e75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcd6e705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcd6e6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a760a2c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a760a2c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a760a10f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a7606c0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a7606bfe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcd6e6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcd6e6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcd6e6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a7606bfd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c (2298 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32mf2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m1( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m4( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m8( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32mf2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m1_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: # | ... # `---data was truncated (10240/13649) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f2bf23657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f2bf233515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f2bf236cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f19a1a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f19a1aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f19a1a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f19a1a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f2bf1cc24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f2bf1cc096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f2bf1b0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f2bee60176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f2bee5fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f19a1a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f19a1a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f19a1a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f2bee5fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c (2299 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555e0cc5757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555e0cc54515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555e0cc57cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f880fa1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f880fa725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f880fa1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f880fa03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555e0cbed24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555e0cbed096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555e0cbd1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555e0c881176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555e0c880e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f880fa04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f880fa050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f880fa050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555e0c880d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c (2300 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none # | ... # `---data was truncated (10240/61673) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056233e2fc57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056233e2f9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056233e2fccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2b67c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2b67ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2b67c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2b67c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056233e29224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056233e292096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056233e276f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056233df26176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056233df25e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2b67c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2b67c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2b67c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056233df25d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c (2301 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_i8mf8x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_i8mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_i8mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_i8m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_u8mf8x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_u8mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_u8mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_u8m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_i8mf8x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, al # | ... # `---data was truncated (10240/21566) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fa3889957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fa38896515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fa38899cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0aec705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0aec75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0aec705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0aec6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fa3882f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fa3882f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fa38813f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fa384c3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fa384c2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0aec6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0aec6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0aec6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fa384c2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c (2302 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_i8mf8x5 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564b6a07757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564b6a074515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564b6a077cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fab2aa1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fab2aa725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fab2aa1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fab2aa03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564b6a00d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564b6a00d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564b69ff1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564b69ca1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564b69ca0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fab2aa04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fab2aa050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fab2aa050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564b69ca0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c (2303 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | ... # `---data was truncated (10240/34356) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b46121a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b461217515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b46121acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f204bc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f204bca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f204bc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f204bc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b4611b024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b4611b0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b461194f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b460e44176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b460e43e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f204bc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f204bc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f204bc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b460e43d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c (2304 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m4_tu( %maskedoff, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c (2305 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16m8(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretur # | ... # `---data was truncated (10240/136005) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a334fee57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a334feb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a334feecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5696249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f56962a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5696249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5696231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a334f8424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a334f84096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a334f68f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a334c18176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a334c17e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5696232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f56962330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f56962330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a334c17d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqdmulltq.c (2306 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqdmulltq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1) # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32>, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_m_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_m_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <2 x i64>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <2 x i64> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3) # | %5 = load <2 x i64>, ptr %inactive.addr, align 8 # | %6 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %1, i32 1, <2 x i1> %4, <2 x i64> %5) # | ret <2 x i64> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32>, <4 x i32>, i32, <2 x i1>, <2 x i64>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %.splat, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %.splat, i32 1) # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_m_n_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %.splat, i32 1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_m_n_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <2 x i64>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store <2 x i64> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3) # | %5 = load <2 x i64>, ptr %inactive.addr, align 8 # | %6 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %.splat, i32 1, <2 x i1> %4, <2 x i64> %5) # | ret <2 x i64> %6 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d59489857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d594895515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d594898cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0381905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f038195c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0381905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f03818ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d59482e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d59482e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d594812f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d5944c2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d5944c1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f03818eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f03818ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f03818ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d5944c1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminq.c (2307 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = icmp ule <16 x i8> %0, %1 # | %3 = select <16 x i1> %2, <16 x i8> %0, <16 x i8> %1 # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = icmp sle <8 x i16> %0, %1 # | %3 = select <8 x i1> %2, <8 x i16> %0, <8 x i16> %1 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = icmp ule <4 x i32> %0, %1 # | %3 = select <4 x i1> %2, <4 x i32> %0, <4 x i32> %1 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.min.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.min.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.min.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.min.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.min.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.min.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminq_x_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557bd032c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557bd0329515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557bd032ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fae5f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fae5f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fae5f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fae5f71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557bd02c224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557bd02c2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557bd02a6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557bcff56176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557bcff55e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fae5f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fae5f71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fae5f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557bcff55d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c (2308 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv1i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv1i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv2i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv2i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv4i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv4i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv8i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv8i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/226585) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b0d39b657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b0d39b3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b0d39b6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe656c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe656ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe656c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe656c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b0d394c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b0d394c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b0d3930f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b0d35e0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b0d35dfe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe656c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe656c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe656c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b0d35dfd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c (2309 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c (2310 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c53241357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c532410515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c532413cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2f9de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2f9dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2f9de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2f9de31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c5323a924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c5323a9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c53238df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c53203d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c53203ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2f9de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2f9de330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2f9de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c53203cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c (2311 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none # | ... # `---data was truncated (10240/61673) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055985144b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559851448515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055985144bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7eebc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7eebca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7eebc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7eebc31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005598513e124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005598513e1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005598513c5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559851075176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559851074e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7eebc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7eebc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7eebc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559851074d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c (2312 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16mf4x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16mf2x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16m1x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16m2x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16m1x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16m2x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca targ # | ... # `---data was truncated (10240/11920) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c20a0cb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c20a0c8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c20a0cbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb38b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb38b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb38b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb38b631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c20a06124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c20a061096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c20a045f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c209cf5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c209cf4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb38b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb38b6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb38b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c209cf4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c (2313 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv8i8.nxv8i8.i64(, , , , i # | ... # `---data was truncated (10240/63579) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005561d451657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005561d4513515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005561d4516cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f61cb533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f61cb58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f61cb533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f61cb51b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005561d44ac24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005561d44ac096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005561d4490f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005561d4140176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005561d413fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f61cb51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f61cb51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f61cb51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005561d413fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c (2314 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16m1x5_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056381936c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563819369515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056381936ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3808133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f380818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3808133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f380811b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056381930224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563819302096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005638192e6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563818f96176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563818f95e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f380811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f380811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f380811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563818f95d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c (2315 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv16i8.nxv16i16.i64.i64( poison, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c (2316 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c (2317 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m1x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m2x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ece8f7857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ece8f75515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ece8f78cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f583ae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f583aea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f583ae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f583ae31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ece8f0e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ece8f0e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ece8ef2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ece8ba2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ece8ba1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f583ae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f583ae330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f583ae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ece8ba1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c (2318 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a22847e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a22847b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a22847ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f02dd249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f02dd2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f02dd249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f02dd231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a22841424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a228414096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a2283f8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a2280a8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a2280a7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f02dd232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f02dd2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f02dd2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a2280a7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c (2319 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv1i32.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv2i32.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv4i32.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv8i32.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv16i32.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv1i64.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv2i64.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv4i64.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv8i64.nxv8i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 4 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | % # | ... # `---data was truncated (10240/39922) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ad1ad3e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ad1ad3b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ad1ad3ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fab1781bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fab178725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fab1781ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fab17803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ad1acd424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ad1acd4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ad1acb8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ad1a968176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ad1a967e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fab17804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fab178050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fab178050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ad1a967d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c (2320 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m2_bf16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv8bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv8bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m4_bf16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m8_bf16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m4_bf16m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m8_bf16m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m8_bf16m4( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv16bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv16bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x2_bf16mf4(target("riscv.vector.tuple", , 2) %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %index.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %src.addr, align 2 # | %1 = call @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_2t(target("riscv.vector.tuple", , 2) %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_2t(target("riscv.vector.tuple", , 2), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x3_bf16mf4(target("riscv.vector.tuple", , 3) %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %index.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %src.addr, align 2 # | %1 = call @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_3t(target("riscv.vector.tuple", , 3) %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_3t(target("riscv.vector.tuple", , 3), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x4_bf16mf4(target("riscv.vector.tuple", , 4) %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %index.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %src.addr, align 2 # | %1 = call @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_4t(target("riscv.vector.tuple", , 4) %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_4t(target("riscv.vector.tuple", , 4), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x5_bf16mf4(target("riscv.vector.tuple", , 5) %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %index.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %src.addr, align 2 # | %1 = call @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_5t(target("riscv.vector.tuple", , 5) %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_5t(target("riscv.vector.tuple", , 5), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x6_bf16mf4(target("riscv.vector.tuple", , 6) %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %index.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %src.addr, align 2 # | %1 = call @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_6t(target("riscv.vector.tuple", , 6) %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_6t(target("riscv.vector.tuple", , 6), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x7_bf16mf4(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c (2321 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_i8mf8x6_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c (2322 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv2i16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv4i16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv8i16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv16i16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv32i16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i32.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv2i32.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv4i32.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv8i32.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i32.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv16i32.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv16i32.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i64.nxv1i32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i64.nxv1i32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op # | ... # `---data was truncated (10240/28563) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c834dec57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c834de9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c834deccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc163249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc1632a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc163249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc163231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c834d8224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c834d82096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c834d66f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c834a16176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c834a15e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc163232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc1632330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc1632330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c834a15d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c (2323 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf8x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8mf8x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = l # | ... # `---data was truncated (10240/64341) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055be12c6057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055be12c5d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055be12c60cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f37fb333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f37fb38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f37fb333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f37fb31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055be12bf624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055be12bf6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055be12bdaf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055be1288a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055be12889e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f37fb31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f37fb31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f37fb31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055be12889d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c (2324 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf4( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf2( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m1( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m2( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m4( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m8( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf4_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf2_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.mask.nxv2bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.mask.nxv2bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m1_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.mask.nxv4bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.mask.nxv4bf16.bf16.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c (2325 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv32i8.nxv32i8.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c (2326 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_i64m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_i64m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_u64m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_u64m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_i64m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_i64m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_u64m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.t # | ... # `---data was truncated (10240/12089) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005555a761857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005555a7615515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005555a7618cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f93c9449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f93c94a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f93c9449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f93c9431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005555a75ae24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005555a75ae096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005555a7592f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005555a7242176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005555a7241e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f93c9432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f93c94330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f93c94330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005555a7241d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c (2327 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8m2_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c (2328 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_f64m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1f64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_f64m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2f64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_f64m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4f64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_f64m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8f64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_i64m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_i64m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_i64m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_i64m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_u64m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_u64m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | def # | ... # `---data was truncated (10240/26764) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560e8e43d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560e8e43a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560e8e43dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f46f4d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f46f4d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f46f4d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f46f4d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560e8e3d324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560e8e3d3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560e8e3b7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560e8e067176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560e8e066e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f46f4d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f46f4d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f46f4d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560e8e066d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c (2329 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/284336) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056460ba1f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056460ba1c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056460ba1fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd7f8249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd7f82a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd7f8249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd7f8231507 abort ./stdlib/abort.c:85:3 # | #7 0x000056460b9b524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056460b9b5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056460b999f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056460b649176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056460b648e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd7f8232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd7f82330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd7f82330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056460b648d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/bitwise-imm.c (2330 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/bitwise-imm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_n_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = and <8 x i16> %0, splat (i16 11007) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_n_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = and <4 x i32> %0, splat (i32 -252) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_n_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = and <8 x i16> %0, splat (i16 -243) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_n_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = and <4 x i32> %0, splat (i32 -8193) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_n_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = or <8 x i16> %0, splat (i16 195) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_n_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = or <4 x i32> %0, splat (i32 65536) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_n_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = or <8 x i16> %0, splat (i16 -4096) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_n_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = or <4 x i32> %0, splat (i32 8978432) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_n_s16() #0 { # | entry: # | ret <8 x i16> splat (i16 27391) # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_n_s32() #0 { # | entry: # | ret <4 x i32> splat (i32 -5570561) # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_n_u16() #0 { # | entry: # | ret <8 x i16> splat (i16 -18689) # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_n_u32() #0 { # | entry: # | ret <4 x i32> splat (i32 1023410175) # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_m_n_s16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load <8 x i16>, ptr %a.addr, align 8 # | %4 = and <8 x i16> %3, splat (i16 -11265) # | %5 = select <8 x i1> %2, <8 x i16> %4, <8 x i16> %3 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_n_s32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load <4 x i32>, ptr %a.addr, align 8 # | %4 = and <4 x i32> %3, splat (i32 -13893633) # | %5 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %3 # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_m_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load <8 x i16>, ptr %a.addr, align 8 # | %4 = and <8 x i16> %3, splat (i16 -37) # | %5 = select <8 x i1> %2, <8 x i16> %4, <8 x i16> %3 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_n_u32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load <4 x i32>, ptr %a.addr, align 8 # | %4 = and <4 x i32> %3, splat (i32 -1644167169) # | %5 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %3 # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_m_n_s16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load <8 x i16>, ptr %a.addr, align 8 # | %4 = or <8 x i16> %3, splat (i16 13568) # | %5 = select <8 x i1> %2, <8 x i16> %4, <8 x i16> %3 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_n_s32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load <4 x i32>, ptr %a.addr, align 8 # | %4 = or <4 x i32> %3, splat (i32 654311424) # | %5 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %3 # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_m_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load <8 x i16>, ptr %a.addr, align 8 # | %4 = or <8 x i16> %3, splat (i16 175) # | %5 = select <8 x i1> %2, <8 x i16> %4, <8 x i16> %3 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_n_u32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load <4 x i32>, ptr %a.addr, align 8 # | %4 = or <4 x i32> %3, splat (i32 89) # | %5 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %3 # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_m_n_s16(<8 x i16> noundef %inactive, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load <8 x i16>, ptr %inactive.addr, align 8 # | %4 = select <8 x i1> %2, <8 x i16> splat (i16 -3841), <8 x i16> %3 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_m_n_s32(<4 x i32> noundef %inactive, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load <4 x i32>, ptr %inactive.addr, align 8 # | %4 = select <4 x i1> %2, <4 x i32> splat (i32 -18945), <4 x i32> %3 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_m_n_u16(<8 x i16> noundef %inactive, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load <8 x i16>, ptr %inactive.addr, align 8 # | %4 = select <8 x i1> % # | ... # `---data was truncated (10240/13125) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005639a75d557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005639a75d2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005639a75d5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4de2c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4de2ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4de2c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4de2c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005639a756b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005639a756b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005639a754ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005639a71ff176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005639a71fee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4de2c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4de2c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4de2c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005639a71fed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c (2331 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv64i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv64i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv32i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv32i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv16i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv16i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv8i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv8i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv4i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv4i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv2i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv2i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv1i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv1i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv64i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.mask.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv32i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.mask.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv16i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.mask.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv8i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.mask.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b16_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv4i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.mask.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b32_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv2i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nof # | ... # `---data was truncated (10240/11966) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c7bb3bd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c7bb3ba515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c7bb3bdcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7cb1649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7cb16a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7cb1649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7cb1631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c7bb35324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c7bb353096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c7bb337f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c7bafe7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c7bafe6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7cb1632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7cb16330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7cb16330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c7bafe6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c (2332 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d1f86d657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d1f86d3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d1f86d6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdf87e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdf87ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdf87e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdf87e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d1f866c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d1f866c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d1f8650f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d1f8300176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d1f82ffe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fdf87e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdf87e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdf87e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d1f82ffd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c (2333 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_i8mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/69980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005596725a557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005596725a2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005596725a5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f194b305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f194b35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f194b305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f194b2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055967253b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055967253b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055967251ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005596721cf176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005596721cee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f194b2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f194b2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f194b2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005596721ced81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c (2334 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_i8mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/69980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560c5f68b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560c5f688515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560c5f68bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6a9d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6a9d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6a9d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6a9d71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560c5f62124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560c5f621096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560c5f605f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560c5f2b5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560c5f2b4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6a9d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6a9d71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6a9d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560c5f2b4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c (2335 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4e # | ... # `---data was truncated (10240/228857) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055905cde757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055905cde4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055905cde7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2ce9649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2ce96a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2ce9649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2ce9631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055905cd7d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055905cd7d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055905cd61f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055905ca11176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055905ca10e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2ce9632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2ce96330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2ce96330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055905ca10d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c (2336 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16mf4_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16mf2_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m1_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m2_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m4_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m8_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32mf2_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32m1_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv2f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind # | ... # `---data was truncated (10240/77062) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556bf19c157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556bf19be515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556bf19c1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fee90449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fee904a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fee90449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fee90431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556bf195724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556bf1957096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556bf193bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556bf15eb176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556bf15eae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fee90432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fee904330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fee904330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556bf15ead81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c (2337 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define d # | ... # `---data was truncated (10240/12208) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055784c3ed57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055784c3ea515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055784c3edcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2579e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2579ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2579e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2579e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055784c38324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055784c383096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055784c367f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055784c017176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055784c016e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2579e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2579e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2579e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055784c016d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c (2338 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv32i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv32i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vx_i8m4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c (2339 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0. # | ... # `---data was truncated (10240/87884) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005616990e457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005616990e1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005616990e4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb1a0049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb1a00a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb1a0049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb1a0031507 abort ./stdlib/abort.c:85:3 # | #7 0x000056169907a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056169907a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056169905ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561698d0e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561698d0de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb1a0032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb1a00330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb1a00330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561698d0dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c (2340 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564047c9f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564047c9c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564047c9fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbf9c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbf9c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbf9c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbf9c231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564047c3524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564047c35096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564047c19f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005640478c9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005640478c8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbf9c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbf9c2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbf9c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005640478c8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c (2341 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055943c31a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055943c317515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055943c31acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6c58133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6c5818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6c58133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6c5811b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055943c2b024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055943c2b0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055943c294f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055943bf44176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055943bf43e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6c5811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6c5811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6c5811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055943bf43d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c (2342 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_i8mf4x7(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d8bef0157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d8beefe515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d8bef01cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc604a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc604aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc604a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc604a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d8bee9724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d8bee97096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d8bee7bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d8beb2b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d8beb2ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc604a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc604a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc604a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d8beb2ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c (2343 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005631e7d4b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005631e7d48515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005631e7d4bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f10b8b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f10b8b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f10b8b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f10b8b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005631e7ce124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005631e7ce1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005631e7cc5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005631e7975176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005631e7974e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f10b8b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f10b8b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f10b8b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005631e7974d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c (2344 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv16f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv16f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m8_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv32f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv32f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32mf2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv1f32.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32m1_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv2f32.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32m2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c (2345 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_i8mf4x7(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555f6c58a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555f6c587515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555f6c58acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f03fe849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f03fe8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f03fe849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f03fe831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555f6c52024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555f6c520096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555f6c504f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555f6c1b4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555f6c1b3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f03fe832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f03fe8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f03fe8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555f6c1b3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c (2346 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cfd519d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cfd519a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cfd519dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4fa8c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4fa8ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4fa8c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4fa8c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cfd513324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cfd5133096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cfd5117f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cfd4dc7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cfd4dc6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4fa8c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4fa8c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4fa8c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cfd4dc6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c (2347 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv32i8.nxv32i8.i64( %0, # | ... # `---data was truncated (10240/171381) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005603c668957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005603c6686515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005603c6689cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb145733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb14578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb145733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb14571b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005603c661f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005603c661f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005603c6603f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005603c62b3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005603c62b2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb14571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb14571d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb14571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005603c62b2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c (2348 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_i8mf4x8(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560cd9f2857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560cd9f25515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560cd9f28cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f287a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f287a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f287a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f287a431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560cd9ebe24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560cd9ebe096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560cd9ea2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560cd9b52176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560cd9b51e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f287a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f287a4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f287a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560cd9b51d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c (2349 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv1i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv1i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv2i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv2i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv4i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv4i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv8i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv8i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv16i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv16i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; # | ... # `---data was truncated (10240/100289) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005649041e857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005649041e5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005649041e8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f29bba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f29bbaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f29bba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f29bba31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056490417e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056490417e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564904162f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564903e12176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564903e11e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f29bba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f29bba330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f29bba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564903e11d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c (2350 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_i32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_i32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_u32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_u32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32mf2x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple" # | ... # `---data was truncated (10240/35929) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555850b1c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555850b19515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555850b1ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f44a5b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f44a5b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f44a5b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f44a5b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555850ab224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555850ab2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555850a96f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555850746176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555850745e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f44a5b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f44a5b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f44a5b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555850745d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c (2351 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_f64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_i64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_u64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055651ec2d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055651ec2a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055651ec2dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4dcfd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4dcfd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4dcfd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4dcfd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055651ebc324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055651ebc3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055651eba7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055651e857176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055651e856e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4dcfd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4dcfd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4dcfd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055651e856d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vector-shift-var.c (2352 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vector-shift-var.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %0, <16 x i8> %1, i32 0, i32 0, i32 0) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8>, <16 x i8>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0, i32 0, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16>, <8 x i16>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> %0, <4 x i32> %1, i32 0, i32 0, i32 0) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32>, <4 x i32>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %0, <16 x i8> %1, i32 0, i32 0, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0, i32 0, i32 1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> %0, <4 x i32> %1, i32 0, i32 0, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_r_s8(<16 x i8> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i32, align 4 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8> %0, i32 %1, i32 0, i32 0, i32 0) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8>, i32, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_r_s16(<8 x i16> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i32, align 4 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16> %0, i32 %1, i32 0, i32 0, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16>, i32, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_r_s32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32> %0, i32 %1, i32 0, i32 0, i32 0) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32>, i32, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_r_u8(<16 x i8> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i32, align 4 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8> %0, i32 %1, i32 0, i32 0, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_r_u16(<8 x i16> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i32, align 4 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16> %0, i32 %1, i32 0, i32 0, i32 1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_r_u32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32> %0, i32 %1, i32 0, i32 0, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqshlq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1, i32 0, i32 0) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqshlq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %0, <8 x i16> %1, i32 1, i32 0, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqshlq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1, i32 0, i32 0) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqshlq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1, i32 0, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqshlq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %0, <8 x i16> %1, i32 1, i32 0, i32 1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounw # | ... # `---data was truncated (10240/79071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559c3476b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559c34768515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559c3476bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f48fbd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f48fbd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f48fbd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f48fbd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559c3470124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559c34701096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559c346e5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559c34395176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559c34394e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f48fbd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f48fbd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f48fbd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559c34394d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c (2353 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559706c7557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559706c72515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559706c75cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1052333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f105238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1052333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f105231b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559706c0b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559706c0b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559706beff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055970689f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055970689ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f105231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f105231d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f105231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055970689ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c (2354 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv # | ... # `---data was truncated (10240/53726) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055886c9fa57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055886c9f7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055886c9facbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f540b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f540b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f540b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f540b631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055886c99024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055886c990096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055886c974f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055886c624176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055886c623e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f540b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f540b6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f540b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055886c623d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c (2355 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align # | ... # `---data was truncated (10240/52607) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055693689157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055693688e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556936891cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7a69249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7a692a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7a69249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7a69231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055693682724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556936827096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055693680bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005569364bb176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005569364bae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7a69232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7a692330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7a692330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005569364bad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c (2356 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16mf4x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16mf2x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16mf4x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16mf2x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16mf4x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16mf2x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16mf4x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16m1x5_m( %mask, ptr noundef %base, i64 # | ... # `---data was truncated (10240/17523) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562ecabb657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562ecabb3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562ecabb6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f87a0333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f87a038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f87a0333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f87a031b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562ecab4c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562ecab4c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562ecab30f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562eca7e0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562eca7dfe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f87a031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f87a031d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f87a031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562eca7dfd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c (2357 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f65848f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f65848c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f65848fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc2cce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc2ccea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc2cce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc2cce31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f65842524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f658425096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f658409f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f6580b9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f6580b8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc2cce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc2cce330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc2cce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f6580b8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c (2358 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d601cea57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d601ce7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d601ceacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fedaa733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fedaa78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fedaa733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fedaa71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d601c8024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d601c80096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d601c64f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d601914176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d601913e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fedaa71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fedaa71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fedaa71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d601913d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c (2359 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560f4599257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560f4598f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560f45992cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fabd4533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fabd458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fabd4533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fabd451b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560f4592824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560f45928096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560f4590cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560f455bc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560f455bbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fabd451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fabd451d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fabd451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560f455bbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c (2360 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf4_u16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf2_u16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m1_u16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m2_u16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m4_u16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m8_u16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf4_u16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfclass.mask.nxv1bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf2_u16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfclass.mask.nxv2bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m1_u16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfclass.mask.nxv4bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m2_u16m2_tum( %vm, %vd, %vs2, i64 noundef %vl) # # | ... # `---data was truncated (10240/26584) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055efe4bf057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055efe4bed515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055efe4bf0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb137d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb137d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb137d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb137ced507 abort ./stdlib/abort.c:85:3 # | #7 0x000055efe4b8624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055efe4b86096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055efe4b6af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055efe481a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055efe4819e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb137ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb137cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb137cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055efe4819d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c (2361 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c (2362 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561c6d97557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561c6d972515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561c6d975cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0871733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f087178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0871733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f087171b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561c6d90b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561c6d90b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561c6d8eff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561c6d59f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561c6d59ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f087171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f087171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f087171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561c6d59ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c (2363 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562cdd47757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562cdd474515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562cdd477cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5666f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5666f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5666f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5666eed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562cdd40d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562cdd40d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562cdd3f1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562cdd0a1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562cdd0a0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5666eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5666eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5666eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562cdd0a0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c (2364 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfm # | ... # `---data was truncated (10240/65574) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a12ee5757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a12ee54515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a12ee57cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd118905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd11895c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd118905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd1188ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a12eded24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a12eded096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a12edd1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a12ea81176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a12ea80e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd1188eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd1188ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd1188ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a12ea80d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c (2365 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, pt # | ... # `---data was truncated (10240/66557) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005572266d557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005572266d2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005572266d5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0d7f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0d7f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0d7f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0d7f831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055722666b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055722666b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055722664ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005572262ff176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005572262fee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0d7f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0d7f8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0d7f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005572262fed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c (2366 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c396bb157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c396bae515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c396bb1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe33b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe33b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe33b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe33b631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c396b4724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c396b47096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c396b2bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c3967db176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c3967dae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe33b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe33b6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe33b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c3967dad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c (2367 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16mf4x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16mf2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16mf4x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16mf2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8 # | ... # `---data was truncated (10240/15457) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560468d1c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560468d19515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560468d1ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8f8be49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8f8bea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8f8be49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8f8be31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560468cb224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560468cb2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560468c96f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560468946176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560468945e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8f8be32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8f8be330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8f8be330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560468945d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c (2368 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c (2369 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv8bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, al # | ... # `---data was truncated (10240/12389) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564f88a3957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564f88a36515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564f88a39cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbe95049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbe950a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbe95049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbe95031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564f889cf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564f889cf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564f889b3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564f88663176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564f88662e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbe95032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbe950330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbe950330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564f88662d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c (2370 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_v # | ... # `---data was truncated (10240/228865) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005593dad0557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005593dad02515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005593dad05cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efcb741bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efcb74725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efcb741ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efcb7403507 abort ./stdlib/abort.c:85:3 # | #7 0x00005593dac9b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005593dac9b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005593dac7ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005593da92f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005593da92ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efcb7404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efcb74050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efcb74050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005593da92ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c (2371 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv1i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv1i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv2i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv2i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv4i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv4i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv8i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv8i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , al # | ... # `---data was truncated (10240/226593) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a958e9157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a958e8e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a958e91cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff45a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff45a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff45a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff45a51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a958e2724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a958e27096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a958e0bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a958abb176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a958abae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff45a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff45a51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff45a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a958abad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c (2372 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv8i32.nxv8i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv8i32.nxv8i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv16i32.nxv16i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv16i32.nxv16i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i64m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv1i64.nxv1i32.i32.i64( poison, %0, i32 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i64.nxv1i32.i32.i64(, , i32, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i64m2( %src, i64 noundef # | ... # `---data was truncated (10240/29167) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a28801257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a28800f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a288012cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd177b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd177b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd177b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd177b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a287fa824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a287fa8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a287f8cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a287c3c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a287c3be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd177b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd177b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd177b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a287c3bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c (2373 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e75a17657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e75a173515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e75a176cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5747449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f57474a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5747449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5747431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e75a10c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e75a10c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e75a0f0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e759da0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e759d9fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5747432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f57474330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f57474330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e759d9fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c (2374 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_i8mf8x6_tu(target("riscv.vector.tuple", , 6) %m # | ... # `---data was truncated (10240/160133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005589696ce57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005589696cb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005589696cecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3369a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3369a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3369a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3369a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055896966424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558969664096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558969648f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005589692f8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005589692f7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3369a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3369a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3369a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005589692f7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c (2375 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf8x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf4x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf8x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf4x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf8x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf4x3_m( %mask, ptr noundef %bas # | ... # `---data was truncated (10240/20340) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555ce045957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555ce0456515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555ce0459cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c1c41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c1c4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c1c41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c1c403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555ce03ef24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555ce03ef096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555ce03d3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555ce0083176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555ce0082e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2c1c404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c1c4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c1c4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555ce0082d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vadc.c (2376 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vadc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vadciq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %carry_out.addr = alloca ptr, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store ptr %carry_out, ptr %carry_out.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 0) # | %3 = extractvalue { <4 x i32>, i32 } %2, 1 # | %4 = lshr i32 %3, 29 # | %5 = and i32 1, %4 # | %6 = load ptr, ptr %carry_out.addr, align 4 # | store i32 %5, ptr %6, align 4 # | %7 = extractvalue { <4 x i32>, i32 } %2, 0 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32>, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vadcq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %carry.addr = alloca ptr, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store ptr %carry, ptr %carry.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load ptr, ptr %carry.addr, align 4 # | %3 = load i32, ptr %2, align 4 # | %4 = shl i32 %3, 29 # | %5 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 %4) # | %6 = extractvalue { <4 x i32>, i32 } %5, 1 # | %7 = lshr i32 %6, 29 # | %8 = and i32 1, %7 # | store i32 %8, ptr %2, align 4 # | %9 = extractvalue { <4 x i32>, i32 } %5, 0 # | ret <4 x i32> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vadciq_m_u32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %carry_out.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store ptr %carry_out, ptr %carry_out.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %inactive.addr, align 8 # | %1 = load <4 x i32>, ptr %a.addr, align 8 # | %2 = load <4 x i32>, ptr %b.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4) # | %6 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 0, <4 x i1> %5) # | %7 = extractvalue { <4 x i32>, i32 } %6, 1 # | %8 = lshr i32 %7, 29 # | %9 = and i32 1, %8 # | %10 = load ptr, ptr %carry_out.addr, align 4 # | store i32 %9, ptr %10, align 4 # | %11 = extractvalue { <4 x i32>, i32 } %6, 0 # | ret <4 x i32> %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i32>, i32, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vadcq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %carry.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store ptr %carry, ptr %carry.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %inactive.addr, align 8 # | %1 = load <4 x i32>, ptr %a.addr, align 8 # | %2 = load <4 x i32>, ptr %b.addr, align 8 # | %3 = load ptr, ptr %carry.addr, align 4 # | %4 = load i32, ptr %3, align 4 # | %5 = shl i32 %4, 29 # | %6 = load i16, ptr %p.addr, align 2 # | %7 = zext i16 %6 to i32 # | %8 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %7) # | %9 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 %5, <4 x i1> %8) # | %10 = extractvalue { <4 x i32>, i32 } %9, 1 # | %11 = lshr i32 %10, 29 # | %12 = and i32 1, %11 # | store i32 %12, ptr %3, align 4 # | %13 = extractvalue { <4 x i32>, i32 } %9, 0 # | ret <4 x i32> %13 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbciq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %carry_out.addr = alloca ptr, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store ptr %carry_out, ptr %carry_out.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 536870912) # | %3 = extractvalue { <4 x i32>, i32 } %2, 1 # | %4 = lshr i32 %3, 29 # | %5 = and i32 1, %4 # | %6 = load ptr, ptr %carry_out.addr, align 4 # | store i32 %5, ptr %6, align 4 # | %7 = extractvalue { <4 x i32>, i32 } %2, 0 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32>, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbciq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %carry_out.addr = alloca ptr, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store ptr %carry_out, ptr %carry_out.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 536870912) # | %3 = extractvalue { <4 x i32>, i32 } %2, 1 # | %4 = lshr i32 %3, 29 # | %5 = and i32 1, %4 # | %6 = load ptr, ptr %carry_out.addr, align 4 # | store i32 %5, ptr %6, align 4 # | %7 = extractvalue { <4 x i32>, i32 } %2, 0 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbcq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %carry.addr = alloca ptr, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store ptr %carry, ptr %carry.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load ptr, ptr %carry.addr, align 4 # | %3 = load i32, ptr %2, align 4 # | %4 = shl i32 %3, 29 # | %5 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 %4) # | %6 = extractvalue { <4 x i32>, i32 } %5, 1 # | %7 = lshr i32 %6, 29 # | %8 = and i32 1, %7 # | store i32 %8, ptr %2, align 4 # | %9 = extractvalue { <4 x i32>, i32 } %5, 0 # | ret <4 x i32> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbcq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %carry.addr = alloca ptr, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store ptr %carry, ptr %carry.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load ptr, ptr %carry.addr, align 4 # | %3 = load i32, ptr %2, align 4 # | %4 = shl i32 %3, 29 # | %5 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 %4) # | %6 = extractvalue { <4 x i32>, i32 } %5, 1 # | %7 = lshr i32 %6, 29 # | %8 = and i32 1, %7 # | store i32 %8, ptr %2, align 4 # | %9 = extractvalue { <4 x i32>, i32 } %5, 0 # | ret <4 x i32> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbciq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %carry_out.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store ptr %carry_out, ptr %carry_out.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %inactive.addr, align 8 # | %1 = load <4 x i32>, ptr %a.addr, align 8 # | %2 = load <4 x i32>, ptr %b.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4) # | %6 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 536870912, <4 x i1> %5) # | %7 = extractvalue { <4 x i32>, i32 } %6, 1 # | %8 = lshr i32 %7, 29 # | %9 = and i32 1, %8 # | %10 = load ptr, ptr %carry_out.addr, align 4 # | store i32 %9, ptr %10, align 4 # | %11 = extractvalue { <4 x i32>, i32 } %6, 0 # | ret <4 x i32> %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <4 x i32>, i32 } @llvm.arm.mve.vsbc.predicated.v4i32.v4i1(<4 x i32>, # | ... # `---data was truncated (10240/14775) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d2d3d4957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d2d3d46515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d2d3d49cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe9db333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe9db38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe9db333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe9db31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d2d3cdf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d2d3cdf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d2d3cc3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d2d3973176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d2d3972e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe9db31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe9db31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe9db31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d2d3972d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c (2377 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettnt_e8w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.sf.vsettnt.i64(i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettnt_e8w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettnt_e8w4(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettnt_e16w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettnt_e16w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettnt_e16w4(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettnt_e32w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 2, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettnt_e32w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 2, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettnt_e64w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 3, i64 1) # | ret i64 %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055adbaeb357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055adbaeb0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055adbaeb3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6ddd533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6ddd58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6ddd533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6ddd51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055adbae4924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055adbae49096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055adbae2df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055adbaadd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055adbaadce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6ddd51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6ddd51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6ddd51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055adbaadcd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c (2378 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv8f32.nxv8bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv8f32.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m8_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv16f32.nxv16bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv16f32.nxv16bf16.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_ran # | ... # `---data was truncated (10240/10777) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562b1c9f657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562b1c9f3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562b1c9f6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe5b281bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe5b28725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe5b281ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe5b2803507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562b1c98c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562b1c98c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562b1c970f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562b1c620176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562b1c61fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe5b2804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe5b28050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe5b28050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562b1c61fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c (2379 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv1i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv2i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv4i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv8i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv16i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ef9c1aa57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ef9c1a7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ef9c1aacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9f92e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9f92ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9f92e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9f92e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ef9c14024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ef9c140096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ef9c124f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ef9bdd4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ef9bdd3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9f92e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9f92e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9f92e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ef9bdd3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c (2380 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c (2381 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf8_tu( %maskedoff, %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv1i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf4_tu( %maskedoff, %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv2i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf2_tu( %maskedoff, %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv4i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8m1_tu( %maskedoff, %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | de # | ... # `---data was truncated (10240/148020) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005583b064b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005583b0648515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005583b064bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdf20449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdf204a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdf20449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdf20431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005583b05e124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005583b05e1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005583b05c5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005583b0275176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005583b0274e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fdf20432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdf204330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdf204330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005583b0274d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c (2382 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c (2383 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m2_bf16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv8bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv8bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m4_bf16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m8_bf16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m4_bf16m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m8_bf16m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m8_bf16m4( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv16bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv16bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x2_bf16mf4(target("riscv.vector.tuple", , 2) %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %index.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %src.addr, align 2 # | %1 = call @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_2t(target("riscv.vector.tuple", , 2) %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_2t(target("riscv.vector.tuple", , 2), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x3_bf16mf4(target("riscv.vector.tuple", , 3) %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %index.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %src.addr, align 2 # | %1 = call @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_3t(target("riscv.vector.tuple", , 3) %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_3t(target("riscv.vector.tuple", , 3), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x4_bf16mf4(target("riscv.vector.tuple", , 4) %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %index.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %src.addr, align 2 # | %1 = call @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_4t(target("riscv.vector.tuple", , 4) %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_4t(target("riscv.vector.tuple", , 4), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x5_bf16mf4(target("riscv.vector.tuple", , 5) %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %index.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %src.addr, align 2 # | %1 = call @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_5t(target("riscv.vector.tuple", , 5) %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_5t(target("riscv.vector.tuple", , 5), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x6_bf16mf4(target("riscv.vector.tuple", , 6) %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %index.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %src.addr, align 2 # | %1 = call @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_6t(target("riscv.vector.tuple", , 6) %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_6t(target("riscv.vector.tuple", , 6), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x7_bf16mf4(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c (2384 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16mf4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16mf2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv16i16.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv16i16.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv16i16.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv16i16.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vsca # | ... # `---data was truncated (10240/68133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b45f3ae57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b45f3ab515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b45f3aecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f15a861bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f15a86725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f15a861ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f15a8603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b45f34424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b45f344096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b45f328f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b45efd8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b45efd7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f15a8604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f15a86050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f15a86050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b45efd7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c (2385 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f32.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f32.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline noun # | ... # `---data was truncated (10240/121187) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055da95e8157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055da95e7e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055da95e81cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3edbf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3edbf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3edbf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3edbf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055da95e1724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055da95e17096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055da95dfbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055da95aab176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055da95aaae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3edbf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3edbf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3edbf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055da95aaad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c (2386 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f64m1x4(ptr noundef %base, %binde # | ... # `---data was truncated (10240/99754) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cb7e51557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cb7e512515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cb7e515cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fab0da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fab0daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fab0da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fab0da31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cb7e4ab24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cb7e4ab096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cb7e48ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cb7e13f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cb7e13ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fab0da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fab0da330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fab0da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cb7e13ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c (2387 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005626412b257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005626412af515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005626412b2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7f5c61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7f5c6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7f5c61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7f5c603507 abort ./stdlib/abort.c:85:3 # | #7 0x000056264124824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562641248096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056264122cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562640edc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562640edbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7f5c604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7f5c6050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7f5c6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562640edbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c (2388 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055971996157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055971995e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559719961cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efcd1849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efcd18a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efcd1849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efcd1831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005597198f724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005597198f7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005597198dbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055971958b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055971958ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efcd1832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efcd18330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efcd18330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055971958ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c (2389 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettk_e8w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 0, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.sf.vsettk.i64(i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettk_e8w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 0, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettk_e8w4(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 0, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettk_e16w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 1, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettk_e16w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 1, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettk_e16w4(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 1, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettk_e32w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 2, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettk_e32w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 2, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettk_e64w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 3, i64 1) # | ret i64 %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056521843a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000565218437515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056521843acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff19a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff19a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff19a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff19a71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005652183d024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005652183d0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005652183b4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000565218064176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000565218063e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff19a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff19a71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff19a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565218063d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c (2390 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwi # | ... # `---data was truncated (10240/44369) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557887b2657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557887b23515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557887b26cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f04ded33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f04ded8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f04ded33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f04ded1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557887abc24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557887abc096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557887aa0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557887750176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055788774fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f04ded1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f04ded1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f04ded1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055788774fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll (2391 of 27911) ******************** TEST 'Clang :: CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-diagnostic-handler-remarks-with-hotness.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-diagnostic-handler-remarks-with-hotness.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-diagnostic-handler-remarks-with-hotness.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll # | #0 0x000055ae4bc4e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ae4bc4b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ae4bc4ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f371ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f371ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f371ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f371ff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ae4bbe424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ae4bbe4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ae4bbc8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ae4b878176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ae4b877e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f371ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f371ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f371ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ae4b877d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c (2392 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf8_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf4_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf2_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m1_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m2_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m4_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m8_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u16mf4_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u16mf2_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u16m1_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %sc # | ... # `---data was truncated (10240/52741) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560cb3c8b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560cb3c88515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560cb3c8bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc5b3533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc5b358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc5b3533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc5b351b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560cb3c2124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560cb3c21096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560cb3c05f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560cb38b5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560cb38b4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc5b351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc5b351d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc5b351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560cb38b4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c (2393 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m1x4_tum(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c (2394 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vx_u16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wv_u16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wx_u16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.w.nxv1i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vx_u16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wv_u16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wx_u16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.w.nxv2i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vx_u16m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c (2395 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | ... # `---data was truncated (10240/20149) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005632e58d657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005632e58d3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005632e58d6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8856d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8856d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8856d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8856d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005632e586c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005632e586c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005632e5850f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005632e5500176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005632e54ffe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8856d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8856d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8856d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005632e54ffd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c (2396 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c (2397 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m4_tu( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c (2398 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | # | ... # `---data was truncated (10240/26748) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cf938b657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cf938b3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cf938b6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc34aa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc34aaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc34aa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc34aa31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cf9384c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cf9384c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cf93830f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cf934e0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cf934dfe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc34aa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc34aa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc34aa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cf934dfd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c (2399 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c (2400 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf8x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf4x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf8x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf4x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv8i1(target("riscv.vector.tup # | ... # `---data was truncated (10240/11031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558e4126a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558e41267515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558e4126acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8a90649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8a906a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8a90649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8a90631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558e4120024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558e41200096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558e411e4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558e40e94176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558e40e93e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8a90632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8a906330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8a906330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558e40e93d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c (2401 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, a # | ... # `---data was truncated (10240/424843) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dbd1f5457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055dbd1f51515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055dbd1f54cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb419b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb419b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb419b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb419b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dbd1eea24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055dbd1eea096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055dbd1ecef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055dbd1b7e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055dbd1b7de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb419b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb419b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb419b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dbd1b7dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c (2402 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c4fc22957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c4fc226515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c4fc229cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6123c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6123ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6123c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6123c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c4fc1bf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c4fc1bf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c4fc1a3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c4fbe53176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c4fbe52e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6123c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6123c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6123c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c4fbe52d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c (2403 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f01f2c957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f01f2c6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f01f2c9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f51ebf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f51ebf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f51ebf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f51ebf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f01f25f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f01f25f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f01f243f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f01eef3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f01eef2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f51ebf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f51ebf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f51ebf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f01eef2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c (2404 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_i32mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_i32m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_u32mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_u32m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005636ac65557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005636ac652515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005636ac655cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdeec649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdeec6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdeec649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdeec631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005636ac5eb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005636ac5eb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005636ac5cff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005636ac27f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005636ac27ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fdeec632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdeec6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdeec6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005636ac27ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c (2405 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvfwmaccqqq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvfwmaccqqq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e41ad0157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e41acfe515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e41ad01cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0989f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0989f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0989f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0989eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e41ac9724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e41ac97096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e41ac7bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e41a92b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e41a92ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0989eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0989eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0989eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e41a92ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c (2406 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf8_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf4_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf2_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8m1_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c (2407 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_i64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_i64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_u64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_u64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m1x3_tum( %mask, target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m2x3_tum( %mask, target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 # | ... # `---data was truncated (10240/32125) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005557389d257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005557389cf515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005557389d2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb4e3849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb4e38a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb4e3849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb4e3831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055573896824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555738968096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055573894cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005557385fc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005557385fbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb4e3832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb4e38330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb4e38330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005557385fbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c (2408 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", # | ... # `---data was truncated (10240/19492) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005569238a257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055692389f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005569238a2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f459c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f459c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f459c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f459c431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055692383824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556923838096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055692381cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005569234cc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005569234cbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f459c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f459c4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f459c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005569234cbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c (2409 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_i64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_u64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_f64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 5) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_i64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 5) %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_u64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c (2410 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv1i8.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1i8.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv2i8.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2i8.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv4i8.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv4i8.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m1_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv8i8.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv8i8.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv16i8.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv16i8.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv32i8.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv32i8.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv64i8.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv64i8.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv1i8.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv2i8.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_ # | ... # `---data was truncated (10240/15323) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563bbf03357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563bbf030515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563bbf033cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc29b01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc29b0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc29b01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc29b003507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563bbefc924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563bbefc9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563bbefadf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563bbec5d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563bbec5ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc29b004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc29b0050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc29b0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563bbec5cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c (2411 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32mf2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m1_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m4_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c (2412 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf4_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf2_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32.i64(, , , i64 immarg, i64, i64 immarg) # | ... # `---data was truncated (10240/32178) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055894c1dd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055894c1da515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055894c1ddcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb387a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb387aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb387a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb387a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055894c17324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055894c173096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055894c157f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055894be07176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055894be06e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb387a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb387a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb387a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055894be06d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/absneg.c (2413 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/absneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vabsq_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %0) # | ret <8 x half> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.fabs.v8f16(<8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vabsq_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %0) # | ret <4 x float> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.fabs.v4f32(<4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vabsq_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = icmp slt <16 x i8> %0, zeroinitializer # | %2 = sub <16 x i8> zeroinitializer, %0 # | %3 = select <16 x i1> %1, <16 x i8> %2, <16 x i8> %0 # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vabsq_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = icmp slt <8 x i16> %0, zeroinitializer # | %2 = sub <8 x i16> zeroinitializer, %0 # | %3 = select <8 x i1> %1, <8 x i16> %2, <8 x i16> %0 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vabsq_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = icmp slt <4 x i32> %0, zeroinitializer # | %2 = sub <4 x i32> zeroinitializer, %0 # | %3 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %0 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = xor <16 x i8> %0, splat (i8 -1) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = xor <8 x i16> %0, splat (i16 -1) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = xor <4 x i32> %0, splat (i32 -1) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = xor <16 x i8> %0, splat (i8 -1) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = xor <8 x i16> %0, splat (i16 -1) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = xor <4 x i32> %0, splat (i32 -1) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = load <16 x i8>, ptr %inactive.addr, align 8 # | %5 = call <16 x i8> @llvm.arm.mve.mvn.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i1> %3, <16 x i8> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.mvn.predicated.v16i8.v16i1(<16 x i8>, <16 x i1>, <16 x i8>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.mvn.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.mvn.predicated.v8i16.v8i1(<8 x i16>, <8 x i1>, <8 x i16>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x i32>, ptr %inactive.addr, align 8 # | %5 = call <4 x i32> @llvm.arm.mve.mvn.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i1> %3, <4 x i32> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.mvn.predicated.v4i32.v4i1(<4 x i32>, <4 x i1>, <4 x i32>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_m_u8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = load <16 x i8>, ptr %inactive.addr, align 8 # | %5 = call <16 x i8> @llvm.arm.mve.mvn.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i1> %3, <16 x i8> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.mvn.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_m_u32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x i32>, ptr %inactive.addr, align 8 # | %5 = call <4 x i32> @llvm.arm.mve.mvn.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i1> %3, <4 x i32> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_x_s8(<16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = al # | ... # `---data was truncated (10240/40137) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005576c4dff57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005576c4dfc515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005576c4dffcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5073a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5073aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5073a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5073a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005576c4d9524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005576c4d95096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005576c4d79f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005576c4a29176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005576c4a28e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5073a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5073a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5073a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005576c4a28d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c (2414 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b1_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv64i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b2_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv32i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b4_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv16i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b8_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv8i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b16_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv4i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv4i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b32_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv2i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv2i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b64_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv1i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv1i1.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563b8903357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563b89030515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563b89033cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f63da649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f63da6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f63da649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f63da631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563b88fc924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563b88fc9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563b88fadf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563b88c5d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563b88c5ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f63da632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f63da6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f63da6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563b88c5cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/cx-complex-range-real.c (2415 of 27911) ******************** TEST 'Clang :: CodeGen/cx-complex-range-real.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c -O0 -disable-O0-optnone -emit-llvm -triple x86_64-unknown-unknown -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c --check-prefix=FULL # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c -O0 -disable-O0-optnone -emit-llvm -triple x86_64-unknown-unknown -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-unknown" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @mulaf(<2 x float> noundef %a.coerce, float noundef %b) #0 { # | entry: # | %retval = alloca { float, float }, align 4 # | %a = alloca { float, float }, align 4 # | %b.addr = alloca float, align 4 # | store <2 x float> %a.coerce, ptr %a, align 4 # | store float %b, ptr %b.addr, align 4 # | %a.realp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 0 # | %a.real = load float, ptr %a.realp, align 4 # | %a.imagp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 1 # | %a.imag = load float, ptr %a.imagp, align 4 # | %0 = load float, ptr %b.addr, align 4 # | %mul.rl = fmul float %a.real, %0 # | %mul.il = fmul float %a.imag, %0 # | %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0 # | %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1 # | store float %mul.rl, ptr %retval.realp, align 4 # | store float %mul.il, ptr %retval.imagp, align 4 # | %1 = load <2 x float>, ptr %retval, align 4 # | ret <2 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @mulassignf(ptr noundef %a, float noundef %b) #1 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca float, align 4 # | store ptr %a, ptr %a.addr, align 8 # | store float %b, ptr %b.addr, align 4 # | %0 = load float, ptr %b.addr, align 4 # | %1 = load ptr, ptr %a.addr, align 8 # | %.realp = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 0 # | %.real = load float, ptr %.realp, align 4 # | %.imagp = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 1 # | %.imag = load float, ptr %.imagp, align 4 # | %mul.rl = fmul float %.real, %0 # | %mul.il = fmul float %.imag, %0 # | %.realp1 = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 0 # | %.imagp2 = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 1 # | store float %mul.rl, ptr %.realp1, align 4 # | store float %mul.il, ptr %.imagp2, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @mulbf(float noundef %a, <2 x float> noundef %b.coerce) #0 { # | entry: # | %retval = alloca { float, float }, align 4 # | %b = alloca { float, float }, align 4 # | %a.addr = alloca float, align 4 # | store <2 x float> %b.coerce, ptr %b, align 4 # | store float %a, ptr %a.addr, align 4 # | %0 = load float, ptr %a.addr, align 4 # | %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0 # | %b.real = load float, ptr %b.realp, align 4 # | %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1 # | %b.imag = load float, ptr %b.imagp, align 4 # | %mul.rl = fmul float %0, %b.real # | %mul.ir = fmul float %0, %b.imag # | %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0 # | %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1 # | store float %mul.rl, ptr %retval.realp, align 4 # | store float %mul.ir, ptr %retval.imagp, align 4 # | %1 = load <2 x float>, ptr %retval, align 4 # | ret <2 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @divf(<2 x float> noundef %a.coerce, float noundef %b) #0 { # | entry: # | %retval = alloca { float, float }, align 4 # | %a = alloca { float, float }, align 4 # | %b.addr = alloca float, align 4 # | store <2 x float> %a.coerce, ptr %a, align 4 # | store float %b, ptr %b.addr, align 4 # | %a.realp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 0 # | %a.real = load float, ptr %a.realp, align 4 # | %a.imagp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 1 # | %a.imag = load float, ptr %a.imagp, align 4 # | %0 = load float, ptr %b.addr, align 4 # | %1 = fdiv float %a.real, %0 # | %2 = fdiv float %a.imag, %0 # | %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0 # | %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1 # | store float %1, ptr %retval.realp, align 4 # | store float %2, ptr %retval.imagp, align 4 # | %3 = load <2 x float>, ptr %retval, align 4 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @divassignf(ptr noundef %a, float noundef %b) #1 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca float, align 4 # | store ptr %a, ptr %a.addr, align 8 # | store float %b, ptr %b.addr, align 4 # | %0 = load float, ptr %b.addr, align 4 # | %1 = load ptr, ptr %a.addr, align 8 # | %.realp = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 0 # | %.real = load float, ptr %.realp, align 4 # | %.imagp = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 1 # | %.imag = load float, ptr %.imagp, align 4 # | %2 = fdiv float %.real, %0 # | %3 = fdiv float %.imag, %0 # | %.realp1 = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 0 # | %.imagp2 = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 1 # | store float %2, ptr %.realp1, align 4 # | store float %3, ptr %.imagp2, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local { double, double } @divd(double noundef %a.coerce0, double noundef %a.coerce1, double noundef %b) #1 { # | entry: # | %retval = alloca { double, double }, align 8 # | %a = alloca { double, double }, align 8 # | %b.addr = alloca double, align 8 # | %0 = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 0 # | store double %a.coerce0, ptr %0, align 8 # | %1 = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 1 # | store double %a.coerce1, ptr %1, align 8 # | store double %b, ptr %b.addr, align 8 # | %a.realp = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 0 # | %a.real = load double, ptr %a.realp, align 8 # | %a.imagp = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 1 # | %a.imag = load double, ptr %a.imagp, align 8 # | %2 = load double, ptr %b.addr, align 8 # | %3 = fdiv double %a.real, %2 # | %4 = fdiv double %a.imag, %2 # | %retval.realp = getelementptr inbounds nuw { double, double }, ptr %retval, i32 0, i32 0 # | %retval.imagp = getelementptr inbounds nuw { double, double }, ptr %retval, i32 0, i32 1 # | store double %3, ptr %retval.realp, align 8 # | store double %4, ptr %retval.imagp, align 8 # | %5 = load { double, double }, ptr %retval, align 8 # | ret { double, double } %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @divbd(double noundef %a, double noundef %b.coerce0, double noundef %b.coerce1) #0 { # | entry: # | %retval = alloca { float, float }, align 4 # | %b = alloca { double, double }, align 8 # | %a.addr = alloca double, align 8 # | %0 = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 0 # | store double %b.coerce0, ptr %0, align 8 # | %1 = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 1 # | store double %b.coerce1, ptr %1, align 8 # | store double %a, ptr %a.addr, align 8 # | %2 = load double, ptr %a.addr, align 8 # | %b.realp = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 0 # | %b.real = load double, ptr %b.realp, align 8 # | %b.imagp = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 1 # | %b.imag = load double, ptr %b.imagp, align 8 # | %call = call { double, double } @__divdc3(double noundef %2, double noundef 0.000000e+00, double noundef %b.real, double noundef %b.imag) #2 # | %3 = extractvalue { double, double } %call, 0 # | %4 = extractvalue { double, double } %call, 1 # | %conv = fptrunc double %3 to float # | %conv1 = fptrunc double %4 to float # | %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0 # | %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1 # | store float %conv, ptr %retval.realp, align 4 # | store float %conv1, ptr %retval.imagp, align 4 # | %5 = load <2 x float>, ptr %retval, align 4 # | ret <2 x float> %5 # | } # | # | declare { double, double } @__divdc3(double, double, double, double) # | # | ; Function Attrs: noinline nounwind # | define dso_local void @divassignd(ptr noundef %a, double noundef %b) #1 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca double, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store double %b, ptr %b.addr, align 8 # | %0 = load double, ptr %b.addr, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %.realp = getelementptr inbounds nuw { double, double }, ptr %1, i32 0, i32 0 # | %.real = load double, ptr %.realp, align 8 # | %.imagp = getelementptr inbounds nuw { double, double }, ptr %1, i32 0, i32 1 # | %.imag = load double, ptr %.imagp, align 8 # | %2 = fdiv double %.real, %0 # | %3 = fdiv double %.imag, %0 # | %.realp1 = getelementptr inbounds nuw { double, double }, ptr %1, i32 0, i32 0 # | %.imagp2 = getelementptr inbounds nuw { double, double }, ptr %1, i32 0, i32 1 # | store double %2, ptr %.realp1, align 8 # | store double %3, ptr %.imagp2, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local { x86_fp80, x86_fp80 } @divld(ptr noundef byval({ x86_fp80, x86_fp80 }) align 16 %a, x86_fp80 noundef %b) #1 { # | entry: # | %retval = alloca { x86_fp80, x86_fp80 }, align 16 # | %b.addr = alloca x86_fp80, align 16 # | store x86_fp80 %b, ptr %b.addr, align 16 # | %a.realp = getelementptr inbounds nuw { x86_fp80, x86_fp80 }, ptr %a, i32 0, i32 0 # | %a.real = load x86_fp80, ptr %a.realp, align 16 # | %a.imagp = getelementptr inbounds nuw { x86_fp80, x86_fp80 }, ptr %a, i32 0, i32 1 # | %a.imag = load x86_fp80, ptr %a.imagp, align 16 # | %0 = load x86_fp80, ptr %b.addr, align 16 # | %1 = fdiv x86_fp80 %a.real, %0 # | %2 = fdiv x86_fp80 %a.imag, %0 # | %retval.realp = getelementptr inbounds nuw { x86_fp80, x86_fp80 }, ptr %retval, i32 0, i32 0 # | %retval.imagp = getelementptr inbounds nuw { x86_fp80, x86_fp80 }, ptr %retval, i32 0, i32 1 # | store x86_fp80 %1, ptr %retval.realp, align 16 # | store x86_fp80 %2, ptr %retval.imagp, align 16 # | %3 = load { x86_fp80, x86_fp80 }, ptr %retval, align 16 # | ret { x86_fp80, x86_fp80 } %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @divassignld(ptr noundef %a, x86_fp80 noundef %b) #1 { # | entry: # | %a.addr # | ... # `---data was truncated (10240/11567) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x000055c8baa3b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c8baa38515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c8baa3bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4888533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f488858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4888533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f488851b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c8ba9d124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c8ba9d1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c8ba9b5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c8ba665176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c8ba664e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f488851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f488851d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f488851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c8ba664d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c --check-prefix=FULL # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c --check-prefix=FULL # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c (2416 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_f16mf4x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_f16mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_f16m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_f16m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_i16mf4x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_i16mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_i16m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_i16m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_u16mf4x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_u16mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local vo # | ... # `---data was truncated (10240/26928) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c08670857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c086705515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c086708cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1203933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f120398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1203933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f120391b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c08669e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c08669e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c086682f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c086332176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c086331e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f120391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f120391d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f120391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c086331d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c (2417 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_i64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_u64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_f64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_i64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_u64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_f64m1x7_tumu( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 0, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_i64m1x7_tumu( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tu # | ... # `---data was truncated (10240/16560) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a75bfd357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a75bfd0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a75bfd3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efe54333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efe5438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efe54333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efe5431b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a75bf6924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a75bf69096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a75bf4df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a75bbfd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a75bbfce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efe5431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efe5431d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efe5431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a75bbfcd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c (2418 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple # | ... # `---data was truncated (10240/113757) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559f648a757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559f648a4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559f648a7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc887f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc887f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc887f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc887f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559f6483d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559f6483d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559f64821f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559f644d1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559f644d0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc887f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc887f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc887f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559f644d0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c (2419 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_i8mf4x8(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556454c8357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556454c80515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556454c83cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3126849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f31268a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3126849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3126831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556454c1924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556454c19096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556454bfdf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005564548ad176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005564548ace93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3126832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f31268330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f31268330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005564548acd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c (2420 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf8x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv1i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv1i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf4x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf2x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf8x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv1i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf4x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf2x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/12668) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558d9b85f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558d9b85c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558d9b85fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f838af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f838af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f838af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f838af1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558d9b7f524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558d9b7f5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558d9b7d9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558d9b489176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558d9b488e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f838af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f838af1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f838af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558d9b488d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c (2421 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_f16mf4x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_f16mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_f16m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_i16mf4x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_i16mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_i16m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_u16mf4x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_u16mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_u16m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_f16mf4x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsse # | ... # `---data was truncated (10240/20441) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560cbfce757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560cbfce4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560cbfce7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb301533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb30158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb301533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb30151b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560cbfc7d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560cbfc7d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560cbfc61f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560cbf911176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560cbf910e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb30151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb30151d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb30151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560cbf910d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c (2422 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_f16mf4x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_f16mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_f16m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_i16mf4x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_i16mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_i16m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_u16mf4x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_u16mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_u16m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_f16mf4x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.ri # | ... # `---data was truncated (10240/20449) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005625ab58d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005625ab58a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005625ab58dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4047333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f404738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4047333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f404731b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005625ab52324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005625ab523096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005625ab507f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005625ab1b7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005625ab1b6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f404731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f404731d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f404731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005625ab1b6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c (2423 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf4x4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf2x4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16m1x4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16m2x4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf4x4_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf2x4_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16m1x4_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c (2424 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16mf4( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv1f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16mf2( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv2f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m1( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv4f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv4f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m2( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv8f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv8f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m4( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv16f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv16f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m8( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv32f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv32f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32mf2( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv1f32.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32m1( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv2f32.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32m2( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv4f32.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv4f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32m4( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv8f32.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv8f32.i64(, , i # | ... # `---data was truncated (10240/120468) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559381d9957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559381d96515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559381d99cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb9c8e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb9c8ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb9c8e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb9c8e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559381d2f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559381d2f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559381d13f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005593819c3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005593819c2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb9c8e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb9c8e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb9c8e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005593819c2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c (2425 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte8_i8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte8.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vlte8.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte8_u8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte8.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055caab28657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055caab283515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055caab286cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2220049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f22200a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2220049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2220031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055caab21c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055caab21c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055caab200f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055caaaeb0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055caaaeafe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2220032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f22200330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f22200330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055caaaeafd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c (2426 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m1x # | ... # `---data was truncated (10240/25695) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055619209d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055619209a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055619209dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f450c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f450c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f450c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f450c31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055619203324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556192033096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556192017f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556191cc7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556191cc6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f450c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f450c31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f450c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556191cc6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c (2427 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv16bf16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv16bf16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv32bf16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.n # | ... # `---data was truncated (10240/33624) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556a0bb7a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556a0bb77515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556a0bb7acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f384b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f384b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f384b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f384b91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556a0bb1024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556a0bb10096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556a0baf4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556a0b7a4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556a0b7a3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f384b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f384b91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f384b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556a0b7a3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c (2428 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv8i8.nxv8f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c (2429 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555956f1d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555956f1a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555956f1dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9987449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f99874a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9987449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9987431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555956eb324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555956eb3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555956e97f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555956b47176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555956b46e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9987432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f99874330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f99874330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555956b46d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c (2430 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m4_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/riscv-xandesperf-rv32.c (2431 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesperf-rv32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c --check-prefix=CHECK-RV32 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ffb(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.nds.ffb.i32(i32 %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i32 @llvm.riscv.nds.ffb.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ffzmism(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.nds.ffzmism.i32(i32 %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i32 @llvm.riscv.nds.ffzmism.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ffmism(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.nds.ffmism.i32(i32 %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i32 @llvm.riscv.nds.ffmism.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_flmism(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.nds.flmism.i32(i32 %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i32 @llvm.riscv.nds.flmism.i32(i32, i32) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+xandesperf" } # | attributes #1 = { nounwind speculatable memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_xandesperf5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cb5a53d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cb5a53a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cb5a53dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1668c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1668ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1668c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1668c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cb5a4d324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cb5a4d3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cb5a4b7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cb5a167176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cb5a166e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1668c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1668c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1668c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cb5a166d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c --check-prefix=CHECK-RV32 # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c --check-prefix=CHECK-RV32 # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c (2432 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c (2433 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e1 # | ... # `---data was truncated (10240/63053) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a6c5e4157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a6c5e3e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a6c5e41cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3e5ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3e5caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3e5ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3e5ca31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a6c5dd724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a6c5dd7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a6c5dbbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a6c5a6b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a6c5a6ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3e5ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3e5ca330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3e5ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a6c5a6ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c (2434 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv16i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv32i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv32i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv64i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv64i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_u8mf8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_u8mf4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, a # | ... # `---data was truncated (10240/71115) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c0d463357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c0d4630515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c0d4633cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff875333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff87538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff875333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff87531b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c0d45c924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c0d45c9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c0d45adf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c0d425d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c0d425ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff87531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff87531d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff87531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c0d425cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c (2435 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055838bf2157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055838bf1e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055838bf21cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f82d3a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f82d3aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f82d3a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f82d3a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055838beb724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055838beb7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055838be9bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055838bb4b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055838bb4ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f82d3a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f82d3a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f82d3a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055838bb4ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c (2436 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf4x2_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf2x2_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m1x2_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m2x2_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m4x2_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558889ee457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558889ee1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558889ee4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4a59133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4a5918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4a59133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4a5911b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558889e7a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558889e7a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558889e5ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558889b0e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558889b0de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4a5911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4a5911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4a5911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558889b0dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c (2437 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1f64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2f64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4f64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8f64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1i64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2i64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4i64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4i64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8i64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.risc # | ... # `---data was truncated (10240/62752) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056398cce657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056398cce3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056398cce6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2a03049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2a030a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2a03049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2a03031507 abort ./stdlib/abort.c:85:3 # | #7 0x000056398cc7c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056398cc7c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056398cc60f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056398c910176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056398c90fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2a03032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2a030330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2a030330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056398c90fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c (2438 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d69488457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d694881515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d694884cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f89d4f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f89d4f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f89d4f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f89d4f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d69481a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d69481a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d6947fef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d6944ae176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d6944ade93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f89d4f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f89d4f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f89d4f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d6944add81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/get-set-lane.c (2439 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/get-set-lane.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc half @test_vgetq_lane_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = extractelement <8 x half> %0, i32 2 # | ret half %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc float @test_vgetq_lane_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = extractelement <4 x float> %0, i32 3 # | ret float %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc signext i16 @test_vgetq_lane_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = extractelement <8 x i16> %0, i32 4 # | ret i16 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vgetq_lane_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = extractelement <4 x i32> %0, i32 0 # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vgetq_lane_s64(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | %1 = extractelement <2 x i64> %0, i32 0 # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc signext i8 @test_vgetq_lane_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = extractelement <16 x i8> %0, i32 10 # | ret i8 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vgetq_lane_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = extractelement <8 x i16> %0, i32 3 # | ret i16 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vgetq_lane_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = extractelement <4 x i32> %0, i32 3 # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vgetq_lane_u64(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | %1 = extractelement <2 x i64> %0, i32 1 # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vgetq_lane_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = extractelement <16 x i8> %0, i32 1 # | ret i8 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vsetq_lane_f16(half noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca <8 x half>, align 8 # | store half %a, ptr %a.addr, align 2 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %b.addr, align 8 # | %1 = load half, ptr %a.addr, align 2 # | %2 = insertelement <8 x half> %0, half %1, i32 4 # | ret <8 x half> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vsetq_lane_f32(float noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca float, align 4 # | %b.addr = alloca <4 x float>, align 8 # | store float %a, ptr %a.addr, align 4 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %b.addr, align 8 # | %1 = load float, ptr %a.addr, align 4 # | %2 = insertelement <4 x float> %0, float %1, i32 2 # | ret <4 x float> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vsetq_lane_s8(i8 noundef signext %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | %b.addr = alloca <16 x i8>, align 8 # | store i8 %a, ptr %a.addr, align 1 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %b.addr, align 8 # | %1 = load i8, ptr %a.addr, align 1 # | %2 = insertelement <16 x i8> %0, i8 %1, i32 12 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vsetq_lane_s16(i16 noundef signext %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %b.addr = alloca <8 x i16>, align 8 # | store i16 %a, ptr %a.addr, align 2 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %b.addr, align 8 # | %1 = load i16, ptr %a.addr, align 2 # | %2 = insertelement <8 x i16> %0, i16 %1, i32 6 # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsetq_lane_s32(i32 noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %b.addr, align 8 # | %1 = load i32, ptr %a.addr, align 4 # | %2 = insertelement <4 x i32> %0, i32 %1, i32 2 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vsetq_lane_s64(i64 noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <2 x i64>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <2 x i64> %b, ptr %b.addr, align 8 # | %0 = load <2 x i64>, ptr %b.addr, align 8 # | %1 = load i64, ptr %a.addr, align 8 # | %2 = insertelement <2 x i64> %0, i64 %1, i32 0 # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vsetq_lane_u8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | %b.addr = alloca <16 x i8>, align 8 # | store i8 %a, ptr %a.addr, align 1 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %b.addr, align 8 # | %1 = load i8, ptr %a.addr, align 1 # | %2 = insertelement <16 x i8> %0, i8 %1, i32 2 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vsetq_lane_u16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %b.addr = alloca <8 x i16>, align 8 # | store i16 %a, ptr %a.addr, align 2 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %b.addr, align 8 # | %1 = load i16, ptr %a.addr, align 2 # | %2 = insertelement <8 x i16> %0, i16 %1, i32 7 # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsetq_lane_u32(i32 noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %b.addr, align 8 # | %1 = load i32, ptr %a.addr, align 4 # | %2 = insertelement <4 x i32> %0, i32 %1, i32 0 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vsetq_lane_u64(i64 noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <2 x i64>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <2 x i64> %b, ptr %b.addr, align 8 # | %0 = load <2 x i64>, ptr %b.addr, align 8 # | %1 = load i64, ptr %a.addr, align 8 # | %2 = insertelement <2 x i64> %0, i64 %1, i32 1 # | ret <2 x i64> %2 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>' # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<> # | #0 0x000056043d4ab57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056043d4a8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056043d4abcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f99ea133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f99ea18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f99ea133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f99ea11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056043d44124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056043d441096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056043d425f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056043d0d5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056043d0d4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f99ea11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f99ea11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f99ea11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056043d0d4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c (2440 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dc63bca57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055dc63bc7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055dc63bcacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f10b7b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f10b7b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f10b7b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f10b7b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dc63b6024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055dc63b60096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055dc63b44f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055dc637f4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055dc637f3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f10b7b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f10b7b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f10b7b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dc637f3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c (2441 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_f64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_i64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_u64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_f64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_i64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_u64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b4e35e157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b4e35de515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b4e35e1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f07a5f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f07a5f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f07a5f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f07a5f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b4e357724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b4e3577096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b4e355bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b4e320b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b4e320ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f07a5f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f07a5f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f07a5f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b4e320ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c (2442 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32mf2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32mf2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_u32mf2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_u32m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_u3 # | ... # `---data was truncated (10240/11880) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f577fe057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f577fdd515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f577fe0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f010d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f010d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f010d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f010d031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f577f7624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f577f76096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f577f5af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f577c0a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f577c09e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f010d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f010d0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f010d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f577c09d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c (2443 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf4x4(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf2x4(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m1x4(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m2x4(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m1x4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m2x4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055df2e55457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055df2e551515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055df2e554cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff2d2449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff2d24a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff2d2449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff2d2431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055df2e4ea24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055df2e4ea096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055df2e4cef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055df2e17e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055df2e17de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff2d2432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff2d24330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff2d24330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055df2e17dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c (2444 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i32.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv2i32.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv4i32.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv8i32.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv16i32.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i64.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv2i64.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv4i64.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv8i64.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv1i32.nxv1i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv1i32.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv2i32.nxv2i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv2i32.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv4i32.nxv4 # | ... # `---data was truncated (10240/17503) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005647e8bf457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005647e8bf1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005647e8bf4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f015921bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f01592725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f015921ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0159203507 abort ./stdlib/abort.c:85:3 # | #7 0x00005647e8b8a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005647e8b8a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005647e8b6ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005647e881e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005647e881de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0159204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f01592050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f01592050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005647e881dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c (2445 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558ccee9657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558ccee93515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558ccee96cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8c9ea1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8c9ea725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8c9ea1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8c9ea03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558ccee2c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558ccee2c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558ccee10f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558cceac0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558cceabfe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8c9ea04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8c9ea050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8c9ea050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558cceabfd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c (2446 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_f64m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_i64m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_u64m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_f64m1x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_i64m1x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_u64m1x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558a0ee9457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558a0ee91515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558a0ee94cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd50361bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd5036725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd50361ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd503603507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558a0ee2a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558a0ee2a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558a0ee0ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558a0eabe176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558a0eabde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd503604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd5036050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd5036050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558a0eabdd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c (2447 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf2 # | ... # `---data was truncated (10240/54694) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b271b3c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b271b39515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b271b3ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fee77a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fee77a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fee77a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fee77a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b271ad224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b271ad2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b271ab6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b271766176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b271765e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fee77a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fee77a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fee77a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b271765d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c (2448 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_u16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca # | ... # `---data was truncated (10240/60551) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055697564357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556975640515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556975643cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2d23933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2d2398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2d23933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2d2391b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005569755d924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005569755d9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005569755bdf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055697526d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055697526ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2d2391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2d2391d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2d2391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055697526cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c (2449 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560841b4157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560841b3e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560841b41cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4654933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f465498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4654933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f465491b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560841ad724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560841ad7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560841abbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056084176b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056084176ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f465491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f465491d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f465491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056084176ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c (2450 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv16f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv32f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv32f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2i16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4i16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv # | ... # `---data was truncated (10240/83637) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b51c2c857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b51c2c5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b51c2c8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fda8e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fda8e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fda8e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fda8e11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b51c25e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b51c25e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b51c242f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b51bef2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b51bef1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fda8e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fda8e11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fda8e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b51bef1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c (2451 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f2aa60957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f2aa606515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f2aa609cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3d66849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3d668a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3d66849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3d66831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f2aa59f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f2aa59f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f2aa583f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f2aa233176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f2aa232e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3d66832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3d668330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3d668330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f2aa232d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c (2452 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf4x2(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf2x2(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m1x2(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m2x2(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m4x2(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m1x2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m2x2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c (2453 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16mf4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b325dca57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b325dc7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b325dcacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa04e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa04e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa04e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa04e51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b325d6024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b325d60096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b325d44f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b3259f4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b3259f3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa04e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa04e51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa04e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b3259f3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c (2454 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf8x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf4x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf8x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf4x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv8i1(target("riscv.vector.tup # | ... # `---data was truncated (10240/11031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056352f9d457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056352f9d1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056352f9d4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6cab133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6cab18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6cab133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6cab11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056352f96a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056352f96a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056352f94ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056352f5fe176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056352f5fde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6cab11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6cab11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6cab11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056352f5fdd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c (2455 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64( %1, %2, float %3, %0, i64 2, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64( %1, %2, float %3, %0, i64 2, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.ad # | ... # `---data was truncated (10240/26762) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055de1adbe57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055de1adbb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055de1adbecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f466881bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f46688725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f466881ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4668803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055de1ad5424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055de1ad54096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055de1ad38f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055de1a9e8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055de1a9e7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4668804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f46688050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f46688050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055de1a9e7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c (2456 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32mf2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m1_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m4_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m8_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32mf2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m1_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noin # | ... # `---data was truncated (10240/25042) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a07e9fd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a07e9fa515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a07e9fdcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8459449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f84594a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8459449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8459431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a07e99324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a07e993096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a07e977f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a07e627176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a07e626e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8459432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f84594330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f84594330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a07e626d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c (2457 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m4_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c (2458 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564f15c8757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564f15c84515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564f15c87cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8929a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8929a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8929a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8929a03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564f15c1d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564f15c1d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564f15c01f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564f158b1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564f158b0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8929a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8929a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8929a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564f158b0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c (2459 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_i32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_i32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_u32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_u32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32mf2x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret ta # | ... # `---data was truncated (10240/32031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fdde7d157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fdde7ce515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fdde7d1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f21bab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f21bab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f21bab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f21bab1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fdde76724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fdde767096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fdde74bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fdde3fb176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fdde3fae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f21bab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f21bab1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f21bab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fdde3fad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c (2460 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c (2461 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_f16mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_f16mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_f16m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_f16m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_f16m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_i16mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_i16mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_i16m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_i16m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %b # | ... # `---data was truncated (10240/38307) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eb7fdc057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055eb7fdbd515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055eb7fdc0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faa4bc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faa4bc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faa4bc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faa4bc03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eb7fd5624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055eb7fd56096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055eb7fd3af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055eb7f9ea176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055eb7f9e9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007faa4bc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faa4bc050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faa4bc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eb7f9e9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c (2462 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf8_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf4_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf2_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m1_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m2_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m4_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m8_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u16mf4_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557d0fdc457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557d0fdc1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557d0fdc4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3448d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3448d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3448d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3448d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557d0fd5a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557d0fd5a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557d0fd3ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557d0f9ee176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557d0f9ede93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3448d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3448d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3448d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557d0f9edd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c (2463 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16mf4( %op1, %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %index.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16mf4( %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv1f16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv1f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16mf2( %op1, %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %index.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16mf2( %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv2f16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv2f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m1( %op1, %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %index.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16m1( %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv4f16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv4f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m2( %op1, %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %index.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16m2( %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv8f16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv8f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m4( %op1, %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %index.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16m4( %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv16f16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwin # | ... # `---data was truncated (10240/273705) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056418e8ae57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056418e8ab515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056418e8aecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9834905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f983495c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9834905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f98348ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056418e84424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056418e844096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056418e828f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056418e4d8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056418e4d7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f98348eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f98348ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f98348ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056418e4d7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c (2464 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7 # | ... # `---data was truncated (10240/64374) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055aa7765557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055aa77652515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055aa77655cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7e94f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7e94f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7e94f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7e94f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aa775eb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055aa775eb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055aa775cff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055aa7727f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055aa7727ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7e94f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7e94f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7e94f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aa7727ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c (2465 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | # | ... # `---data was truncated (10240/63571) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a2023bc57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a2023b9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a2023bccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fae12d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fae12d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fae12d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fae12ced507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a20235224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a202352096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a202336f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a201fe6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a201fe5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fae12ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fae12cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fae12cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a201fe5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c (2466 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f32.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f32.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16f32.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f32.p0.nxv16i32.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c (2467 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_i8mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/69980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005589556a857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005589556a5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005589556a8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f569a305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f569a35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f569a305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f569a2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055895563e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055895563e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558955622f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005589552d2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005589552d1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f569a2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f569a2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f569a2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005589552d1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c (2468 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_f16mf4x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_f16mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_f16m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_f16m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_i16mf4x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_i16mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_i16m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_i16m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_u16mf4x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_u16mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local vo # | ... # `---data was truncated (10240/26928) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558a617c557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558a617c2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558a617c5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f82b8f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f82b8f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f82b8f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f82b8f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558a6175b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558a6175b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558a6173ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558a613ef176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558a613eee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f82b8f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f82b8f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f82b8f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558a613eed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c (2469 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv16i8.nxv16i16.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv16i8.nxv16i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv16i8.nxv16i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv16i8.nxv16i16.i64.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c (2470 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ... # `---data was truncated (10240/64958) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561a1b12c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561a1b129515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561a1b12ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4724c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4724ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4724c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4724c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561a1b0c224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561a1b0c2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561a1b0a6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561a1ad56176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561a1ad55e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4724c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4724c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4724c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561a1ad55d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c (2471 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv8i8.nxv8f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c (2472 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8mf8() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 5) # | ret i64 %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vsetvlimax.i64(i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8mf4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 6) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8mf2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8m1() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8m2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8m4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8m8() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 3) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16mf4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 6) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16mf2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16m1() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16m2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16m4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16m8() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 3) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e32mf2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e32m1() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e32m2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e32m4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e32m8() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 3) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e64m1() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e64m2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e64m4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e64m8() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 3) # | ret i64 %0 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556c42c9757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556c42c94515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556c42c97cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0d6bf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0d6bf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0d6bf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0d6beed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556c42c2d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556c42c2d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556c42c11f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556c428c1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556c428c0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0d6beeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0d6beef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0d6beef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556c428c0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c (2473 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c4d3eb157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c4d3eae515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c4d3eb1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fab9881bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fab988725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fab9881ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fab98803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c4d3e4724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c4d3e47096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c4d3e2bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c4d3adb176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c4d3adae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fab98804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fab988050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fab988050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c4d3adad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c (2474 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_u16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_u16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), # | ... # `---data was truncated (10240/53330) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056473044557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564730442515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564730445cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f71e721bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f71e72725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f71e721ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f71e7203507 abort ./stdlib/abort.c:85:3 # | #7 0x00005647303db24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005647303db096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005647303bff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056473006f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056473006ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f71e7204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f71e72050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f71e72050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056473006ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c (2475 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf8( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c (2476 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr # | ... # `---data was truncated (10240/29202) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005583bf26057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005583bf25d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005583bf260cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f531b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f531b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f531b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f531b11b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005583bf1f624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005583bf1f6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005583bf1daf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005583bee8a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005583bee89e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f531b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f531b11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f531b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005583bee89d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c (2477 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16m1x7_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558b7d64257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558b7d63f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558b7d642cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1175649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f11756a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1175649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1175631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558b7d5d824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558b7d5d8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558b7d5bcf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558b7d26c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558b7d26be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1175632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f11756330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f11756330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558b7d26bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c (2478 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax. # | ... # `---data was truncated (10240/69313) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560c41d0757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560c41d04515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560c41d07cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f83e1f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f83e1f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f83e1f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f83e1f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560c41c9d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560c41c9d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560c41c81f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560c41931176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560c41930e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f83e1f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f83e1f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f83e1f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560c41930d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqdmullbq.c (2479 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqdmullbq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %1, i32 0) # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32>, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_m_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_m_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <2 x i64>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <2 x i64> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3) # | %5 = load <2 x i64>, ptr %inactive.addr, align 8 # | %6 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %1, i32 0, <2 x i1> %4, <2 x i64> %5) # | ret <2 x i64> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32>, <4 x i32>, i32, <2 x i1>, <2 x i64>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %.splat, i32 0) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %.splat, i32 0) # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_m_n_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %.splat, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_m_n_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <2 x i64>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store <2 x i64> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3) # | %5 = load <2 x i64>, ptr %inactive.addr, align 8 # | %6 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %.splat, i32 0, <2 x i1> %4, <2 x i64> %5) # | ret <2 x i64> %6 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005629a780c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005629a7809515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005629a780ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8192c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8192ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8192c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8192c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005629a77a224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005629a77a2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005629a7786f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005629a7436176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005629a7435e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8192c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8192c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8192c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005629a7435d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c (2480 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056193c0c957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056193c0c6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056193c0c9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f369621bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f36962725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f369621ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3696203507 abort ./stdlib/abort.c:85:3 # | #7 0x000056193c05f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056193c05f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056193c043f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056193bcf3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056193bcf2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3696204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f36962050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f36962050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056193bcf2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c (2481 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32mf2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m1_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 # | ... # `---data was truncated (10240/14429) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056362175257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056362174f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563621752cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdb77049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdb770a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdb77049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdb77031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005636216e824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005636216e8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005636216ccf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056362137c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056362137be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fdb77032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdb770330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdb770330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056362137bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c (2482 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16mf2_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m1_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m2_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m4_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c (2483 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557d0cca657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557d0cca3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557d0cca6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f22b2849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f22b28a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f22b2849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f22b2831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557d0cc3c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557d0cc3c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557d0cc20f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557d0c8d0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557d0c8cfe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f22b2832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f22b28330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f22b28330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557d0c8cfd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c (2484 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005643be70257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005643be6ff515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005643be702cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f81af849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f81af8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f81af849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f81af831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005643be69824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005643be698096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005643be67cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005643be32c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005643be32be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f81af832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f81af8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f81af8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005643be32bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp (2485 of 27911) ******************** TEST 'Clang :: CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O1 -disable-llvm-passes -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp -o - -triple=x86_64-linux-gnu | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=lower-expect -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O1 -disable-llvm-passes -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp -o - -triple=x86_64-linux-gnu # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | ; Function Attrs: mustprogress nounwind # | define dso_local void @_Z3ab1Ri(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 { # | entry: # | %i.addr = alloca ptr, align 8 # | store ptr %i, ptr %i.addr, align 8, !tbaa !6 # | %call = call noundef zeroext i1 @_Z1av() # | br i1 %call, label %land.lhs.true, label %land.end # | # | land.lhs.true: ; preds = %entry # | %call1 = call noundef zeroext i1 @_Z1bv() # | br i1 %call1, label %land.rhs, label %land.end # | # | land.rhs: ; preds = %land.lhs.true # | %call2 = call noundef zeroext i1 @_Z1av() # | br label %land.end # | # | land.end: ; preds = %land.rhs, %land.lhs.true, %entry # | %0 = phi i1 [ false, %land.lhs.true ], [ false, %entry ], [ %call2, %land.rhs ] # | %conv = zext i1 %0 to i64 # | %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1) # | %tobool = icmp ne i64 %expval, 0 # | br i1 %tobool, label %if.then, label %if.else # | # | if.then: ; preds = %land.end # | %1 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | %2 = load i32, ptr %1, align 4, !tbaa !11 # | %inc = add nsw i32 %2, 1 # | store i32 %inc, ptr %1, align 4, !tbaa !11 # | br label %if.end # | # | if.else: ; preds = %land.end # | %3 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | %4 = load i32, ptr %3, align 4, !tbaa !11 # | %dec = add nsw i32 %4, -1 # | store i32 %dec, ptr %3, align 4, !tbaa !11 # | br label %if.end # | # | if.end: ; preds = %if.else, %if.then # | ret void # | } # | # | declare noundef zeroext i1 @_Z1av() #1 # | # | declare noundef zeroext i1 @_Z1bv() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.expect.i64(i64, i64) #2 # | # | ; Function Attrs: mustprogress nounwind # | define dso_local void @_Z2alRi(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 { # | entry: # | %i.addr = alloca ptr, align 8 # | store ptr %i, ptr %i.addr, align 8, !tbaa !6 # | %call = call noundef zeroext i1 @_Z1av() # | %call.expval = call i1 @llvm.expect.i1(i1 %call, i1 true) # | br i1 %call.expval, label %land.lhs.true, label %if.else # | # | land.lhs.true: ; preds = %entry # | %call1 = call noundef zeroext i1 @_Z1bv() # | %call1.expval = call i1 @llvm.expect.i1(i1 %call1, i1 true) # | br i1 %call1.expval, label %land.lhs.true2, label %if.else # | # | land.lhs.true2: ; preds = %land.lhs.true # | %call3 = call noundef zeroext i1 @_Z1cv() # | %call3.expval = call i1 @llvm.expect.i1(i1 %call3, i1 true) # | br i1 %call3.expval, label %if.then, label %if.else # | # | if.then: ; preds = %land.lhs.true2 # | %0 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | %1 = load i32, ptr %0, align 4, !tbaa !11 # | %inc = add nsw i32 %1, 1 # | store i32 %inc, ptr %0, align 4, !tbaa !11 # | br label %if.end # | # | if.else: ; preds = %land.lhs.true2, %land.lhs.true, %entry # | %2 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | %3 = load i32, ptr %2, align 4, !tbaa !11 # | %dec = add nsw i32 %3, -1 # | store i32 %dec, ptr %2, align 4, !tbaa !11 # | br label %if.end # | # | if.end: ; preds = %if.else, %if.then # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i1 @llvm.expect.i1(i1, i1) #2 # | # | declare noundef zeroext i1 @_Z1cv() #1 # | # | ; Function Attrs: mustprogress nounwind # | define dso_local void @_Z3ab0Ri(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 { # | entry: # | %i.addr = alloca ptr, align 8 # | store ptr %i, ptr %i.addr, align 8, !tbaa !6 # | %call = call noundef zeroext i1 @_Z1av() # | br i1 %call, label %land.lhs.true, label %land.end # | # | land.lhs.true: ; preds = %entry # | %call1 = call noundef zeroext i1 @_Z1bv() # | br i1 %call1, label %land.rhs, label %land.end # | # | land.rhs: ; preds = %land.lhs.true # | %call2 = call noundef zeroext i1 @_Z1cv() # | br label %land.end # | # | land.end: ; preds = %land.rhs, %land.lhs.true, %entry # | %0 = phi i1 [ false, %land.lhs.true ], [ false, %entry ], [ %call2, %land.rhs ] # | %conv = zext i1 %0 to i64 # | %expval = call i64 @llvm.expect.i64(i64 %conv, i64 0) # | %tobool = icmp ne i64 %expval, 0 # | br i1 %tobool, label %if.then, label %if.else # | # | if.then: ; preds = %land.end # | %1 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | %2 = load i32, ptr %1, align 4, !tbaa !11 # | %inc = add nsw i32 %2, 1 # | store i32 %inc, ptr %1, align 4, !tbaa !11 # | br label %if.end # | # | if.else: ; preds = %land.end # | %3 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | %4 = load i32, ptr %3, align 4, !tbaa !11 # | %dec = add nsw i32 %4, -1 # | store i32 %dec, ptr %3, align 4, !tbaa !11 # | br label %if.end # | # | if.end: ; preds = %if.else, %if.then # | ret void # | } # | # | ; Function Attrs: mustprogress nounwind # | define dso_local void @_Z2auRi(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 { # | entry: # | %i.addr = alloca ptr, align 8 # | store ptr %i, ptr %i.addr, align 8, !tbaa !6 # | %call = call noundef zeroext i1 @_Z1av() # | br i1 %call, label %land.lhs.true, label %if.else # | # | land.lhs.true: ; preds = %entry # | %call1 = call noundef zeroext i1 @_Z1bv() # | br i1 %call1, label %land.lhs.true2, label %if.else # | # | land.lhs.true2: ; preds = %land.lhs.true # | %call3 = call noundef zeroext i1 @_Z1cv() # | %call3.expval = call i1 @llvm.expect.i1(i1 %call3, i1 false) # | br i1 %call3.expval, label %if.then, label %if.else # | # | if.then: ; preds = %land.lhs.true2 # | %0 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | %1 = load i32, ptr %0, align 4, !tbaa !11 # | %inc = add nsw i32 %1, 1 # | store i32 %inc, ptr %0, align 4, !tbaa !11 # | br label %if.end # | # | if.else: ; preds = %land.lhs.true2, %land.lhs.true, %entry # | %2 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | %3 = load i32, ptr %2, align 4, !tbaa !11 # | %dec = add nsw i32 %3, -1 # | store i32 %dec, ptr %2, align 4, !tbaa !11 # | br label %if.end # | # | if.end: ; preds = %if.else, %if.then # | ret void # | } # | # | ; Function Attrs: mustprogress nounwind # | define dso_local void @_Z3ob1Ri(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 { # | entry: # | %i.addr = alloca ptr, align 8 # | store ptr %i, ptr %i.addr, align 8, !tbaa !6 # | %call = call noundef zeroext i1 @_Z1av() # | br i1 %call, label %lor.end, label %lor.lhs.false # | # | lor.lhs.false: ; preds = %entry # | %call1 = call noundef zeroext i1 @_Z1bv() # | br i1 %call1, label %lor.end, label %lor.rhs # | # | lor.rhs: ; preds = %lor.lhs.false # | %call2 = call noundef zeroext i1 @_Z1av() # | br label %lor.end # | # | lor.end: ; preds = %lor.rhs, %lor.lhs.false, %entry # | %0 = phi i1 [ true, %lor.lhs.false ], [ true, %entry ], [ %call2, %lor.rhs ] # | %conv = zext i1 %0 to i64 # | %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1) # | %tobool = icmp ne i64 %expval, 0 # | br i1 %tobool, label %if.then, label %if.else # | # | if.then: ; preds = %lor.end # | %1 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | store i32 0, ptr %1, align 4, !tbaa !11 # | br label %if.end # | # | if.else: ; preds = %lor.end # | %2 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | %3 = load i32, ptr %2, align 4, !tbaa !11 # | %dec = add nsw i32 %3, -1 # | store i32 %dec, ptr %2, align 4, !tbaa !11 # | br label %if.end # | # | if.end: ; preds = %if.else, %if.then # | ret void # | } # | # | ; Function Attrs: mustprogress nounwind # | define dso_local void @_Z2olRi(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 { # | entry: # | %i.addr = alloca ptr, align 8 # | store ptr %i, ptr %i.addr, align 8, !tbaa !6 # | %call = call noundef zeroext i1 @_Z1av() # | br i1 %call, label %if.then, label %lor.lhs.false # | # | lor.lhs.false: ; preds = %entry # | %call1 = call noundef zeroext i1 @_Z1bv() # | br i1 %call1, label %if.then, label %lor.lhs.false2 # | # | lor.lhs.false2: ; preds = %lor.lhs.false # | %call3 = call noundef zeroext i1 @_Z1cv() # | %call3.expval = call i1 @llvm.expect.i1(i1 %call3, i1 true) # | br i1 %call3.expval, label %if.then, label %if.else # | # | if.then: ; preds = %lor.lhs.false2, %lor.lhs.false, %entry # | %0 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | store i32 0, ptr %0, align 4, !tbaa !11 # | br label %if.end # | # | if.else: ; preds = %lor.lhs.false2 # | %1 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | %2 = load i32, ptr %1, align 4, !tbaa !11 # | %dec = add nsw i32 %2, -1 # | store i32 %dec, ptr %1, align 4, !tbaa !11 # | br label %if.end # | # | if.end: ; preds = %if.else, %if.then # | ret void # | } # | # | ; Function Attrs: mustprogress nounwind # | define dso_local void @_Z3ob0Ri(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 { # | entry: # | %i.addr = alloca ptr, align 8 # | store ptr %i, ptr %i.addr, align 8, !tbaa !6 # | %call = call noundef zeroext i1 @_Z1av() # | br i1 %call, label %lor.end, label %lor.lhs.false # | # | lor.lhs.false: ; preds = %entry # | %call1 = call noundef zeroext i1 @_Z1bv() # | br i1 %call1, label %lor.end, label %lor.rhs # | # | lor.rhs: # | ... # `---data was truncated (10240/28468) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=lower-expect -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=lower-expect -S # | #0 0x000055ad0a0fc57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ad0a0f9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ad0a0fccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd106d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd106d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd106d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd106ced507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ad0a09224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ad0a092096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ad0a076f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ad09d26176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ad09d25e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd106ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd106cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd106cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ad09d25d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c (2486 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561884e7257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561884e6f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561884e72cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efe17d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efe17d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efe17d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efe17d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561884e0824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561884e08096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561884decf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561884a9c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561884a9be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efe17d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efe17d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efe17d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561884a9bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c (2487 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_f16mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_f16mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_f16m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_f16m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_f16m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_i16mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_i16mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_i16m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_i16m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.a # | ... # `---data was truncated (10240/38299) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005564d75ec57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005564d75e9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005564d75eccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2573849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f25738a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2573849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2573831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005564d758224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005564d7582096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005564d7566f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005564d7216176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005564d7215e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2573832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f25738330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f25738330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005564d7215d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c (2488 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8mf8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare < # | ... # `---data was truncated (10240/40411) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561a04e0c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561a04e09515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561a04e0ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f73f5d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f73f5d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f73f5d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f73f5d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561a04da224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561a04da2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561a04d86f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561a04a36176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561a04a35e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f73f5d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f73f5d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f73f5d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561a04a35d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c (2489 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 # | ... # `---data was truncated (10240/66565) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005568a977657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005568a9773515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005568a9776cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f39fc049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f39fc0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f39fc049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f39fc031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005568a970c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005568a970c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005568a96f0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005568a93a0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005568a939fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f39fc032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f39fc0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f39fc0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005568a939fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c (2490 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16mf4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f64m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declar # | ... # `---data was truncated (10240/44434) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560cbc90657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560cbc903515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560cbc906cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6bd6133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6bd618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6bd6133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6bd611b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560cbc89c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560cbc89c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560cbc880f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560cbc530176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560cbc52fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6bd611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6bd611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6bd611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560cbc52fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c (2491 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nx # | ... # `---data was truncated (10240/18660) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564d8b9b257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564d8b9af515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564d8b9b2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc886449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc8864a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc886449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc886431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564d8b94824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564d8b948096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564d8b92cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564d8b5dc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564d8b5dbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc886432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc8864330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc8864330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564d8b5dbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c (2492 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555e8ae8f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555e8ae8c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555e8ae8fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f69e8a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f69e8aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f69e8a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f69e8a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555e8ae2524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555e8ae25096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555e8ae09f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555e8aab9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555e8aab8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f69e8a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f69e8a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f69e8a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555e8aab8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c (2493 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf4x3(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf2x3(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m1x3(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m2x3(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m1x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m2x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tup # | ... # `---data was truncated (10240/11051) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005624a9d2557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005624a9d22515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005624a9d25cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1b85b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1b85b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1b85b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1b85b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005624a9cbb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005624a9cbb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005624a9c9ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005624a994f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005624a994ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1b85b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1b85b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1b85b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005624a994ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c (2494 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf4x4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf2x4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m1x4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m2x4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m1x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m2x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tup # | ... # `---data was truncated (10240/11051) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055637fe3957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055637fe36515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055637fe39cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2f36649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2f366a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2f36649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2f36631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055637fdcf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055637fdcf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055637fdb3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055637fa63176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055637fa62e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2f36632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2f366330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2f366330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055637fa62d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c (2495 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv16i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv32i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv64i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv16i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv32i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv64i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | % # | ... # `---data was truncated (10240/21774) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564a2f44357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564a2f440515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564a2f443cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f110d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f110d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f110d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f110d431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564a2f3d924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564a2f3d9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564a2f3bdf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564a2f06d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564a2f06ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f110d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f110d4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f110d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564a2f06cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c (2496 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c5bdbb257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c5bdbaf515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c5bdbb2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc33eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc33eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc33eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc33eb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c5bdb4824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c5bdb48096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c5bdb2cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c5bd7dc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c5bd7dbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc33eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc33eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc33eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c5bd7dbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c (2497 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32mf2_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m1_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m2_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %ma # | ... # `---data was truncated (10240/18353) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b3936f457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b3936f1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b3936f4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa510b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa510b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa510b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa510b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b39368a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b39368a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b39366ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b39331e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b39331de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa510b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa510b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa510b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b39331dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c (2498 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf8x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf8x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf8x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf4x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c (2499 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c (2500 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32mf2x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_i32mf2x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_i32m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_u32mf2x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_u32m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_i32mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_i32m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_u32mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8 # | ... # `---data was truncated (10240/12059) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056038916357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560389160515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560389163cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffb42f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffb42f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffb42f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffb42f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005603890f924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005603890f9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005603890ddf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560388d8d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560388d8ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ffb42f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffb42f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffb42f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560388d8cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c (2501 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005650b26af57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005650b26ac515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005650b26afcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2174933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f217498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2174933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f217491b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005650b264524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005650b2645096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005650b2629f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005650b22d9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005650b22d8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f217491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f217491d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f217491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005650b22d8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c (2502 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretur # | ... # `---data was truncated (10240/20190) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055de2676457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055de26761515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055de26764cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe2d7305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe2d735c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe2d7305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe2d72ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055de266fa24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055de266fa096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055de266def49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055de2638e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055de2638de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe2d72eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe2d72ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe2d72ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055de2638dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c (2503 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1f64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2f64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4f64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8f64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2i64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4i64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8i64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_u64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c (2504 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b0adb4957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b0adb46515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b0adb49cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fea5c305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fea5c35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fea5c305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fea5c2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b0adadf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b0adadf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b0adac3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b0ad773176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b0ad772e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fea5c2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fea5c2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fea5c2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b0ad772d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c (2505 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | st # | ... # `---data was truncated (10240/11797) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560d8f2a057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560d8f29d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560d8f2a0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3e40049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3e400a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3e40049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3e40031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560d8f23624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560d8f236096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560d8f21af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560d8eeca176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560d8eec9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3e40032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3e400330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3e400330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560d8eec9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c (2506 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562b618c857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562b618c5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562b618c8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f819fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f819fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f819fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f819fe31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562b6185e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562b6185e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562b61842f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562b614f2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562b614f1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f819fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f819fe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f819fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562b614f1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c (2507 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_f32mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1f32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_f32m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2f32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_f32m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4f32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_f32m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8f32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_f32m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv16f32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv16f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_i32mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_i32m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_i32m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4i32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_i32m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8i32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_i32m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.a # | ... # `---data was truncated (10240/33190) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c8094be57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c8094bb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c8094becbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff3d6505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff3d655c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff3d6505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff3d64ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c80945424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c809454096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c809438f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c8090e8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c8090e7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff3d64eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff3d64ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff3d64ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c8090e7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c (2508 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m1x3_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m2x3_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558a8e80857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558a8e805515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558a8e808cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff224d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff224d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff224d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff224ced507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558a8e79e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558a8e79e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558a8e782f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558a8e432176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558a8e431e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff224ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff224cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff224cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558a8e431d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c (2509 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vect # | ... # `---data was truncated (10240/113765) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558f75e4d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558f75e4a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558f75e4dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f59f8049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f59f80a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f59f8049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f59f8031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558f75de324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558f75de3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558f75dc7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558f75a77176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558f75a76e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f59f8032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f59f80330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f59f80330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558f75a76d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c (2510 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @ll # | ... # `---data was truncated (10240/20090) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056286fcda57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056286fcd7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056286fcdacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8256249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f82562a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8256249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8256231507 abort ./stdlib/abort.c:85:3 # | #7 0x000056286fc7024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056286fc70096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056286fc54f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056286f904176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056286f903e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8256232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f82562330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f82562330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056286f903d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c (2511 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32mf2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m1_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m4_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmac # | ... # `---data was truncated (10240/179511) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005626acb9e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005626acb9b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005626acb9ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2860a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2860a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2860a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2860a03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005626acb3424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005626acb34096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005626acb18f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005626ac7c8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005626ac7c7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2860a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2860a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2860a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005626ac7c7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c (2512 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64( %1, %2, %0, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64( %1, %2, %0, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64( %1, %2, %0, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | # | ... # `---data was truncated (10240/43478) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564e4db3357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564e4db30515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564e4db33cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb188a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb188aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb188a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb188a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564e4dac924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564e4dac9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564e4daadf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564e4d75d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564e4d75ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb188a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb188a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb188a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564e4d75cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c (2513 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005575243f157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005575243ee515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005575243f1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f226d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f226d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f226d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f226d31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055752438724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557524387096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055752436bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055752401b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055752401ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f226d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f226d31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f226d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055752401ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c (2514 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_i8mf8x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_i8mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_i8mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_i8m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_u8mf8x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_u8mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_u8mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_u8m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_i8mf8x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, al # | ... # `---data was truncated (10240/21566) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a9b6c9157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a9b6c8e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a9b6c91cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f89ae133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f89ae18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f89ae133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f89ae11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a9b6c2724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a9b6c27096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a9b6c0bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a9b68bb176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a9b68bae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f89ae11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f89ae11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f89ae11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a9b68bad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c (2515 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055658a09d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055658a09a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055658a09dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb3e7b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb3e7b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb3e7b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb3e7b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055658a03324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055658a033096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055658a017f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556589cc7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556589cc6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb3e7b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb3e7b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb3e7b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556589cc6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c (2516 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf4_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf2_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m1_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m2_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m4_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv16bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m8_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv32bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv32bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vlse.mask.nxv1bf16.p0.i64( %1, ptr %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vlse.mask.nxv2bf16.p0.i64( %1, ptr %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 # | ... # `---data was truncated (10240/28361) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558af824757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558af8244515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558af8247cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9be1e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9be1ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9be1e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9be1e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558af81dd24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558af81dd096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558af81c1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558af7e71176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558af7e70e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9be1e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9be1e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9be1e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558af7e70d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c (2517 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005609791a057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056097919d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005609791a0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7a47849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7a478a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7a47849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7a47831507 abort ./stdlib/abort.c:85:3 # | #7 0x000056097913624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560979136096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056097911af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560978dca176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560978dc9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7a47832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7a478330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7a478330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560978dc9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c (2518 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function # | ... # `---data was truncated (10240/66322) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005613ee92957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005613ee926515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005613ee929cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbc22649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbc226a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbc22649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbc22631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005613ee8bf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005613ee8bf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005613ee8a3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005613ee553176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005613ee552e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbc22632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbc226330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbc226330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005613ee552d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c (2519 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f1b5e5257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f1b5e4f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f1b5e52cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe8b0133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe8b018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe8b0133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe8b011b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f1b5de824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f1b5de8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f1b5dccf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f1b5a7c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f1b5a7be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe8b011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe8b011d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe8b011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f1b5a7bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c (2520 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vx_i8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vx_i8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vx_i8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vx_i8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv32i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv32i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vx_i8m4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr % # | ... # `---data was truncated (10240/66087) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f68af9a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f68af97515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f68af9acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2ce4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2ce478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2ce4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2ce471b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f68af3024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f68af30096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f68af14f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f68abc4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f68abc3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2ce471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2ce471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2ce471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f68abc3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c (2521 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none # | ... # `---data was truncated (10240/61673) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e631bf057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e631bed515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e631bf0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f73dc21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f73dc2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f73dc21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f73dc203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e631b8624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e631b86096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e631b6af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e63181a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e631819e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f73dc204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f73dc2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f73dc2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e631819d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c (2522 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_i64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_u64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_f64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 8) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_i64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 8) %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_u64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple # | ... # `---data was truncated (10240/20903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560951f5b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560951f58515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560951f5bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbd27733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbd2778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbd27733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbd2771b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560951ef124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560951ef1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560951ed5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560951b85176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560951b84e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbd2771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbd2771d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbd2771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560951b84d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-v8.2a-neon-intrinsics-generic.c (2523 of 27911) ******************** TEST 'Clang :: CodeGen/arm-v8.2a-neon-intrinsics-generic.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-linux-gnu -target-abi apcs-gnu -target-feature +neon -target-feature -fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c --check-prefixes=CHECK-NOFP16 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-linux-gnu -target-abi apcs-gnu -target-feature +neon -target-feature -fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c" # | target datalayout = "e-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" # | target triple = "armv8.2a-unknown-linux-gnu" # | # | %struct.float16x4x2_t = type { [2 x <4 x half>] } # | %struct.float16x8x2_t = type { [2 x <8 x half>] } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vbsl_f16(<4 x i16> noundef %a, <2 x i32> noundef %b.coerce, <2 x i32> noundef %c.coerce) #0 { # | entry: # | %retval.i = alloca <4 x half>, align 8 # | %__p1.i = alloca <4 x half>, align 8 # | %__p2.i = alloca <4 x half>, align 8 # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %retval = alloca <4 x half>, align 8 # | %b = alloca <4 x half>, align 8 # | %c = alloca <4 x half>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | %coerce = alloca <4 x half>, align 8 # | %coerce3 = alloca <4 x half>, align 8 # | %coerce4 = alloca <4 x half>, align 8 # | store <2 x i32> %b.coerce, ptr %b, align 8 # | %b1 = load <4 x half>, ptr %b, align 8 # | store <2 x i32> %c.coerce, ptr %c, align 8 # | %c2 = load <4 x half>, ptr %c, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x half> %b1, ptr %b.addr, align 8 # | store <4 x half> %c2, ptr %c.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <4 x half> %1, ptr %coerce, align 8 # | %3 = load <2 x i32>, ptr %coerce, align 8 # | store <4 x half> %2, ptr %coerce3, align 8 # | %4 = load <2 x i32>, ptr %coerce3, align 8 # | store <2 x i32> %3, ptr %__p1.i, align 8 # | %__p11.i = load <4 x half>, ptr %__p1.i, align 8 # | store <2 x i32> %4, ptr %__p2.i, align 8 # | %__p22.i = load <4 x half>, ptr %__p2.i, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %__p11.i, ptr %__p1.addr.i, align 8 # | store <4 x half> %__p22.i, ptr %__p2.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %6 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %7 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vbsl_v.i = call <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8> %5, <8 x i8> %6, <8 x i8> %7) # | store <8 x i8> %vbsl_v.i, ptr %ref.tmp.i, align 8 # | %8 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %8, ptr %__ret.i, align 8 # | %9 = load <4 x half>, ptr %__ret.i, align 8 # | store <4 x half> %9, ptr %retval.i, align 8 # | %10 = load <2 x i32>, ptr %retval.i, align 8 # | store <2 x i32> %10, ptr %coerce4, align 8 # | %11 = load <4 x half>, ptr %coerce4, align 8 # | store <4 x half> %11, ptr %retval, align 8 # | %12 = load <2 x i32>, ptr %retval, align 8 # | ret <2 x i32> %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vbslq_f16(<8 x i16> noundef %a, <4 x i32> noundef %b.coerce, <4 x i32> noundef %c.coerce) #0 { # | entry: # | %retval.i = alloca <8 x half>, align 16 # | %__p1.i = alloca <8 x half>, align 16 # | %__p2.i = alloca <8 x half>, align 16 # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %retval = alloca <8 x half>, align 16 # | %b = alloca <8 x half>, align 16 # | %c = alloca <8 x half>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <8 x half>, align 16 # | %coerce = alloca <8 x half>, align 16 # | %coerce3 = alloca <8 x half>, align 16 # | %coerce4 = alloca <8 x half>, align 16 # | store <4 x i32> %b.coerce, ptr %b, align 16 # | %b1 = load <8 x half>, ptr %b, align 16 # | store <4 x i32> %c.coerce, ptr %c, align 16 # | %c2 = load <8 x half>, ptr %c, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | store <8 x half> %b1, ptr %b.addr, align 16 # | store <8 x half> %c2, ptr %c.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | %2 = load <8 x half>, ptr %c.addr, align 16 # | store <8 x half> %1, ptr %coerce, align 16 # | %3 = load <4 x i32>, ptr %coerce, align 16 # | store <8 x half> %2, ptr %coerce3, align 16 # | %4 = load <4 x i32>, ptr %coerce3, align 16 # | store <4 x i32> %3, ptr %__p1.i, align 16 # | %__p11.i = load <8 x half>, ptr %__p1.i, align 16 # | store <4 x i32> %4, ptr %__p2.i, align 16 # | %__p22.i = load <8 x half>, ptr %__p2.i, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %__p11.i, ptr %__p1.addr.i, align 16 # | store <8 x half> %__p22.i, ptr %__p2.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %6 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %7 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vbslq_v.i = call <16 x i8> @llvm.arm.neon.vbsl.v16i8(<16 x i8> %5, <16 x i8> %6, <16 x i8> %7) # | store <16 x i8> %vbslq_v.i, ptr %ref.tmp.i, align 16 # | %8 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %8, ptr %__ret.i, align 16 # | %9 = load <8 x half>, ptr %__ret.i, align 16 # | store <8 x half> %9, ptr %retval.i, align 16 # | %10 = load <4 x i32>, ptr %retval.i, align 16 # | store <4 x i32> %10, ptr %coerce4, align 16 # | %11 = load <8 x half>, ptr %coerce4, align 16 # | store <8 x half> %11, ptr %retval, align 16 # | %12 = load <4 x i32>, ptr %retval, align 16 # | ret <4 x i32> %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vzip_f16(ptr dead_on_unwind noalias writable sret(%struct.float16x4x2_t) align 8 %agg.result, <2 x i32> noundef %a.coerce, <2 x i32> noundef %b.coerce) #0 { # | entry: # | %__p0.i = alloca <4 x half>, align 8 # | %__p1.i = alloca <4 x half>, align 8 # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %a = alloca <4 x half>, align 8 # | %b = alloca <4 x half>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %coerce = alloca <4 x half>, align 8 # | %coerce3 = alloca <4 x half>, align 8 # | store <2 x i32> %a.coerce, ptr %a, align 8 # | %a1 = load <4 x half>, ptr %a, align 8 # | store <2 x i32> %b.coerce, ptr %b, align 8 # | %b2 = load <4 x half>, ptr %b, align 8 # | store <4 x half> %a1, ptr %a.addr, align 8 # | store <4 x half> %b2, ptr %b.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %0, ptr %coerce, align 8 # | %2 = load <2 x i32>, ptr %coerce, align 8 # | store <4 x half> %1, ptr %coerce3, align 8 # | %3 = load <2 x i32>, ptr %coerce3, align 8 # | call void @llvm.experimental.noalias.scope.decl(metadata !3) # | store <2 x i32> %2, ptr %__p0.i, align 8, !noalias !3 # | %__p01.i = load <4 x half>, ptr %__p0.i, align 8, !noalias !3 # | store <2 x i32> %3, ptr %__p1.i, align 8, !noalias !3 # | %__p12.i = load <4 x half>, ptr %__p1.i, align 8, !noalias !3 # | store <4 x half> %__p01.i, ptr %__p0.addr.i, align 8, !noalias !3 # | store <4 x half> %__p12.i, ptr %__p1.addr.i, align 8, !noalias !3 # | %4 = load <8 x i8>, ptr %__p0.addr.i, align 8, !noalias !3 # | %5 = load <8 x i8>, ptr %__p1.addr.i, align 8, !noalias !3 # | %6 = bitcast <8 x i8> %4 to <4 x i16> # | %7 = bitcast <8 x i8> %5 to <4 x i16> # | %vzip.i = shufflevector <4 x i16> %6, <4 x i16> %7, <4 x i32> # | store <4 x i16> %vzip.i, ptr %agg.result, align 4, !alias.scope !3 # | %8 = getelementptr inbounds <4 x i16>, ptr %agg.result, i32 1 # | %vzip3.i = shufflevector <4 x i16> %6, <4 x i16> %7, <4 x i32> # | store <4 x i16> %vzip3.i, ptr %8, align 4, !alias.scope !3 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vzipq_f16(ptr dead_on_unwind noalias writable sret(%struct.float16x8x2_t) align 16 %agg.result, <4 x i32> noundef %a.coerce, <4 x i32> noundef %b.coerce) #0 { # | entry: # | %__p0.i = alloca <8 x half>, align 16 # | %__p1.i = alloca <8 x half>, align 16 # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %a = alloca <8 x half>, align 16 # | %b = alloca <8 x half>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %coerce = alloca <8 x half>, align 16 # | %coerce3 = alloca <8 x half>, align 16 # | store <4 x i32> %a.coerce, ptr %a, align 16 # | %a1 = load <8 x half>, ptr %a, align 16 # | store <4 x i32> %b.coerce, ptr %b, align 16 # | %b2 = load <8 x half>, ptr %b, align 16 # | store <8 x half> %a1, ptr %a.addr, align 16 # | store <8 x half> %b2, ptr %b.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %0, ptr %coerce, align 16 # | %2 = load <4 x i32>, ptr %coerce, align 16 # | store <8 x half> %1, ptr %coerce3, align 16 # | %3 = load <4 x i32>, ptr %coerce3, align 16 # | call void @llvm.experimental.noalias.scope.decl(metadata !6) # | store <4 x i32> %2, ptr %__p0.i, align 16, !noalias !6 # | %__p01.i = load <8 x half>, ptr %__p0.i, align 16, !noalias !6 # | store <4 x i32> %3, ptr %__p1.i, align 16, !noalias !6 # | %__p12.i = load <8 x half>, ptr %__p1.i, align 16, !noalias !6 # | store <8 x half> %__p01.i, ptr %__p0.addr.i, align 16, !noalias !6 # | store <8 x half> %__p12.i, ptr %__p1.addr.i, align 16, !noalias !6 # | %4 = load <16 x i8>, ptr %__p0.addr.i, align 16, !noalias !6 # | %5 = load <16 x i8>, ptr %__p1.addr.i, align 16, !noalias !6 # | %6 = bitcast <16 x i8> %4 to <8 x i16> # | %7 = bitcast <16 x i8> %5 to <8 x i16> # | %vzip.i = shufflevector <8 x i16> %6, <8 x i16> %7, <8 x i32> # | store <8 x i16> %vzip.i, ptr %agg.result, align 4, !alias.scope !6 # | %8 = getelementptr inbounds <8 x i16>, ptr %agg.result, i32 1 # | %vzip3.i = shufflevector <8 x i16> %6, <8 x i16> %7, <8 x i32> # | store <8 x i16> %vzip3.i, ptr %8, align 4, !alias.scope !6 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vuzp_f16(ptr dead_on_unwind noalias writable sret(%struct.float16x4x2_t) align 8 %agg.result, <2 x i32> noundef # | ... # `---data was truncated (10240/35874) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x00005617336e557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005617336e2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005617336e5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcf91e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcf91ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcf91e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcf91e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056173367b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056173367b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056173365ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056173330f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056173330ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcf91e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcf91e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcf91e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056173330ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c --check-prefixes=CHECK-NOFP16 # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c --check-prefixes=CHECK-NOFP16 # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c (2524 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16mf4x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16mf2x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16m1x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16m2x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16m4x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16m1x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("risc # | ... # `---data was truncated (10240/14659) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055886040d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055886040a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055886040dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcb3b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcb3b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcb3b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcb3b91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005588603a324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005588603a3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558860387f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558860037176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558860036e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcb3b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcb3b91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcb3b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558860036d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c (2525 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_i8mf4x6(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a37da5b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a37da58515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a37da5bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa41f705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa41f75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa41f705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa41f6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a37d9f124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a37d9f1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a37d9d5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a37d685176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a37d684e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa41f6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa41f6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa41f6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a37d684d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c (2526 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ed6a61857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ed6a615515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ed6a618cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2d51105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2d5115c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2d51105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2d510ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ed6a5ae24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ed6a5ae096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ed6a592f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ed6a242176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ed6a241e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2d510eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2d510ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2d510ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ed6a241d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c (2527 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1bf16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv2bf16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m1(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv4bf16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv8bf16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv16bf16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m8(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv32bf16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv32bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv1bf16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv2bf16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m1_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv4bf16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv4bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv8bf16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv8bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | defin # | ... # `---data was truncated (10240/13035) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056025f53657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056025f533515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056025f536cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff080533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff08058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff080533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff08051b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056025f4cc24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056025f4cc096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056025f4b0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056025f160176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056025f15fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff08051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff08051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff08051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056025f15fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c (2528 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c05a1f757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c05a1f4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c05a1f7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbade933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbade98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbade933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbade91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c05a18d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c05a18d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c05a171f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c059e21176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c059e20e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbade91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbade91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbade91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c059e20d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c (2529 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16mf4_i8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16mf2_i8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m1_i8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m2_i8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m4_i8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m8_i8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16mf4_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16mf2_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m1_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m2_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m4_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m8_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32bf16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c (2530 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_f32mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_f32m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_i32mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_i32m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_u32mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_u32m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_f32mf2x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_f32m1x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_i32mf2x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_i32m1x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/14010) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fb4ea9a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fb4ea97515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fb4ea9acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f699bf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f699bf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f699bf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f699beed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fb4ea3024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fb4ea30096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fb4ea14f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fb4e6c4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fb4e6c3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f699beeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f699beef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f699beef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fb4e6c3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c (2531 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f32.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f32.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline noun # | ... # `---data was truncated (10240/121187) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d112a0057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d1129fd515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d112a00cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5af6449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5af64a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5af6449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5af6431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d11299624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d112996096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d11297af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d11262a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d112629e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5af6432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5af64330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5af64330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d112629d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c (2532 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv8i8.nxv8f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs # | ... # `---data was truncated (10240/12433) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b1c2fd057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b1c2fcd515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b1c2fd0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5fb1133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5fb118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5fb1133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5fb111b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b1c2f6624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b1c2f66096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b1c2f4af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b1c2bfa176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b1c2bf9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5fb111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5fb111d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5fb111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b1c2bf9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c (2533 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563d3428f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563d3428c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563d3428fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd204d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd204d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd204d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd204d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563d3422524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563d34225096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563d34209f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563d33eb9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563d33eb8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd204d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd204d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd204d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563d33eb8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c (2534 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16mf4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16mf2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m1_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m8_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f32mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f32m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, al # | ... # `---data was truncated (10240/81312) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f6237fc57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f6237f9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f6237fccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb247c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb247ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb247c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb247c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f62379224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f623792096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f623776f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f623426176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f623425e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb247c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb247c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb247c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f623425d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c (2535 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055665b2cd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055665b2ca515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055665b2cdcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9704333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f970438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9704333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f970431b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055665b26324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055665b263096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055665b247f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055665aef7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055665aef6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f970431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f970431d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f970431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055665aef6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c (2536 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_i8mf8x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_i8mf4x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_i8mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_i8m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_i8m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_u8mf8x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_u8mf4x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_u8mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_u8m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_u8m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | cal # | ... # `---data was truncated (10240/23487) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559ec881b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559ec8818515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559ec881bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd93f449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd93f4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd93f449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd93f431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559ec87b124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559ec87b1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559ec8795f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559ec8445176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559ec8444e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd93f432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd93f4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd93f4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559ec8444d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c (2537 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv8i8.nxv8i8.i64(, , , , i # | ... # `---data was truncated (10240/63579) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005654fd8ea57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005654fd8e7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005654fd8eacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f44e921bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f44e92725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f44e921ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f44e9203507 abort ./stdlib/abort.c:85:3 # | #7 0x00005654fd88024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005654fd880096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005654fd864f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005654fd514176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005654fd513e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f44e9204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f44e92050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f44e92050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005654fd513d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-neon-directed-rounding-constrained.c (2538 of 27911) ******************** TEST 'Clang :: CodeGen/arm-neon-directed-rounding-constrained.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8-unknown-linux-gnueabihf" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrndi_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndi_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vrndi_v1.i = call <2 x float> @llvm.nearbyint.v2f32(<2 x float> %vrndi_v.i) # | store <2 x float> %vrndi_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrndiq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vrndiq_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vrndiq_v1.i = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %vrndiq_v.i) # | store <4 x float> %vrndiq_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %2, ptr %__ret.i, align 8 # | %3 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <2 x float> @llvm.nearbyint.v2f32(<2 x float>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.nearbyint.v4f32(<4 x float>) #1 # | # | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a57" "target-features"="+aes,+armv8-a,+crc,+d32,+dsp,+fp-armv8,+fp-armv8d16,+fp-armv8d16sp,+fp-armv8sp,+fp16,+fp64,+hwdiv,+hwdiv-arm,+neon,+sha2,+thumb-mode,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp,+vfp4,+vfp4d16,+vfp4d16sp,+vfp4sp" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1} # | !llvm.ident = !{!2} # | # | !0 = !{i32 1, !"target-abi", !"aapcs-linux"} # | !1 = !{i32 1, !"min_enum_size", i32 4} # | !2 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055aea2eeb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055aea2ee8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055aea2eebcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fac60649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fac606a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fac60649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fac60631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aea2e8124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055aea2e81096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055aea2e65f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055aea2b15176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055aea2b14e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fac60632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fac606330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fac606330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aea2b14d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/2005-06-15-ExpandGotoInternalProblem.c (2539 of 27911) ******************** TEST 'Clang :: CodeGen/2005-06-15-ExpandGotoInternalProblem.c' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wno-error=return-type -std=c99 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 -disable-output # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wno-error=return-type -std=c99 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c -emit-llvm -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | @X = global i32 0, align 4 # | @Y = global i32 0, align 4 # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local i32 @foo() #0 { # | entry: # | %retval = alloca i32, align 4 # | %i = alloca i32, align 4 # | store i32 0, ptr %i, align 4 # | br label %for.cond # | # | for.cond: ; preds = %for.inc, %entry # | %0 = load i32, ptr %i, align 4 # | %cmp = icmp slt i32 %0, 100 # | br i1 %cmp, label %for.body, label %for.end # | # | for.body: ; preds = %for.cond # | br label %for.end # | # | for.inc: ; No predecessors! # | %1 = load i32, ptr %i, align 4 # | %inc = add nsw i32 %1, 1 # | store i32 %inc, ptr %i, align 4 # | br label %for.cond # | # | for.end: ; preds = %for.body, %for.cond # | %2 = load i32, ptr %retval, align 4 # | ret i32 %2 # | } # | # | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # .---command stderr------------ # | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c:13:1: warning: non-void function does not return a value [-Wreturn-type] # | 13 | } # | | ^ # | 1 warning generated. # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 -disable-output # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 -disable-output # | #0 0x0000565103f7c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000565103f79515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000565103f7ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f27c1049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f27c10a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f27c1049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f27c1031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565103f1224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000565103f12096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000565103ef6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000565103ba6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000565103ba5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f27c1032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f27c10330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f27c10330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565103ba5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c (2540 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_f64m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_i64m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_u64m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_f64m1x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_i64m1x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_u64m1x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563070fff57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563070ffc515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563070fffcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3b91d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3b91d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3b91d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3b91d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563070f9524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563070f95096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563070f79f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563070c29176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563070c28e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3b91d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3b91d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3b91d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563070c28d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c (2541 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf4x6_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf2x6_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16m1x6_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b51c3a757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b51c3a4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b51c3a7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8f3f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8f3f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8f3f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8f3f231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b51c33d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b51c33d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b51c321f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b51bfd1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b51bfd0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8f3f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8f3f2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8f3f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b51bfd0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c (2542 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64( %1, %2, float %3, %0, i64 2, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64( %1, %2, float %3, %0, i64 2, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, alig # | ... # `---data was truncated (10240/26754) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b71462157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b71461e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b714621cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6c95333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6c9538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6c95333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6c9531b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b7145b724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b7145b7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b71459bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b71424b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b71424ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6c9531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6c9531d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6c9531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b71424ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c (2543 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf4( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf2( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m1( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv4bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv4bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m2( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv8bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv8bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m4( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv16bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv16bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m8( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv32bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv32bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf4_m( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslideup.mask.nxv1bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.mask.nxv1bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf2_m( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslideup.mask.nxv2bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.mask.nxv2bf16.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c (2544 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c95275a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c952757515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c95275acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efcdf849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efcdf8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efcdf849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efcdf831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c9526f024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c9526f0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c9526d4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c952384176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c952383e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efcdf832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efcdf8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efcdf8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c952383d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c (2545 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_u32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_u32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tupl # | ... # `---data was truncated (10240/53454) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560a72adb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560a72ad8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560a72adbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5b47933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5b4798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5b47933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5b4791b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560a72a7124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560a72a71096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560a72a55f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560a72705176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560a72704e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5b4791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5b4791d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5b4791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560a72704d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c (2546 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vundefined_bf16mf4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vundefined_bf16mf2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vundefined_bf16m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vundefined_bf16m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vundefined_bf16m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vundefined_bf16m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vundefined_bf16mf4x2() #0 { # | entry: # | ret target("riscv.vector.tuple", , 2) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vundefined_bf16mf4x3() #0 { # | entry: # | ret target("riscv.vector.tuple", , 3) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vundefined_bf16mf4x4() #0 { # | entry: # | ret target("riscv.vector.tuple", , 4) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vundefined_bf16mf4x5() #0 { # | entry: # | ret target("riscv.vector.tuple", , 5) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vundefined_bf16mf4x6() #0 { # | entry: # | ret target("riscv.vector.tuple", , 6) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vundefined_bf16mf4x7() #0 { # | entry: # | ret target("riscv.vector.tuple", , 7) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vundefined_bf16mf4x8() #0 { # | entry: # | ret target("riscv.vector.tuple", , 8) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vundefined_bf16mf2x2() #0 { # | entry: # | ret target("riscv.vector.tuple", , 2) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vundefined_bf16mf2x3() #0 { # | entry: # | ret target("riscv.vector.tuple", , 3) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vundefined_bf16mf2x4() #0 { # | entry: # | ret target("riscv.vector.tuple", , 4) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vundefined_bf16mf2x5() #0 { # | entry: # | ret target("riscv.vector.tuple", , 5) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vundefined_bf16mf2x6() #0 { # | entry: # | ret target("riscv.vector.tuple", , 6) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vundefined_bf16mf2x7() #0 { # | entry: # | ret target("riscv.vector.tuple", , 7) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vundefined_bf16mf2x8() #0 { # | entry: # | ret target("riscv.vector.tuple", , 8) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vundefined_bf16m1x2() #0 { # | entry: # | ret target("riscv.vector.tuple", , 2) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vundefined_bf16m1x3() #0 { # | entry: # | ret target("riscv.vector.tuple", , 3) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vundefined_bf16m1x4() #0 { # | entry: # | ret target("riscv.vector.tuple", , 4) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vundefined_bf16m1x5() #0 { # | entry: # | ret target("riscv.vector.tuple", , 5) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vundefined_bf16m1x6() #0 { # | entry: # | ret target("riscv.vector.tuple", , 6) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vundefined_bf16m1x7() #0 { # | entry: # | ret target("riscv.vector.tuple", , 7) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vundefined_bf16m1x8() #0 { # | entry: # | ret target("riscv.vector.tuple", , 8) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vundefined_bf16m2x2() #0 { # | entry: # | ret target("riscv.vector.tuple", , 2) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vundefined_bf16m2x3() #0 { # | entry: # | ret target("riscv.vector.tuple", , 3) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vundefined_bf16m2x4() #0 { # | entry: # | ret target("riscv.vector.tuple", , 4) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vundefined_bf16m4x2() #0 { # | entry: # | ret target("riscv.vector.tuple", , 2) poison # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563c3c44257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563c3c43f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563c3c442cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6cee049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6cee0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6cee049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6cee031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563c3c3d824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563c3c3d8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563c3c3bcf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563c3c06c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563c3c06be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6cee032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6cee0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6cee0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563c3c06bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c (2547 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv4i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv4i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv8i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv8i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv16i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv16i32.i64(, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dd4781f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055dd4781c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055dd4781fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9fc2e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9fc2ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9fc2e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9fc2e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dd477b524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055dd477b5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055dd47799f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055dd47449176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055dd47448e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9fc2e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9fc2e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9fc2e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dd47448d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c (2548 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_i32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_i32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_u32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_u32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32mf2x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple" # | ... # `---data was truncated (10240/35929) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005583ca5f557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005583ca5f2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005583ca5f5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fce41933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fce4198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fce41933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fce4191b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005583ca58b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005583ca58b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005583ca56ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005583ca21f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005583ca21ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fce4191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fce4191d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fce4191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005583ca21ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c (2549 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf4_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf2_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m1_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m2_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m4_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m8_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf4_tum( %mask, %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %src.addr, align 2 # | %3 = load bfloat, ptr %value.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf2_tum( %mask, %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, alig # | ... # `---data was truncated (10240/32578) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055711603157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055711602e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557116031cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3281e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3281ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3281e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3281e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557115fc724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557115fc7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557115fabf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557115c5b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557115c5ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3281e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3281e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3281e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557115c5ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c (2550 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = loa # | ... # `---data was truncated (10240/14529) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056389fc1957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056389fc16515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056389fc19cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f980ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f980ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f980ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f980ef1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056389fbaf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056389fbaf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056389fb93f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056389f843176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056389f842e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f980ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f980ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f980ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056389f842d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminnmaq.c (2551 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminnmaq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %0) # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %2) # | %4 = call <8 x half> @llvm.minnum.v8f16(<8 x half> %1, <8 x half> %3) # | ret <8 x half> %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.fabs.v8f16(<8 x half>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.minnum.v8f16(<8 x half>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmaq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %0) # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %2) # | %4 = call <4 x float> @llvm.minnum.v4f32(<4 x float> %1, <4 x float> %3) # | ret <4 x float> %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.fabs.v4f32(<4 x float>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmaq_m_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x half> @llvm.arm.mve.vminnma.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vminnma.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmaq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x float> @llvm.arm.mve.vminnma.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4) # | ret <4 x float> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.vminnma.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>) #2 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055aae9f9057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055aae9f8d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055aae9f90cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fddba533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fddba58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fddba533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fddba51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aae9f2624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055aae9f26096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055aae9f0af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055aae9bba176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055aae9bb9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fddba51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fddba51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fddba51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aae9bb9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c (2552 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle # | ... # `---data was truncated (10240/18668) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005613b3c7b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005613b3c78515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005613b3c7bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fce04b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fce04b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fce04b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fce04aed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005613b3c1124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005613b3c11096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005613b3bf5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005613b38a5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005613b38a4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fce04aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fce04aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fce04aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005613b38a4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vorrq.c (2553 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vorrq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vorrq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = or <16 x i8> %0, %1 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = or <8 x i16> %0, %1 # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = or <4 x i32> %0, %1 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vorrq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = bitcast <4 x float> %2 to <4 x i32> # | %4 = or <4 x i32> %1, %3 # | %5 = bitcast <4 x i32> %4 to <4 x float> # | ret <4 x float> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vorrq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.orr.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.orr.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vorrq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = bitcast <8 x half> %0 to <8 x i16> # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = bitcast <8 x half> %2 to <8 x i16> # | %4 = load i16, ptr %p.addr, align 2 # | %5 = zext i16 %4 to i32 # | %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5) # | %7 = load <8 x half>, ptr %inactive.addr, align 8 # | %8 = bitcast <8 x half> %7 to <8 x i16> # | %9 = call <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8) # | %10 = bitcast <8 x i16> %9 to <8 x half> # | ret <8 x half> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vorrq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.orr.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vorrq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = bitcast <4 x float> %2 to <4 x i32> # | %4 = load i16, ptr %p.addr, align 2 # | %5 = zext i16 %4 to i32 # | %6 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %5) # | %7 = call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32 # | ... # `---data was truncated (10240/10897) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005586a3ad357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005586a3ad0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005586a3ad3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f966f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f966f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f966f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f966f91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005586a3a6924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005586a3a69096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005586a3a4df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005586a36fd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005586a36fce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f966f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f966f91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f966f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005586a36fcd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c (2554 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16m8(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i8.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i8.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs # | ... # `---data was truncated (10240/15504) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559bc301157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559bc300e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559bc3011cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2309533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f230958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2309533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f230951b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559bc2fa724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559bc2fa7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559bc2f8bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559bc2c3b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559bc2c3ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f230951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f230951d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f230951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559bc2c3ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c (2555 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_u16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, ali # | ... # `---data was truncated (10240/60543) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005641c00ec57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005641c00e9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005641c00eccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff807a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff807aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff807a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff807a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005641c008224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005641c0082096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005641c0066f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005641bfd16176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005641bfd15e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff807a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff807a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff807a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005641bfd15d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c (2556 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16mf4_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16mf4_f32mf2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16mf2_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16mf2_f32m1( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16m1_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16m1_f32m2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16m2_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16m2_f32m4( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.bf16.nxv # | ... # `---data was truncated (10240/51702) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005646fe91357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005646fe910515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005646fe913cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff905d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff905d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff905d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff905d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005646fe8a924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005646fe8a9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005646fe88df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005646fe53d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005646fe53ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff905d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff905d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff905d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005646fe53cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c (2557 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16m1x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557c4553757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557c45534515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557c45537cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5997849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f59978a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5997849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5997831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557c454cd24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557c454cd096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557c454b1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557c45161176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557c45160e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5997832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f59978330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f59978330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557c45160d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c (2558 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005559bf6fa57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005559bf6f7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005559bf6facbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f04c5c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f04c5ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f04c5c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f04c5c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005559bf69024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005559bf690096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005559bf674f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005559bf324176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005559bf323e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f04c5c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f04c5c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f04c5c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005559bf323d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c (2559 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define ds # | ... # `---data was truncated (10240/95215) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555b021cb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555b021c8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555b021cbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa099c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa099ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa099c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa099c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555b0216124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555b02161096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555b02145f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555b01df5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555b01df4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa099c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa099c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa099c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555b01df4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c (2560 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m4_tu( %maskedoff, %op1, # | ... # `---data was truncated (10240/157173) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556f777d957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556f777d6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556f777d9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3b29a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3b29aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3b29a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3b29a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556f7776f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556f7776f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556f77753f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556f77403176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556f77402e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3b29a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3b29a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3b29a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556f77402d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c (2561 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d03d42557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d03d422515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d03d425cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007febe3049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007febe30a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007febe3049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007febe3031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d03d3bb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d03d3bb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d03d39ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d03d04f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d03d04ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007febe3032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007febe30330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007febe30330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d03d04ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-poly-add.c (2562 of 27911) ******************** TEST 'Clang :: CodeGen/arm-poly-add.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-arm-none-eabi -target-feature +neon -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-arm-none-eabi -target-feature +neon -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8.2a-arm-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i8> @test_vadd_p8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %4 = xor <8 x i8> %2, %3 # | store <8 x i8> %4, ptr %ref.tmp.i, align 8 # | %5 = load <8 x i8>, ptr %ref.tmp.i, align 8 # | store <8 x i8> %5, ptr %__ret.i, align 8 # | %6 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i16> @test_vadd_p16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %4 = xor <8 x i8> %2, %3 # | %5 = bitcast <8 x i8> %4 to <4 x i16> # | store <4 x i16> %5, ptr %ref.tmp.i, align 8 # | %6 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %6, ptr %__ret.i, align 8 # | %7 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <1 x i64> @test_vadd_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | %1 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %4 = xor <8 x i8> %2, %3 # | %5 = bitcast <8 x i8> %4 to <1 x i64> # | store <1 x i64> %5, ptr %ref.tmp.i, align 8 # | %6 = load <1 x i64>, ptr %ref.tmp.i, align 8 # | store <1 x i64> %6, ptr %__ret.i, align 8 # | %7 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vaddq_p8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 8 # | %__p1.addr.i = alloca <16 x i8>, align 8 # | %__ret.i = alloca <16 x i8>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | store <16 x i8> %0, ptr %__p0.addr.i, align 8 # | store <16 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %4 = xor <16 x i8> %2, %3 # | store <16 x i8> %4, ptr %ref.tmp.i, align 8 # | %5 = load <16 x i8>, ptr %ref.tmp.i, align 8 # | store <16 x i8> %5, ptr %__ret.i, align 8 # | %6 = load <16 x i8>, ptr %__ret.i, align 8 # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vaddq_p16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 8 # | %__p1.addr.i = alloca <8 x i16>, align 8 # | %__ret.i = alloca <8 x i16>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | store <8 x i16> %0, ptr %__p0.addr.i, align 8 # | store <8 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %4 = xor <16 x i8> %2, %3 # | %5 = bitcast <16 x i8> %4 to <8 x i16> # | store <8 x i16> %5, ptr %ref.tmp.i, align 8 # | %6 = load <8 x i16>, ptr %ref.tmp.i, align 8 # | store <8 x i16> %6, ptr %__ret.i, align 8 # | %7 = load <8 x i16>, ptr %__ret.i, align 8 # | ret <8 x i16> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vaddq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 8 # | %__p1.addr.i = alloca <2 x i64>, align 8 # | %__ret.i = alloca <2 x i64>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <2 x i64>, align 8 # | %b.addr = alloca <2 x i64>, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | store <2 x i64> %b, ptr %b.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | %1 = load <2 x i64>, ptr %b.addr, align 8 # | store <2 x i64> %0, ptr %__p0.addr.i, align 8 # | store <2 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %4 = xor <16 x i8> %2, %3 # | %5 = bitcast <16 x i8> %4 to <2 x i64> # | store <2 x i64> %5, ptr %ref.tmp.i, align 8 # | %6 = load <2 x i64>, ptr %ref.tmp.i, align 8 # | store <2 x i64> %6, ptr %__ret.i, align 8 # | %7 = load <2 x i64>, ptr %__ret.i, align 8 # | ret <2 x i64> %7 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.2-a,+neon,+v8.1a,+v8.2a,-thumb-mode" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x00005630eca0c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005630eca09515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005630eca0ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc985b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc985b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc985b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc985b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005630ec9a224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005630ec9a2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005630ec986f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005630ec636176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005630ec635e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc985b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc985b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc985b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005630ec635d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-neon-vcadd.c (2563 of 27911) ******************** TEST 'Clang :: CodeGen/arm-neon-vcadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.3a-arm-none-eabi -target-cpu generic -target-feature +fullfp16 -mfloat-abi soft -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.3a-arm-none-eabi -target-cpu generic -target-feature +fullfp16 -mfloat-abi soft -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8.3a-arm-none-eabi" # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @foo16x4_rot90(<4 x half> noundef %a, <4 x half> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %result = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vcadd_rot90_f16.i = bitcast <8 x i8> %2 to <4 x half> # | %vcadd_rot90_f161.i = bitcast <8 x i8> %3 to <4 x half> # | %vcadd_rot90_f162.i = call <4 x half> @llvm.arm.neon.vcadd.rot90.v4f16(<4 x half> %vcadd_rot90_f16.i, <4 x half> %vcadd_rot90_f161.i) # | %vcadd_rot90_f163.i = bitcast <4 x half> %vcadd_rot90_f162.i to <8 x i8> # | store <8 x i8> %vcadd_rot90_f163.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %4, ptr %__ret.i, align 8 # | %5 = load <4 x half>, ptr %__ret.i, align 8 # | store <4 x half> %5, ptr %result, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @foo32x2_rot90(<2 x float> noundef %a, <2 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | %result = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vcadd_rot90_f32.i = bitcast <8 x i8> %2 to <2 x float> # | %vcadd_rot90_f321.i = bitcast <8 x i8> %3 to <2 x float> # | %vcadd_rot90_f322.i = call <2 x float> @llvm.arm.neon.vcadd.rot90.v2f32(<2 x float> %vcadd_rot90_f32.i, <2 x float> %vcadd_rot90_f321.i) # | %vcadd_rot90_f323.i = bitcast <2 x float> %vcadd_rot90_f322.i to <8 x i8> # | store <8 x i8> %vcadd_rot90_f323.i, ptr %ref.tmp.i, align 8 # | %4 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %4, ptr %__ret.i, align 8 # | %5 = load <2 x float>, ptr %__ret.i, align 8 # | store <2 x float> %5, ptr %result, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @foo16x8_rot90(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 8 # | %__p1.addr.i = alloca <8 x half>, align 8 # | %__ret.i = alloca <8 x half>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %result = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | store <8 x half> %0, ptr %__p0.addr.i, align 8 # | store <8 x half> %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %vcaddq_rot90_f16.i = bitcast <16 x i8> %2 to <8 x half> # | %vcaddq_rot90_f161.i = bitcast <16 x i8> %3 to <8 x half> # | %vcaddq_rot90_f162.i = call <8 x half> @llvm.arm.neon.vcadd.rot90.v8f16(<8 x half> %vcaddq_rot90_f16.i, <8 x half> %vcaddq_rot90_f161.i) # | %vcaddq_rot90_f163.i = bitcast <8 x half> %vcaddq_rot90_f162.i to <16 x i8> # | store <16 x i8> %vcaddq_rot90_f163.i, ptr %ref.tmp.i, align 8 # | %4 = load <8 x half>, ptr %ref.tmp.i, align 8 # | store <8 x half> %4, ptr %__ret.i, align 8 # | %5 = load <8 x half>, ptr %__ret.i, align 8 # | store <8 x half> %5, ptr %result, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @foo32x4_rot90(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__p1.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %result = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %vcaddq_rot90_f32.i = bitcast <16 x i8> %2 to <4 x float> # | %vcaddq_rot90_f321.i = bitcast <16 x i8> %3 to <4 x float> # | %vcaddq_rot90_f322.i = call <4 x float> @llvm.arm.neon.vcadd.rot90.v4f32(<4 x float> %vcaddq_rot90_f32.i, <4 x float> %vcaddq_rot90_f321.i) # | %vcaddq_rot90_f323.i = bitcast <4 x float> %vcaddq_rot90_f322.i to <16 x i8> # | store <16 x i8> %vcaddq_rot90_f323.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %4, ptr %__ret.i, align 8 # | %5 = load <4 x float>, ptr %__ret.i, align 8 # | store <4 x float> %5, ptr %result, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @foo16x4_rot270(<4 x half> noundef %a, <4 x half> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %result = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vcadd_rot270_f16.i = bitcast <8 x i8> %2 to <4 x half> # | %vcadd_rot270_f161.i = bitcast <8 x i8> %3 to <4 x half> # | %vcadd_rot270_f162.i = call <4 x half> @llvm.arm.neon.vcadd.rot270.v4f16(<4 x half> %vcadd_rot270_f16.i, <4 x half> %vcadd_rot270_f161.i) # | %vcadd_rot270_f163.i = bitcast <4 x half> %vcadd_rot270_f162.i to <8 x i8> # | store <8 x i8> %vcadd_rot270_f163.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %4, ptr %__ret.i, align 8 # | %5 = load <4 x half>, ptr %__ret.i, align 8 # | store <4 x half> %5, ptr %result, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @foo32x2_rot270(<2 x float> noundef %a, <2 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | %result = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vcadd_rot270_f32.i = bitcast <8 x i8> %2 to <2 x float> # | %vcadd_rot270_f321.i = bitcast <8 x i8> %3 to <2 x float> # | %vcadd_rot270_f322.i = call <2 x float> @llvm.arm.neon.vcadd.rot270.v2f32(<2 x float> %vcadd_rot270_f32.i, <2 x float> %vcadd_rot270_f321.i) # | %vcadd_rot270_f323.i = bitcast <2 x float> %vcadd_rot270_f322.i to <8 x i8> # | store <8 x i8> %vcadd_rot270_f323.i, ptr %ref.tmp.i, align 8 # | %4 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %4, ptr %__ret.i, align 8 # | %5 = load <2 x float>, ptr %__ret.i, align 8 # | store <2 x float> %5, ptr %result, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @foo16x8_rot270(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 8 # | %__p1.addr.i = alloca <8 x half>, align 8 # | %__ret.i = alloca <8 x half>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %result = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | store <8 x half> %0, ptr %__p0.addr.i, align 8 # | store <8 x half> %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %vcaddq_rot270_f16.i = bitcast <16 x i8> %2 to <8 x half> # | %vcaddq_rot270_f161.i = bitcast <16 x i8> %3 to <8 x half> # | %vcaddq_rot270_f162.i = call <8 x half> @llvm.arm.neon.vcadd.rot270.v8f16(<8 x half> %vcaddq_rot270_f16.i, <8 x half> %vcaddq_rot270_f161.i) # | %vcaddq_rot270_f163.i = bitcast <8 x half> %vcaddq_rot270_f162.i to <16 x i8> # | store <16 x i8> %vcaddq_rot270_f163.i, ptr %ref.tmp.i, align 8 # | %4 = load <8 x half>, ptr %ref.tmp.i, align 8 # | store <8 x half> %4, ptr %__ret.i, align 8 # | %5 = load <8 x half>, ptr %__ret.i, align 8 # | store <8 x half> %5, ptr %result, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @foo32x4_rot270(<4 x float> noundef %a, <4 # | ... # `---data was truncated (10240/13572) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa -o - # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa -o - # | #0 0x0000557f4a14b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557f4a148515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557f4a14bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f90b9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f90b9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f90b9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f90b9f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557f4a0e124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557f4a0e1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557f4a0c5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557f49d75176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557f49d74e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f90b9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f90b9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f90b9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557f49d74d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c (2564 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv16i32.nxv16i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv16i32.nxv16i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u64m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32.i64( poison, %0, i32 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32.i64(, , i32, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x # | ... # `---data was truncated (10240/29267) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561643a9257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561643a8f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561643a92cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f453b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f453b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f453b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f453b71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561643a2824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561643a28096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561643a0cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005616436bc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005616436bbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f453b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f453b71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f453b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005616436bbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c (2565 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv1bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv2bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv4bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv8bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m4_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv16bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m8_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv32bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(, , bfloat, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557aa9a9257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557aa9a8f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557aa9a92cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efe1c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efe1c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efe1c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efe1c91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557aa9a2824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557aa9a28096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557aa9a0cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557aa96bc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557aa96bbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efe1c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efe1c91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efe1c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557aa96bbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c (2566 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv8i8.nxv8i8.i64(, , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c (2567 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f6215cd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f6215ca515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f6215cdcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f580eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f580eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f580eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f580eb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f62156324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f621563096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f621547f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f6211f7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f6211f6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f580eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f580eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f580eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f6211f6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c (2568 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv8bf16.p0.nxv8i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-feature # | ... # `---data was truncated (10240/10692) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056153403757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561534034515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561534037cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f83b8a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f83b8aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f83b8a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f83b8a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561533fcd24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561533fcd096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561533fb1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561533c61176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561533c60e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f83b8a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f83b8a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f83b8a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561533c60d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-bf16-params-returns.c (2569 of 27911) ******************** TEST 'Clang :: CodeGen/arm-bf16-params-returns.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.6a-arm-none-eabi -target-abi aapcs -mfloat-abi hard -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c --check-prefix=CHECK32-HARD # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.6a-arm-none-eabi -target-abi aapcs -mfloat-abi hard -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8.6a-arm-none-eabi" # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) # | define dso_local arm_aapcs_vfpcc noundef bfloat @test_ret_bf16(bfloat noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret bfloat %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) # | define dso_local arm_aapcs_vfpcc noundef <4 x bfloat> @test_ret_bf16x4_t(<4 x bfloat> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <4 x bfloat> %v # | } # | # | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.6-a,+bf16,+neon,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,-thumb-mode" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | !llvm.errno.tbaa = !{!6} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # | !6 = !{!7, !8, i64 0} # | !7 = !{!"__libc_errno", !8, i64 0} # | !8 = !{!"int", !9, i64 0} # | !9 = !{!"omnipotent char", !10, i64 0} # | !10 = !{!"Simple C/C++ TBAA"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000557a7b9ff57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557a7b9fc515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557a7b9ffcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1f06e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1f06ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1f06e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1f06e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557a7b99524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557a7b995096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557a7b979f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557a7b629176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557a7b628e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1f06e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1f06e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1f06e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557a7b628d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c --check-prefix=CHECK32-HARD # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c --check-prefix=CHECK32-HARD # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c (2570 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv32bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf4_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.mask.nxv1bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf2_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.mask.nxv2bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.mask.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m1_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.add # | ... # `---data was truncated (10240/15312) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056136b87c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056136b879515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056136b87ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2e55a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2e55aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2e55a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2e55a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056136b81224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056136b812096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056136b7f6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056136b4a6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056136b4a5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2e55a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2e55a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2e55a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056136b4a5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/WebAssembly/builtins-table-funcref.c (2571 of 27911) ******************** TEST 'Clang :: CodeGen/WebAssembly/builtins-table-funcref.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple wasm32 -target-feature +reference-types -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple wasm32 -target-feature +reference-types -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c" # | target datalayout = "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-i128:128-n32:64-S128-ni:1:10:20" # | target triple = "wasm32" # | # | @table = internal addrspace(1) global [0 x target("wasm.funcref")] zeroinitializer, align 4 # | @other_table = internal addrspace(1) global [0 x target("wasm.funcref")] zeroinitializer, align 4 # | # | ; Function Attrs: noinline nounwind # | define target("wasm.funcref") @test_builtin_wasm_table_get(i32 noundef %index) #0 { # | entry: # | %index.addr = alloca i32, align 4 # | store i32 %index, ptr %index.addr, align 4 # | %0 = load i32, ptr %index.addr, align 4 # | %1 = call target("wasm.funcref") @llvm.wasm.table.get.funcref(ptr addrspace(1) @table, i32 %0) # | ret target("wasm.funcref") %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("wasm.funcref") @llvm.wasm.table.get.funcref(ptr addrspace(1), i32) #1 # | # | ; Function Attrs: noinline nounwind # | define void @test_builtin_wasm_table_set(i32 noundef %index, target("wasm.funcref") noundef %ref) #0 { # | entry: # | %index.addr = alloca i32, align 4 # | %ref.addr = alloca target("wasm.funcref"), align 4 # | store i32 %index, ptr %index.addr, align 4 # | store target("wasm.funcref") %ref, ptr %ref.addr, align 4 # | %0 = load i32, ptr %index.addr, align 4 # | %1 = load target("wasm.funcref"), ptr %ref.addr, align 4 # | call void @llvm.wasm.table.set.funcref(ptr addrspace(1) @table, i32 %0, target("wasm.funcref") %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.wasm.table.set.funcref(ptr addrspace(1), i32, target("wasm.funcref")) #2 # | # | ; Function Attrs: noinline nounwind # | define i32 @test_builtin_wasm_table_size() #0 { # | entry: # | %0 = call i32 @llvm.wasm.table.size(ptr addrspace(1) @table) # | ret i32 %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare i32 @llvm.wasm.table.size(ptr addrspace(1)) #1 # | # | ; Function Attrs: noinline nounwind # | define i32 @test_builtin_wasm_table_grow(target("wasm.funcref") noundef %ref, i32 noundef %nelem) #0 { # | entry: # | %ref.addr = alloca target("wasm.funcref"), align 4 # | %nelem.addr = alloca i32, align 4 # | store target("wasm.funcref") %ref, ptr %ref.addr, align 4 # | store i32 %nelem, ptr %nelem.addr, align 4 # | %0 = load target("wasm.funcref"), ptr %ref.addr, align 4 # | %1 = load i32, ptr %nelem.addr, align 4 # | %2 = call i32 @llvm.wasm.table.grow.funcref(ptr addrspace(1) @table, target("wasm.funcref") %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare i32 @llvm.wasm.table.grow.funcref(ptr addrspace(1), target("wasm.funcref"), i32) #3 # | # | ; Function Attrs: noinline nounwind # | define void @test_builtin_wasm_table_fill(i32 noundef %index, target("wasm.funcref") noundef %ref, i32 noundef %nelem) #0 { # | entry: # | %index.addr = alloca i32, align 4 # | %ref.addr = alloca target("wasm.funcref"), align 4 # | %nelem.addr = alloca i32, align 4 # | store i32 %index, ptr %index.addr, align 4 # | store target("wasm.funcref") %ref, ptr %ref.addr, align 4 # | store i32 %nelem, ptr %nelem.addr, align 4 # | %0 = load i32, ptr %index.addr, align 4 # | %1 = load target("wasm.funcref"), ptr %ref.addr, align 4 # | %2 = load i32, ptr %nelem.addr, align 4 # | call void @llvm.wasm.table.fill.funcref(ptr addrspace(1) @table, i32 %0, target("wasm.funcref") %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.wasm.table.fill.funcref(ptr addrspace(1), i32, target("wasm.funcref"), i32) #3 # | # | ; Function Attrs: noinline nounwind # | define void @test_table_copy(i32 noundef %dst_idx, i32 noundef %src_idx, i32 noundef %nelem) #0 { # | entry: # | %dst_idx.addr = alloca i32, align 4 # | %src_idx.addr = alloca i32, align 4 # | %nelem.addr = alloca i32, align 4 # | store i32 %dst_idx, ptr %dst_idx.addr, align 4 # | store i32 %src_idx, ptr %src_idx.addr, align 4 # | store i32 %nelem, ptr %nelem.addr, align 4 # | %0 = load i32, ptr %dst_idx.addr, align 4 # | %1 = load i32, ptr %src_idx.addr, align 4 # | %2 = load i32, ptr %nelem.addr, align 4 # | call void @llvm.wasm.table.copy(ptr addrspace(1) @table, ptr addrspace(1) @other_table, i32 %1, i32 %0, i32 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.wasm.table.copy(ptr addrspace(1), ptr addrspace(1), i32, i32, i32) #3 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+reference-types" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(write) } # | attributes #3 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561451cdb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561451cd8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561451cdbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f92fb81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f92fb8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f92fb81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f92fb803507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561451c7124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561451c71096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561451c55f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561451905176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561451904e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f92fb804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f92fb8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f92fb8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561451904d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c (2572 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_f32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_f32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_f32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_i32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_i32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_i32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_u32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_u32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_u32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.v # | ... # `---data was truncated (10240/23413) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056208f46957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056208f466515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056208f469cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb7e8849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb7e88a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb7e8849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb7e8831507 abort ./stdlib/abort.c:85:3 # | #7 0x000056208f3ff24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056208f3ff096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056208f3e3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056208f093176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056208f092e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb7e8832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb7e88330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb7e88330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056208f092d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c (2573 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16mf4x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16mf2x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16m1x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16m1x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562b6083657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562b60833515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562b60836cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc6a9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc6a9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc6a9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc6a9b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562b607cc24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562b607cc096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562b607b0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562b60460176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562b6045fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc6a9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc6a9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc6a9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562b6045fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c (2574 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/87892) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d5408cd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d5408ca515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d5408cdcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f88b9905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f88b995c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f88b9905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f88b98ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d54086324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d540863096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d540847f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d5404f7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d5404f6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f88b98eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f88b98ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f88b98ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d5404f6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c (2575 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | stor # | ... # `---data was truncated (10240/94371) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559ce088a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559ce0887515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559ce088acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa4feb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa4feb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa4feb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa4feb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559ce082024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559ce0820096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559ce0804f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559ce04b4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559ce04b3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa4feb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa4feb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa4feb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559ce04b3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c (2576 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8 # | ... # `---data was truncated (10240/96911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055feb22e657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055feb22e3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055feb22e6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5202849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f52028a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5202849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5202831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055feb227c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055feb227c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055feb2260f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055feb1f10176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055feb1f0fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5202832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f52028330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f52028330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055feb1f0fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c (2577 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_i8mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/69980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562bd197957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562bd1976515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562bd1979cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9331933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f933198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9331933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f933191b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562bd190f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562bd190f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562bd18f3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562bd15a3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562bd15a2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f933191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f933191d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f933191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562bd15a2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vaddq.c (2578 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vaddq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c --check-prefixes=CHECK,CHECK-NONSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vaddq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = add <4 x i32> %0, %1 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vaddq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = fadd <8 x half> %0, %1 # | ret <8 x half> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vaddq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.add.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.add.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vaddq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x float>, ptr %inactive.addr, align 8 # | %6 = call <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4, <4 x float> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vaddq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.add.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.add.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vaddq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x half> @llvm.arm.mve.add.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4, <8 x half> undef) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.add.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vaddq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = add <4 x i32> %0, %.splat # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vaddq_n_f16(<8 x half> noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca half, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store half %b, ptr %b.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load half, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x half> poison, half %1, i64 0 # | %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer # | %2 = fadd <8 x half> %0, %.splat # | ret <8 x half> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vaddq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.add.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vaddq_m_n_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, float noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca float, align 4 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store float %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load float, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x float> poison, float %1, i64 0 # | %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x float>, ptr %inactive.addr, align 8 # | %6 = call <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %.splat, <4 x i1> %4, <4 x float> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vaddq_x_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.add.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @t # | ... # `---data was truncated (10240/11617) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x00005652367d657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005652367d3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005652367d6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4e4dd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4e4dd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4e4dd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4e4dced507 abort ./stdlib/abort.c:85:3 # | #7 0x000056523676c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056523676c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000565236750f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000565236400176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005652363ffe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4e4dceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4e4dcef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4e4dcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005652363ffd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c --check-prefixes=CHECK,CHECK-NONSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c --check-prefixes=CHECK,CHECK-NONSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c (2579 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, ali # | ... # `---data was truncated (10240/14621) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560892a0257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005608929ff515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560892a02cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0cb2449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0cb24a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0cb2449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0cb2431507 abort ./stdlib/abort.c:85:3 # | #7 0x000056089299824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560892998096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056089297cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056089262c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056089262be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0cb2432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0cb24330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0cb24330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056089262bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c (2580 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f64m1x4(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/thinlto-funcattr-prop.ll (2581 of 27911) ******************** TEST 'Clang :: CodeGen/thinlto-funcattr-prop.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 5 split-file /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-funcattr-prop.ll /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp # executed command: split-file /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-funcattr-prop.ll /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp # RUN: at line 6 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.bc # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.bc # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.bc # | #0 0x000055582321a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555823217515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055582321acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f476b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f476b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f476b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f476b91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005558231b024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005558231b0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555823194f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555822e44176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555822e43e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f476b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f476b91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f476b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555822e43d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c (2582 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv16bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv32bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf4_m( %mask, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(, , bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf2_m( %mask, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.mask.nxv2bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.mask.nxv2bf16.bf16.i64(, , bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m1_m( %mask, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.mask.nxv4bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.mask.nxv4bf16.bf16.i64(, , bfloat, , i # | ... # `---data was truncated (10240/14788) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563ca209557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563ca2092515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563ca2095cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f691eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f691eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f691eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f691eb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563ca202b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563ca202b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563ca200ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563ca1cbf176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563ca1cbee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f691eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f691eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f691eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563ca1cbed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c (2583 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf4_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf2_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m1_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m2_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m4_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m8_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf4_tum( %mask, %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %src.addr, align 2 # | %3 = load bfloat, ptr %value.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf2_tum( %mask, %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load # | ... # `---data was truncated (10240/32702) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f1a54a957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f1a54a6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f1a54a9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fef66049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fef660a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fef66049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fef66031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f1a543f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f1a543f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f1a5423f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f1a50d3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f1a50d2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fef66032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fef660330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fef660330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f1a50d2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c (2584 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558c1d79e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558c1d79b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558c1d79ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f288bd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f288bd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f288bd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f288bced507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558c1d73424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558c1d734096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558c1d718f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558c1d3c8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558c1d3c7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f288bceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f288bcef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f288bcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558c1d3c7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c (2585 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m1_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, # | ... # `---data was truncated (10240/26468) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056137c9f457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056137c9f1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056137c9f4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5e93133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5e9318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5e93133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5e9311b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056137c98a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056137c98a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056137c96ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056137c61e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056137c61de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5e9311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5e9311d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5e9311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056137c61dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c (2586 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_f16mf4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_f16mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_f16m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_f16m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_f16m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_i16mf4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_i16mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_i16m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_i16m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_i16m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, p # | ... # `---data was truncated (10240/33435) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560eae3f057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560eae3ed515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560eae3f0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd8b6f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd8b6f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd8b6f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd8b6f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560eae38624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560eae386096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560eae36af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560eae01a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560eae019e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd8b6f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd8b6f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd8b6f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560eae019d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c (2587 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056310906457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563109061515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563109064cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0a7d705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0a7d75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0a7d705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0a7d6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563108ffa24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563108ffa096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563108fdef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563108c8e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563108c8de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0a7d6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0a7d6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0a7d6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563108c8dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c (2588 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf8x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf8x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf8x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %m # | ... # `---data was truncated (10240/22258) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056004467357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560044670515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560044673cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3074e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3074e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3074e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3074e03507 abort ./stdlib/abort.c:85:3 # | #7 0x000056004460924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560044609096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005600445edf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056004429d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056004429ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3074e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3074e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3074e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056004429cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c (2589 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64(, , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c (2590 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | ... # `---data was truncated (10240/34356) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c4eea7e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c4eea7b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c4eea7ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdc01b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdc01b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdc01b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdc01b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c4eea1424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c4eea14096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c4ee9f8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c4ee6a8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c4ee6a7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fdc01b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdc01b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdc01b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c4ee6a7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c (2591 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf4x8_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf2x8_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16m1x8_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005639277d557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005639277d2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005639277d5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3d16a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3d16aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3d16a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3d16a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056392776b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056392776b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056392774ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005639273ff176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005639273fee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3d16a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3d16a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3d16a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005639273fed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c (2592 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf8_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf4_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf2_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m1_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m2_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m4_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m8_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u16mf4_u32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv2i32.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv2i32.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u16mf2_u32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv2i32.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv2i32.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u16m1_u32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align # | ... # `---data was truncated (10240/43617) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557f4eb9157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557f4eb8e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557f4eb91cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb6f6733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb6f678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb6f6733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb6f671b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557f4eb2724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557f4eb27096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557f4eb0bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557f4e7bb176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557f4e7bae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb6f671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb6f671d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb6f671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557f4e7bad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c (2593 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_i8mf8x5 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bd809d757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bd809d4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bd809d7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff192733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff19278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff192733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff19271b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bd8096d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bd8096d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bd80951f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bd80601176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bd80600e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff19271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff19271d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff19271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bd80600d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c (2594 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_i8mf4x5(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005640d7d3657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005640d7d33515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005640d7d36cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb0d3733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb0d378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb0d3733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb0d371b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005640d7ccc24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005640d7ccc096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005640d7cb0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005640d7960176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005640d795fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb0d371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb0d371d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb0d371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005640d795fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c (2595 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c (2596 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv2f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32m2_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c (2597 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c (2598 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretu # | ... # `---data was truncated (10240/61937) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561f98f2f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561f98f2c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561f98f2fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f60abc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f60abca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f60abc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f60abc31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561f98ec524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561f98ec5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561f98ea9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561f98b59176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561f98b58e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f60abc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f60abc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f60abc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561f98b58d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c (2599 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055af9e15557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055af9e152515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055af9e155cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f39fcb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f39fcb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f39fcb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f39fcaed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055af9e0eb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055af9e0eb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055af9e0cff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055af9dd7f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055af9dd7ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f39fcaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f39fcaef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f39fcaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055af9dd7ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c (2600 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557abc51357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557abc510515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557abc513cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8bc2733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8bc278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8bc2733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8bc271b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557abc4a924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557abc4a9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557abc48df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557abc13d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557abc13ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8bc271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8bc271d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8bc271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557abc13cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c (2601 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cc63bec57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cc63be9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cc63beccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8fb3849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8fb38a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8fb3849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8fb3831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cc63b8224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cc63b82096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cc63b66f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cc63816176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cc63815e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8fb3832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8fb38330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8fb38330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cc63815d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c (2602 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv1bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv2bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv4bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv4bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv8bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv8bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv16bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv16bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv32bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv32bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf4_m( %vm, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.mask.nxv1bf16.i64( poison, %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.mask.nxv1bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf2_m( %vm, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.mask.nxv2bf16.i64( poison, %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.mask.nxv2bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m1_m( %vm, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.mask.nxv4bf16.i64( poison, %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.mask.nxv4bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m2_m( %vm, %vs2, i64 noundef %rs1, i # | ... # `---data was truncated (10240/14325) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005612c1cb657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005612c1cb3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005612c1cb6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9269049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f92690a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9269049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9269031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005612c1c4c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005612c1c4c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005612c1c30f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005612c18e0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005612c18dfe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9269032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f92690330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f92690330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005612c18dfd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c (2603 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c0efdfe57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c0efdfb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c0efdfecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5484249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f54842a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5484249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5484231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c0efd9424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c0efd94096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c0efd78f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c0efa28176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c0efa27e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5484232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f54842330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f54842330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c0efa27d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c (2604 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m1x3_tum(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c (2605 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_f32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_f32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_f32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_i32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_i32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_i32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_u32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_u32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_u32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tu # | ... # `---data was truncated (10240/23405) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555ff139057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555ff138d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555ff1390cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9910649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f99106a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9910649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9910631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555ff132624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555ff1326096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555ff130af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555ff0fba176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555ff0fb9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9910632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f99106330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f99106330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555ff0fb9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c (2606 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16mf4x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16mf2x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16mf4x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16mf2x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16mf4x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16mf2x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16mf4x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16m1x7_m( %mask, ptr noundef %base, i64 # | ... # `---data was truncated (10240/17523) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055627b86757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055627b864515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055627b867cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4c28f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4c28f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4c28f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4c28f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055627b7fd24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055627b7fd096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055627b7e1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055627b491176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055627b490e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4c28f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4c28f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4c28f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055627b490d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/AArch64/neon-vsqadd-float-conversion.c (2607 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon-vsqadd-float-conversion.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,dce | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local i8 @test_vsqaddb_u8() #0 { # | entry: # | %__p0.addr.i = alloca i8, align 1 # | %__p1.addr.i = alloca i8, align 1 # | %__ret.i = alloca i8, align 1 # | %ref.tmp.i = alloca i8, align 1 # | store i8 1, ptr %__p0.addr.i, align 1 # | store i8 -1, ptr %__p1.addr.i, align 1 # | %0 = load i8, ptr %__p0.addr.i, align 1 # | %1 = load i8, ptr %__p1.addr.i, align 1 # | %2 = insertelement <8 x i8> poison, i8 %0, i64 0 # | %3 = insertelement <8 x i8> poison, i8 %1, i64 0 # | %vsqaddb_u8.i = call <8 x i8> @llvm.aarch64.neon.usqadd.v8i8(<8 x i8> %2, <8 x i8> %3) # | %4 = extractelement <8 x i8> %vsqaddb_u8.i, i64 0 # | store i8 %4, ptr %ref.tmp.i, align 1 # | %5 = load i8, ptr %ref.tmp.i, align 1 # | store i8 %5, ptr %__ret.i, align 1 # | %6 = load i8, ptr %__ret.i, align 1 # | ret i8 %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vsqaddh_u16() #0 { # | entry: # | %__p0.addr.i = alloca i16, align 2 # | %__p1.addr.i = alloca i16, align 2 # | %__ret.i = alloca i16, align 2 # | %ref.tmp.i = alloca i16, align 2 # | store i16 1, ptr %__p0.addr.i, align 2 # | store i16 -1, ptr %__p1.addr.i, align 2 # | %0 = load i16, ptr %__p0.addr.i, align 2 # | %1 = load i16, ptr %__p1.addr.i, align 2 # | %2 = insertelement <4 x i16> poison, i16 %0, i64 0 # | %3 = insertelement <4 x i16> poison, i16 %1, i64 0 # | %vsqaddh_u16.i = call <4 x i16> @llvm.aarch64.neon.usqadd.v4i16(<4 x i16> %2, <4 x i16> %3) # | %4 = extractelement <4 x i16> %vsqaddh_u16.i, i64 0 # | store i16 %4, ptr %ref.tmp.i, align 2 # | %5 = load i16, ptr %ref.tmp.i, align 2 # | store i16 %5, ptr %__ret.i, align 2 # | %6 = load i16, ptr %__ret.i, align 2 # | ret i16 %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_vsqadds_u32() #0 { # | entry: # | %__p0.addr.i = alloca i32, align 4 # | %__p1.addr.i = alloca i32, align 4 # | %__ret.i = alloca i32, align 4 # | %ref.tmp.i = alloca i32, align 4 # | store i32 1, ptr %__p0.addr.i, align 4 # | store i32 -1, ptr %__p1.addr.i, align 4 # | %0 = load i32, ptr %__p0.addr.i, align 4 # | %1 = load i32, ptr %__p1.addr.i, align 4 # | %vsqadds_u32.i = call i32 @llvm.aarch64.neon.usqadd.i32(i32 %0, i32 %1) # | store i32 %vsqadds_u32.i, ptr %ref.tmp.i, align 4 # | %2 = load i32, ptr %ref.tmp.i, align 4 # | store i32 %2, ptr %__ret.i, align 4 # | %3 = load i32, ptr %__ret.i, align 4 # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_vsqaddd_u64() #0 { # | entry: # | %__p0.addr.i = alloca i64, align 8 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca i64, align 8 # | %ref.tmp.i = alloca i64, align 8 # | store i64 1, ptr %__p0.addr.i, align 8 # | store i64 -1, ptr %__p1.addr.i, align 8 # | %0 = load i64, ptr %__p0.addr.i, align 8 # | %1 = load i64, ptr %__p1.addr.i, align 8 # | %vsqaddd_u64.i = call i64 @llvm.aarch64.neon.usqadd.i64(i64 %0, i64 %1) # | store i64 %vsqaddd_u64.i, ptr %ref.tmp.i, align 8 # | %2 = load i64, ptr %ref.tmp.i, align 8 # | store i64 %2, ptr %__ret.i, align 8 # | %3 = load i64, ptr %__ret.i, align 8 # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i8> @llvm.aarch64.neon.usqadd.v8i8(<8 x i8>, <8 x i8>) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i16> @llvm.aarch64.neon.usqadd.v4i16(<4 x i16>, <4 x i16>) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.neon.usqadd.i32(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.aarch64.neon.usqadd.i64(i64, i64) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,dce # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,dce # | #0 0x000055eb09a2557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055eb09a22515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055eb09a25cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffa14933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffa1498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffa14933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffa1491b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eb099bb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055eb099bb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055eb0999ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055eb0964f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055eb0964ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ffa1491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffa1491d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffa1491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eb0964ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c (2608 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv1i32.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv2i32.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv4i32.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv8i32.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv16i32.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv1i64.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv2i64.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv4i64.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv8i64.nxv8i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 4 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | % # | ... # `---data was truncated (10240/39922) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c902b9c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c902b99515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c902b9ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fafa3533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fafa358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fafa3533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fafa351b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c902b3224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c902b32096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c902b16f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c9027c6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c9027c5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fafa351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fafa351d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fafa351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c9027c5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c (2609 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f64m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tu # | ... # `---data was truncated (10240/99186) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a4cdcc457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a4cdcc1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a4cdcc4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa3a1a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa3a1aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa3a1a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa3a1a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a4cdc5a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a4cdc5a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a4cdc3ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a4cd8ee176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a4cd8ede93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa3a1a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa3a1a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa3a1a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a4cd8edd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c (2610 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_i64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_u64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_f64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_i64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_u64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_f64m1x6_tumu( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.ve # | ... # `---data was truncated (10240/18498) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056514cd7f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056514cd7c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056514cd7fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f485d21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f485d2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f485d21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f485d203507 abort ./stdlib/abort.c:85:3 # | #7 0x000056514cd1524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056514cd15096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056514ccf9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056514c9a9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056514c9a8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f485d204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f485d2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f485d2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056514c9a8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c (2611 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i6 # | ... # `---data was truncated (10240/25511) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558eb3e8257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558eb3e7f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558eb3e82cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c88933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c8898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c88933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c8891b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558eb3e1824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558eb3e18096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558eb3dfcf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558eb3aac176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558eb3aabe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2c8891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c8891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c8891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558eb3aabd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c (2612 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16m1x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005557d8eaf57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005557d8eac515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005557d8eafcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8c4cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8c4cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8c4cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8c4cf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005557d8e4524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005557d8e45096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005557d8e29f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005557d8ad9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005557d8ad8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8c4cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8c4cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8c4cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005557d8ad8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c (2613 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556007a3e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556007a3b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556007a3ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f687a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f687a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f687a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f687a231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005560079d424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005560079d4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005560079b8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556007668176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556007667e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f687a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f687a2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f687a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556007667d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c (2614 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf8x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf4x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv16i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv16i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf8x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf4x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c (2615 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_ # | ... # `---data was truncated (10240/63061) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562fb31c457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562fb31c1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562fb31c4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f765741bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f76574725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f765741ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7657403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562fb315a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562fb315a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562fb313ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562fb2dee176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562fb2dede93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7657404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f76574050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f76574050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562fb2dedd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c (2616 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_u16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, ali # | ... # `---data was truncated (10240/60543) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fd0efda57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fd0efd7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fd0efdacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f03e6305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f03e635c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f03e6305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f03e62ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fd0ef7024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fd0ef70096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fd0ef54f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fd0ec04176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fd0ec03e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f03e62eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f03e62ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f03e62ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fd0ec03d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c (2617 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_f16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_f16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_f16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_i16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_i16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_i16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_u16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_u16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_u16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c (2618 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | ... # `---data was truncated (10240/40669) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b21d95157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b21d94e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b21d951cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd26ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd26ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd26ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd26ed1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b21d8e724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b21d8e7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b21d8cbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b21d57b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b21d57ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd26ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd26ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd26ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b21d57ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c (2619 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_f32mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_f32m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_f32m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_i32mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_i32m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_i32m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_u32mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_u32m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_u32m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_f32mf2x4_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void # | ... # `---data was truncated (10240/20489) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005630f3adf57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005630f3adc515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005630f3adfcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fee08533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fee0858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fee08533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fee0851b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005630f3a7524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005630f3a75096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005630f3a59f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005630f3709176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005630f3708e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fee0851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fee0851d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fee0851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005630f3708d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c (2620 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare # | ... # `---data was truncated (10240/20141) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ab8c05057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ab8c04d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ab8c050cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe8e1c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe8e1ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe8e1c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe8e1c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ab8bfe624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ab8bfe6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ab8bfcaf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ab8bc7a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ab8bc79e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe8e1c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe8e1c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe8e1c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ab8bc79d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c (2621 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16mf4_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv1f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16mf2_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv2f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m1_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv4f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m2_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv8f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv8f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m4_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv16f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv16f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m8_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv32f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv32f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f32mf2_tu( %maskedoff, %op1, float noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv1f32.f32.i64( %0, %1, float %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1f32.f32.i64(, , float, , i64) #1 # | # | ; Function Attrs: # | ... # `---data was truncated (10240/22367) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d6c0ac557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d6c0ac2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d6c0ac5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcd06449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcd064a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcd06449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcd06431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d6c0a5b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d6c0a5b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d6c0a3ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d6c06ef176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d6c06eee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcd06432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcd064330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcd064330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d6c06eed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c (2622 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_i32mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_i32m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_u32mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_u32m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32mf2x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: # | ... # `---data was truncated (10240/16382) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cbb364e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cbb364b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cbb364ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f81def33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f81def8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f81def33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f81def1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cbb35e424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cbb35e4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cbb35c8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cbb3278176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cbb3277e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f81def1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f81def1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f81def1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cbb3277d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c (2623 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 5) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 5) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { targ # | ... # `---data was truncated (10240/21111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005560b478d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005560b478a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005560b478dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f314be1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f314be725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f314be1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f314be03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005560b472324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005560b4723096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005560b4707f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005560b43b7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005560b43b6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f314be04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f314be050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f314be050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005560b43b6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/builtin-cpu-is.c (2624 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/builtin-cpu-is.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-unknown-linux-gnu -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c --check-prefix=CHECK-RV64 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-unknown-linux-gnu -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64-unknown-linux-gnu" # | # | @__riscv_cpu_model = external dso_local global { i32, i64, i64 } # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @test_cpu_is_spacemit_x60() #0 { # | entry: # | %0 = load i32, ptr @__riscv_cpu_model, align 4 # | %1 = icmp eq i32 %0, 1808 # | %2 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 8), align 8 # | %3 = icmp eq i64 %2, -9223372035378380799 # | %4 = and i1 %1, %3 # | %5 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 16), align 8 # | %6 = icmp eq i64 %5, 1152921505839391232 # | %7 = and i1 %4, %6 # | %conv = zext i1 %7 to i32 # | ret i32 %conv # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @test_cpu_is_sifive_p550() #0 { # | entry: # | %0 = load i32, ptr @__riscv_cpu_model, align 4 # | %1 = icmp eq i32 %0, 1161 # | %2 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 8), align 8 # | %3 = icmp eq i64 %2, -9223372036854775800 # | %4 = and i1 %1, %3 # | %5 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 16), align 8 # | %6 = icmp eq i64 %5, 102892581 # | %7 = and i1 %4, %6 # | %conv = zext i1 %7 to i32 # | ret i32 %conv # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @test_cpu_is_sifive_p870_d() #0 { # | entry: # | %0 = load i32, ptr @__riscv_cpu_model, align 4 # | %1 = icmp eq i32 %0, 1161 # | %2 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 8), align 8 # | %3 = icmp eq i64 %2, -9223372036854775543 # | %4 = and i1 %1, %3 # | %5 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 16), align 8 # | %6 = icmp eq i64 %5, 337970694 # | %7 = and i1 %4, %6 # | %conv = zext i1 %7 to i32 # | ret i32 %conv # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i" } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c8577b357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c8577b0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c8577b3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4134705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f413475c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4134705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f41346ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c85774924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c857749096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c85772df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c8573dd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c8573dce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f41346eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f41346ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f41346ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c8573dcd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c --check-prefix=CHECK-RV64 # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c --check-prefix=CHECK-RV64 # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c (2625 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c (2626 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m8_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function A # | ... # `---data was truncated (10240/30415) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557dafd7057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557dafd6d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557dafd70cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5143649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f51436a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5143649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5143631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557dafd0624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557dafd06096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557dafceaf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557daf99a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557daf999e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5143632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f51436330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f51436330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557daf999d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c (2627 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cba37d457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cba37d1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cba37d4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7810333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f781038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7810333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f781031b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cba376a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cba376a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cba374ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cba33fe176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cba33fde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f781031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f781031d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f781031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cba33fdd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c (2628 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 8) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 8) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("risc # | ... # `---data was truncated (10240/21103) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558d108e057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558d108dd515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558d108e0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f17e001bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f17e00725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f17e001ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f17e0003507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558d1087624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558d10876096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558d1085af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558d1050a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558d10509e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f17e0004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f17e00050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f17e00050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558d10509d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c (2629 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/48313) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005566d326357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005566d3260515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005566d3263cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f477ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f477eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f477ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f477ea31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005566d31f924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005566d31f9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005566d31ddf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005566d2e8d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005566d2e8ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f477ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f477ea330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f477ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005566d2e8cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c (2630 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16mf4( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16mf2( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16m1( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16m2( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.ad # | ... # `---data was truncated (10240/79671) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056085395157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056085394e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560853951cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3f16249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3f162a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3f16249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3f16231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005608538e724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005608538e7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005608538cbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056085357b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056085357ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3f16232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3f162330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3f162330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056085357ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c (2631 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv1f16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv2f16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv4f16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c (2632 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_e5m2_e4m3_w4_f8e5m2m8_f8e4m3m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.e5m2.e4m3.i64.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.e5m2.e4m3.i64.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056138cafd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056138cafa515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056138cafdcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3f74f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3f74f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3f74f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3f74f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056138ca9324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056138ca93096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056138ca77f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056138c727176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056138c726e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3f74f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3f74f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3f74f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056138c726d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c (2633 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16mf4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16mf2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m1_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m8_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f32mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f32m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, a # | ... # `---data was truncated (10240/44177) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557ab9cc757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557ab9cc4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557ab9cc7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efeaa21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efeaa2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efeaa21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efeaa203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557ab9c5d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557ab9c5d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557ab9c41f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557ab98f1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557ab98f0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efeaa204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efeaa2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efeaa2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557ab98f0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c (2634 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d2f1f6057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d2f1f5d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d2f1f60cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4c40a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4c40aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4c40a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4c40a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d2f1ef624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d2f1ef6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d2f1edaf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d2f1b8a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d2f1b89e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4c40a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4c40a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4c40a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d2f1b89d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c (2635 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | % # | ... # `---data was truncated (10240/14613) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555671feb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555671fe8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555671febcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff75da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff75daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff75da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff75da31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555671f8124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555671f81096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555671f65f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555671c15176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555671c14e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff75da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff75da330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff75da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555671c14d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c (2636 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv8i8.nxv8i8.i64(, , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c (2637 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32mf2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m1( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m4( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f32.f16.nx # | ... # `---data was truncated (10240/90875) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564199a1457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564199a11515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564199a14cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd0e0905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd0e095c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd0e0905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd0e08ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005641999aa24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005641999aa096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056419998ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056419963e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056419963de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd0e08eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd0e08ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd0e08ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056419963dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c (2638 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_i64m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_i64m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_u64m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_u64m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b13e32f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b13e32c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b13e32fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f23ec849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f23ec8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f23ec849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f23ec831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b13e2c524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b13e2c5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b13e2a9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b13df59176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b13df58e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f23ec832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f23ec8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f23ec8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b13df58d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c (2639 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16mf4(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16mf2(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m1(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m2(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m4(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m8(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv32bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv32bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16mf4_m( %vm, ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.mask.nxv1bf16.p0.i64( %2, ptr %1, %0, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.mask.nxv1bf16.p0.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16mf2_m( %vm, ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.mask.nxv2bf16.p0.i64( %2, ptr %1, %0, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.mask.nxv2bf16.p0.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m1_m( %vm, ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.mask.nxv4bf16.p0.i64( %2, ptr %1, %0, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.mask.nxv4bf16.p0.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m2_m( %vm, ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.mask.nxv8bf16.p0.i64( %2, ptr %1, %0, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.mask.nxv8bf16.p0.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m4_m( %vm, ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/12652) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005595a7de557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005595a7de2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005595a7de5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c00f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c00f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c00f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c00f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005595a7d7b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005595a7d7b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005595a7d5ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005595a7a0f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005595a7a0ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2c00f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c00f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c00f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005595a7a0ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c (2640 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, a # | ... # `---data was truncated (10240/424843) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f22b30657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f22b303515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f22b306cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f567cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f567cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f567cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f567cd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f22b29c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f22b29c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f22b280f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f22af30176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f22af2fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f567cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f567cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f567cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f22af2fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c (2641 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m1x # | ... # `---data was truncated (10240/25695) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557099de057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557099ddd515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557099de0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5face49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5facea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5face49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5face31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557099d7624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557099d76096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557099d5af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557099a0a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557099a09e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5face32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5face330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5face330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557099a09d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c (2642 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nx # | ... # `---data was truncated (10240/18660) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056040c5db57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056040c5d8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056040c5dbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc955105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc95515c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc955105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc9550ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056040c57124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056040c571096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056040c555f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056040c205176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056040c204e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc9550eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc9550ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc9550ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056040c204d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c (2643 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, pt # | ... # `---data was truncated (10240/66557) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e57025557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e570252515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e570255cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc321f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc321f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc321f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc321f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e5701eb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e5701eb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e5701cff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e56fe7f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e56fe7ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc321f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc321f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc321f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e56fe7ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c (2644 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m1x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m4x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m1x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m4x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_u64m1x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_u64m2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_ # | ... # `---data was truncated (10240/11895) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ebe7bbe57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ebe7bbb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ebe7bbecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1069933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f106998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1069933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f106991b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ebe7b5424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ebe7b54096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ebe7b38f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ebe77e8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ebe77e7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f106991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f106991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f106991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ebe77e7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c (2645 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f32m1x2_tu(target("riscv.vector. # | ... # `---data was truncated (10240/295525) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562ba2d5757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562ba2d54515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562ba2d57cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9981b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9981b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9981b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9981b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562ba2ced24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562ba2ced096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562ba2cd1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562ba2981176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562ba2980e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9981b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9981b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9981b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562ba2980d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c (2646 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c (2647 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv1i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv2i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv4i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv8i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv16i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv16i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaa # | ... # `---data was truncated (10240/99585) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055aa6e52657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055aa6e523515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055aa6e526cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f57a0533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f57a058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f57a0533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f57a051b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aa6e4bc24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055aa6e4bc096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055aa6e4a0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055aa6e150176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055aa6e14fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f57a051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f57a051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f57a051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aa6e14fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c (2648 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_bf16mf4_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_bf16mf4_f32mf2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_bf16mf4_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_bf16_f32mf2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_bf16mf2_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_bf16mf2_f32m1( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_bf16mf2_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_bf16_f32m1( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_bf16m1_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv4f32.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_bf16m1_f32m2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.a # | ... # `---data was truncated (10240/86092) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ef23e8257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ef23e7f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ef23e82cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f12ac81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f12ac8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f12ac81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f12ac803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ef23e1824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ef23e18096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ef23dfcf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ef23aac176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ef23aabe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f12ac804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f12ac8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f12ac8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ef23aabd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c (2649 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ab9821d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ab9821a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ab9821dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f42eed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f42eed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f42eed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f42eed1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ab981b324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ab981b3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ab98197f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ab97e47176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ab97e46e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f42eed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f42eed1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f42eed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ab97e46d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c (2650 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_e5m2_e5m2_w4_f8e5m2m8_f8e5m2m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.e5m2.e5m2.i64.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.e5m2.e5m2.i64.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055badd3c457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055badd3c1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055badd3c4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fda47449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fda474a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fda47449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fda47431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055badd35a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055badd35a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055badd33ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055badcfee176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055badcfede93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fda47432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fda474330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fda474330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055badcfedd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-builtin-reduce-ops.c (2651 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-builtin-reduce-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @reduce_add_i32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.add = call i32 @llvm.vector.reduce.add.nxv2i32( %0) # | ret i32 %rdx.add # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.vector.reduce.add.nxv2i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @reduce_and_i32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.and = call i32 @llvm.vector.reduce.and.nxv2i32( %0) # | ret i32 %rdx.and # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.vector.reduce.and.nxv2i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @reduce_or_i32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.or = call i32 @llvm.vector.reduce.or.nxv2i32( %0) # | ret i32 %rdx.or # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.vector.reduce.or.nxv2i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @reduce_xor_i32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.xor = call i32 @llvm.vector.reduce.xor.nxv2i32( %0) # | ret i32 %rdx.xor # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.vector.reduce.xor.nxv2i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @reduce_smax_i32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.min = call i32 @llvm.vector.reduce.smax.nxv2i32( %0) # | ret i32 %rdx.min # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.vector.reduce.smax.nxv2i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @reduce_smin_i32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.min = call i32 @llvm.vector.reduce.smin.nxv2i32( %0) # | ret i32 %rdx.min # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.vector.reduce.smin.nxv2i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @reduce_umax_u32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.min = call i32 @llvm.vector.reduce.umax.nxv2i32( %0) # | ret i32 %rdx.min # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.vector.reduce.umax.nxv2i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @reduce_umin_u32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.min = call i32 @llvm.vector.reduce.umin.nxv2i32( %0) # | ret i32 %rdx.min # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.vector.reduce.umin.nxv2i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local float @reduce_fmax_f32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.min = call float @llvm.vector.reduce.fmax.nxv2f32( %0) # | ret float %rdx.min # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare float @llvm.vector.reduce.fmax.nxv2f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local float @reduce_fmin_f32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.min = call float @llvm.vector.reduce.fmin.nxv2f32( %0) # | ret float %rdx.min # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare float @llvm.vector.reduce.fmin.nxv2f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local float @reduce_fmaximum_f32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.maximum = call float @llvm.vector.reduce.fmaximum.nxv2f32( %0) # | ret float %rdx.maximum # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare float @llvm.vector.reduce.fmaximum.nxv2f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local float @reduce_fminimum_f32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.minimum = call float @llvm.vector.reduce.fminimum.nxv2f32( %0) # | ret float %rdx.minimum # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare float @llvm.vector.reduce.fminimum.nxv2f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @reduce_add_i32_m8( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.add = call i32 @llvm.vector.reduce.add.nxv16i32( %0) # | ret i32 %rdx.add # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.vector.reduce.add.nxv16i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @reduce_add_i64( %a) #0 { # | entry: # | %a.addr = alloca , align 8 # | store %a, ptr %a.addr, align 8 # | %0 = load , ptr %a.addr, align 8 # | %rdx.add = call i64 @llvm.vector.reduce.add.nxv1i64( %0) # | ret i64 %rdx.add # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.vector.reduce.add.nxv1i64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @reduce_mul_i32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.mul = call i32 @llvm.vector.reduce.mul.nxv2i32( %0) # | ret i32 %rdx.mul # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.vector.reduce.mul.nxv2i32() #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x000055bcd2bb457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bcd2bb1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bcd2bb4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0fbf649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0fbf6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0fbf649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0fbf631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bcd2b4a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bcd2b4a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bcd2b2ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bcd27de176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bcd27dde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0fbf632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0fbf6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0fbf6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bcd27ddd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c (2652 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_i8mf8x7 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563fa2b9f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563fa2b9c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563fa2b9fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f107e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f107e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f107e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f107e11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563fa2b3524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563fa2b35096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563fa2b19f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563fa27c9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563fa27c8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f107e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f107e11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f107e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563fa27c8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c (2653 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4 # | ... # `---data was truncated (10240/25575) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563dda6b957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563dda6b6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563dda6b9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9b1dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9b1dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9b1dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9b1dc31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563dda64f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563dda64f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563dda633f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563dda2e3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563dda2e2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9b1dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9b1dc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9b1dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563dda2e2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmaxnmq.c (2654 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmaxnmq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = call <8 x half> @llvm.maxnum.v8f16(<8 x half> %0, <8 x half> %1) # | ret <8 x half> %2 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.maxnum.v8f16(<8 x half>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %0, <4 x float> %1) # | ret <4 x float> %2 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x half>, ptr %inactive.addr, align 8 # | %6 = call <8 x half> @llvm.arm.mve.max.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> %5) # | ret <8 x half> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.max.predicated.v8f16.v8i1(<8 x half>, <8 x half>, i32, <8 x i1>, <8 x half>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x float>, ptr %inactive.addr, align 8 # | %6 = call <4 x float> @llvm.arm.mve.max.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.max.predicated.v4f32.v4i1(<4 x float>, <4 x float>, i32, <4 x i1>, <4 x float>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x half> @llvm.arm.mve.max.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> undef) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmq_x_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x float> @llvm.arm.mve.max.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> undef) # | ret <4 x float> %5 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005577265a557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005577265a2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005577265a5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fba71133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fba7118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fba71133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fba7111b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055772653b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055772653b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055772651ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005577261cf176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005577261cee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fba7111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fba7111d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fba7111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005577261ced81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c (2655 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16m2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store # | ... # `---data was truncated (10240/79861) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ab92b0057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ab92afd515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ab92b00cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feecd81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feecd8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feecd81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feecd803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ab92a9624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ab92a96096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ab92a7af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ab9272a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ab92729e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007feecd804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feecd8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feecd8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ab92729d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c (2656 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8bf16.nxv8f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8bf16.nxv8f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv16bf16.nxv16f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv16bf16.nxv16f32.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vs # | ... # `---data was truncated (10240/10886) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556d581ea57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556d581e7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556d581eacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7a94049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7a940a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7a94049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7a94031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556d5818024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556d58180096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556d58164f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556d57e14176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556d57e13e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7a94032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7a940330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7a940330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556d57e13d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c (2657 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u64m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u64m1( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv1i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u64m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u64m2( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u64m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u64m4( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u64m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u64m8( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u64m1_m( %mask, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load , ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.mask.nxv1i64.nxv1i64.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u64m1_m( %mask, %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load i64, ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv. # | ... # `---data was truncated (10240/18641) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005654fc83a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005654fc837515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005654fc83acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f24b3c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f24b3ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f24b3c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f24b3c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005654fc7d024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005654fc7d0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005654fc7b4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005654fc464176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005654fc463e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f24b3c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f24b3c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f24b3c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005654fc463d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c (2658 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_v # | ... # `---data was truncated (10240/228865) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f55ad9857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f55ad95515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f55ad98cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fec69533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fec6958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fec69533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fec6951b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f55ad2e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f55ad2e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f55ad12f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f55a9c2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f55a9c1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fec6951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fec6951d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fec6951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f55a9c1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c (2659 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv1i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv2i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv4i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv8i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/225205) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005597675e857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005597675e5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005597675e8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7da1905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7da195c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7da1905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7da18ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055976757e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055976757e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559767562f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559767212176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559767211e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7da18eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7da18ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7da18ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559767211d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c (2660 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563b50b1457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563b50b11515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563b50b14cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007facd1b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007facd1b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007facd1b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007facd1b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563b50aaa24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563b50aaa096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563b50a8ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563b5073e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563b5073de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007facd1b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007facd1b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007facd1b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563b5073dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c (2661 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32mf2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1f32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2f32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4f32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8f32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv16f32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32mf2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1i32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2i32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4i32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff. # | ... # `---data was truncated (10240/78156) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ef9e7ad57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ef9e7aa515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ef9e7adcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5dbf849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5dbf8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5dbf849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5dbf831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ef9e74324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ef9e743096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ef9e727f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ef9e3d7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ef9e3d6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5dbf832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5dbf8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5dbf8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ef9e3d6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c (2662 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv16bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m8_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv32bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf4_tum( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(, , bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf2_tum( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.a # | ... # `---data was truncated (10240/32394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bca8b8a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bca8b87515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bca8b8acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fae02a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fae02aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fae02a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fae02a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bca8b2024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bca8b20096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bca8b04f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bca87b4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bca87b3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fae02a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fae02a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fae02a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bca87b3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c (2663 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_i8mf8x8_tu(target("riscv.vector.tuple", , 8) %m # | ... # `---data was truncated (10240/160133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557f42e1a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557f42e17515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557f42e1acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8655449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f86554a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8655449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8655431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557f42db024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557f42db0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557f42d94f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557f42a44176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557f42a43e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8655432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f86554330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f86554330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557f42a43d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c (2664 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf8( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c (2665 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_f64m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_i64m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_u64m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_f64m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_i64m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_u64m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560b64b3457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560b64b31515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560b64b34cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f479a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f479a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f479a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f479a91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560b64aca24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560b64aca096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560b64aaef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560b6475e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560b6475de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f479a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f479a91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f479a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560b6475dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c (2666 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561e8459057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561e8458d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561e84590cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f43f8d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f43f8d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f43f8d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f43f8d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561e8452624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561e84526096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561e8450af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561e841ba176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561e841b9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f43f8d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f43f8d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f43f8d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561e841b9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c (2667 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005616ac76857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005616ac765515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005616ac768cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f04d7649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f04d76a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f04d7649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f04d7631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005616ac6fe24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005616ac6fe096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005616ac6e2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005616ac392176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005616ac391e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f04d7632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f04d76330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f04d76330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005616ac391d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c (2668 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005619fec2457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005619fec21515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005619fec24cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6cd3933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6cd398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6cd3933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6cd391b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005619febba24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005619febba096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005619feb9ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005619fe84e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005619fe84de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6cd391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6cd391d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6cd391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005619fe84dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c (2669 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf4x6_tumu( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2. # | ... # `---data was truncated (10240/18498) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005609c015157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005609c014e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005609c0151cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efef0a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efef0a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efef0a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efef0a03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005609c00e724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005609c00e7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005609c00cbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005609bfd7b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005609bfd7ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efef0a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efef0a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efef0a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005609bfd7ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c (2670 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8bf16.nxv8f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8bf16.nxv8f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv16bf16.nxv16f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv16bf16.nxv16f32.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_ran # | ... # `---data was truncated (10240/10878) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cfe085357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cfe0850515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cfe0853cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fba9c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fba9c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fba9c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fba9c51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cfe07e924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cfe07e9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cfe07cdf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cfe047d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cfe047ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fba9c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fba9c51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fba9c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cfe047cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c (2671 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_f64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_f64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_f64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_i64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_i64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_i64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_u64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_u64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_u64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target # | ... # `---data was truncated (10240/23439) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556b84b0357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556b84b00515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556b84b03cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f11a3049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f11a30a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f11a3049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f11a3031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556b84a9924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556b84a99096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556b84a7df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556b8472d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556b8472ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f11a3032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f11a30330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f11a30330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556b8472cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c (2672 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f56764757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f567644515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f567647cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa063133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa06318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa063133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa06311b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f5675dd24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f5675dd096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f5675c1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f567271176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f567270e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa06311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa06311d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa06311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f567270d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c (2673 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_u16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_u16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), # | ... # `---data was truncated (10240/53330) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556f22d8357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556f22d80515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556f22d83cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe1d9533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe1d958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe1d9533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe1d951b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556f22d1924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556f22d19096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556f22cfdf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556f229ad176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556f229ace93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe1d951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe1d951d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe1d951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556f229acd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c (2674 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f64m1x4(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c (2675 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055820a7da57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055820a7d7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055820a7dacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6c21a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6c21aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6c21a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6c21a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055820a77024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055820a770096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055820a754f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055820a404176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055820a403e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6c21a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6c21a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6c21a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055820a403d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c (2676 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vect # | ... # `---data was truncated (10240/31946) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a13913f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a13913c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a13913fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbed1d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbed1d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbed1d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbed1ced507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a1390d524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a1390d5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a1390b9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a138d69176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a138d68e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbed1ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbed1cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbed1cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a138d68d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c (2677 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_f32mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_f32m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_f32m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_f32m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_i32mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_i32m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_i32m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_i32m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_u32mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_u32m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define d # | ... # `---data was truncated (10240/26976) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005566de22257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005566de21f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005566de222cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faec3f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faec3f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faec3f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faec3f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005566de1b824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005566de1b8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005566de19cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005566dde4c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005566dde4be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007faec3f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faec3f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faec3f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005566dde4bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c (2678 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16mf4x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16mf2x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16mf4x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16mf2x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16mf4x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16mf2x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16mf4x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16m1x6_m( %mask, ptr noundef %base, i64 # | ... # `---data was truncated (10240/17523) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559d599ac57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559d599a9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559d599accbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa2f9449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa2f94a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa2f9449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa2f9431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559d5994224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559d59942096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559d59926f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559d595d6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559d595d5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa2f9432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa2f94330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa2f94330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559d595d5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c (2679 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste16_bf16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.sf.vste16.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste16_f16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste16_i16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste16_u16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvfbfmin,+zvfhmin,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfhmin1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005558eb70557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005558eb702515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005558eb705cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fabfdd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fabfdd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fabfdd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fabfdd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005558eb69b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005558eb69b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005558eb67ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005558eb32f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005558eb32ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fabfdd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fabfdd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fabfdd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005558eb32ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c (2680 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf4_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv1bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf2_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv2bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m1_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv4bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv4bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m2_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv8bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv8bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m4_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv16bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv16bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m8_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv32bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv32bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslidedown.mask.nxv1bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.mask.nxv1bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslidedown.mask.nxv2bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedo # | ... # `---data was truncated (10240/30751) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005624da38c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005624da389515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005624da38ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f216d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f216d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f216d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f216d831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005624da32224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005624da322096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005624da306f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005624d9fb6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005624d9fb5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f216d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f216d8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f216d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005624d9fb5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c (2681 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_u32mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_u32m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("ris # | ... # `---data was truncated (10240/26965) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005595ed14a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005595ed147515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005595ed14acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3a19849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3a198a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3a19849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3a19831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005595ed0e024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005595ed0e0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005595ed0c4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005595ecd74176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005595ecd73e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3a19832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3a198330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3a198330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005595ecd73d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c (2682 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf8x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf8x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf8x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %m # | ... # `---data was truncated (10240/22258) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561b4d4a657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561b4d4a3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561b4d4a6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc3dcd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc3dcd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc3dcd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc3dcd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561b4d43c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561b4d43c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561b4d420f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561b4d0d0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561b4d0cfe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc3dcd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc3dcd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc3dcd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561b4d0cfd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/distributed-thin-lto/cfi-devirt.ll (2683 of 27911) ******************** TEST 'Clang :: CodeGen/distributed-thin-lto/cfi-devirt.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 7 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi-devirt.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi-devirt.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi-devirt.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi-devirt.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi-devirt.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi-devirt.ll # | #0 0x00005654026b057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005654026ad515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005654026b0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f74cec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f74ceca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f74cec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f74cec31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056540264624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000565402646096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056540262af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005654022da176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005654022d9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f74cec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f74cec330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f74cec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005654022d9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c (2684 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret < # | ... # `---data was truncated (10240/34430) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f4d121457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f4d1211515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f4d1214cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0053133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f005318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0053133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f005311b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f4d11aa24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f4d11aa096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f4d118ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f4d0e3e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f4d0e3de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f005311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f005311d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f005311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f4d0e3dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c (2685 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1f64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2f64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4f64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8f64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1i64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2i64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4i64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8i64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1i64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2i64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4i64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8i64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1f64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1f64.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2f64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2f64.p0.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c (2686 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561b9c89457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561b9c891515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561b9c894cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe564b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe564b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe564b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe564b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561b9c82a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561b9c82a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561b9c80ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561b9c4be176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561b9c4bde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe564b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe564b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe564b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561b9c4bdd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c (2687 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv16i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv32i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv64i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = l # | ... # `---data was truncated (10240/54480) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ffdd03457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ffdd031515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ffdd034cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f94d9c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f94d9ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f94d9c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f94d9c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ffdcfca24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ffdcfca096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ffdcfaef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ffdcc5e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ffdcc5de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f94d9c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f94d9c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f94d9c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ffdcc5dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c (2688 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align # | ... # `---data was truncated (10240/47596) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fbfa43157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fbfa42e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fbfa431cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3b3b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3b3b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3b3b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3b3b431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fbfa3c724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fbfa3c7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fbfa3abf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fbfa05b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fbfa05ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3b3b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3b3b4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3b3b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fbfa05ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c (2689 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_i32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_i32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_u32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_u32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32mf2x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple" # | ... # `---data was truncated (10240/35929) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005609e2d9557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005609e2d92515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005609e2d95cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7f64533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7f6458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7f64533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7f6451b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005609e2d2b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005609e2d2b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005609e2d0ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005609e29bf176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005609e29bee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7f6451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7f6451d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7f6451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005609e29bed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGenCXX/thinlto_public_type_test_distributed.ll (2690 of 27911) ******************** TEST 'Clang :: CodeGenCXX/thinlto_public_type_test_distributed.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenCXX/Output/thinlto_public_type_test_distributed.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/thinlto_public_type_test_distributed.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenCXX/Output/thinlto_public_type_test_distributed.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/thinlto_public_type_test_distributed.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenCXX/Output/thinlto_public_type_test_distributed.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/thinlto_public_type_test_distributed.ll # | #0 0x000055fa079f157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fa079ee515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fa079f1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5e3cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5e3cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5e3cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5e3cc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fa0798724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fa07987096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fa0796bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fa0761b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fa0761ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5e3cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5e3cc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5e3cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fa0761ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-cde-vec.c (2691 of 27911) ******************** TEST 'Clang :: CodeGen/arm-cde-vec.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +cdecp1 -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +cdecp1 -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx1q_u8() #0 { # | entry: # | %0 = call <16 x i8> @llvm.arm.cde.vcx1q(i32 0, i32 1111) # | ret <16 x i8> %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.cde.vcx1q(i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx1qa_1(<16 x i8> noundef %acc) #0 { # | entry: # | %acc.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %acc, ptr %acc.addr, align 8 # | %0 = load <16 x i8>, ptr %acc.addr, align 8 # | %1 = call <16 x i8> @llvm.arm.cde.vcx1qa(i32 1, <16 x i8> %0, i32 1112) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.cde.vcx1qa(i32 immarg, <16 x i8>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcx1qa_2(<4 x i32> noundef %acc) #0 { # | entry: # | %acc.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %acc, ptr %acc.addr, align 8 # | %0 = load <4 x i32>, ptr %acc.addr, align 8 # | %1 = bitcast <4 x i32> %0 to <16 x i8> # | %2 = call <16 x i8> @llvm.arm.cde.vcx1qa(i32 0, <16 x i8> %1, i32 1113) # | %3 = bitcast <16 x i8> %2 to <4 x i32> # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx2q_u8(<8 x half> noundef %n) #0 { # | entry: # | %n.addr = alloca <8 x half>, align 8 # | store <8 x half> %n, ptr %n.addr, align 8 # | %0 = load <8 x half>, ptr %n.addr, align 8 # | %1 = bitcast <8 x half> %0 to <16 x i8> # | %2 = call <16 x i8> @llvm.arm.cde.vcx2q(i32 1, <16 x i8> %1, i32 111) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.cde.vcx2q(i32 immarg, <16 x i8>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcx2q(<4 x float> noundef %n) #0 { # | entry: # | %n.addr = alloca <4 x float>, align 8 # | store <4 x float> %n, ptr %n.addr, align 8 # | %0 = load <4 x float>, ptr %n.addr, align 8 # | %1 = bitcast <4 x float> %0 to <16 x i8> # | %2 = call <16 x i8> @llvm.arm.cde.vcx2q(i32 1, <16 x i8> %1, i32 112) # | %3 = bitcast <16 x i8> %2 to <4 x float> # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcx2qa(<4 x float> noundef %acc, <2 x i64> noundef %n) #0 { # | entry: # | %acc.addr = alloca <4 x float>, align 8 # | %n.addr = alloca <2 x i64>, align 8 # | store <4 x float> %acc, ptr %acc.addr, align 8 # | store <2 x i64> %n, ptr %n.addr, align 8 # | %0 = load <4 x float>, ptr %acc.addr, align 8 # | %1 = bitcast <4 x float> %0 to <16 x i8> # | %2 = load <2 x i64>, ptr %n.addr, align 8 # | %3 = bitcast <2 x i64> %2 to <16 x i8> # | %4 = call <16 x i8> @llvm.arm.cde.vcx2qa(i32 0, <16 x i8> %1, <16 x i8> %3, i32 113) # | %5 = bitcast <16 x i8> %4 to <4 x float> # | ret <4 x float> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.cde.vcx2qa(i32 immarg, <16 x i8>, <16 x i8>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx3q_u8(<8 x i16> noundef %n, <4 x i32> noundef %m) #0 { # | entry: # | %n.addr = alloca <8 x i16>, align 8 # | %m.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %n, ptr %n.addr, align 8 # | store <4 x i32> %m, ptr %m.addr, align 8 # | %0 = load <8 x i16>, ptr %n.addr, align 8 # | %1 = bitcast <8 x i16> %0 to <16 x i8> # | %2 = load <4 x i32>, ptr %m.addr, align 8 # | %3 = bitcast <4 x i32> %2 to <16 x i8> # | %4 = call <16 x i8> @llvm.arm.cde.vcx3q(i32 0, <16 x i8> %1, <16 x i8> %3, i32 11) # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.cde.vcx3q(i32 immarg, <16 x i8>, <16 x i8>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vcx3q(<2 x i64> noundef %n, <4 x float> noundef %m) #0 { # | entry: # | %n.addr = alloca <2 x i64>, align 8 # | %m.addr = alloca <4 x float>, align 8 # | store <2 x i64> %n, ptr %n.addr, align 8 # | store <4 x float> %m, ptr %m.addr, align 8 # | %0 = load <2 x i64>, ptr %n.addr, align 8 # | %1 = bitcast <2 x i64> %0 to <16 x i8> # | %2 = load <4 x float>, ptr %m.addr, align 8 # | %3 = bitcast <4 x float> %2 to <16 x i8> # | %4 = call <16 x i8> @llvm.arm.cde.vcx3q(i32 1, <16 x i8> %1, <16 x i8> %3, i32 12) # | %5 = bitcast <16 x i8> %4 to <2 x i64> # | ret <2 x i64> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx3qa(<16 x i8> noundef %acc, <8 x i16> noundef %n, <4 x float> noundef %m) #0 { # | entry: # | %acc.addr = alloca <16 x i8>, align 8 # | %n.addr = alloca <8 x i16>, align 8 # | %m.addr = alloca <4 x float>, align 8 # | store <16 x i8> %acc, ptr %acc.addr, align 8 # | store <8 x i16> %n, ptr %n.addr, align 8 # | store <4 x float> %m, ptr %m.addr, align 8 # | %0 = load <16 x i8>, ptr %acc.addr, align 8 # | %1 = load <8 x i16>, ptr %n.addr, align 8 # | %2 = bitcast <8 x i16> %1 to <16 x i8> # | %3 = load <4 x float>, ptr %m.addr, align 8 # | %4 = bitcast <4 x float> %3 to <16 x i8> # | %5 = call <16 x i8> @llvm.arm.cde.vcx3qa(i32 1, <16 x i8> %0, <16 x i8> %2, <16 x i8> %4, i32 13) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.cde.vcx3qa(i32 immarg, <16 x i8>, <16 x i8>, <16 x i8>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcx1q_m(<8 x i16> noundef %inactive, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %inactive.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = call <8 x i16> @llvm.arm.cde.vcx1q.predicated.v8i16.v8i1(i32 0, <8 x i16> %0, i32 1111, <8 x i1> %3) # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.cde.vcx1q.predicated.v8i16.v8i1(i32 immarg, <8 x i16>, i32 immarg, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx1qa_m(<16 x i8> noundef %acc, i16 noundef zeroext %p) #0 { # | entry: # | %acc.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %acc, ptr %acc.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %acc.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = call <16 x i8> @llvm.arm.cde.vcx1qa.predicated.v16i8.v16i1(i32 1, <16 x i8> %0, i32 1112, <16 x i1> %3) # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.cde.vcx1qa.predicated.v16i8.v16i1(i32 immarg, <16 x i8>, i32 immarg, <16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcx2q_m(<4 x i32> noundef %inactive, <4 x float> noundef %n, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %n.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %n, ptr %n.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %inactive.addr, align 8 # | %1 = load <4 x float>, ptr %n.addr, align 8 # | %2 = bitcast <4 x float> %1 to <16 x i8> # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4) # | %6 = call <4 x i32> @llvm.arm.cde.vcx2q.predicated.v4i32.v4i1(i32 0, <4 x i32> %0, <16 x i8> %2, i32 111, <4 x i1> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.cde.vcx2q.predicated.v4i32.v4i1(i32 immarg, <4 x i32>, <16 x i8>, i32 immarg, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcx2qa_m(<4 x float> noundef %acc, <8 x half> noundef %n, i16 noundef zeroext %p) #0 { # | entry: # | %acc.addr = alloca <4 x float>, align 8 # | %n.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %acc, ptr %acc.addr, align 8 # | store <8 x half> %n, ptr %n.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %acc.addr, align 8 # | %1 = load <8 x half>, ptr %n.addr, align 8 # | %2 = bitcast <8 x half> %1 to <16 x i8> # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4) # | %6 = call <4 x float> @llvm.arm.cde.vcx2qa.predicated.v4f32.v4i1(i32 0, <4 x float> %0, <16 x i8> %2, i32 112, <4 x i1> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.cde.vcx2qa.predicated.v4f32.v4i1(i32 immarg, <4 x float>, <16 x i8>, i32 immarg, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vcx3q_m(<2 x i64> noundef %inactive, <4 x float> noundef %n, <16 x i8> noundef %m, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <2 x i64>, align 8 # | %n.addr = alloca <4 x float>, align 8 # | %m.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <2 x i64> %inactive, ptr %inactive.addr, align 8 # | ... # `---data was truncated (10240/13030) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056098b7e257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056098b7df515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056098b7e2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fca1e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fca1e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fca1e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fca1e31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056098b77824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056098b778096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056098b75cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056098b40c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056098b40be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fca1e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fca1e31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fca1e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056098b40bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c (2692 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv16bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv32bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf4_m( %mask, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(, , bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf2_m( %mask, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.mask.nxv2bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.mask.nxv2bf16.bf16.i64(, , bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m1_m( %mask, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.mask.nxv4bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.mask.nxv4bf16.bf16.i64(, , bfloat, , i64 immar # | ... # `---data was truncated (10240/14780) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055567fffd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055567fffa515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055567fffdcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8cd6905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8cd695c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8cd6905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8cd68ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055567ff9324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055567ff93096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055567ff77f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055567fc27176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055567fc26e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8cd68eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8cd68ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8cd68ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055567fc26d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c (2693 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvfwmaccqqq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvfwmaccqqq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005632fe65157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005632fe64e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005632fe651cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1b55049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1b550a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1b55049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1b55031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005632fe5e724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005632fe5e7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005632fe5cbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005632fe27b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005632fe27ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1b55032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1b550330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1b550330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005632fe27ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c (2694 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv1f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv2f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv4f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv8f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv8f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv16f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | de # | ... # `---data was truncated (10240/12091) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a3a2abe57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a3a2abb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a3a2abecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efe60449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efe604a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efe60449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efe60431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a3a2a5424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a3a2a54096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a3a2a38f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a3a26e8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a3a26e7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efe60432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efe604330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efe604330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a3a26e7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/ternary.c (2695 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/ternary.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c --check-prefixes=CHECK,CHECK-NOSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vfmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %c.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store <8 x half> %c, ptr %c.addr, align 8 # | %0 = load <8 x half>, ptr %b.addr, align 8 # | %1 = load <8 x half>, ptr %c.addr, align 8 # | %2 = load <8 x half>, ptr %a.addr, align 8 # | %3 = call <8 x half> @llvm.fma.v8f16(<8 x half> %0, <8 x half> %1, <8 x half> %2) # | ret <8 x half> %3 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.fma.v8f16(<8 x half>, <8 x half>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vfmaq_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %c.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store <4 x float> %c, ptr %c.addr, align 8 # | %0 = load <4 x float>, ptr %b.addr, align 8 # | %1 = load <4 x float>, ptr %c.addr, align 8 # | %2 = load <4 x float>, ptr %a.addr, align 8 # | %3 = call <4 x float> @llvm.fma.v4f32(<4 x float> %0, <4 x float> %1, <4 x float> %2) # | ret <4 x float> %3 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vfmaq_n_f16(<8 x half> noundef %a, <8 x half> noundef %b, half noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %c.addr = alloca half, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store half %c, ptr %c.addr, align 2 # | %0 = load half, ptr %c.addr, align 2 # | %.splatinsert = insertelement <8 x half> poison, half %0, i64 0 # | %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load <8 x half>, ptr %a.addr, align 8 # | %3 = call <8 x half> @llvm.fma.v8f16(<8 x half> %1, <8 x half> %.splat, <8 x half> %2) # | ret <8 x half> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vfmaq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %c.addr = alloca float, align 4 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store float %c, ptr %c.addr, align 4 # | %0 = load float, ptr %c.addr, align 4 # | %.splatinsert = insertelement <4 x float> poison, float %0, i64 0 # | %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load <4 x float>, ptr %a.addr, align 8 # | %3 = call <4 x float> @llvm.fma.v4f32(<4 x float> %1, <4 x float> %.splat, <4 x float> %2) # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vfmasq_n_f16(<8 x half> noundef %a, <8 x half> noundef %b, half noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %c.addr = alloca half, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store half %c, ptr %c.addr, align 2 # | %0 = load half, ptr %c.addr, align 2 # | %.splatinsert = insertelement <8 x half> poison, half %0, i64 0 # | %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer # | %1 = load <8 x half>, ptr %a.addr, align 8 # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = call <8 x half> @llvm.fma.v8f16(<8 x half> %1, <8 x half> %2, <8 x half> %.splat) # | ret <8 x half> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vfmasq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %c.addr = alloca float, align 4 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store float %c, ptr %c.addr, align 4 # | %0 = load float, ptr %c.addr, align 4 # | %.splatinsert = insertelement <4 x float> poison, float %0, i64 0 # | %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer # | %1 = load <4 x float>, ptr %a.addr, align 8 # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = call <4 x float> @llvm.fma.v4f32(<4 x float> %1, <4 x float> %2, <4 x float> %.splat) # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vfmsq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %c.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store <8 x half> %c, ptr %c.addr, align 8 # | %0 = load <8 x half>, ptr %b.addr, align 8 # | %1 = load <8 x half>, ptr %c.addr, align 8 # | %2 = fneg <8 x half> %1 # | %3 = load <8 x half>, ptr %a.addr, align 8 # | %4 = call <8 x half> @llvm.fma.v8f16(<8 x half> %0, <8 x half> %2, <8 x half> %3) # | ret <8 x half> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vfmsq_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %c.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store <4 x float> %c, ptr %c.addr, align 8 # | %0 = load <4 x float>, ptr %b.addr, align 8 # | %1 = load <4 x float>, ptr %c.addr, align 8 # | %2 = fneg <4 x float> %1 # | %3 = load <4 x float>, ptr %a.addr, align 8 # | %4 = call <4 x float> @llvm.fma.v4f32(<4 x float> %0, <4 x float> %2, <4 x float> %3) # | ret <4 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmlaq_n_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i8 noundef signext %c) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i8 %c, ptr %c.addr, align 1 # | %0 = load <16 x i8>, ptr %b.addr, align 8 # | %1 = load i8, ptr %c.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = mul <16 x i8> %0, %.splat # | %3 = load <16 x i8>, ptr %a.addr, align 8 # | %4 = add <16 x i8> %2, %3 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmlaq_n_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef signext %c) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %c, ptr %c.addr, align 2 # | %0 = load <8 x i16>, ptr %b.addr, align 8 # | %1 = load i16, ptr %c.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = mul <8 x i16> %0, %.splat # | %3 = load <8 x i16>, ptr %a.addr, align 8 # | %4 = add <8 x i16> %2, %3 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmlaq_n_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i32 noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i32 %c, ptr %c.addr, align 4 # | %0 = load <4 x i32>, ptr %b.addr, align 8 # | %1 = load i32, ptr %c.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = mul <4 x i32> %0, %.splat # | %3 = load <4 x i32>, ptr %a.addr, align 8 # | %4 = add <4 x i32> %2, %3 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmlaq_n_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i8 noundef zeroext %c) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i8 %c, ptr %c.addr, align 1 # | %0 = load <16 x i8>, ptr %b.addr, align 8 # | %1 = load i8, ptr %c.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = mul <16 x i8> %0, %.splat # | %3 = load <16 x i8>, ptr %a.addr, align 8 # | %4 = add <16 x i8> %2, %3 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmlaq_n_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %c) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, ali # | ... # `---data was truncated (10240/60411) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x0000563e6f9d857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563e6f9d5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563e6f9d8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0d6361bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0d636725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0d6361ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0d63603507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563e6f96e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563e6f96e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563e6f952f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563e6f602176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563e6f601e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0d63604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0d636050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0d636050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563e6f601d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c --check-prefixes=CHECK,CHECK-NOSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c --check-prefixes=CHECK,CHECK-NOSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c (2696 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e1719b557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e1719b2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e1719b5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2d6b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2d6b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2d6b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2d6b51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e17194b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e17194b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e17192ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e1715df176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e1715dee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2d6b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2d6b51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2d6b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e1715ded81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c (2697 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f32.i64(, # | ... # `---data was truncated (10240/47764) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055800a31457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055800a311515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055800a314cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f434a21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f434a2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f434a21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f434a203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055800a2aa24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055800a2aa096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055800a28ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558009f3e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558009f3de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f434a204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f434a2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f434a2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558009f3dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c (2698 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv16f16 # | ... # `---data was truncated (10240/69305) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562875fb057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562875fad515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562875fb0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcf9c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcf9c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcf9c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcf9c11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562875f4624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562875f46096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562875f2af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562875bda176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562875bd9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcf9c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcf9c11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcf9c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562875bd9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c (2699 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_i32mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_i32m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_u32mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_u32m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_i32mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_i32m1x6_m( %mask, ptr noundef % # | ... # `---data was truncated (10240/14001) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055663852b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556638528515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055663852bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3da4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3da478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3da4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3da471b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005566384c124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005566384c1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005566384a5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556638155176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556638154e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3da471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3da471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3da471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556638154d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c (2700 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_i64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_u64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_f64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_i64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_u64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_f64m1x8_tumu( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.ve # | ... # `---data was truncated (10240/18498) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b0ee96257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b0ee95f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b0ee962cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8c1a01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8c1a0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8c1a01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8c1a003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b0ee8f824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b0ee8f8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b0ee8dcf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b0ee58c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b0ee58be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8c1a004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8c1a0050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8c1a0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b0ee58bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c (2701 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/48305) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005622da89057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005622da88d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005622da890cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd79b705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd79b75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd79b705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd79b6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005622da82624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005622da826096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005622da80af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005622da4ba176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005622da4b9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd79b6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd79b6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd79b6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005622da4b9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c (2702 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf8_b64( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf4_b32( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf2_b16( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8m1_b8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8m2_b4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.n # | ... # `---data was truncated (10240/95355) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005568291f557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005568291f2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005568291f5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f82e1133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f82e118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f82e1133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f82e111b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055682918b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055682918b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055682916ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556828e1f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556828e1ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f82e111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f82e111d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f82e111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556828e1ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c (2703 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zkne -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c -check-prefix=RV64ZKNE # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zkne -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @aes64es(i64 noundef %rs1, i64 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i64, align 8 # | %__y.addr.i = alloca i64, align 8 # | %rs1.addr = alloca i64, align 8 # | %rs2.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | store i64 %0, ptr %__x.addr.i, align 8 # | store i64 %1, ptr %__y.addr.i, align 8 # | %2 = load i64, ptr %__x.addr.i, align 8 # | %3 = load i64, ptr %__y.addr.i, align 8 # | %4 = call i64 @llvm.riscv.aes64es(i64 %2, i64 %3) # | ret i64 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @aes64esm(i64 noundef %rs1, i64 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i64, align 8 # | %__y.addr.i = alloca i64, align 8 # | %rs1.addr = alloca i64, align 8 # | %rs2.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | store i64 %0, ptr %__x.addr.i, align 8 # | store i64 %1, ptr %__y.addr.i, align 8 # | %2 = load i64, ptr %__x.addr.i, align 8 # | %3 = load i64, ptr %__y.addr.i, align 8 # | %4 = call i64 @llvm.riscv.aes64esm(i64 %2, i64 %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.aes64es(i64, i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.aes64esm(i64, i64) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zkne" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zkne1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f9a664757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f9a6644515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f9a6647cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1abaa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1abaaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1abaa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1abaa31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f9a65dd24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f9a65dd096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f9a65c1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f9a6271176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f9a6270e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1abaa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1abaa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1abaa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f9a6270d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c -check-prefix=RV64ZKNE # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c -check-prefix=RV64ZKNE # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c (2704 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf8_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf4_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf2_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m1_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m2_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m4_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m8_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u16mf4_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u16mf2_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u16m1_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, pt # | ... # `---data was truncated (10240/52733) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c2dd32557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c2dd322515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c2dd325cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f695df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f695df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f695df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f695df1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c2dd2bb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c2dd2bb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c2dd29ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c2dcf4f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c2dcf4ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f695df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f695df1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f695df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c2dcf4ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c (2705 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557cc2b2657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557cc2b23515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557cc2b26cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa9e2133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa9e218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa9e2133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa9e211b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557cc2abc24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557cc2abc096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557cc2aa0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557cc2750176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557cc274fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa9e211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa9e211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa9e211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557cc274fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c (2706 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf8_b64( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf4_b32( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf2_b16( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8m1_b8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8m2_b4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.n # | ... # `---data was truncated (10240/95355) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055870ddb557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055870ddb2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055870ddb5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f76a8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f76a898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f76a8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f76a891b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055870dd4b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055870dd4b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055870dd2ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055870d9df176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055870d9dee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f76a891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f76a891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f76a891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055870d9ded81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c (2707 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv8bf16.p0.nxv8i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-feature # | ... # `---data was truncated (10240/10692) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bbcddb757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bbcddb4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bbcddb7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f47a4b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f47a4b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f47a4b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f47a4b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bbcdd4d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bbcdd4d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bbcdd31f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bbcd9e1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bbcd9e0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f47a4b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f47a4b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f47a4b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bbcd9e0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmovl.c (2708 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmovl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> # | %2 = sext <8 x i8> %1 to <8 x i16> # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> # | %2 = sext <4 x i16> %1 to <4 x i32> # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> # | %2 = zext <8 x i8> %1 to <8 x i16> # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> # | %2 = zext <4 x i16> %1 to <4 x i32> # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovltq_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> # | %2 = sext <8 x i8> %1 to <8 x i16> # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovltq_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> # | %2 = sext <4 x i16> %1 to <4 x i32> # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovltq_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> # | %2 = zext <8 x i8> %1 to <8 x i16> # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovltq_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> # | %2 = zext <4 x i16> %1 to <4 x i32> # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_m_s8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, i32 0, i32 0, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8>, i32, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_m_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x i32>, ptr %inactive.addr, align 8 # | %5 = call <4 x i32> @llvm.arm.mve.vmovl.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, i32 0, i32 0, <4 x i1> %3, <4 x i32> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vmovl.predicated.v4i32.v8i16.v4i1(<8 x i16>, i32, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_m_u8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, i32 1, i32 0, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_m_u16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x i32>, ptr %inactive.addr, align 8 # | %5 = call <4 x i32> @llvm.arm.mve.vmovl.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, i32 1, i32 0, <4 x i1> %3, <4 x i32> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovltq_m_s8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, i32 0, i32 1, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovltq_m_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x i32>, ptr %inactive.addr, align 8 # | %5 = call <4 x i32> @llvm.arm.mve.vmovl.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, i32 0, i32 1, <4 x i1> %3, <4 x i32> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovltq_m_u8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, i32 1, i32 1, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovltq_m_u16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.ad # | ... # `---data was truncated (10240/16274) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005654f28e357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005654f28e0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005654f28e3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7e86449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7e864a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7e86449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7e86431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005654f287924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005654f2879096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005654f285df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005654f250d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005654f250ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7e86432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7e864330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7e864330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005654f250cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c (2709 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_i32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_i32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_u32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_u32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32mf2x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, # | ... # `---data was truncated (10240/40726) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cff147a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cff1477515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cff147acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7cecd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7cecd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7cecd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7cecd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cff141024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cff1410096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cff13f4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cff10a4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cff10a3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7cecd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7cecd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7cecd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cff10a3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c (2710 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16mf4x4(ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16mf2x4(ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16m1x4(ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16m2x4(ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16m1x4_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16m2x4_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwin # | ... # `---data was truncated (10240/10798) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055baf1e1d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055baf1e1a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055baf1e1dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2d01333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2d0138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2d01333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2d0131b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055baf1db324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055baf1db3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055baf1d97f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055baf1a47176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055baf1a46e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2d0131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2d0131d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2d0131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055baf1a46d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c (2711 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = # | ... # `---data was truncated (10240/14319) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563b6514a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563b65147515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563b6514acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe61c41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe61c4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe61c41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe61c403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563b650e024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563b650e0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563b650c4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563b64d74176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563b64d73e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe61c404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe61c4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe61c4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563b64d73d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c (2712 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fd37c2557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fd37c22515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fd37c25cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbb95105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbb9515c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbb95105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbb950ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fd37bbb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fd37bbb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fd37b9ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fd3784f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fd3784ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbb950eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbb950ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbb950ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fd3784ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c (2713 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i64m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i64m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i64.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm # | ... # `---data was truncated (10240/35597) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563d78f1c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563d78f19515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563d78f1ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8b80d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8b80d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8b80d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8b80d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563d78eb224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563d78eb2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563d78e96f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563d78b46176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563d78b45e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8b80d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8b80d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8b80d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563d78b45d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbkc.c (2714 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbkc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkc -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c -check-prefix=RV32ZBKC # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkc -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @clmul_32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.clmul.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @clmulh_32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.clmulh.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.clmul.i32(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.clmulh.i32(i32, i32) #2 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbkc" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_zbkc1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dcb9b2657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055dcb9b23515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055dcb9b26cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f98b0c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f98b0ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f98b0c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f98b0c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dcb9abc24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055dcb9abc096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055dcb9aa0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055dcb9750176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055dcb974fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f98b0c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f98b0c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f98b0c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dcb974fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c -check-prefix=RV32ZBKC # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c -check-prefix=RV32ZBKC # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c (2715 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bcfecf557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bcfecf2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bcfecf5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbcd8249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbcd82a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbcd8249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbcd8231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bcfec8b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bcfec8b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bcfec6ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bcfe91f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bcfe91ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbcd8232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbcd82330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbcd82330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bcfe91ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c (2716 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005630211e057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005630211dd515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005630211e0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fadfe41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fadfe4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fadfe41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fadfe403507 abort ./stdlib/abort.c:85:3 # | #7 0x000056302117624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563021176096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056302115af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563020e0a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563020e09e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fadfe404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fadfe4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fadfe4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563020e09d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c (2717 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32mf2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m1_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m4_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m8_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32mf2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m1_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Fu # | ... # `---data was truncated (10240/25086) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055feae4b057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055feae4ad515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055feae4b0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7403333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f740338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7403333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f740331b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055feae44624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055feae446096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055feae42af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055feae0da176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055feae0d9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f740331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f740331d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f740331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055feae0d9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c (2718 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_u16mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_u16mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_u16m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16mf4x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.v # | ... # `---data was truncated (10240/20439) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559de355557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559de3552515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559de3555cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1747d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1747d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1747d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1747d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559de34eb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559de34eb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559de34cff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559de317f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559de317ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1747d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1747d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1747d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559de317ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c (2719 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv16bf16.nxv16bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | stor # | ... # `---data was truncated (10240/29518) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559b2035357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559b20350515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559b20353cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f573ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f573ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f573ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f573ff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559b202e924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559b202e9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559b202cdf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559b1ff7d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559b1ff7ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f573ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f573ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f573ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559b1ff7cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c (2720 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_i8mf4x7(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562a05f2057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562a05f1d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562a05f20cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2450105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f245015c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2450105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f24500ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562a05eb624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562a05eb6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562a05e9af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562a05b4a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562a05b49e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f24500eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f24500ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f24500ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562a05b49d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c (2721 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf4x5_tumu( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 0, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", # | ... # `---data was truncated (10240/16800) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556d11bf157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556d11bee515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556d11bf1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcb8be49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcb8bea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcb8be49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcb8be31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556d11b8724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556d11b87096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556d11b6bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556d1181b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556d1181ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcb8be32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcb8be330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcb8be330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556d1181ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c (2722 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsm4k.nxv1i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv1i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsm4k.nxv2i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv2i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsm4k.nxv4i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv4i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsm4k.nxv8i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv8i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsm4k.nxv16i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv16i32.i64.i64(, , i64 immarg, i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a5d6b7e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a5d6b7b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a5d6b7ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f025c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f025c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f025c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f025c631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a5d6b1424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a5d6b14096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a5d6af8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a5d67a8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a5d67a7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f025c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f025c6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f025c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a5d67a7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c (2723 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | stor # | ... # `---data was truncated (10240/52599) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e6f7aed57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e6f7aea515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e6f7aedcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fab58449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fab584a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fab58449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fab58431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e6f7a8324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e6f7a83096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e6f7a67f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e6f7717176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e6f7716e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fab58432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fab584330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fab584330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e6f7716d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c (2724 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv1i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv2i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv4i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv8i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv16i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv32i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv64i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf8_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf4_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf2_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c (2725 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d46a55e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d46a55b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d46a55ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd4f6449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd4f64a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd4f6449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd4f6431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d46a4f424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d46a4f4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d46a4d8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d46a188176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d46a187e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd4f6432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd4f64330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd4f64330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d46a187d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c (2726 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf4_tum( %mask, %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , alig # | ... # `---data was truncated (10240/41926) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d038a5e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d038a5b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d038a5ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f116b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f116b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f116b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f116b51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d0389f424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d0389f4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d0389d8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d038688176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d038687e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f116b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f116b51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f116b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d038687d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c (2727 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv1i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv2i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv4i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv8i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv16i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055584a6d957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055584a6d6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055584a6d9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff4e8533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff4e858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff4e8533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff4e851b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055584a66f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055584a66f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055584a653f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055584a303176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055584a302e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff4e851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff4e851d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff4e851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055584a302d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c (2728 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 4) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractva # | ... # `---data was truncated (10240/27866) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056391baaf57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056391baac515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056391baafcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb202c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb202ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb202c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb202c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056391ba4524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056391ba45096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056391ba29f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056391b6d9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056391b6d8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb202c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb202c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb202c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056391b6d8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c (2729 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_i64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_u64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_f64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_i64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_u64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_f64m1x7_tumu( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.ve # | ... # `---data was truncated (10240/18498) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556c348a657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556c348a3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556c348a6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa559e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa559ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa559e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa559e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556c3483c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556c3483c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556c34820f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556c344d0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556c344cfe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa559e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa559e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa559e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556c344cfd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c (2730 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32mf2x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_i32mf2x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_i32m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_u32mf2x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_u32m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_i32mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_i32m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_u32mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8 # | ... # `---data was truncated (10240/12059) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d47842357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d478420515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d478423cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2676e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2676ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2676e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2676e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d4783b924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d4783b9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d47839df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d47804d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d47804ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2676e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2676e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2676e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d47804cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c (2731 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %o # | ... # `---data was truncated (10240/29054) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005627f793a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005627f7937515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005627f793acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fca71849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fca718a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fca71849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fca71831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005627f78d024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005627f78d0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005627f78b4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005627f7564176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005627f7563e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fca71832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fca718330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fca718330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005627f7563d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c (2732 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_i64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_u64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_f64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_i64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_u64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_f64m1x8_tumu( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 0, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_i64m1x8_tumu( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tu # | ... # `---data was truncated (10240/16560) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056454cf2457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056454cf21515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056454cf24cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9fcde49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9fcdea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9fcde49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9fcde31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056454ceba24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056454ceba096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056454ce9ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056454cb4e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056454cb4de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9fcde32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9fcde330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9fcde330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056454cb4dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c (2733 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca # | ... # `---data was truncated (10240/14311) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556d8455757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556d84554515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556d84557cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f133b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f133b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f133b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f133b31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556d844ed24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556d844ed096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556d844d1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556d84181176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556d84180e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f133b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f133b31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f133b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556d84180d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c (2734 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m1x # | ... # `---data was truncated (10240/25695) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e77942457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e779421515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e779424cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5e7dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5e7dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5e7dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5e7dc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e7793ba24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e7793ba096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e77939ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e77904e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e77904de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5e7dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5e7dc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5e7dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e77904dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c (2735 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv1f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv2f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv4f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv8f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m8_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv16f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv16f32.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfvfexp32e,+zicsr,+zve32f,+zve32x,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfvfexp32e0p5"} # | !3 = !{i32 8, !"SmallDataLi # | ... # `---data was truncated (10240/10285) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bc64f4b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bc64f48515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bc64f4bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3043d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3043d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3043d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3043d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bc64ee124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bc64ee1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bc64ec5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bc64b75176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bc64b74e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3043d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3043d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3043d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bc64b74d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c (2736 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf4_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf2_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m1_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m2_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m4_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m8_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf4_tum( %mask, %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %src.addr, align 2 # | %3 = load bfloat, ptr %value.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf2_tum( %mask, %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 # | ... # `---data was truncated (10240/32570) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005635126e757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005635126e4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005635126e7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd068333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd06838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd068333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd06831b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056351267d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056351267d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563512661f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563512311176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563512310e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd06831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd06831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd06831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563512310d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c (2737 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv16bf16.nxv16bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/riscv-xcvalu-c-api.c (2738 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/riscv-xcvalu-c-api.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xcvalu -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xcvalu -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_sle(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 %1, ptr %b.addr.i, align 4 # | %2 = load i32, ptr %a.addr.i, align 4 # | %3 = load i32, ptr %b.addr.i, align 4 # | %4 = icmp sle i32 %2, %3 # | %sle.i = zext i1 %4 to i32 # | ret i32 %sle.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_sleu(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 %1, ptr %b.addr.i, align 4 # | %2 = load i32, ptr %a.addr.i, align 4 # | %3 = load i32, ptr %b.addr.i, align 4 # | %4 = icmp ule i32 %2, %3 # | %sleu.i = zext i1 %4 to i32 # | ret i32 %sleu.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_min(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 %1, ptr %b.addr.i, align 4 # | %2 = load i32, ptr %a.addr.i, align 4 # | %3 = load i32, ptr %b.addr.i, align 4 # | %elt.min.i = call i32 @llvm.smin.i32(i32 %2, i32 %3) # | ret i32 %elt.min.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_minu(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 %1, ptr %b.addr.i, align 4 # | %2 = load i32, ptr %a.addr.i, align 4 # | %3 = load i32, ptr %b.addr.i, align 4 # | %elt.min.i = call i32 @llvm.umin.i32(i32 %2, i32 %3) # | ret i32 %elt.min.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_max(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 %1, ptr %b.addr.i, align 4 # | %2 = load i32, ptr %a.addr.i, align 4 # | %3 = load i32, ptr %b.addr.i, align 4 # | %elt.max.i = call i32 @llvm.smax.i32(i32 %2, i32 %3) # | ret i32 %elt.max.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_maxu(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 %1, ptr %b.addr.i, align 4 # | %2 = load i32, ptr %a.addr.i, align 4 # | %3 = load i32, ptr %b.addr.i, align 4 # | %elt.max.i = call i32 @llvm.umax.i32(i32 %2, i32 %3) # | ret i32 %elt.max.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_exths(i16 noundef signext %a) #0 { # | entry: # | %a.addr.i = alloca i16, align 2 # | %a.addr = alloca i16, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | store i16 %0, ptr %a.addr.i, align 2 # | %1 = load i16, ptr %a.addr.i, align 2 # | %conv.i = sext i16 %1 to i32 # | %exths.i = sext i16 %1 to i32 # | ret i32 %exths.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_exthz(i16 noundef zeroext %a) #0 { # | entry: # | %a.addr.i = alloca i16, align 2 # | %a.addr = alloca i16, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | store i16 %0, ptr %a.addr.i, align 2 # | %1 = load i16, ptr %a.addr.i, align 2 # | %conv.i = zext i16 %1 to i32 # | %exthz.i = zext i16 %1 to i32 # | ret i32 %exthz.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_extbs(i8 noundef signext %a) #0 { # | entry: # | %a.addr.i = alloca i8, align 1 # | %a.addr = alloca i8, align 1 # | store i8 %a, ptr %a.addr, align 1 # | %0 = load i8, ptr %a.addr, align 1 # | store i8 %0, ptr %a.addr.i, align 1 # | %1 = load i8, ptr %a.addr.i, align 1 # | %conv.i = sext i8 %1 to i32 # | %extbs.i = sext i8 %1 to i32 # | ret i32 %extbs.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_extbz(i8 noundef zeroext %a) #0 { # | entry: # | %a.addr.i = alloca i8, align 1 # | %a.addr = alloca i8, align 1 # | store i8 %a, ptr %a.addr, align 1 # | %0 = load i8, ptr %a.addr, align 1 # | store i8 %0, ptr %a.addr.i, align 1 # | %1 = load i8, ptr %a.addr.i, align 1 # | %conv.i = zext i8 %1 to i32 # | %extbz.i = zext i8 %1 to i32 # | ret i32 %extbz.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_clip(i32 noundef %a) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 0, ptr %b.addr.i, align 4 # | %1 = load i32, ptr %a.addr.i, align 4 # | %2 = load i32, ptr %b.addr.i, align 4 # | %3 = call i32 @llvm.riscv.cv.alu.clip(i32 %1, i32 %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_clipu(i32 noundef %a) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 0, ptr %b.addr.i, align 4 # | %1 = load i32, ptr %a.addr.i, align 4 # | %2 = load i32, ptr %b.addr.i, align 4 # | %3 = call i32 @llvm.riscv.cv.alu.clipu(i32 %1, i32 %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_addN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %shft.addr.i = alloca i8, align 1 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 %1, ptr %b.addr.i, align 4 # | store i8 0, ptr %shft.addr.i, align 1 # | %2 = load i32, ptr %a.addr.i, align 4 # | %3 = load i32, ptr %b.addr.i, align 4 # | %4 = load i8, ptr %shft.addr.i, align 1 # | %conv.i = zext i8 %4 to i32 # | %5 = call i32 @llvm.riscv.cv.alu.addN(i32 %2, i32 %3, i32 %conv.i) # | ret i32 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_adduN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %shft.addr.i = alloca i8, align 1 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 %1, ptr %b.addr.i, align 4 # | store i8 0, ptr %shft.addr.i, align 1 # | %2 = load i32, ptr %a.addr.i, align 4 # | %3 = load i32, ptr %b.addr.i, align 4 # | %4 = load i8, ptr %shft.addr.i, align 1 # | %conv.i = zext i8 %4 to i32 # | %5 = call i32 @llvm.riscv.cv.alu.adduN(i32 %2, i32 %3, i32 %conv.i) # | ret i32 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_addRN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %shft.addr.i = alloca i8, align 1 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 %1, ptr %b.addr.i, align 4 # | store i8 0, ptr %shft.addr.i, align 1 # | %2 = load i32, ptr %a.addr.i, align 4 # | %3 = load i32, ptr %b.addr.i, align 4 # | %4 = load i8, ptr %shft.addr.i, align 1 # | %conv.i = zext i8 %4 to i32 # | %5 = call i32 @llvm.riscv.cv.alu.addRN(i32 %2, i32 %3, i32 %conv.i) # | ret i32 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_adduRN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %shft.addr.i = alloca i8, align 1 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 %1, ptr %b.addr.i, align 4 # | store i8 0, ptr %shft.addr.i, align 1 # | %2 = load i32, ptr %a.addr.i, align 4 # | %3 = load i32, ptr %b.addr.i, align 4 # | %4 = load i8, ptr %shft.addr.i, align 1 # | %conv.i = zext i8 %4 to i32 # | %5 = call i32 @llvm.riscv.cv.alu.adduRN(i32 %2, i32 %3, i32 %conv.i) # | ret i32 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_subN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %shft.addr.i = alloca i8, align 1 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | st # | ... # `---data was truncated (10240/15696) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558f59ecd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558f59eca515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558f59ecdcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc1ce733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc1ce78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc1ce733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc1ce71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558f59e6324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558f59e63096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558f59e47f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558f59af7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558f59af6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc1ce71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc1ce71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc1ce71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558f59af6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c (2739 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c (2740 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e4d76ba57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e4d76b7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e4d76bacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f69d1505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f69d155c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f69d1505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f69d14ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e4d765024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e4d7650096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e4d7634f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e4d72e4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e4d72e3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f69d14eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f69d14ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f69d14ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e4d72e3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c (2741 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv32i16.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.v # | ... # `---data was truncated (10240/58683) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558145ecc57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558145ec9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558145ecccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb29c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb29c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb29c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb29c71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558145e6224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558145e62096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558145e46f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558145af6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558145af5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb29c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb29c71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb29c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558145af5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c (2742 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_i64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_i64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_u64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_u64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m1x3_tum( %mask, target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local t # | ... # `---data was truncated (10240/36031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564688bf757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564688bf4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564688bf7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa6ad849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa6ad8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa6ad849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa6ad831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564688b8d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564688b8d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564688b71f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564688821176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564688820e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa6ad832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa6ad8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa6ad8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564688820d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c (2743 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf8x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_u8mf8x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_u8mf4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_u8mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_u8m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstrid # | ... # `---data was truncated (10240/28111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fc52dbc57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fc52db9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fc52dbccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff7e4b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff7e4b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff7e4b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff7e4b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fc52d5224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fc52d52096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fc52d36f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fc529e6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fc529e5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff7e4b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff7e4b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff7e4b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fc529e5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c (2744 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf4_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f16.nxv1f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f16.nxv1f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf2_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f16.nxv2f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f16.nxv2f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define # | ... # `---data was truncated (10240/18595) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056382aec657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056382aec3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056382aec6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f78d9d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f78d9d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f78d9d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f78d9d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056382ae5c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056382ae5c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056382ae40f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056382aaf0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056382aaefe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f78d9d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f78d9d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f78d9d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056382aaefd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c (2745 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_i8m2_i8m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv8i8.nxv16i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8i8.nxv16i8(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_i8m4_i8m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv8i8.nxv32i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8i8.nxv32i8(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_i8m8_i8m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv8i8.nxv64i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8i8.nxv64i8(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_i8m4_i8m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv16i8.nxv32i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv16i8.nxv32i8(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_i8m8_i8m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv16i8.nxv64i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv16i8.nxv64i8(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_i8m8_i8m4( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv32i8.nxv64i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv32i8.nxv64i8(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_u8m2_u8m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv8i8.nxv16i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_u8m4_u8m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv8i8.nxv32i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_u8m8_u8m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv8i8.nxv64i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_u8m4_u8m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv16i8.nxv32i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_u8m8_u8m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv16i8.nxv64i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_u8m8_u8m4( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv32i8.nxv64i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_i16m2_i16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4i16.nxv8i16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4i16.nxv8i16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_i16m4_i16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4i16.nxv16i16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4i16.nxv16i16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_i16m8_i16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4i16.nxv32i16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4i16.nxv32i16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale # | ... # `---data was truncated (10240/40902) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a630ede57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a630edb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a630edecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4681449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f46814a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4681449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4681431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a630e7424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a630e74096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a630e58f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a630b08176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a630b07e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4681432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f46814330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f46814330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a630b07d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c (2746 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_u32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | ... # `---data was truncated (10240/60691) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cca817c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cca8179515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cca817ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe164c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe164ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe164c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe164c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cca811224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cca8112096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cca80f6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cca7da6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cca7da5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe164c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe164c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe164c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cca7da5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c (2747 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf8x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf4x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv16i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv16i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8mf8x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8mf4x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8mf2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl. # | ... # `---data was truncated (10240/13557) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558b2e30c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558b2e309515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558b2e30ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa65cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa65cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa65cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa65cd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558b2e2a224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558b2e2a2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558b2e286f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558b2df36176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558b2df35e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa65cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa65cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa65cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558b2df35d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/compare.c (2748 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/compare.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c --check-prefixes=CHECK,CHECK-NOSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = fcmp oeq <8 x half> %0, %1 # | %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = fcmp oeq <4 x float> %0, %1 # | %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = icmp eq <16 x i8> %0, %1 # | %3 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = icmp eq <8 x i16> %0, %1 # | %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = icmp eq <4 x i32> %0, %1 # | %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = icmp eq <16 x i8> %0, %1 # | %3 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = icmp eq <8 x i16> %0, %1 # | %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = icmp eq <4 x i32> %0, %1 # | %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_f16(<8 x half> noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca half, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store half %b, ptr %b.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load half, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x half> poison, half %1, i64 0 # | %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer # | %2 = fcmp oeq <8 x half> %0, %.splat # | %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_f32(<4 x float> noundef %a, float noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca float, align 4 # | store <4 x float> %a, ptr %a.addr, align 8 # | store float %b, ptr %b.addr, align 4 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load float, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x float> poison, float %1, i64 0 # | %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer # | %2 = fcmp oeq <4 x float> %0, %.splat # | %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_s8(<16 x i8> noundef %a, i8 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = icmp eq <16 x i8> %0, %.splat # | %3 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = icmp eq <8 x i16> %0, %.splat # | %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = icmp eq <4 x i32> %0, %.splat # | %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = icmp eq <16 x i8> %0, %.splat # | %3 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = icmp eq <8 x i16> %0, %.splat # | %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = # | ... # `---data was truncated (10240/125481) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ad2b29b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ad2b298515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ad2b29bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8dd2933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8dd298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8dd2933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8dd291b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ad2b23124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ad2b231096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ad2b215f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ad2aec5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ad2aec4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8dd291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8dd291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8dd291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ad2aec4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c --check-prefixes=CHECK,CHECK-NOSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c --check-prefixes=CHECK,CHECK-NOSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c (2749 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none # | ... # `---data was truncated (10240/61673) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056286e4e757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056286e4e4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056286e4e7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5f79c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5f79ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5f79c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5f79c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056286e47d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056286e47d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056286e461f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056286e111176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056286e110e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5f79c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5f79c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5f79c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056286e110d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c (2750 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16mf4_i8mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16mf2_i8mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m1_i8mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m2_i8m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m4_i8m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m8_i8m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16mf4_u8mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16mf2_u8mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m1_u8mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m2_u8m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %v # | ... # `---data was truncated (10240/142327) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559114dc757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559114dc4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559114dc7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faf8181bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faf818725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faf8181ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faf81803507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559114d5d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559114d5d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559114d41f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005591149f1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005591149f0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007faf81804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faf818050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faf818050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005591149f0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c (2751 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_f64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_f64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_i64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_i64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_u64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_u64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_f64m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_f64m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs # | ... # `---data was truncated (10240/15978) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560ccfc2757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560ccfc24515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560ccfc27cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff1c301bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff1c30725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff1c301ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff1c3003507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560ccfbbd24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560ccfbbd096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560ccfba1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560ccf851176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560ccf850e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff1c3004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff1c30050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff1c30050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560ccf850d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c (2752 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16mf4( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16mf2( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m1( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m2( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m4( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv16f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m8( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv32f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv32f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32mf2( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv1f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32m1( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv2f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32m2( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv4f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv4f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32m4( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv8f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv8f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2, # | ... # `---data was truncated (10240/34589) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d7a162e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d7a162b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d7a162ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcd24d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcd24d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcd24d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcd24d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d7a15c424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d7a15c4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d7a15a8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d7a1258176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d7a1257e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcd24d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcd24d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcd24d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d7a1257d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c (2753 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16mf4( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16mf2( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m1( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv4f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv4f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m2( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv8f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv8f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m4( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv16f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv16f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m8( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv32f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv32f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32mf2( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1f32.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32m1( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2f32.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32m2( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c (2754 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16mf4x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16mf2x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16mf4x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16mf2x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_u16mf4x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("ri # | ... # `---data was truncated (10240/13634) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ab89db057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ab89dad515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ab89db0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3616a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3616a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3616a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3616a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ab89d4624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ab89d46096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ab89d2af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ab899da176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ab899d9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3616a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3616a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3616a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ab899d9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c (2755 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_bf16mf4_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_bf16mf4_f32mf2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_bf16mf4_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_bf16_f32mf2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_bf16mf2_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_bf16mf2_f32m1( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_bf16mf2_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_bf16_f32m1( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_bf16m1_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv4f32.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_bf16m1_f32m2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | # | ... # `---data was truncated (10240/86100) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565259d5657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000565259d53515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000565259d56cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe5f2b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe5f2b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe5f2b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe5f2b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565259cec24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000565259cec096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000565259cd0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000565259980176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056525997fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe5f2b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe5f2b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe5f2b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056525997fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c (2756 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16mf4_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m4_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m8_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f32mf2_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f32m1_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f32m2_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv1f64.nxv4f32.i64( poison, %0, %1, i64 7, i64 %2 # | ... # `---data was truncated (10240/50524) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bfbff5c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bfbff59515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bfbff5ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f31cb933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f31cb98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f31cb933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f31cb91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bfbfef224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bfbfef2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bfbfed6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bfbfb86176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bfbfb85e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f31cb91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f31cb91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f31cb91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bfbfb85d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c (2757 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c (2758 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32mf2_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m1_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m2_m( %mask, %src, i64 noundef %vl) #0 { # | entr # | ... # `---data was truncated (10240/18361) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005627c859c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005627c8599515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005627c859ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4763c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4763ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4763c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4763c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005627c853224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005627c8532096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005627c8516f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005627c81c6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005627c81c5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4763c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4763c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4763c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005627c81c5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c (2759 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf4_rm_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf2_rm_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m1_rm_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m2_rm_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m4_rm_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwin # | ... # `---data was truncated (10240/10610) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562c66bf857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562c66bf5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562c66bf8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f04a5c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f04a5ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f04a5c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f04a5c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562c66b8e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562c66b8e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562c66b72f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562c66822176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562c66821e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f04a5c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f04a5c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f04a5c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562c66821d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c (2760 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555c9633457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555c96331515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555c96334cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7888933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f788898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7888933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f788891b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555c962ca24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555c962ca096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555c962aef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555c95f5e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555c95f5de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f788891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f788891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f788891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555c95f5dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c (2761 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv8i8.nxv8f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: # | ... # `---data was truncated (10240/12431) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005582c3d2c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005582c3d29515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005582c3d2ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feee1933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feee198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feee1933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feee191b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005582c3cc224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005582c3cc2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005582c3ca6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005582c3956176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005582c3955e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007feee191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feee191d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feee191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005582c3955d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c (2762 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range( # | ... # `---data was truncated (10240/12227) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056400d14e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056400d14b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056400d14ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6946c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6946ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6946c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6946c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056400d0e424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056400d0e4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056400d0c8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056400cd78176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056400cd77e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6946c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6946c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6946c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056400cd77d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c (2763 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv1i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv2i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv4i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv8i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv16i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005563ee0ac57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005563ee0a9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005563ee0accbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fac2f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fac2f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fac2f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fac2f91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005563ee04224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005563ee042096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005563ee026f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005563edcd6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005563edcd5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fac2f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fac2f91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fac2f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005563edcd5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c (2764 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bdce3ff57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bdce3fc515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bdce3ffcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc8d5d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc8d5d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc8d5d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc8d5d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bdce39524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bdce395096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bdce379f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bdce029176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bdce028e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc8d5d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc8d5d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc8d5d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bdce028d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c (2765 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv32i16.i64( poison, %0, i64 %1) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c (2766 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsqrt7.mask. # | ... # `---data was truncated (10240/28162) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e35b29257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e35b28f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e35b292cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f77f1333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f77f138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f77f1333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f77f131b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e35b22824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e35b228096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e35b20cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e35aebc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e35aebbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f77f131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f77f131d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f77f131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e35aebbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c (2767 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f917ac757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f917ac4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f917ac7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0077a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0077a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0077a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0077a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f917a5d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f917a5d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f917a41f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f9176f1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f9176f0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0077a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0077a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0077a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f9176f0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c (2768 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16mf4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv1f16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1f16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16mf2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv2f16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2f16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m1_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv4f16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv4f16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv8f16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv8f16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv16f16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv16f16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv32f16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv32f16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16mf4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv1i16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1i16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16mf2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv2i16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2i16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16m1_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, # | ... # `---data was truncated (10240/20307) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055638971257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055638970f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556389712cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fae70533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fae7058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fae70533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fae7051b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005563896a824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005563896a8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055638968cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055638933c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055638933be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fae7051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fae7051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fae7051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055638933bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c (2769 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m1x4_tum(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmovn.c (2770 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmovn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovnbq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %b.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = shufflevector <16 x i8> %1, <16 x i8> poison, <16 x i32> # | %3 = bitcast <16 x i8> %2 to <8 x i16> # | %4 = shufflevector <8 x i16> %0, <8 x i16> %3, <16 x i32> # | %5 = trunc <16 x i16> %4 to <16 x i8> # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovnbq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %b.addr, align 8 # | %1 = load <8 x i16>, ptr %a.addr, align 8 # | %2 = shufflevector <8 x i16> %1, <8 x i16> poison, <8 x i32> # | %3 = bitcast <8 x i16> %2 to <4 x i32> # | %4 = shufflevector <4 x i32> %0, <4 x i32> %3, <8 x i32> # | %5 = trunc <8 x i32> %4 to <8 x i16> # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovnbq_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %b.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = shufflevector <16 x i8> %1, <16 x i8> poison, <16 x i32> # | %3 = bitcast <16 x i8> %2 to <8 x i16> # | %4 = shufflevector <8 x i16> %0, <8 x i16> %3, <16 x i32> # | %5 = trunc <16 x i16> %4 to <16 x i8> # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovnbq_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %b.addr, align 8 # | %1 = load <8 x i16>, ptr %a.addr, align 8 # | %2 = shufflevector <8 x i16> %1, <8 x i16> poison, <8 x i32> # | %3 = bitcast <8 x i16> %2 to <4 x i32> # | %4 = shufflevector <4 x i32> %0, <4 x i32> %3, <8 x i32> # | %5 = trunc <8 x i32> %4 to <8 x i16> # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovntq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <8 x i16> # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <16 x i32> # | %4 = trunc <16 x i16> %3 to <16 x i8> # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovntq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = bitcast <8 x i16> %0 to <4 x i32> # | %2 = load <4 x i32>, ptr %b.addr, align 8 # | %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <8 x i32> # | %4 = trunc <8 x i32> %3 to <8 x i16> # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovntq_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <8 x i16> # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <16 x i32> # | %4 = trunc <16 x i16> %3 to <16 x i8> # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovntq_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = bitcast <8 x i16> %0 to <4 x i32> # | %2 = load <4 x i32>, ptr %b.addr, align 8 # | %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <8 x i32> # | %4 = trunc <8 x i32> %3 to <8 x i16> # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovnbq_m_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 0, <8 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vmovn.predicated.v16i8.v8i16.v8i1(<16 x i8>, <8 x i16>, i32, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovnbq_m_s32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 0, <4 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vmovn.predicated.v8i16.v4i32.v4i1(<8 x i16>, <4 x i32>, i32, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovnbq_m_u16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 0, <8 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovnbq_m_u32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 0, <4 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovntq_m_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, a # | ... # `---data was truncated (10240/13410) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d03bf9e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d03bf9b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d03bf9ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd61e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd61e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd61e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd61e231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d03bf3424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d03bf34096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d03bf18f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d03bbc8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d03bbc7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd61e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd61e2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd61e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d03bbc7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c (2771 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv16bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv32bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv32bf16.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055588f63157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055588f62e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055588f631cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc71761bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc7176725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc71761ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc717603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055588f5c724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055588f5c7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055588f5abf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055588f25b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055588f25ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc717604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc7176050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc7176050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055588f25ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c (2772 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055888ffd757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055888ffd4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055888ffd7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6535733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f653578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6535733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f653571b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055888ff6d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055888ff6d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055888ff51f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055888fc01176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055888fc00e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f653571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f653571d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f653571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055888fc00d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c (2773 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv1f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv2f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv4f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv8f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m8_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+xsfvfexpa,+xsfvfexpa64e,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfvfexpa0p2_xsfvfexpa64e0p2"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564ef7e3b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564ef7e38515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564ef7e3bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f896a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f896a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f896a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f896a51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564ef7dd124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564ef7dd1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564ef7db5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564ef7a65176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564ef7a64e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f896a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f896a51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f896a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564ef7a64d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c (2774 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32mf2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m1( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m4( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c (2775 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16mf4(bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load bfloat, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv1bf16.i64( poison, bfloat %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv1bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16mf2(bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load bfloat, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv2bf16.i64( poison, bfloat %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv2bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m1(bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load bfloat, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv4bf16.i64( poison, bfloat %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv4bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m2(bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load bfloat, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv8bf16.i64( poison, bfloat %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv8bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m4(bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load bfloat, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv16bf16.i64( poison, bfloat %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv16bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m8(bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load bfloat, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv32bf16.i64( poison, bfloat %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv32bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16mf4_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv1bf16( %0) # | ret bfloat %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare bfloat @llvm.riscv.vfmv.f.s.nxv1bf16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16mf4(bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load bfloat, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.s.f.nxv1bf16.i64( poison, bfloat %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv1bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16mf2_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv2bf16( %0) # | ret bfloat %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare bfloat @llvm.riscv.vfmv.f.s.nxv2bf16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16mf2(bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load bfloat, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.s.f.nxv2bf16.i64( poison, bfloat %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv2bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16m1_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv4bf16( %0) # | ret bfloat %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare bfloat @llvm.riscv.vfmv.f.s.nxv4bf16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16m1(bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load bfloat, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.s.f.nxv4bf16.i64( poison, bfloat %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv4bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16m2_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv8bf16( %0) # | ret bfloat %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare bfloat @llvm.riscv.vfmv.f.s.nxv8bf16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16m2(bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load bfloat, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.s.f.nxv8bf16.i64( poison, bfloat %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv8bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16m4_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store % # | ... # `---data was truncated (10240/13308) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055853c08f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055853c08c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055853c08fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4195b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4195b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4195b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4195b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055853c02524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055853c025096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055853c009f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055853bcb9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055853bcb8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4195b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4195b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4195b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055853bcb8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c (2776 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16m8(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i16.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i16.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c (2777 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056259ab3e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056259ab3b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056259ab3ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f45a8849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f45a88a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f45a8849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f45a8831507 abort ./stdlib/abort.c:85:3 # | #7 0x000056259aad424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056259aad4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056259aab8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056259a768176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056259a767e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f45a8832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f45a88330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f45a88330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056259a767d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c (2778 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3e # | ... # `---data was truncated (10240/228857) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558e89ef057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558e89eed515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558e89ef0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd1a4a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd1a4aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd1a4a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd1a4a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558e89e8624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558e89e86096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558e89e6af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558e89b1a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558e89b19e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd1a4a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd1a4a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd1a4a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558e89b19d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vabdq.c (2779 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vabdq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vabdq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vabd.v16i8(<16 x i8> %0, <16 x i8> %1, i32 0) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vabd.v16i8(<16 x i8>, <16 x i8>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vabdq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vabd.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vabd.v4i32(<4 x i32>, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vabdq_f32(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = call <8 x half> @llvm.arm.mve.vabd.v8f16(<8 x half> %0, <8 x half> %1, i32 0) # | ret <8 x half> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vabd.v8f16(<8 x half>, <8 x half>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vabdq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.abd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.abd.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vabdq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.abd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.abd.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vabdq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x float>, ptr %inactive.addr, align 8 # | %6 = call <4 x float> @llvm.arm.mve.abd.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.abd.predicated.v4f32.v4i1(<4 x float>, <4 x float>, i32, <4 x i1>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vabdq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.abd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vabdq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.abd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.abd.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vabdq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x half> @llvm.arm.mve.abd.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> undef) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.abd.predicated.v8f16.v8i1(<8 x half>, <8 x half>, i32, <8 x i1>, <8 x half>) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055be57d9a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055be57d97515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055be57d9acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe1d9649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe1d96a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe1d9649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe1d9631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055be57d3024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055be57d30096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055be57d14f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055be579c4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055be579c3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe1d9632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe1d96330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe1d96330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055be579c3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c (2780 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16mf4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16mf2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m1x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16mf4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16mf2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16m1x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16m2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv. # | ... # `---data was truncated (10240/16654) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005556bfbce57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005556bfbcb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005556bfbcecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff799905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff79995c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff799905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff7998ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005556bfb6424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005556bfb64096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005556bfb48f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005556bf7f8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005556bf7f7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff7998eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff7998ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff7998ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005556bf7f7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c (2781 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m4_tu( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c (2782 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16mf4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16mf2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m1x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16mf4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16mf2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16m1x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16m2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16m4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_u16mf4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_u16mf2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline n # | ... # `---data was truncated (10240/28559) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556f27a8b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556f27a88515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556f27a8bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcc05849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcc058a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcc05849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcc05831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556f27a2124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556f27a21096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556f27a05f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556f276b5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556f276b4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcc05832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcc058330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcc058330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556f276b4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c (2783 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005600d6ed757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005600d6ed4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005600d6ed7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8f95933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8f9598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8f95933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8f9591b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005600d6e6d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005600d6e6d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005600d6e51f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005600d6b01176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005600d6b00e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8f9591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8f9591d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8f9591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005600d6b00d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c (2784 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf8x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf4x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf8x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf4x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005570c9ca057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005570c9c9d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005570c9ca0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9059849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f90598a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9059849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9059831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005570c9c3624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005570c9c36096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005570c9c1af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005570c98ca176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005570c98c9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9059832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f90598330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f90598330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005570c98c9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c (2785 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8mf8x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8mf4x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_u8mf8x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_u8mf4x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_u8mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_u8m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8mf8x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8mf4x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask. # | ... # `---data was truncated (10240/18972) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559128db657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559128db3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559128db6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd0a9b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd0a9b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd0a9b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd0a9aed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559128d4c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559128d4c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559128d30f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005591289e0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005591289dfe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd0a9aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd0a9aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd0a9aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005591289dfd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c (2786 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_f32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_f32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_i32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_i32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_u32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_u32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_f32mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_f32m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounw # | ... # `---data was truncated (10240/15952) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005626dba5657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005626dba53515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005626dba56cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4e8fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4e8fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4e8fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4e8fb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005626db9ec24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005626db9ec096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005626db9d0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005626db680176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005626db67fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4e8fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4e8fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4e8fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005626db67fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c (2787 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32mf2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m1_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m4_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64( # | ... # `---data was truncated (10240/179185) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557a5577457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557a55771515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557a55774cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6462249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f64622a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6462249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6462231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557a5570a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557a5570a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557a556eef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557a5539e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557a5539de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6462232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f64622330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f64622330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557a5539dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vld24.c (2788 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vld24.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | %struct.float16x8x2_t = type { [2 x <8 x half>] } # | %struct.uint8x16x4_t = type { [4 x <16 x i8>] } # | %struct.uint32x4x2_t = type { [2 x <4 x i32>] } # | %struct.int8x16x4_t = type { [4 x <16 x i8>] } # | %struct.uint16x8x2_t = type { [2 x <8 x i16>] } # | %struct.int32x4x2_t = type { [2 x <4 x i32>] } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc %struct.float16x8x2_t @test_vld2q_f16(ptr noundef %addr) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | store ptr %addr, ptr %addr.addr, align 4 # | %0 = load ptr, ptr %addr.addr, align 4 # | %1 = call { <8 x half>, <8 x half> } @llvm.arm.mve.vld2q.v8f16.p0(ptr %0) # | %2 = extractvalue { <8 x half>, <8 x half> } %1, 0 # | %3 = insertvalue %struct.float16x8x2_t poison, <8 x half> %2, 0, 0 # | %4 = extractvalue { <8 x half>, <8 x half> } %1, 1 # | %5 = insertvalue %struct.float16x8x2_t %3, <8 x half> %4, 0, 1 # | ret %struct.float16x8x2_t %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <8 x half>, <8 x half> } @llvm.arm.mve.vld2q.v8f16.p0(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc %struct.uint8x16x4_t @test_vld4q_u8(ptr noundef %addr) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | store ptr %addr, ptr %addr.addr, align 4 # | %0 = load ptr, ptr %addr.addr, align 4 # | %1 = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.mve.vld4q.v16i8.p0(ptr %0) # | %2 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 0 # | %3 = insertvalue %struct.uint8x16x4_t poison, <16 x i8> %2, 0, 0 # | %4 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 1 # | %5 = insertvalue %struct.uint8x16x4_t %3, <16 x i8> %4, 0, 1 # | %6 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 2 # | %7 = insertvalue %struct.uint8x16x4_t %5, <16 x i8> %6, 0, 2 # | %8 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 3 # | %9 = insertvalue %struct.uint8x16x4_t %7, <16 x i8> %8, 0, 3 # | ret %struct.uint8x16x4_t %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.mve.vld4q.v16i8.p0(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc void @test_vst2q_u32(ptr noundef %addr, %struct.uint32x4x2_t %value.coerce) #0 { # | entry: # | %value = alloca %struct.uint32x4x2_t, align 8 # | %addr.addr = alloca ptr, align 4 # | %tmp = alloca %struct.uint32x4x2_t, align 8 # | %0 = getelementptr inbounds nuw %struct.uint32x4x2_t, ptr %value, i32 0, i32 0 # | %1 = extractvalue %struct.uint32x4x2_t %value.coerce, 0 # | store [2 x <4 x i32>] %1, ptr %0, align 8 # | store ptr %addr, ptr %addr.addr, align 4 # | %2 = load ptr, ptr %addr.addr, align 4 # | call void @llvm.memcpy.p0.p0.i32(ptr align 8 %tmp, ptr align 8 %value, i32 32, i1 false) # | %3 = load %struct.uint32x4x2_t, ptr %tmp, align 8 # | %4 = extractvalue %struct.uint32x4x2_t %3, 0, 0 # | %5 = extractvalue %struct.uint32x4x2_t %3, 0, 1 # | call void @llvm.arm.mve.vst2q.p0.v4i32(ptr %2, <4 x i32> %4, <4 x i32> %5, i32 0) # | call void @llvm.arm.mve.vst2q.p0.v4i32(ptr %2, <4 x i32> %4, <4 x i32> %5, i32 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.memcpy.p0.p0.i32(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i32, i1 immarg) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.arm.mve.vst2q.p0.v4i32(ptr, <4 x i32>, <4 x i32>, i32) #3 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc void @test_vst4q_s8(ptr noundef %addr, %struct.int8x16x4_t %value.coerce) #0 { # | entry: # | %value = alloca %struct.int8x16x4_t, align 8 # | %addr.addr = alloca ptr, align 4 # | %tmp = alloca %struct.int8x16x4_t, align 8 # | %0 = getelementptr inbounds nuw %struct.int8x16x4_t, ptr %value, i32 0, i32 0 # | %1 = extractvalue %struct.int8x16x4_t %value.coerce, 0 # | store [4 x <16 x i8>] %1, ptr %0, align 8 # | store ptr %addr, ptr %addr.addr, align 4 # | %2 = load ptr, ptr %addr.addr, align 4 # | call void @llvm.memcpy.p0.p0.i32(ptr align 8 %tmp, ptr align 8 %value, i32 64, i1 false) # | %3 = load %struct.int8x16x4_t, ptr %tmp, align 8 # | %4 = extractvalue %struct.int8x16x4_t %3, 0, 0 # | %5 = extractvalue %struct.int8x16x4_t %3, 0, 1 # | %6 = extractvalue %struct.int8x16x4_t %3, 0, 2 # | %7 = extractvalue %struct.int8x16x4_t %3, 0, 3 # | call void @llvm.arm.mve.vst4q.p0.v16i8(ptr %2, <16 x i8> %4, <16 x i8> %5, <16 x i8> %6, <16 x i8> %7, i32 0) # | call void @llvm.arm.mve.vst4q.p0.v16i8(ptr %2, <16 x i8> %4, <16 x i8> %5, <16 x i8> %6, <16 x i8> %7, i32 1) # | call void @llvm.arm.mve.vst4q.p0.v16i8(ptr %2, <16 x i8> %4, <16 x i8> %5, <16 x i8> %6, <16 x i8> %7, i32 2) # | call void @llvm.arm.mve.vst4q.p0.v16i8(ptr %2, <16 x i8> %4, <16 x i8> %5, <16 x i8> %6, <16 x i8> %7, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.arm.mve.vst4q.p0.v16i8(ptr, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, i32) #3 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc void @test_vst2q_f16(ptr noundef %addr, %struct.float16x8x2_t %value.coerce) #0 { # | entry: # | %value = alloca %struct.float16x8x2_t, align 8 # | %addr.addr = alloca ptr, align 4 # | %tmp = alloca %struct.float16x8x2_t, align 8 # | %0 = getelementptr inbounds nuw %struct.float16x8x2_t, ptr %value, i32 0, i32 0 # | %1 = extractvalue %struct.float16x8x2_t %value.coerce, 0 # | store [2 x <8 x half>] %1, ptr %0, align 8 # | store ptr %addr, ptr %addr.addr, align 4 # | %2 = load ptr, ptr %addr.addr, align 4 # | call void @llvm.memcpy.p0.p0.i32(ptr align 8 %tmp, ptr align 8 %value, i32 32, i1 false) # | %3 = load %struct.float16x8x2_t, ptr %tmp, align 8 # | %4 = extractvalue %struct.float16x8x2_t %3, 0, 0 # | %5 = extractvalue %struct.float16x8x2_t %3, 0, 1 # | call void @llvm.arm.mve.vst2q.p0.v8f16(ptr %2, <8 x half> %4, <8 x half> %5, i32 0) # | call void @llvm.arm.mve.vst2q.p0.v8f16(ptr %2, <8 x half> %4, <8 x half> %5, i32 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.arm.mve.vst2q.p0.v8f16(ptr, <8 x half>, <8 x half>, i32) #3 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc void @load_into_variable(ptr noundef %addr, ptr noundef %values) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | %values.addr = alloca ptr, align 4 # | %v = alloca %struct.uint16x8x2_t, align 8 # | %tmp = alloca %struct.uint16x8x2_t, align 8 # | store ptr %addr, ptr %addr.addr, align 4 # | store ptr %values, ptr %values.addr, align 4 # | %0 = load ptr, ptr %addr.addr, align 4 # | %1 = call { <8 x i16>, <8 x i16> } @llvm.arm.mve.vld2q.v8i16.p0(ptr %0) # | %2 = extractvalue { <8 x i16>, <8 x i16> } %1, 0 # | %3 = insertvalue %struct.uint16x8x2_t poison, <8 x i16> %2, 0, 0 # | %4 = extractvalue { <8 x i16>, <8 x i16> } %1, 1 # | %5 = insertvalue %struct.uint16x8x2_t %3, <8 x i16> %4, 0, 1 # | store %struct.uint16x8x2_t %5, ptr %tmp, align 8 # | call void @llvm.memcpy.p0.p0.i32(ptr align 8 %v, ptr align 8 %tmp, i32 32, i1 false) # | %val = getelementptr inbounds nuw %struct.uint16x8x2_t, ptr %v, i32 0, i32 0 # | %arrayidx = getelementptr inbounds [2 x <8 x i16>], ptr %val, i32 0, i32 0 # | %6 = load <8 x i16>, ptr %arrayidx, align 8 # | %7 = load ptr, ptr %values.addr, align 4 # | %arrayidx1 = getelementptr inbounds <8 x i16>, ptr %7, i32 0 # | store <8 x i16> %6, ptr %arrayidx1, align 8 # | %val2 = getelementptr inbounds nuw %struct.uint16x8x2_t, ptr %v, i32 0, i32 0 # | %arrayidx3 = getelementptr inbounds [2 x <8 x i16>], ptr %val2, i32 0, i32 1 # | %8 = load <8 x i16>, ptr %arrayidx3, align 8 # | %9 = load ptr, ptr %values.addr, align 4 # | %arrayidx4 = getelementptr inbounds <8 x i16>, ptr %9, i32 1 # | store <8 x i16> %8, ptr %arrayidx4, align 8 # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <8 x i16>, <8 x i16> } @llvm.arm.mve.vld2q.v8i16.p0(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @extract_one_vector(ptr noundef %addr) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | %ref.tmp = alloca %struct.int32x4x2_t, align 8 # | store ptr %addr, ptr %addr.addr, align 4 # | %0 = load ptr, ptr %addr.addr, align 4 # | %1 = call { <4 x i32>, <4 x i32> } @llvm.arm.mve.vld2q.v4i32.p0(ptr %0) # | %2 = extractvalue { <4 x i32>, <4 x i32> } %1, 0 # | %3 = insertvalue %struct.int32x4x2_t poison, <4 x i32> %2, 0, 0 # | %4 = extractvalue { <4 x i32>, <4 x i32> } %1, 1 # | %5 = insertvalue %struct.int32x4x2_t %3, <4 x i32> %4, 0, 1 # | store %struct.int32x4x2_t %5, ptr %ref.tmp, align 8 # | %val = getelementptr inbounds nuw %struct.int32x4x2_t, ptr %ref.tmp, i32 0, i32 0 # | %arrayidx = getelementptr inbounds [2 x <4 x i32>], ptr %val, i32 0, i32 0 # | %6 = load <4 x i32>, ptr %arrayidx, align 8 # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <4 x i32>, <4 x i32> } @llvm.arm.mve.vld2q.v4i32.p0(ptr) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } # | attributes #3 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>' # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<> # | #0 0x000055aaf31d257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055aaf31cf515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055aaf31d2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0299c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0299ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0299c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0299c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aaf316824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055aaf3168096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055aaf314cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055aaf2dfc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055aaf2dfbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0299c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0299c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0299c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aaf2dfbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c (2789 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv8i32.nxv8i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv8i32.nxv8i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv16i32.nxv16i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv16i32.nxv16i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i64m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv1i64.nxv1i32.i32.i64( poison, %0, i32 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i64.nxv1i32.i32.i64(, , i32, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i64m2( %src, i64 # | ... # `---data was truncated (10240/29175) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561a4319c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561a43199515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561a4319ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcf14049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcf140a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcf14049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcf14031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561a4313224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561a43132096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561a43116f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561a42dc6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561a42dc5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcf14032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcf140330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcf140330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561a42dc5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c (2790 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i64.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv2i64.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv4i64.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv8i64.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fb808df57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fb808dc515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fb808dfcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd651f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd651f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd651f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd651eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fb8087524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fb80875096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fb80859f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fb80509176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fb80508e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd651eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd651eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd651eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fb80508d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c (2791 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16mf2_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m1_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m2_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m4_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c (2792 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_f64m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_i64m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_u64m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_f64m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_i64m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_u64m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056454e2e557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056454e2e2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056454e2e5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1095449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f10954a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1095449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1095431507 abort ./stdlib/abort.c:85:3 # | #7 0x000056454e27b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056454e27b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056454e25ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056454df0f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056454df0ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1095432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f10954330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f10954330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056454df0ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c (2793 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf4_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf2_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32.i64(, , , i64 immarg, i64, i64 # | ... # `---data was truncated (10240/32186) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558530f6f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558530f6c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558530f6fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb20b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb20b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb20b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb20b431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558530f0524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558530f05096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558530ee9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558530b99176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558530b98e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb20b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb20b4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb20b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558530b98d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c (2794 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf4_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf2_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m1_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m2_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m4_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m8_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf4_u16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.mask.nxv1bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf2_u16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.mask.nxv2bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m1_u16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.mask.nxv4bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m2_u16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.mask.nxv8bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m4_u16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.mask.nxv16bf16.i64( poison, # | ... # `---data was truncated (10240/12298) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005615c5fb157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005615c5fae515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005615c5fb1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9b1ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9b1cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9b1ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9b1ce31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005615c5f4724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005615c5f47096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005615c5f2bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005615c5bdb176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005615c5bdae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9b1ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9b1ce330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9b1ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005615c5bdad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c (2795 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b503e0e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b503e0b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b503e0ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4424505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f442455c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4424505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f44244ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b503da424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b503da4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b503d88f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b503a38176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b503a37e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f44244eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f44244ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f44244ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b503a37d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c (2796 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16mf4( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv1f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16mf2( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv2f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m1( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv4f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m2( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv8f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv8f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m4( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv16f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv16f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m8( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv32f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv32f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f32mf2( %op1, float noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv1f32.f32.i64( poison, %0, float %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1f32.f32.i64(, , float, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f32m1( %op1, float noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv2f32.f32.i64( poison, %0, float %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv2f32.f32.i64(, , float, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f32m2( %op1, float noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %mask.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c (2797 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bf817c457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bf817c1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bf817c4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb1c3b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb1c3b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb1c3b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb1c3b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bf8175a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bf8175a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bf8173ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bf813ee176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bf813ede93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb1c3b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb1c3b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb1c3b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bf813edd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c (2798 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt # | ... # `---data was truncated (10240/18668) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005564e9ef057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005564e9eed515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005564e9ef0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb21eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb21eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb21eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb21eb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005564e9e8624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005564e9e86096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005564e9e6af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005564e9b1a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005564e9b19e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb21eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb21eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb21eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005564e9b19d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c (2799 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c (2800 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e6a848357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e6a8480515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e6a8483cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff1a0533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff1a058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff1a0533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff1a051b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e6a841924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e6a8419096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e6a83fdf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e6a80ad176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e6a80ace93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff1a051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff1a051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff1a051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e6a80acd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c (2801 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_f32mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_f32m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_f32m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_i32mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_i32m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_i32m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_u32mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_u32m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_u32m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_f32mf2x3_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | decl # | ... # `---data was truncated (10240/20497) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564e2106d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564e2106a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564e2106dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f47f6f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f47f6f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f47f6f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f47f6f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564e2100324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564e21003096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564e20fe7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564e20c97176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564e20c96e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f47f6f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f47f6f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f47f6f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564e20c96d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c (2802 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | st # | ... # `---data was truncated (10240/11797) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056135292f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056135292c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056135292fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4310b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4310b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4310b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4310b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005613528c524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005613528c5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005613528a9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561352559176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561352558e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4310b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4310b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4310b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561352558d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c (2803 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_u_u_w4_u8m8_u8m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.u.u.i64.nxv64i8.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.u.u.i64.nxv64i8.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559af766d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559af766a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559af766dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f70bff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f70bff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f70bff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f70bff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559af760324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559af7603096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559af75e7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559af7297176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559af7296e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f70bff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f70bff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f70bff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559af7296d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c (2804 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005636abd9d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005636abd9a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005636abd9dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4359d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4359d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4359d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4359ced507 abort ./stdlib/abort.c:85:3 # | #7 0x00005636abd3324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005636abd33096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005636abd17f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005636ab9c7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005636ab9c6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4359ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4359cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4359cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005636ab9c6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c (2805 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a6504d257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a6504cf515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a6504d2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f97a7b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f97a7b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f97a7b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f97a7b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a65046824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a650468096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a65044cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a6500fc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a6500fbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f97a7b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f97a7b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f97a7b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a6500fbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c (2806 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005577d265d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005577d265a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005577d265dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efdbe733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efdbe78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efdbe733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efdbe71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005577d25f324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005577d25f3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005577d25d7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005577d2287176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005577d2286e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efdbe71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efdbe71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efdbe71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005577d2286d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c (2807 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , , i64, i64 immarg) # # | ... # `---data was truncated (10240/12075) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d7fffaf57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d7fffac515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d7fffafcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4688649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f46886a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4688649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4688631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d7fff4524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d7fff45096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d7fff29f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d7ffbd9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d7ffbd8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4688632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f46886330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f46886330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d7ffbd8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c (2808 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_i8mf4x6(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563d2ff6f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563d2ff6c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563d2ff6fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f31f3b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f31f3b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f31f3b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f31f3b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563d2ff0524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563d2ff05096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563d2fee9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563d2fb99176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563d2fb98e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f31f3b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f31f3b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f31f3b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563d2fb98d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c (2809 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_u16mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_u16mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector. # | ... # `---data was truncated (10240/26921) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557f3435e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557f3435b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557f3435ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa265733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa26578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa265733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa26571b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557f342f424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557f342f4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557f342d8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557f33f88176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557f33f87e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa26571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa26571d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa26571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557f33f87d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c (2810 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf4x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf2x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m1x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m2x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m4x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf4x2_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf2x2_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c (2811 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562a2ced957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562a2ced6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562a2ced9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f320fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f320fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f320fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f320fe31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562a2ce6f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562a2ce6f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562a2ce53f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562a2cb03176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562a2cb02e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f320fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f320fe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f320fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562a2cb02d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c (2812 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563acbf5357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563acbf50515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563acbf53cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9b1ac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9b1aca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9b1ac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9b1ac31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563acbee924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563acbee9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563acbecdf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563acbb7d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563acbb7ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9b1ac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9b1ac330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9b1ac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563acbb7cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c (2813 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_f64m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_f64m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_i64m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_i64m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_u64m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_u64m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_f64m1x4_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_f64m2x4_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_i64m1x4_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_i64m2x4_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 # | ... # `---data was truncated (10240/14036) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559aca3a457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559aca3a1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559aca3a4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff3e2649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff3e26a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff3e2649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff3e2631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559aca33a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559aca33a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559aca31ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559ac9fce176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559ac9fcde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff3e2632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff3e26330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff3e26330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559ac9fcdd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c (2814 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16mf4( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv1f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16mf2( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv2f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m1( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv4f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv4f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m2( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv8f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv8f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m4( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv16f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv16f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m8( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv32f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv32f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32mf2( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv1f32.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32m1( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv2f32.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32m2( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv4f32.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv4f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32m4( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv8f32.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv8f32.i64(, , i64, i64, # | ... # `---data was truncated (10240/120460) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ec51d6657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ec51d63515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ec51d66cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb48b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb48b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb48b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb48b11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ec51cfc24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ec51cfc096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ec51ce0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ec51990176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ec5198fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb48b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb48b11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb48b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ec5198fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c (2815 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m4_tu( %maskedoff, %o # | ... # `---data was truncated (10240/70102) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055856778557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558567782515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558567785cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8c19649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8c196a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8c19649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8c19631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055856771b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055856771b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005585676fff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005585673af176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005585673aee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8c19632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8c196330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8c196330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005585673aed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c (2816 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16mf4( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16mf2( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m1( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m2( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m4( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m8( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32mf2( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32m1( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32m2( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32m4( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c (2817 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtzero_t_e8w1(i64 noundef %tm, i64 noundef %tn) #0 { # | entry: # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tm.addr, align 8 # | %1 = load i64, ptr %tn.addr, align 8 # | call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 3, i64 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtzero.t.i64(i64 immarg, i64, i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtzero_t_e8w2(i64 noundef %tm, i64 noundef %tn) #0 { # | entry: # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tm.addr, align 8 # | %1 = load i64, ptr %tn.addr, align 8 # | call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 3, i64 2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtzero_t_e8w4(i64 noundef %tm, i64 noundef %tn) #0 { # | entry: # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tm.addr, align 8 # | %1 = load i64, ptr %tn.addr, align 8 # | call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtzero_t_e16w1(i64 noundef %tm, i64 noundef %tn) #0 { # | entry: # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tm.addr, align 8 # | %1 = load i64, ptr %tn.addr, align 8 # | call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 4, i64 1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtzero_t_e16w2(i64 noundef %tm, i64 noundef %tn) #0 { # | entry: # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tm.addr, align 8 # | %1 = load i64, ptr %tn.addr, align 8 # | call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 4, i64 2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtzero_t_e16w4(i64 noundef %tm, i64 noundef %tn) #0 { # | entry: # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tm.addr, align 8 # | %1 = load i64, ptr %tn.addr, align 8 # | call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 4, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtzero_t_e32w1(i64 noundef %tm, i64 noundef %tn) #0 { # | entry: # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tm.addr, align 8 # | %1 = load i64, ptr %tn.addr, align 8 # | call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 5, i64 1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtzero_t_e32w2(i64 noundef %tm, i64 noundef %tn) #0 { # | entry: # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tm.addr, align 8 # | %1 = load i64, ptr %tn.addr, align 8 # | call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 5, i64 2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtzero_t_e64w1(i64 noundef %tm, i64 noundef %tn) #0 { # | entry: # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tm.addr, align 8 # | %1 = load i64, ptr %tn.addr, align 8 # | call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 6, i64 1) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c8a6aca57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c8a6ac7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c8a6acacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f970f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f970f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f970f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f970f31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c8a6a6024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c8a6a60096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c8a6a44f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c8a66f4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c8a66f3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f970f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f970f31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f970f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c8a66f3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c (2818 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf8_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf4_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf2_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m1_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m2_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv16i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m4_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv32i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m8_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv64i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16mf4_tu( %maskedoff, %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i16, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv1i16.i16.i64( %0, %1, i16 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16mf2_tu( %maskedoff, %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = # | ... # `---data was truncated (10240/210435) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556c832ff57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556c832fc515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556c832ffcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe0fd049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe0fd0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe0fd049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe0fd031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556c8329524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556c83295096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556c83279f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556c82f29176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556c82f28e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe0fd032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe0fd0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe0fd0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556c82f28d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c (2819 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c3fd89057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c3fd88d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c3fd890cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb409a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb409a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb409a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb409a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c3fd82624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c3fd826096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c3fd80af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c3fd4ba176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c3fd4b9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb409a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb409a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb409a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c3fd4b9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c (2820 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf4_bf16mf2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv2bf16.nxv1bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2bf16.nxv1bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf4_bf16m1( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv4bf16.nxv1bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4bf16.nxv1bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf4_bf16m2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8bf16.nxv1bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8bf16.nxv1bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf4_bf16m4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16bf16.nxv1bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv1bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf4_bf16m8( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32bf16.nxv1bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv1bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf2_bf16m1( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv4bf16.nxv2bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4bf16.nxv2bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf2_bf16m2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8bf16.nxv2bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8bf16.nxv2bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf2_bf16m4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16bf16.nxv2bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv2bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf2_bf16m8( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32bf16.nxv2bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv2bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16m1_bf16m2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8bf16.nxv4bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16m1_bf16m4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16bf16.nxv4bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16m1_bf16m8( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16m2_bf16m4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16bf16.nxv8bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv8bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16m2_bf16m8( %value) #0 { # | entry: # | %value.addr = alloca # | ... # `---data was truncated (10240/12137) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559b959fd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559b959fa515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559b959fdcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f147da1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f147da725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f147da1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f147da03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559b9599324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559b95993096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559b95977f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559b95627176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559b95626e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f147da04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f147da050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f147da050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559b95626d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c (2821 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv8i8.nxv8f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c (2822 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562277e5657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562277e53515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562277e56cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe654533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe65458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe654533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe65451b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562277dec24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562277dec096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562277dd0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562277a80176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562277a7fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe65451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe65451d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe65451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562277a7fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c (2823 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret < # | ... # `---data was truncated (10240/34430) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c623f8457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c623f81515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c623f84cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f66b5c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f66b5ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f66b5c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f66b5c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c623f1a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c623f1a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c623efef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c623bae176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c623bade93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f66b5c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f66b5c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f66b5c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c623badd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c (2824 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564461cc957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564461cc6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564461cc9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3ec6505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3ec655c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3ec6505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3ec64ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564461c5f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564461c5f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564461c43f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005644618f3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005644618f2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3ec64eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3ec64ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3ec64ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005644618f2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c (2825 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_f64m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_i64m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_u64m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005633c86e357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005633c86e0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005633c86e3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5bdb533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5bdb58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5bdb533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5bdb51b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005633c867924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005633c8679096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005633c865df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005633c830d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005633c830ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5bdb51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5bdb51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5bdb51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005633c830cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c (2826 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv8i8.nxv8i8.i64(, , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c (2827 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_f16mf4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_f16mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_f16m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_f16m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_f16m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_i16mf4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_i16mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_i16m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_i16m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_i16m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = loa # | ... # `---data was truncated (10240/33443) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e8dd35c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e8dd359515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e8dd35ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcfc4449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcfc44a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcfc4449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcfc4431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e8dd2f224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e8dd2f2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e8dd2d6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e8dcf86176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e8dcf85e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcfc4432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcfc44330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcfc44330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e8dcf85d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c (2828 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 % # | ... # `---data was truncated (10240/29210) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055aff005057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055aff004d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055aff0050cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f127241bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f12724725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f127241ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1272403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055afeffe624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055afeffe6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055afeffcaf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055afefc7a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055afefc79e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1272404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f12724050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f12724050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055afefc79d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c (2829 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv32bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf4_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.mask.nxv1bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf2_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.mask.nxv2bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.mask.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m1_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.add # | ... # `---data was truncated (10240/15312) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556b78a5057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556b78a4d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556b78a50cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffaa8733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffaa878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffaa8733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffaa871b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556b789e624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556b789e6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556b789caf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556b7867a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556b78679e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ffaa871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffaa871d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffaa871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556b78679d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c (2830 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c3ae66c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c3ae669515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c3ae66ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6975f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6975f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6975f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6975f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c3ae60224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c3ae602096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c3ae5e6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c3ae296176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c3ae295e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6975f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6975f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6975f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c3ae295d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c (2831 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 6) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 6) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { targ # | ... # `---data was truncated (10240/21111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056360852257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056360851f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563608522cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd4bcc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd4bcca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd4bcc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd4bcc31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005636084b824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005636084b8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056360849cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056360814c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056360814be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd4bcc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd4bcc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd4bcc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056360814bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c (2832 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16mf4_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16mf4_f32mf2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16mf2_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16mf2_f32m1_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16m1_f32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16m1_f32m2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16m2_f32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16m2_f32m4_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback n # | ... # `---data was truncated (10240/100952) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005617c0b6357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005617c0b60515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005617c0b63cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3c97049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3c970a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3c97049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3c97031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005617c0af924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005617c0af9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005617c0addf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005617c078d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005617c078ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3c97032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3c970330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3c970330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005617c078cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c (2833 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind w # | ... # `---data was truncated (10240/20198) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562568cf357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562568cf0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562568cf3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f00f441bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f00f44725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f00f441ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f00f4403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562568c8924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562568c89096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562568c6df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056256891d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056256891ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f00f4404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f00f44050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f00f44050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056256891cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c (2834 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8m4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c (2835 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f32m2x2(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/X86/bfloat16-convert-half.c (2836 of 27911) ******************** TEST 'Clang :: CodeGen/X86/bfloat16-convert-half.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_convert_from_bf16_to_fp16(bfloat noundef %a) #0 { # | entry: # | %a.addr = alloca bfloat, align 2 # | store bfloat %a, ptr %a.addr, align 2 # | %0 = load bfloat, ptr %a.addr, align 2 # | %fpext = fpext bfloat %0 to float # | %fptrunc = fptrunc float %fpext to half # | ret half %fptrunc # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local bfloat @test_convert_from_fp16_to_bf16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | %fpext = fpext half %0 to float # | %fptrunc = fptrunc float %fpext to bfloat # | ret bfloat %fptrunc # | } # | # | attributes #0 = { noinline nounwind "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055acb420057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055acb41fd515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055acb4200cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f38bd733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f38bd78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f38bd733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f38bd71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055acb419624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055acb4196096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055acb417af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055acb3e2a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055acb3e29e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f38bd71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f38bd71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f38bd71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055acb3e29d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c (2837 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563b2fb6757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563b2fb64515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563b2fb67cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3fa3849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3fa38a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3fa3849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3fa3831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563b2fafd24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563b2fafd096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563b2fae1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563b2f791176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563b2f790e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3fa3832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3fa38330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3fa38330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563b2f790d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c (2838 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_f32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_f32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_f32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_i32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_i32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_i32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_u32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_u32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_u32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tu # | ... # `---data was truncated (10240/23405) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563a4f0fd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563a4f0fa515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563a4f0fdcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fddf1533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fddf158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fddf1533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fddf151b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563a4f09324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563a4f093096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563a4f077f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563a4ed27176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563a4ed26e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fddf151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fddf151d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fddf151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563a4ed26d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c (2839 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64(, , # | ... # `---data was truncated (10240/13290) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055587eb6a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055587eb67515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055587eb6acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3690133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f369018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3690133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f369011b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055587eb0024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055587eb00096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055587eae4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055587e794176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055587e793e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f369011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f369011d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f369011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055587e793d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c (2840 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | st # | ... # `---data was truncated (10240/11797) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556e4529a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556e45297515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556e4529acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5f39249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5f392a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5f39249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5f39231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556e4523024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556e45230096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556e45214f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556e44ec4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556e44ec3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5f39232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5f392330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5f392330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556e44ec3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c (2841 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c (2842 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_i64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_u64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_f64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_i64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_u64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_f64m1x5_tumu( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.ve # | ... # `---data was truncated (10240/18498) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005558e535d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005558e535a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005558e535dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe52e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe52e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe52e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe52e031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005558e52f324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005558e52f3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005558e52d7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005558e4f87176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005558e4f86e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe52e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe52e0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe52e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005558e4f86d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c (2843 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16mf4_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16mf4_f32mf2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16mf2_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16mf2_f32m1_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16m1_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16m1_f32m2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16m2_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16m2_f32m4_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llv # | ... # `---data was truncated (10240/101576) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560ed110d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560ed110a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560ed110dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd2fae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd2faea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd2fae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd2fae31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560ed10a324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560ed10a3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560ed1087f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560ed0d37176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560ed0d36e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd2fae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd2fae330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd2fae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560ed0d36d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqrdmulhq.c (2844 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqrdmulhq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmulhq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vqrdmulh.v16i8(<16 x i8> %0, <16 x i8> %1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vqrdmulh.v16i8(<16 x i8>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqrdmulhq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vqrdmulh.v8i16(<8 x i16> %0, <8 x i16> %1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vqrdmulh.v8i16(<8 x i16>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqrdmulhq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %0, <4 x i32> %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmulhq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.qrdmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.qrdmulh.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqrdmulhq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.qrdmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.qrdmulh.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqrdmulhq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.qrdmulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.qrdmulh.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmulhq_n_s8(<16 x i8> noundef %a, i8 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = call <16 x i8> @llvm.arm.mve.vqrdmulh.v16i8(<16 x i8> %0, <16 x i8> %.splat) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqrdmulhq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = call <8 x i16> @llvm.arm.mve.vqrdmulh.v8i16(<8 x i16> %0, <8 x i16> %.splat) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqrdmulhq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %0, <4 x i32> %.splat) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmulhq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.qrdmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqrdmulhq_m_n_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.qrdmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, <8 x i1> %4, <8 x i16> %5) # | ret <8 # | ... # `---data was truncated (10240/11881) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a6f938f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a6f938c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a6f938fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb001b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb001b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb001b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb001b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a6f932524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a6f9325096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a6f9309f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a6f8fb9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a6f8fb8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb001b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb001b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb001b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a6f8fb8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c (2845 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555ee4e8b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555ee4e88515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555ee4e8bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd268049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd2680a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd268049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd268031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555ee4e2124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555ee4e21096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555ee4e05f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555ee4ab5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555ee4ab4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd268032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd2680330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd2680330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555ee4ab4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c (2846 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056376eaec57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056376eae9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056376eaeccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4f58649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4f586a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4f58649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4f58631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056376ea8224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056376ea82096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056376ea66f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056376e716176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056376e715e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4f58632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4f586330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4f586330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056376e715d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vhcaddq.c (2847 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vhcaddq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot90_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 0, i32 0, <16 x i8> %0, <16 x i8> %1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32, i32, <16 x i8>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot90_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 0, i32 0, <8 x i16> %0, <8 x i16> %1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32, i32, <8 x i16>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot90_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 0, i32 0, <4 x i32> %0, <4 x i32> %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32, i32, <4 x i32>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot270_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 0, i32 1, <16 x i8> %0, <16 x i8> %1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot270_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 0, i32 1, <8 x i16> %0, <8 x i16> %1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot270_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 0, i32 1, <4 x i32> %0, <4 x i32> %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot90_x_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 0, <16 x i8> undef, <16 x i8> %0, <16 x i8> %1, <16 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32, i32, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot90_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 0, <8 x i16> undef, <8 x i16> %0, <8 x i16> %1, <8 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32, i32, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot90_x_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 0, <4 x i32> undef, <4 x i32> %0, <4 x i32> %1, <4 x i1> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32, i32, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot270_x_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 1, <16 x i8> undef, <16 x i8> %0, <16 x i8> %1, <16 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot270_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 1, <8 x i16> undef, <8 x i16> %0, <8 x i16> %1, <8 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot270_x_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 1, <4 x i32> undef, <4 x i32> %0, <4 x i32> %1, <4 x i1> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot90_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %inactive.addr, align 8 # | # | ... # `---data was truncated (10240/15969) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561b923ca57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561b923c7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561b923cacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f153e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f153e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f153e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f153e31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561b9236024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561b92360096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561b92344f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561b91ff4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561b91ff3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f153e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f153e31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f153e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561b91ff3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c (2848 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_i8mf8x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_i8mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_i8mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_i8m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_i8m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_u8mf8x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_u8mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_u8mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_u8m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, a # | ... # `---data was truncated (10240/26721) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005618619c657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005618619c3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005618619c6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5f59e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5f59ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5f59e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5f59e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056186195c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056186195c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561861940f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005618615f0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005618615efe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5f59e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5f59e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5f59e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005618615efd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c (2849 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dcdaa5e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055dcdaa5b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055dcdaa5ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f60c5f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f60c5f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f60c5f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f60c5f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dcda9f424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055dcda9f4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055dcda9d8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055dcda688176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055dcda687e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f60c5f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f60c5f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f60c5f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dcda687d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c (2850 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf4(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1bf16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf2(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2bf16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m1(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4bf16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m2(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8bf16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m4(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv16bf16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m8(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv32bf16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv32bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m1_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv4bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv8bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv8bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv16bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv16bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m8_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %v # | ... # `---data was truncated (10240/11349) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005629c526f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005629c526c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005629c526fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f41adf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f41adf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f41adf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f41adf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005629c520524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005629c5205096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005629c51e9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005629c4e99176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005629c4e98e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f41adf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f41adf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f41adf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005629c4e98d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/thinlto-opaque-typed-mix.ll (2851 of 27911) ******************** TEST 'Clang :: CodeGen/thinlto-opaque-typed-mix.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 4 mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp # executed command: mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp/typed.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-opaque-typed-mix.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp/typed.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-opaque-typed-mix.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp/typed.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-opaque-typed-mix.ll # | #0 0x0000562d3b2dd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562d3b2da515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562d3b2ddcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3e8ca1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3e8ca725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3e8ca1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3e8ca03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562d3b27324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562d3b273096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562d3b257f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562d3af07176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562d3af06e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3e8ca04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3e8ca050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3e8ca050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562d3af06d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c (2852 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c (2853 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_i32mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_i32m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_u32mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_u32m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005585585b257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005585585af515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005585585b2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2811d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2811d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2811d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2811d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055855854824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558558548096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055855852cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005585581dc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005585581dbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2811d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2811d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2811d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005585581dbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c (2854 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c (2855 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv1f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define d # | ... # `---data was truncated (10240/51420) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563a9f21e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563a9f21b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563a9f21ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007effa5a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007effa5aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007effa5a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007effa5a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563a9f1b424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563a9f1b4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563a9f198f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563a9ee48176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563a9ee47e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007effa5a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007effa5a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007effa5a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563a9ee47d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c (2856 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv16bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv32bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf4_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load , ptr %vs1.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vpaire.mask.nxv1bf16.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c (2857 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2e # | ... # `---data was truncated (10240/253148) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b2930f857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b2930f5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b2930f8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f71b1849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f71b18a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f71b1849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f71b1831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b29308e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b29308e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b293072f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b292d22176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b292d21e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f71b1832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f71b18330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f71b18330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b292d21d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c (2858 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16m1x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055db8358a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055db83587515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055db8358acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3c36a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3c36aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3c36a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3c36a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055db8352024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055db83520096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055db83504f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055db831b4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055db831b3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3c36a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3c36a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3c36a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055db831b3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c (2859 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf4_rm( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf2_rm( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m1_rm( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m2_rm( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m4_rm( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005643b68fe57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005643b68fb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005643b68fecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8dcac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8dcaca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8dcac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8dcac31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005643b689424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005643b6894096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005643b6878f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005643b6528176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005643b6527e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8dcac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8dcac330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8dcac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005643b6527d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c (2860 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr # | ... # `---data was truncated (10240/20623) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a08e71b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a08e718515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a08e71bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa72fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa72fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa72fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa72fd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a08e6b124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a08e6b1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a08e695f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a08e345176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a08e344e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa72fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa72fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa72fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a08e344d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c (2861 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_i32mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_i32m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_u32mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_u32m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f2ae6d257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f2ae6cf515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f2ae6d2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fab67a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fab67aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fab67a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fab67a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f2ae66824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f2ae668096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f2ae64cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f2ae2fc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f2ae2fbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fab67a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fab67a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fab67a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f2ae2fbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c (2862 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_bf16m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv32bf16.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv32bf16.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_f16m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv32f16.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv32f16.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_f32m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv16f32.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv16f32.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_f64m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv8f64.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv8f64.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_i8m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_i16m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_i32m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_i64m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_u8m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_u16m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_u32m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_u64m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_f8e4m3m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c (2863 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_i64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_u64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_f64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_i64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_u64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_f64m1x6_tumu( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 0, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_i64m1x6_tumu( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c (2864 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_f64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_i64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_u64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_f64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_i64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_u64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a71ef7357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a71ef70515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a71ef73cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa79af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa79af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa79af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa79af1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a71ef0924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a71ef09096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a71eeedf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a71eb9d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a71eb9ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa79af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa79af1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa79af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a71eb9cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c (2865 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf4x8(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf2x8(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16m1x8(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16m1x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a38aa1157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a38aa0e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a38aa11cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007eff43849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007eff438a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007eff43849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007eff43831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a38a9a724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a38a9a7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a38a98bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a38a63b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a38a63ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007eff43832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007eff438330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007eff438330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a38a63ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c (2866 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557a1583f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557a1583c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557a1583fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb2f6933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb2f698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb2f6933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb2f691b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557a157d524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557a157d5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557a157b9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557a15469176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557a15468e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb2f691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb2f691d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb2f691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557a15468d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c (2867 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_e5m2_e5m2_w4_f8e5m2m8_f8e5m2m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.e5m2.e5m2.i64.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.e5m2.e5m2.i64.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555995d8157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555995d7e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555995d81cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f03b8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f03b818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f03b8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f03b811b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555995d1724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555995d17096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555995cfbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005559959ab176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005559959aae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f03b811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f03b811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f03b811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005559959aad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c (2868 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_i64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_i64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_u64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_u64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m1x4_tum( %mask, target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m2x4_tum( %mask, target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 # | ... # `---data was truncated (10240/32125) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ca7ec5557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ca7ec52515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ca7ec55cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f605af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f605af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f605af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f605af1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ca7ebeb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ca7ebeb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ca7ebcff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ca7e87f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ca7e87ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f605af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f605af1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f605af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ca7e87ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c (2869 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i64.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv2i64.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv4i64.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv8i64.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f6f3bab57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f6f3ba8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f6f3babcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc836449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc8364a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc836449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc836431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f6f3b4124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f6f3b41096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f6f3b25f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f6f37d5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f6f37d4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc836432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc8364330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc8364330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f6f37d4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c (2870 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_f64m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_i64m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_u64m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_f64m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_i64m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_u64m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563b7d8aa57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563b7d8a7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563b7d8aacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb4c1c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb4c1ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb4c1c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb4c1c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563b7d84024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563b7d840096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563b7d824f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563b7d4d4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563b7d4d3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb4c1c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb4c1c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb4c1c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563b7d4d3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c (2871 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 7) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 7) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("risc # | ... # `---data was truncated (10240/21103) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005631e0d1c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005631e0d19515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005631e0d1ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f712a81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f712a8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f712a81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f712a803507 abort ./stdlib/abort.c:85:3 # | #7 0x00005631e0cb224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005631e0cb2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005631e0c96f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005631e0946176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005631e0945e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f712a804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f712a8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f712a8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005631e0945d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c (2872 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv1i32.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv2i32.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv4i32.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv8i32.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv16i32.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv1i64.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv2i64.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv4i64.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv8i64.nxv8i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 4 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call # | ... # `---data was truncated (10240/39914) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b13acb857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b13acb5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b13acb8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f376a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f376a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f376a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f376a231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b13ac4e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b13ac4e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b13ac32f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b13a8e2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b13a8e1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f376a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f376a2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f376a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b13a8e1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c (2873 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf8x6_tum(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c (2874 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_u16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca # | ... # `---data was truncated (10240/60551) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564c318f957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564c318f6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564c318f9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6e56449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6e564a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6e56449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6e56431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564c3188f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564c3188f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564c31873f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564c31523176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564c31522e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6e56432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6e564330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6e564330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564c31522d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/builtins-arm64.c (2875 of 27911) ******************** TEST 'Clang :: CodeGen/builtins-arm64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-unknown-linux -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c --check-prefix=CHECK --check-prefix=CHECK-LINUX # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-unknown-linux -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-unknown-linux" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @f0(ptr noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca ptr, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %1 = load ptr, ptr %b.addr, align 8 # | call void @llvm.clear_cache.p0(ptr %0, ptr %1) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.clear_cache.p0(ptr, ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local ptr @tp() #0 { # | entry: # | %0 = call ptr @llvm.thread.pointer.p0() # | ret ptr %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ptr @llvm.thread.pointer.p0() #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @rbit(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %rbit = call i32 @llvm.bitreverse.i32(i32 %0) # | ret i32 %rbit # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.bitreverse.i32(i32) #3 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @rbitl(i64 noundef %a) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %rbit = call i64 @llvm.bitreverse.i64(i64 %0) # | ret i64 %rbit # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.bitreverse.i64(i64) #3 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @rbit64(i64 noundef %a) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %rbit = call i64 @llvm.bitreverse.i64(i64 %0) # | ret i64 %rbit # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @hints() #0 { # | entry: # | call void @llvm.aarch64.hint(i32 0) # | call void @llvm.aarch64.hint(i32 1) # | call void @llvm.aarch64.hint(i32 2) # | call void @llvm.aarch64.hint(i32 3) # | call void @llvm.aarch64.hint(i32 4) # | call void @llvm.aarch64.hint(i32 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.aarch64.hint(i32) #4 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @barriers() #0 { # | entry: # | call void @llvm.aarch64.dmb(i32 1) # | call void @llvm.aarch64.dsb(i32 2) # | call void @llvm.aarch64.isb(i32 3) # | ret void # | } # | # | ; Function Attrs: nofree nounwind willreturn # | declare void @llvm.aarch64.dmb(i32) #5 # | # | ; Function Attrs: nofree nounwind willreturn # | declare void @llvm.aarch64.dsb(i32) #5 # | # | ; Function Attrs: nofree nounwind willreturn # | declare void @llvm.aarch64.isb(i32) #5 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @prefetch() #0 { # | entry: # | call void @llvm.aarch64.prefetch(ptr null, i32 1, i32 2, i32 0, i32 1) # | call void @llvm.aarch64.prefetch(ptr null, i32 0, i32 0, i32 1, i32 1) # | call void @llvm.aarch64.prefetch(ptr null, i32 0, i32 0, i32 1, i32 1) # | call void @llvm.aarch64.prefetch(ptr null, i32 0, i32 0, i32 0, i32 0) # | call void @llvm.aarch64.prefetch(ptr null, i32 0, i32 3, i32 0, i32 1) # | ret void # | } # | # | ; Function Attrs: nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) # | declare void @llvm.aarch64.prefetch(ptr readonly, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #6 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @range_prefetch() #0 { # | entry: # | call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 0) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 1, i64 0) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 1, i32 0, i64 0) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 1, i32 1, i64 0) # | ret void # | } # | # | ; Function Attrs: nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) # | declare void @llvm.aarch64.range.prefetch(ptr readonly, i32 immarg, i32 immarg, i64) #6 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @range_prefetch_x() #0 { # | entry: # | call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 0) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 1, i64 0) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 1, i32 0, i64 0) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 1, i32 1, i64 0) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 576460752305520640) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 576460752301326335) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 -1152921504606846976) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 -2305843009213693952) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 -6917529027641081856) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @read_intent_prefetch() #0 { # | entry: # | call void @llvm.aarch64.prefetch.ir(ptr null) # | ret void # | } # | # | ; Function Attrs: nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) # | declare void @llvm.aarch64.prefetch.ir(ptr readonly) #6 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @jcvt(double noundef %v) #7 { # | entry: # | %v.addr = alloca double, align 8 # | store double %v, ptr %v.addr, align 8 # | %0 = load double, ptr %v.addr, align 8 # | %1 = call i32 @llvm.aarch64.fjcvtzs(double %0) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.fjcvtzs(double) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @rsr() #0 { # | entry: # | %0 = call i64 @llvm.read_volatile_register.i64(metadata !7) # | %1 = trunc i64 %0 to i32 # | ret i32 %1 # | } # | # | ; Function Attrs: nounwind # | declare i64 @llvm.read_volatile_register.i64(metadata) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @rsr64() #0 { # | entry: # | %0 = call i64 @llvm.read_volatile_register.i64(metadata !7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local ptr @rsrp() #0 { # | entry: # | %0 = call i64 @llvm.read_volatile_register.i64(metadata !7) # | %1 = inttoptr i64 %0 to ptr # | ret ptr %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @wsr(i32 noundef %v) #0 { # | entry: # | %v.addr = alloca i32, align 4 # | store i32 %v, ptr %v.addr, align 4 # | %0 = load i32, ptr %v.addr, align 4 # | %1 = zext i32 %0 to i64 # | call void @llvm.write_register.i64(metadata !7, i64 %1) # | ret void # | } # | # | ; Function Attrs: nocallback nounwind # | declare void @llvm.write_register.i64(metadata, i64) #8 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @wsr64(i64 noundef %v) #0 { # | entry: # | %v.addr = alloca i64, align 8 # | store i64 %v, ptr %v.addr, align 8 # | %0 = load i64, ptr %v.addr, align 8 # | call void @llvm.write_register.i64(metadata !7, i64 %0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @wsrp(ptr noundef %v) #0 { # | entry: # | %v.addr = alloca ptr, align 8 # | store ptr %v, ptr %v.addr, align 8 # | %0 = load ptr, ptr %v.addr, align 8 # | %1 = ptrtoint ptr %0 to i64 # | call void @llvm.write_register.i64(metadata !7, i64 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @cls(i32 noundef %v) #0 { # | entry: # | %v.addr = alloca i32, align 4 # | store i32 %v, ptr %v.addr, align 4 # | %0 = load i32, ptr %v.addr, align 4 # | %cls = call i32 @llvm.aarch64.cls(i32 %0) # | ret i32 %cls # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.cls(i32) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @clsl(i64 noundef %v) #0 { # | entry: # | %v.addr = alloca i64, align 8 # | store i64 %v, ptr %v.addr, align 8 # | %0 = load i64, ptr %v.addr, align 8 # | %cls = call i32 @llvm.aarch64.cls64(i64 %0) # | ret i32 %cls # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.cls64(i64) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @clsll(i64 noundef %v) #0 { # | entry: # | %v.addr = alloca i64, align 8 # | store i64 %v, ptr %v.addr, align 8 # | %0 = load i64, ptr %v.addr, align 8 # | %cls = call i32 @llvm.aarch64.cls64(i64 %0) # | ret i32 %cls # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @rndr(ptr noundef %__addr) #9 { # | entry: # | %__addr.addr = alloca ptr, align 8 # | store ptr %__addr, ptr %__addr.addr, align 8 # | %0 = call { i64, i1 } @llvm.aarch64.rndr() # | %1 = extractvalue { i64, i1 } %0, 0 # | %2 = extractvalue { i64, i1 } %0, 1 # | %3 = load ptr, ptr %__addr.addr, align 8 # | store i64 %1, ptr %3, align 8 # | %4 = zext i1 %2 to i32 # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { i64, i1 } @llvm.aarch64.rndr() #4 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @rndrrs(ptr noundef %__addr) #9 { # | entry: # | %__addr.addr = alloca ptr, align 8 # | store ptr %__addr, ptr %__addr.addr, align 8 # | %0 = call { i64, i1 } @llvm.aarch64.rndrrs() # | %1 = extractvalue { i64, i1 } %0, 0 # | %2 = extractvalue { i64, i1 } %0, 1 # | %3 = load ptr, ptr %__addr.addr, align 8 # | store i64 %1, ptr %3, align 8 # | %4 = zext i1 %2 to i32 # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { i64, i1 } @llvm.aarch64.rndrrs() #4 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @trap() #0 { # | entry: # | call void @llvm.aarch64.break(i32 42) # | ret void # | } # | # | ; Function Attrs: cold noreturn nounwind # | declare void @llvm.aarch64.break(i32 immarg) #10 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @atomic_store_with_hint(ptr noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca i64, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | store atomic i64 %1, ptr %0 monotonic, align 8, !mem.cache_hint !8 # | %2 = load ptr, ptr %a.addr, align 8 # | %3 = load i64, ptr %b.addr, a # | ... # `---data was truncated (10240/16808) (change limit with -D output_limit=N) # .---command stderr------------ # | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:243:3: warning: unrecognised hint type argument to atomic hint operation (5) [-Watomic-hint-type] # | 243 | __builtin_arm_atomic_store_with_hint(a, b, __ATOMIC_RELAXED, 5); // Invalid Hint # | | ^ ~ # | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:305:3: warning: unrecognised hint type argument to atomic hint operation (0) [-Watomic-hint-type] # | 305 | __builtin_arm_atomic_fetch_add_with_hint(a, b, __ATOMIC_RELAXED, HINT_STSHH_KEEP); # | | ^ ~~~~~~~~~~~~~~~ # | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:306:3: warning: unrecognised hint type argument to atomic hint operation (1) [-Watomic-hint-type] # | 306 | __builtin_arm_atomic_fetch_sub_with_hint(a, b, __ATOMIC_RELAXED, HINT_STSHH_STRM); # | | ^ ~~~~~~~~~~~~~~~ # | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:307:3: warning: unrecognised hint type argument to atomic hint operation (2) [-Watomic-hint-type] # | 307 | __builtin_arm_atomic_fetch_and_with_hint(a, b, __ATOMIC_RELAXED, HINT_STCPH); # | | ^ ~~~~~~~~~~ # | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:308:10: warning: unrecognised hint type argument to atomic hint operation (5) [-Watomic-hint-type] # | 308 | return __builtin_arm_atomic_fetch_add_with_hint(a, b, __ATOMIC_RELAXED, 5); # | | ^ ~ # | 5 warnings generated. # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056287c33757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056287c334515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056287c337cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f49ef333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f49ef38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f49ef333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f49ef31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056287c2cd24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056287c2cd096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056287c2b1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056287bf61176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056287bf60e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f49ef31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f49ef31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f49ef31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056287bf60d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c --check-prefix=CHECK --check-prefix=CHECK-LINUX # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c --check-prefix=CHECK --check-prefix=CHECK-LINUX # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c (2876 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e08bc4d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e08bc4a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e08bc4dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb1c161bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb1c16725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb1c161ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb1c1603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e08bbe324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e08bbe3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e08bbc7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e08b877176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e08b876e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb1c1604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb1c16050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb1c16050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e08b876d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c (2877 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m1x4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m2x4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b67e9a357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b67e9a0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b67e9a3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa91c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa91c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa91c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa91c431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b67e93924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b67e939096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b67e91df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b67e5cd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b67e5cce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa91c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa91c4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa91c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b67e5ccd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c (2878 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b1_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv64i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b2_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv32i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b4_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv16i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b8_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv8i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b16_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv4i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv4i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b32_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv2i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv2i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b64_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv1i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv1i1.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565112f9c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000565112f99515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000565112f9ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8c2d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8c2d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8c2d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8c2d431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565112f3224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000565112f32096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000565112f16f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000565112bc6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000565112bc5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8c2d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8c2d4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8c2d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565112bc5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c (2879 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf8x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_u8mf8x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_u8mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_u8mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vec # | ... # `---data was truncated (10240/27595) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005640b25bd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005640b25ba515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005640b25bdcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa651133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa65118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa651133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa65111b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005640b255324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005640b2553096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005640b2537f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005640b21e7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005640b21e6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa65111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa65111d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa65111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005640b21e6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c (2880 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf8_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf4_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf2_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m1_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m2_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m4_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m8_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u16mf4_u32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv2i32.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv2i32.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u16mf2_u32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv2i32.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv2i32.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u16m1_u32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca # | ... # `---data was truncated (10240/43625) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056290e42857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056290e425515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056290e428cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe2b901bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe2b90725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe2b901ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe2b9003507 abort ./stdlib/abort.c:85:3 # | #7 0x000056290e3be24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056290e3be096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056290e3a2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056290e052176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056290e051e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe2b9004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe2b90050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe2b90050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056290e051d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c (2881 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c26aeaf57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c26aeac515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c26aeafcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe9f8d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe9f8d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe9f8d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe9f8d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c26ae4524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c26ae45096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c26ae29f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c26aad9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c26aad8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe9f8d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe9f8d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe9f8d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c26aad8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c (2882 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005586d2a8057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005586d2a7d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005586d2a80cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fabd0b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fabd0b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fabd0b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fabd0b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005586d2a1624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005586d2a16096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005586d29faf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005586d26aa176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005586d26a9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fabd0b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fabd0b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fabd0b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005586d26a9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c (2883 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv # | ... # `---data was truncated (10240/47720) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d80b8d757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d80b8d4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d80b8d7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8fc4e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8fc4ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8fc4e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8fc4e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d80b86d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d80b86d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d80b851f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d80b501176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d80b500e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8fc4e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8fc4e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8fc4e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d80b500d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c (2884 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = al # | ... # `---data was truncated (10240/14209) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b9127a357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b9127a0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b9127a3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1f5b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1f5b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1f5b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1f5b431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b91273924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b912739096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b91271df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b9123cd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b9123cce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1f5b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1f5b4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1f5b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b9123ccd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c (2885 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf4( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf2( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m1( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m2( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m4( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m8( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf4_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf2_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.mask.nxv2bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.mask.nxv2bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m1_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.mask.nxv4bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down. # | ... # `---data was truncated (10240/14900) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cc1f03357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cc1f030515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cc1f033cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1580f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1580f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1580f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1580f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cc1efc924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cc1efc9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cc1efadf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cc1ec5d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cc1ec5ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1580f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1580f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1580f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cc1ec5cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c (2886 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055753ad9e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055753ad9b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055753ad9ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb06f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb06f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb06f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb06f91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055753ad3424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055753ad34096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055753ad18f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055753a9c8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055753a9c7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb06f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb06f91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb06f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055753a9c7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c (2887 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf8x5_tum( %mas # | ... # `---data was truncated (10240/43111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a28db5f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a28db5c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a28db5fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0445649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f04456a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0445649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0445631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a28daf524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a28daf5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a28dad9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a28d789176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a28d788e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0445632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f04456330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f04456330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a28d788d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c (2888 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = al # | ... # `---data was truncated (10240/14209) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056425847a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564258477515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056425847acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff982849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff9828a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff982849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff982831507 abort ./stdlib/abort.c:85:3 # | #7 0x000056425841024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564258410096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005642583f4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005642580a4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005642580a3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff982832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff9828330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff9828330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005642580a3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c (2889 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563c04c4957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563c04c46515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563c04c49cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe3b1f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe3b1f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe3b1f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe3b1f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563c04bdf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563c04bdf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563c04bc3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563c04873176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563c04872e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe3b1f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe3b1f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe3b1f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563c04872d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c (2890 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwi # | ... # `---data was truncated (10240/44369) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055798123857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557981235515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557981238cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1247733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f124778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1247733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f124771b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005579811ce24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005579811ce096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005579811b2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557980e62176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557980e61e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f124771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f124771d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f124771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557980e61d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c (2891 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/97913) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565223bd757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000565223bd4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000565223bd7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5245649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f52456a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5245649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5245631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565223b6d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000565223b6d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000565223b51f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000565223801176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000565223800e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5245632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f52456330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f52456330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565223800d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c (2892 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv1i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv2i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv4i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv8i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv16i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv32i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv64i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv1i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv2i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv4i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | # | ... # `---data was truncated (10240/92362) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005641963de57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005641963db515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005641963decbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fabaa81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fabaa8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fabaa81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fabaa803507 abort ./stdlib/abort.c:85:3 # | #7 0x000056419637424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564196374096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564196358f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564196008176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564196007e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fabaa804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fabaa8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fabaa8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564196007d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c (2893 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005590d7ac057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005590d7abd515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005590d7ac0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c44f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c44f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c44f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c44f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005590d7a5624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005590d7a56096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005590d7a3af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005590d76ea176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005590d76e9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2c44f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c44f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c44f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005590d76e9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c (2894 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_u32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_u32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tupl # | ... # `---data was truncated (10240/53454) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a8b72c657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a8b72c3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a8b72c6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4b5fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4b5fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4b5fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4b5fb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a8b725c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a8b725c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a8b7240f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a8b6ef0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a8b6eefe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4b5fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4b5fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4b5fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a8b6eefd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c (2895 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Fun # | ... # `---data was truncated (10240/12067) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556827b6157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556827b5e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556827b61cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5faf733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5faf78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5faf733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5faf71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556827af724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556827af7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556827adbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055682778b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055682778ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5faf71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5faf71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5faf71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055682778ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c (2896 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf8x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf4x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf2x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf8x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf4x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf2x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf8x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf4x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = c # | ... # `---data was truncated (10240/16451) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563dc1eba57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563dc1eb7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563dc1ebacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd2b0f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd2b0f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd2b0f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd2b0f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563dc1e5024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563dc1e50096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563dc1e34f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563dc1ae4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563dc1ae3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd2b0f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd2b0f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd2b0f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563dc1ae3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c (2897 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16mf4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16mf4( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16mf2( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16m1( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16m2( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c (2898 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c (2899 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf4_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf2_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m1_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m2_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m4_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m8_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { , i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0( %1, ptr %2, %0, i64 %4, i64 2) # | %6 = extractvalue { , i64 } %5, 0 # | %7 = extractvalue { , i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { , i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c (2900 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16mf4_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv1f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv1f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16mf2_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv2f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv2f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m1_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv4f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv4f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m2_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv8f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv8f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m4_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv16f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv16f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m8_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv32f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv32f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32mf2_tu( %maskedoff, float noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load float, ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv1f32.i64( %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv1f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m1_tu( %maskedoff, float noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load float, ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv2f32.i64( %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv2f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m2_tu( %maskedoff, float noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load float, ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv4f32.i64( %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv4f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m4_tu( %maskedoff, float noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load float, ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv8f32.i64( %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv8f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m8_tu( %maskedoff, float noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c (2901 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560aaf95b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560aaf958515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560aaf95bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f58fe649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f58fe6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f58fe649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f58fe631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560aaf8f124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560aaf8f1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560aaf8d5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560aaf585176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560aaf584e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f58fe632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f58fe6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f58fe6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560aaf584d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c (2902 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf4x6_tumu( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 0, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", # | ... # `---data was truncated (10240/16800) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558445af257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558445aef515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558445af2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb1a4d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb1a4d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb1a4d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb1a4d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558445a8824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558445a88096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558445a6cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055844571c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055844571be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb1a4d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb1a4d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb1a4d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055844571bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c (2903 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_i64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_u64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_f64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_i64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_u64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_f64m1x7_tumu( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 0, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_i64m1x7_tumu( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c (2904 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555f5c15557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555f5c152515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555f5c155cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb3a2133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb3a218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb3a2133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb3a211b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555f5c0eb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555f5c0eb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555f5c0cff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555f5bd7f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555f5bd7ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb3a211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb3a211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb3a211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555f5bd7ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGenHIP/offload-pgo-sections.hip (2905 of 27911) ******************** TEST 'Clang :: CodeGenHIP/offload-pgo-sections.hip' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -cuid=abc -fprofile-instrument=clang -emit-llvm -o - -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=instrprof -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefix=DEV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -cuid=abc -fprofile-instrument=clang -emit-llvm -o - -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip" # | target datalayout = "e-m:e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-p10:32:32-p11:32:32-p12:32:32-p13:32:32-p14:32:32-p15:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9" # | target triple = "amdgpu-amd-amdhsa" # | # | $__profc__Z6helperi = comdat any # | # | $__llvm_prf_unifcnt__Z6helperi = comdat any # | # | $__profc__Z6kernelPi = comdat any # | # | $__llvm_prf_unifcnt__Z6kernelPi = comdat any # | # | @__hip_cuid_b04fd23c98500190 = addrspace(1) global i8 0 # | @__profc__Z6helperi = linkonce_odr protected addrspace(1) global [1 x i64] zeroinitializer, section "__llvm_prf_cnts", comdat, align 8 # | @__llvm_prf_unifcnt__Z6helperi = linkonce_odr protected addrspace(1) global [1 x i64] zeroinitializer, section "__llvm_prf_ucnts", comdat, align 8 # | @__profd__Z6helperi = linkonce_odr protected addrspace(1) global { i64, i64, i64, i64, i64, ptr, ptr, i32, [3 x i16], i16, i32 } { i64 6265860958107916728, i64 24, i64 sub (i64 ptrtoint (ptr addrspace(1) @__profc__Z6helperi to i64), i64 ptrtoint (ptr addrspace(1) @__profd__Z6helperi to i64)), i64 sub (i64 ptrtoint (ptr addrspace(1) @__llvm_prf_unifcnt__Z6helperi to i64), i64 ptrtoint (ptr addrspace(1) @__profd__Z6helperi to i64)), i64 0, ptr null, ptr null, i32 1, [3 x i16] zeroinitializer, i16 0, i32 0 }, section "__llvm_prf_data", comdat($__profc__Z6helperi), align 8 # | @__profc__Z6kernelPi = linkonce_odr protected addrspace(1) global [1 x i64] zeroinitializer, section "__llvm_prf_cnts", comdat, align 8 # | @__llvm_prf_unifcnt__Z6kernelPi = linkonce_odr protected addrspace(1) global [1 x i64] zeroinitializer, section "__llvm_prf_ucnts", comdat, align 8 # | @__profd__Z6kernelPi = linkonce_odr protected addrspace(1) global { i64, i64, i64, i64, i64, ptr, ptr, i32, [3 x i16], i16, i32 } { i64 4905896731224577586, i64 0, i64 sub (i64 ptrtoint (ptr addrspace(1) @__profc__Z6kernelPi to i64), i64 ptrtoint (ptr addrspace(1) @__profd__Z6kernelPi to i64)), i64 sub (i64 ptrtoint (ptr addrspace(1) @__llvm_prf_unifcnt__Z6kernelPi to i64), i64 ptrtoint (ptr addrspace(1) @__profd__Z6kernelPi to i64)), i64 0, ptr null, ptr null, i32 1, [3 x i16] zeroinitializer, i16 0, i32 0 }, section "__llvm_prf_data", comdat($__profc__Z6kernelPi), align 8 # | @__llvm_prf_nm_b04fd23c98500190 = protected addrspace(1) constant [32 x i8] c"\16\1Ex\DA\8B\8F2\CBH\CD)H-\CAd\8C\8F2\CBN-\CAK\CD\09\C8\04\00Z\AD\08\03", section "__llvm_prf_names", align 1 # | @__start___llvm_prf_names = external hidden addrspace(1) global i8 # | @__stop___llvm_prf_names = external hidden addrspace(1) global i8 # | @__start___llvm_prf_cnts = external hidden addrspace(1) global i8 # | @__stop___llvm_prf_cnts = external hidden addrspace(1) global i8 # | @__start___llvm_prf_data = external hidden addrspace(1) global i8 # | @__stop___llvm_prf_data = external hidden addrspace(1) global i8 # | @__start___llvm_prf_ucnts = external hidden addrspace(1) global i8 # | @__stop___llvm_prf_ucnts = external hidden addrspace(1) global i8 # | @__llvm_profile_raw_version = external addrspace(1) constant i64 # | @__llvm_profile_sections_b04fd23c98500190 = protected addrspace(1) constant { ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1) } { ptr addrspace(1) @__start___llvm_prf_names, ptr addrspace(1) @__stop___llvm_prf_names, ptr addrspace(1) @__start___llvm_prf_cnts, ptr addrspace(1) @__stop___llvm_prf_cnts, ptr addrspace(1) @__start___llvm_prf_data, ptr addrspace(1) @__stop___llvm_prf_data, ptr addrspace(1) @__start___llvm_prf_ucnts, ptr addrspace(1) @__stop___llvm_prf_ucnts, ptr addrspace(1) @__llvm_profile_raw_version } # | @llvm.compiler.used = appending addrspace(1) global [6 x ptr] [ptr addrspacecast (ptr addrspace(1) @__hip_cuid_b04fd23c98500190 to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_prf_unifcnt__Z6helperi to ptr), ptr addrspacecast (ptr addrspace(1) @__profd__Z6helperi to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_prf_unifcnt__Z6kernelPi to ptr), ptr addrspacecast (ptr addrspace(1) @__profd__Z6kernelPi to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_profile_sections_b04fd23c98500190 to ptr)], section "llvm.metadata" # | @llvm.used = appending addrspace(1) global [1 x ptr] [ptr addrspacecast (ptr addrspace(1) @__llvm_prf_nm_b04fd23c98500190 to ptr)], section "llvm.metadata" # | # | ; Function Attrs: convergent mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z6helperi(i32 noundef %x) #0 { # | entry: # | %0 = call i32 @llvm.amdgcn.wavefrontsize() # | %wavesize.i16 = trunc i32 %0 to i16 # | store i16 %wavesize.i16, ptr addrspace(1) getelementptr inbounds nuw (i8, ptr addrspace(1) @__profd__Z6helperi, i64 66), align 2 # | %pgo.sampled = call i32 @__llvm_profile_sampling_gpu(i32 3) # | %pgo.matched = icmp ne i32 %pgo.sampled, 0 # | %x.addr = alloca i32, align 4, addrspace(5) # | %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr # | store i32 %x, ptr %x.addr.ascast, align 4 # | br i1 %pgo.matched, label %po_then, label %po_cont # | # | po_cont: ; preds = %po_then, %entry # | %1 = load i32, ptr %x.addr.ascast, align 4 # | %add = add nsw i32 %1, 1 # | ret i32 %add # | # | po_then: ; preds = %entry # | call void @__llvm_profile_instrument_gpu(ptr addrspacecast (ptr addrspace(1) @__profc__Z6helperi to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_prf_unifcnt__Z6helperi to ptr), i64 1) # | br label %po_cont # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.instrprof.increment(ptr, i64, i32, i32) #1 # | # | ; Function Attrs: convergent mustprogress noinline norecurse nounwind optnone # | define dso_local amdgpu_kernel void @_Z6kernelPi(ptr addrspace(1) noundef %p.coerce) #2 { # | entry: # | %0 = call i32 @llvm.amdgcn.wavefrontsize() # | %wavesize.i16 = trunc i32 %0 to i16 # | store i16 %wavesize.i16, ptr addrspace(1) getelementptr inbounds nuw (i8, ptr addrspace(1) @__profd__Z6kernelPi, i64 66), align 2 # | %pgo.sampled = call i32 @__llvm_profile_sampling_gpu(i32 3) # | %pgo.matched = icmp ne i32 %pgo.sampled, 0 # | %p = alloca ptr, align 8, addrspace(5) # | %p.addr = alloca ptr, align 8, addrspace(5) # | %p.addr.ascast = addrspacecast ptr addrspace(5) %p.addr to ptr # | store ptr addrspace(1) %p.coerce, ptr addrspace(5) %p, align 8 # | %p1 = load ptr, ptr addrspace(5) %p, align 8 # | store ptr %p1, ptr %p.addr.ascast, align 8 # | br i1 %pgo.matched, label %po_then, label %po_cont # | # | po_cont: ; preds = %po_then, %entry # | %1 = load ptr, ptr %p.addr.ascast, align 8 # | %2 = load i32, ptr %1, align 4 # | %call = call noundef i32 @_Z6helperi(i32 noundef %2) #4 # | %3 = load ptr, ptr %p.addr.ascast, align 8 # | store i32 %call, ptr %3, align 4 # | ret void # | # | po_then: ; preds = %entry # | call void @__llvm_profile_instrument_gpu(ptr addrspacecast (ptr addrspace(1) @__profc__Z6kernelPi to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_prf_unifcnt__Z6kernelPi to ptr), i64 1) # | br label %po_cont # | } # | # | declare i32 @__llvm_profile_sampling_gpu(i32) # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare noundef range(i32 32, 65) i32 @llvm.amdgcn.wavefrontsize() #3 # | # | declare void @__llvm_profile_instrument_gpu(ptr, ptr, i64) # | # | attributes #0 = { convergent mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size" } # | attributes #1 = { nounwind } # | attributes #2 = { convergent mustprogress noinline norecurse nounwind optnone "amdgpu-flat-work-group-size"="1,1024" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size" } # | attributes #3 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #4 = { convergent nounwind "uniform-work-group-size" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 2, !"EnableValueProfiling", i32 0} # | !1 = !{i32 1, !"amdhsa_code_object_version", i32 600} # | !2 = !{i32 1, !"amdgpu_printf_kind", !"hostcall"} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=instrprof -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=instrprof -S # | #0 0x0000563adda4f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563adda4c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563adda4fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe07d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe07d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe07d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe07d231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563add9e524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563add9e5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563add9c9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563add679176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563add678e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe07d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe07d2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe07d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563add678d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefix=DEV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefix=DEV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c (2906 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf8_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf4_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf2_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m1_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m2_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m4_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m8_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u16mf4_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558ce70fb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558ce70f8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558ce70fbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f09c9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f09c998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f09c9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f09c991b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558ce709124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558ce7091096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558ce7075f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558ce6d25176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558ce6d24e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f09c991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f09c991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f09c991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558ce6d24d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c (2907 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_u16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_u16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c (2908 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056207417857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562074175515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562074178cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f25cd533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f25cd58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f25cd533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f25cd51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056207410e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056207410e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005620740f2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562073da2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562073da1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f25cd51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f25cd51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f25cd51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562073da1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c (2909 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561e9a59157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561e9a58e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561e9a591cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd698533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd69858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd698533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd69851b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561e9a52724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561e9a527096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561e9a50bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561e9a1bb176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561e9a1bae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd69851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd69851d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd69851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561e9a1bad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c (2910 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005628b0cc857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005628b0cc5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005628b0cc8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f08f8d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f08f8d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f08f8d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f08f8d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005628b0c5e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005628b0c5e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005628b0c42f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005628b08f2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005628b08f1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f08f8d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f08f8d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f08f8d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005628b08f1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c (2911 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vceqzh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %2 = fcmp oeq half %1, 0.000000e+00 # | %vceqz = sext i1 %2 to i16 # | store i16 %vceqz, ptr %ref.tmp, align 2 # | %3 = load i16, ptr %ref.tmp, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | ret i16 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vcgezh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %2 = fcmp oge half %1, 0.000000e+00 # | %vcgez = sext i1 %2 to i16 # | store i16 %vcgez, ptr %ref.tmp, align 2 # | %3 = load i16, ptr %ref.tmp, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | ret i16 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vcgtzh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %2 = fcmp ogt half %1, 0.000000e+00 # | %vcgtz = sext i1 %2 to i16 # | store i16 %vcgtz, ptr %ref.tmp, align 2 # | %3 = load i16, ptr %ref.tmp, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | ret i16 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vclezh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %2 = fcmp ole half %1, 0.000000e+00 # | %vclez = sext i1 %2 to i16 # | store i16 %vclez, ptr %ref.tmp, align 2 # | %3 = load i16, ptr %ref.tmp, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | ret i16 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vcltzh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %2 = fcmp olt half %1, 0.000000e+00 # | %vcltz = sext i1 %2 to i16 # | store i16 %vcltz, ptr %ref.tmp, align 2 # | %3 = load i16, ptr %ref.tmp, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | ret i16 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_s16(i16 noundef %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca i16, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | store i16 %0, ptr %__s0, align 2 # | %1 = load i16, ptr %__s0, align 2 # | %2 = sitofp i16 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_s32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %__ret = alloca half, align 2 # | %__s0 = alloca i32, align 4 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__s0, align 4 # | %1 = load i32, ptr %__s0, align 4 # | %2 = sitofp i32 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_s64(i64 noundef %a) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %__ret = alloca half, align 2 # | %__s0 = alloca i64, align 8 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i64 %a, ptr %a.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | store i64 %0, ptr %__s0, align 8 # | %1 = load i64, ptr %__s0, align 8 # | %2 = sitofp i64 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_u16(i16 noundef %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca i16, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | store i16 %0, ptr %__s0, align 2 # | %1 = load i16, ptr %__s0, align 2 # | %2 = uitofp i16 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_u32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %__ret = alloca half, align 2 # | %__s0 = alloca i32, align 4 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__s0, align 4 # | %1 = load i32, ptr %__s0, align 4 # | %2 = uitofp i32 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_u64(i64 noundef %a) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %__ret = alloca half, align 2 # | %__s0 = alloca i64, align 8 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i64 %a, ptr %a.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | store i64 %0, ptr %__s0, align 8 # | %1 = load i64, ptr %__s0, align 8 # | %2 = uitofp i64 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vcvth_s16_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %vcvth_s16_f16 = call i16 @llvm.fptosi.sat.i16.f16(half %1) # | store i16 %vcvth_s16_f16, ptr %ref.tmp, align 2 # | %2 = load i16, ptr %ref.tmp, align 2 # | store i16 %2, ptr %__ret, align 2 # | %3 = load i16, ptr %__ret, align 2 # | store i16 %3, ptr %tmp, align 2 # | %4 = load i16, ptr %tmp, align 2 # | ret i16 %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.fptosi.sat.i16.f16(half) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_vcvth_s32_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i32, align 4 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %vcvth_s32_f16 = call i32 @llvm.fptosi.sat.i32.f16(half %1) # | store i32 %vcvth_s32_f16, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.fptosi.sat.i32.f16(half) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_vcvth_s64_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i64, align 8 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i64, align 8 # | %tmp = alloca i64, align 8 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, al # | ... # `---data was truncated (10240/28866) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555998b1957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555998b16515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555998b19cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb702d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb702d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb702d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb702d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555998aaf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555998aaf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555998a93f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555998743176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555998742e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb702d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb702d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb702d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555998742d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c (2912 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf4x3_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf2x3_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16m1x3_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16m2x3_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cfcd14857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cfcd145515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cfcd148cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fec93505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fec9355c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fec93505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fec934ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cfcd0de24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cfcd0de096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cfcd0c2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cfccd72176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cfccd71e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fec934eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fec934ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fec934ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cfccd71d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c (2913 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_i64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_u64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_f64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_i64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_u64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_f64m1x5_tumu( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target(" # | ... # `---data was truncated (10240/18506) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d3ed5d257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d3ed5cf515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d3ed5d2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f03cda49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f03cdaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f03cda49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f03cda31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d3ed56824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d3ed568096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d3ed54cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d3ed1fc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d3ed1fbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f03cda32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f03cda330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f03cda330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d3ed1fbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c (2914 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32mf2_tum( %mask, %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 4 # | %src.addr = al # | ... # `---data was truncated (10240/41670) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055585fbdc57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055585fbd9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055585fbdccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5364e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5364ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5364e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5364e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055585fb7224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055585fb72096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055585fb56f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055585f806176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055585f805e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5364e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5364e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5364e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055585f805d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c (2915 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willr # | ... # `---data was truncated (10240/44361) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557aac5dd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557aac5da515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557aac5ddcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1c74449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1c744a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1c74449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1c74431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557aac57324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557aac573096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557aac557f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557aac207176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557aac206e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1c74432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1c744330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1c744330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557aac206d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c (2916 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_f16mf4x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_f16mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_f16m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_i16mf4x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_i16mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_i16m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_u16mf4x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_u16mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_u16m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_f16mf4x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsse # | ... # `---data was truncated (10240/20441) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564083b8057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564083b7d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564083b80cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f44c2533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f44c258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f44c2533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f44c251b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564083b1624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564083b16096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564083afaf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005640837aa176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005640837a9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f44c251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f44c251d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f44c251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005640837a9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c (2917 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf4x7_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf2x7_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16m1x7_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055699afd657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055699afd3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055699afd6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8e6081bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8e608725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8e6081ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8e60803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055699af6c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055699af6c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055699af50f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055699ac00176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055699abffe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8e60804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8e608050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8e608050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055699abffd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c (2918 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf8_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf2_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m1_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m2_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m8_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i16mf4_i32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c (2919 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m1(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m8(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf4_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf2_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m1_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv4bf16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ... # `---data was truncated (10240/14904) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056027038957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560270386515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560270389cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fee5ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fee5ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fee5ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fee5ed1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056027031f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056027031f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560270303f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056026ffb3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056026ffb2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fee5ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fee5ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fee5ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056026ffb2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c (2920 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7), pt # | ... # `---data was truncated (10240/19484) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b2e0f5c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b2e0f59515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b2e0f5ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4834733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f483478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4834733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f483471b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b2e0ef224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b2e0ef2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b2e0ed6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b2e0b86176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b2e0b85e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f483471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f483471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f483471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b2e0b85d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c (2921 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv1f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c (2922 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560c170d657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560c170d3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560c170d6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6d1b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6d1b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6d1b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6d1b11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560c1706c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560c1706c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560c17050f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560c16d00176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560c16cffe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6d1b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6d1b11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6d1b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560c16cffd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c (2923 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056517cdea57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056517cde7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056517cdeacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f666881bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f66688725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f666881ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6668803507 abort ./stdlib/abort.c:85:3 # | #7 0x000056517cd8024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056517cd80096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056517cd64f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056517ca14176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056517ca13e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6668804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f66688050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f66688050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056517ca13d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c (2924 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/AArch64/neon/fullfp16-constrained.c (2925 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon/fullfp16-constrained.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=strict -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,simplifycfg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not=' @llvm.fma.' --implicit-check-not=' @llvm.sqrt.' # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=strict -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local half @test_vsqrth_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %vsqrt = call half @llvm.experimental.constrained.sqrt.f16(half %1, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store half %vsqrt, ptr %ref.tmp, align 2 # | %2 = load half, ptr %ref.tmp, align 2 # | store half %2, ptr %__ret, align 2 # | %3 = load half, ptr %__ret, align 2 # | store half %3, ptr %tmp, align 2 # | %4 = load half, ptr %tmp, align 2 # | ret half %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare half @llvm.experimental.constrained.sqrt.f16(half, metadata, metadata) #1 # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local half @test_vfmah_f16(half noundef %a, half noundef %b, half noundef %c) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca half, align 2 # | %c.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %__s1 = alloca half, align 2 # | %__s2 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | store half %b, ptr %b.addr, align 2 # | store half %c, ptr %c.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %b.addr, align 2 # | store half %1, ptr %__s1, align 2 # | %2 = load half, ptr %c.addr, align 2 # | store half %2, ptr %__s2, align 2 # | %3 = load half, ptr %__s0, align 2 # | %4 = load half, ptr %__s1, align 2 # | %5 = load half, ptr %__s2, align 2 # | %6 = call half @llvm.experimental.constrained.fma.f16(half %4, half %5, half %3, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store half %6, ptr %ref.tmp, align 2 # | %7 = load half, ptr %ref.tmp, align 2 # | store half %7, ptr %__ret, align 2 # | %8 = load half, ptr %__ret, align 2 # | store half %8, ptr %tmp, align 2 # | %9 = load half, ptr %tmp, align 2 # | ret half %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare half @llvm.experimental.constrained.fma.f16(half, half, half, metadata, metadata) #1 # | # | attributes #0 = { noinline nounwind strictfp "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon" } # | attributes #1 = { nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) } # | attributes #2 = { strictfp } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,simplifycfg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,simplifycfg # | #0 0x000055e76df6957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e76df66515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e76df69cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f788b849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f788b8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f788b849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f788b831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e76deff24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e76deff096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e76dee3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e76db93176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e76db92e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f788b832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f788b8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f788b8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e76db92d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c --check-prefixes=ALL,LLVM '--implicit-check-not= @llvm.fma.' '--implicit-check-not= @llvm.sqrt.' # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not= @llvm.fma. --implicit-check-not= @llvm.sqrt. # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c (2926 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i6 # | ... # `---data was truncated (10240/25511) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055618cc3257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055618cc2f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055618cc32cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6d1f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6d1f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6d1f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6d1f51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055618cbc824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055618cbc8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055618cbacf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055618c85c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055618c85be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6d1f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6d1f51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6d1f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055618c85bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/zksh.c (2927 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/zksh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zksh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c -check-prefix=RV32ZKSH # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zksh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sm3p0(i32 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.sm3p0(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sm3p1(i32 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.sm3p1(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sm3p0(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sm3p1(i32) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zksh" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_zksh1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556c049ec57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556c049e9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556c049eccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff73f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff73f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff73f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff73f51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556c0498224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556c04982096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556c04966f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556c04616176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556c04615e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff73f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff73f51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff73f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556c04615d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c -check-prefix=RV32ZKSH # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c -check-prefix=RV32ZKSH # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c (2928 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005595204a157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055952049e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005595204a1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb2eab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb2eab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb2eab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb2eab1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055952043724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559520437096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055952041bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005595200cb176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005595200cae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb2eab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb2eab1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb2eab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005595200cad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c (2929 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv1bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv2bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv4bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv8bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv16bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv32bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv32bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrec7.mask.nxv1bf16.i64( %1, %2, %0, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrec7.mask.nxv2bf16.i64( %1, %2, %0, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | # | ... # `---data was truncated (10240/28350) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005576e1f9c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005576e1f99515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005576e1f9ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6850a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6850aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6850a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6850a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005576e1f3224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005576e1f32096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005576e1f16f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005576e1bc6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005576e1bc5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6850a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6850a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6850a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005576e1bc5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c (2930 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8mf8x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8mf4x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_u8mf8x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_u8mf4x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_u8mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_u8m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8mf8x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8mf4x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask. # | ... # `---data was truncated (10240/18972) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560b0032c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560b00329515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560b0032ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb76361bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb7636725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb76361ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb763603507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560b002c224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560b002c2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560b002a6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560afff56176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560afff55e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb763604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb7636050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb7636050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560afff55d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c (2931 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_u32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base # | ... # `---data was truncated (10240/60683) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e7c33b957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e7c33b6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e7c33b9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffb2b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffb2b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffb2b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffb2b51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e7c334f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e7c334f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e7c3333f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e7c2fe3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e7c2fe2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ffb2b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffb2b51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffb2b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e7c2fe2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c (2932 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561a4e19457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561a4e191515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561a4e194cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc399733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc39978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc399733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc39971b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561a4e12a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561a4e12a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561a4e10ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561a4ddbe176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561a4ddbde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc39971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc39971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc39971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561a4ddbdd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c (2933 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf4x8(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf2x8(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16m1x8(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16m1x8_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563da89bd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563da89ba515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563da89bdcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1b64f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1b64f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1b64f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1b64f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563da895324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563da8953096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563da8937f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563da85e7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563da85e6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1b64f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1b64f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1b64f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563da85e6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c (2934 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c (2935 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.mask.nxv4bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.mask.nxv8bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c (2936 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willr # | ... # `---data was truncated (10240/44361) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056474a27f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056474a27c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056474a27fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9e79f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9e79f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9e79f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9e79f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056474a21524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056474a215096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056474a1f9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564749ea9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564749ea8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9e79f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9e79f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9e79f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564749ea8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c (2937 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | ... # `---data was truncated (10240/20149) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564fd4c7257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564fd4c6f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564fd4c72cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdd80849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdd808a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdd80849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdd80831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564fd4c0824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564fd4c08096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564fd4becf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564fd489c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564fd489be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fdd80832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdd808330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdd808330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564fd489bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c (2938 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_u16mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_u16mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_u16m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16mf4x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.v # | ... # `---data was truncated (10240/20439) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005641599ae57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005641599ab515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005641599aecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f437ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f437ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f437ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f437ed1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056415994424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564159944096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564159928f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005641595d8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005641595d7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f437ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f437ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f437ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005641595d7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c (2939 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv8f32.nxv8bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv8f32.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m8_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv16f32.nxv16bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv16f32.nxv16bf16.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,102 # | ... # `---data was truncated (10240/10769) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562493a6157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562493a5e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562493a61cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3515c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3515ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3515c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3515c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005624939f724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005624939f7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005624939dbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056249368b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056249368ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3515c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3515c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3515c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056249368ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c (2940 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv1f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv2f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv4f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv8f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m8_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv16f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv16f32.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfvfexp32e,+zicsr,+zve32f,+zve32x,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfvfexp32e0p5"} # | !3 = !{i32 8, !"Sma # | ... # `---data was truncated (10240/10293) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f9ff3e757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f9ff3e4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f9ff3e7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcd9e905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcd9e95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcd9e905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcd9e8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f9ff37d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f9ff37d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f9ff361f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f9ff011176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f9ff010e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcd9e8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcd9e8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcd9e8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f9ff010d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c (2941 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005561ac42e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005561ac42b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005561ac42ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9c5a049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9c5a0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9c5a049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9c5a031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005561ac3c424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005561ac3c4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005561ac3a8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005561ac058176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005561ac057e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9c5a032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9c5a0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9c5a0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005561ac057d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c (2942 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16mf4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16mf4( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16mf2( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16m1( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16m2( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd # | ... # `---data was truncated (10240/58460) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005602bbf1357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005602bbf10515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005602bbf13cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1f58333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1f5838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1f58333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1f5831b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005602bbea924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005602bbea9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005602bbe8df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005602bbb3d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005602bbb3ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1f5831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1f5831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1f5831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005602bbb3cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c (2943 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | % # | ... # `---data was truncated (10240/14613) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d1cd9e857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d1cd9e5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d1cd9e8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1f63533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1f6358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1f63533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1f6351b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d1cd97e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d1cd97e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d1cd962f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d1cd612176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d1cd611e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1f6351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1f6351d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1f6351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d1cd611d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c (2944 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_i32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_i32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_u32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_u32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32mf2x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/riscv-xandesperf-rv64.c (2945 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesperf-rv64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c --check-prefix=CHECK-RV64 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_ffb(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %2 = call i64 @llvm.riscv.nds.ffb.i64(i64 %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i64 @llvm.riscv.nds.ffb.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_ffzmism(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %2 = call i64 @llvm.riscv.nds.ffzmism.i64(i64 %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i64 @llvm.riscv.nds.ffzmism.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_ffmism(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %2 = call i64 @llvm.riscv.nds.ffmism.i64(i64 %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i64 @llvm.riscv.nds.ffmism.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_flmism(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %2 = call i64 @llvm.riscv.nds.flmism.i64(i64 %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i64 @llvm.riscv.nds.flmism.i64(i64, i64) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xandesperf" } # | attributes #1 = { nounwind speculatable memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_xandesperf5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ec03bf657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ec03bf3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ec03bf6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb868133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb86818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb868133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb86811b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ec03b8c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ec03b8c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ec03b70f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ec03820176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ec0381fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb86811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb86811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb86811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ec0381fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c --check-prefix=CHECK-RV64 # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c --check-prefix=CHECK-RV64 # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c (2946 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32mf2x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_i32mf2x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_i32m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_u32mf2x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_u32m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_i32mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_i32m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_u32mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8 # | ... # `---data was truncated (10240/12059) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005613bda7c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005613bda79515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005613bda7ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe0c7b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe0c7b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe0c7b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe0c7b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005613bda1224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005613bda12096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005613bd9f6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005613bd6a6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005613bd6a5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe0c7b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe0c7b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe0c7b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005613bd6a5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c (2947 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_f32mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_f32mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv1f32.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_f32m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_f32m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv2f32.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_f32m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_f32m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2 # | ... # `---data was truncated (10240/151911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562fdf24157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562fdf23e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562fdf241cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9942449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f99424a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9942449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9942431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562fdf1d724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562fdf1d7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562fdf1bbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562fdee6b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562fdee6ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9942432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f99424330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f99424330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562fdee6ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c (2948 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005650d310657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005650d3103515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005650d3106cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f74c9c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f74c9c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f74c9c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f74c9c03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005650d309c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005650d309c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005650d3080f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005650d2d30176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005650d2d2fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f74c9c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f74c9c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f74c9c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005650d2d2fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c (2949 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor # | ... # `---data was truncated (10240/113039) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005585fae1c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005585fae19515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005585fae1ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0540b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0540b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0540b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0540b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005585fadb224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005585fadb2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005585fad96f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005585faa46176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005585faa45e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0540b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0540b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0540b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005585faa45d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c (2950 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare # | ... # `---data was truncated (10240/20141) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005638c423057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005638c422d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005638c4230cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1039133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f103918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1039133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f103911b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005638c41c624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005638c41c6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005638c41aaf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005638c3e5a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005638c3e59e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f103911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f103911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f103911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005638c3e59d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c (2951 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16mf4x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16mf4x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_u16mf4x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_u16mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_u16m1x7_m(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c (2952 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_f64m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_f64m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_f64m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_i64m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_i64m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_i64m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_u64m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_u64m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_u64m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_f64m1x2_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: wri # | ... # `---data was truncated (10240/20523) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005595f696857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005595f6965515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005595f6968cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f97d7249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f97d72a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f97d7249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f97d7231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005595f68fe24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005595f68fe096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005595f68e2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005595f6592176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005595f6591e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f97d7232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f97d72330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f97d72330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005595f6591d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c (2953 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_i32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_i32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_u32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_u32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32mf2x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedof # | ... # `---data was truncated (10240/40734) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560a902ca57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560a902c7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560a902cacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fad9d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fad9d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fad9d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fad9d231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560a9026024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560a90260096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560a90244f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560a8fef4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560a8fef3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fad9d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fad9d2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fad9d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560a8fef3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c (2954 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564721f8a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564721f87515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564721f8acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc3e5449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc3e54a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc3e5449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc3e5431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564721f2024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564721f20096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564721f04f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564721bb4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564721bb3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc3e5432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc3e54330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc3e54330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564721bb3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c (2955 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsqr # | ... # `---data was truncated (10240/28170) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562091e4957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562091e46515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562091e49cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5426249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f54262a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5426249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5426231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562091ddf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562091ddf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562091dc3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562091a73176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562091a72e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5426232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f54262330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f54262330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562091a72d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c (2956 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf8x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf8x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf8x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf4x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c (2957 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_i32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_i32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_u32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_u32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32mf2x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c (2958 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056262f40f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056262f40c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056262f40fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbc8bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbc8bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbc8bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbc8bb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056262f3a524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056262f3a5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056262f389f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056262f039176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056262f038e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbc8bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbc8bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbc8bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056262f038d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c (2959 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8), pt # | ... # `---data was truncated (10240/19484) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f0731f157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f0731ee515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f0731f1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c2f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c2f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c2f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c2f11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f07318724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f073187096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f07316bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f072e1b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f072e1ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2c2f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c2f11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c2f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f072e1ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c (2960 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16mf4x3(ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16mf2x3(ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16m1x3(ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16m2x3(ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16m1x3_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16m2x3_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwin # | ... # `---data was truncated (10240/10798) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055defe06257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055defe05f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055defe062cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8d51133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8d5118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8d51133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8d5111b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055defdff824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055defdff8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055defdfdcf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055defdc8c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055defdc8be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8d5111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8d5111d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8d5111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055defdc8bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c (2961 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16m8(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i8.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i8.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, # | ... # `---data was truncated (10240/15512) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055615029757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556150294515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556150297cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fca39733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fca3978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fca39733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fca3971b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055615022d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055615022d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556150211f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055614fec1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055614fec0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fca3971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fca3971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fca3971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055614fec0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c (2962 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565240c4657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000565240c43515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000565240c46cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb25261bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb2526725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb25261ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb252603507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565240bdc24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000565240bdc096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000565240bc0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000565240870176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056524086fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb252604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb2526050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb2526050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056524086fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c (2963 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_f64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_i64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_u64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_f64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_i64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_u64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560f15d2157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560f15d1e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560f15d21cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3c97933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3c9798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3c97933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3c9791b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560f15cb724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560f15cb7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560f15c9bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560f1594b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560f1594ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3c9791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3c9791d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3c9791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560f1594ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c (2964 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556bd2ea557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556bd2ea2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556bd2ea5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9100849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f91008a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9100849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9100831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556bd2e3b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556bd2e3b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556bd2e1ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556bd2acf176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556bd2acee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9100832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f91008330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f91008330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556bd2aced81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c (2965 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056036154c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560361549515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056036154ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6efa933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6efa98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6efa933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6efa91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005603614e224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005603614e2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005603614c6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560361176176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560361175e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6efa91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6efa91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6efa91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560361175d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c (2966 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.ris # | ... # `---data was truncated (10240/60220) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562fc8d9057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562fc8d8d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562fc8d90cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffa2eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffa2eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffa2eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffa2eb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562fc8d2624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562fc8d26096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562fc8d0af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562fc89ba176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562fc89b9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ffa2eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffa2eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffa2eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562fc89b9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c (2967 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv8i8.nxv8i8.i64(, , , , i # | ... # `---data was truncated (10240/63579) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563242e6f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563242e6c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563242e6fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f402c81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f402c8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f402c81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f402c803507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563242e0524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563242e05096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563242de9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563242a99176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563242a98e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f402c804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f402c8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f402c8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563242a98d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c (2968 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16mf4x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16mf4x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16mf4x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_ # | ... # `---data was truncated (10240/10396) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a0651dd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a0651da515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a0651ddcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5c24133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5c2418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5c24133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5c2411b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a06517324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a065173096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a065157f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a064e07176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a064e06e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5c2411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5c2411d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5c2411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a064e06d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c (2969 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c4c7c6257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c4c7c5f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c4c7c62cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc54cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc54cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc54cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc54cc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c4c7bf824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c4c7bf8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c4c7bdcf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c4c788c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c4c788be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc54cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc54cc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc54cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c4c788bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/riscv-xcvalu.c (2970 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/riscv-xcvalu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xcvalu -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xcvalu -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_abs(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call i32 @llvm.abs.i32(i32 %0, i1 true) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.abs.i32(i32, i1 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_sle(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = icmp sle i32 %0, %1 # | %sle = zext i1 %2 to i32 # | ret i32 %sle # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_sleu(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = icmp ule i32 %0, %1 # | %sleu = zext i1 %2 to i32 # | ret i32 %sleu # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_exths(i16 noundef signext %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | %conv = sext i16 %0 to i32 # | %1 = trunc i32 %conv to i16 # | %exths = sext i16 %1 to i32 # | ret i32 %exths # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_exthz(i16 noundef zeroext %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | %conv = zext i16 %0 to i32 # | %1 = trunc i32 %conv to i16 # | %exthz = zext i16 %1 to i32 # | ret i32 %exthz # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_extbs(i8 noundef signext %a) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | store i8 %a, ptr %a.addr, align 1 # | %0 = load i8, ptr %a.addr, align 1 # | %conv = sext i8 %0 to i32 # | %1 = trunc i32 %conv to i8 # | %extbs = sext i8 %1 to i32 # | ret i32 %extbs # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_extbz(i8 noundef zeroext %a) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | store i8 %a, ptr %a.addr, align 1 # | %0 = load i8, ptr %a.addr, align 1 # | %conv = zext i8 %0 to i32 # | %1 = trunc i32 %conv to i8 # | %extbz = zext i8 %1 to i32 # | ret i32 %extbz # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_clip(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call i32 @llvm.riscv.cv.alu.clip(i32 %0, i32 15) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.cv.alu.clip(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_clipu(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call i32 @llvm.riscv.cv.alu.clipu(i32 %0, i32 15) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.cv.alu.clipu(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_addN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.cv.alu.addN(i32 %0, i32 %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.cv.alu.addN(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_adduN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.cv.alu.adduN(i32 %0, i32 %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.cv.alu.adduN(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_addRN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.cv.alu.addRN(i32 %0, i32 %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.cv.alu.addRN(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_adduRN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.cv.alu.adduRN(i32 %0, i32 %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.cv.alu.adduRN(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_subN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.cv.alu.subN(i32 %0, i32 %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.cv.alu.subN(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_subuN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.cv.alu.subuN(i32 %0, i32 %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.cv.alu.subuN(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_subRN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.cv.alu.subRN(i32 %0, i32 %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.cv.alu.subRN(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_subuRN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.cv.alu.subuRN(i32 %0, i32 %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.cv.alu.subuRN(i32, i32, i32) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+xcvalu" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_xcvalu1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558e9134a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558e91347515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558e9134acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f30d5f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f30d5f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f30d5f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f30d5f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558e912e024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558e912e0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558e912c4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558e90f74176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558e90f73e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f30d5f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f30d5f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f30d5f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558e90f73d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c (2971 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c -check-prefix=RV64ZKND # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @aes64dsm(i64 noundef %rs1, i64 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i64, align 8 # | %__y.addr.i = alloca i64, align 8 # | %rs1.addr = alloca i64, align 8 # | %rs2.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | store i64 %0, ptr %__x.addr.i, align 8 # | store i64 %1, ptr %__y.addr.i, align 8 # | %2 = load i64, ptr %__x.addr.i, align 8 # | %3 = load i64, ptr %__y.addr.i, align 8 # | %4 = call i64 @llvm.riscv.aes64dsm(i64 %2, i64 %3) # | ret i64 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @aes64ds(i64 noundef %rs1, i64 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i64, align 8 # | %__y.addr.i = alloca i64, align 8 # | %rs1.addr = alloca i64, align 8 # | %rs2.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | store i64 %0, ptr %__x.addr.i, align 8 # | store i64 %1, ptr %__y.addr.i, align 8 # | %2 = load i64, ptr %__x.addr.i, align 8 # | %3 = load i64, ptr %__y.addr.i, align 8 # | %4 = call i64 @llvm.riscv.aes64ds(i64 %2, i64 %3) # | ret i64 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @aes64im(i64 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i64, align 8 # | %rs1.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | store i64 %0, ptr %__x.addr.i, align 8 # | %1 = load i64, ptr %__x.addr.i, align 8 # | %2 = call i64 @llvm.riscv.aes64im(i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.aes64dsm(i64, i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.aes64ds(i64, i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.aes64im(i64) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zknd" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zknd1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005585a256957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005585a2566515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005585a2569cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc6c8249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc6c82a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc6c8249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc6c8231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005585a24ff24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005585a24ff096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005585a24e3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005585a2193176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005585a2192e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc6c8232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc6c82330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc6c82330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005585a2192d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c -check-prefix=RV64ZKND # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c -check-prefix=RV64ZKND # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c (2972 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16mf4x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16mf2x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16m1x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16m2x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16m4x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16m1x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store targ # | ... # `---data was truncated (10240/14667) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b14606757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b146064515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b146067cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8231649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f82316a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8231649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8231631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b145ffd24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b145ffd096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b145fe1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b145c91176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b145c90e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8231632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f82316330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f82316330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b145c90d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c (2973 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv4i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willret # | ... # `---data was truncated (10240/15203) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a95584057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a95583d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a955840cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1188449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f11884a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1188449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1188431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a9557d624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a9557d6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a9557baf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a95546a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a955469e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1188432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f11884330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f11884330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a955469d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c (2974 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vvm_i8mf8_b64( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vxm_i8mf8_b64( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadc.carry.in.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.carry.in.nxv1i8.i8.i64(, i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmadc.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmadc.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vvm_i8mf4_b32( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vxm_i8mf4_b32( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadc.carry.in.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.carry.in.nxv2i8.i8.i64(, i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmadc.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmadc.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vvm_i8mf2_b16( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vxm_i8mf2_b16( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, al # | ... # `---data was truncated (10240/169925) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056057848b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560578488515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056057848bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f76c9c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f76c9ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f76c9c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f76c9c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056057842124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560578421096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560578405f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005605780b5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005605780b4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f76c9c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f76c9c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f76c9c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005605780b4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c (2975 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf8x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf4x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf8x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf4x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv8i1(target("riscv.vector.tup # | ... # `---data was truncated (10240/11031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055de888b457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055de888b1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055de888b4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3c2a505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3c2a55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3c2a505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3c2a4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055de8884a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055de8884a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055de8882ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055de884de176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055de884dde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3c2a4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3c2a4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3c2a4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055de884ddd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c (2976 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv64i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv64i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv32i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv32i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv16i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv16i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv8i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv8i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv4i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv4i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv2i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv2i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv1i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv1i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv64i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.mask.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv32i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.mask.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv16i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.mask.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv8i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.mask.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b16_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv4i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.mask.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b32_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv2i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | # | ... # `---data was truncated (10240/11938) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056219b71b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056219b718515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056219b71bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1c0c21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1c0c2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1c0c21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1c0c203507 abort ./stdlib/abort.c:85:3 # | #7 0x000056219b6b124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056219b6b1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056219b695f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056219b345176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056219b344e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1c0c204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1c0c2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1c0c2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056219b344d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c (2977 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", # | ... # `---data was truncated (10240/19492) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056174026557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561740262515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561740265cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f15f0649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f15f06a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f15f0649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f15f0631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005617401fb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005617401fb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005617401dff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056173fe8f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056173fe8ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f15f0632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f15f06330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f15f06330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056173fe8ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmlldav.c (2978 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmlldav.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaq_s16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load <8 x i16>, ptr %b.addr, align 8 # | %5 = load <8 x i16>, ptr %c.addr, align 8 # | %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 0, i32 0, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32, i32, i32, i32, i32, <8 x i16>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load <4 x i32>, ptr %b.addr, align 8 # | %5 = load <4 x i32>, ptr %c.addr, align 8 # | %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 0, i32 0, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32, i32, i32, i32, i32, <4 x i32>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaq_u16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load <8 x i16>, ptr %b.addr, align 8 # | %5 = load <8 x i16>, ptr %c.addr, align 8 # | %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 1, i32 0, i32 0, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaq_u32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load <4 x i32>, ptr %b.addr, align 8 # | %5 = load <4 x i32>, ptr %c.addr, align 8 # | %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 1, i32 0, i32 0, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaxq_s16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load <8 x i16>, ptr %b.addr, align 8 # | %5 = load <8 x i16>, ptr %c.addr, align 8 # | %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 0, i32 1, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaxq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load <4 x i32>, ptr %b.addr, align 8 # | %5 = load <4 x i32>, ptr %c.addr, align 8 # | %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 0, i32 1, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vmlsldavaq_s16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load <8 x i16>, ptr %b.addr, align 8 # | %5 = load <8 x i16>, ptr %c.addr, align 8 # | %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 1, i32 0, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vmlsldavaq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load <4 x i32>, ptr %b.addr, align 8 # | %5 = load <4 x i32>, ptr %c.addr, align 8 # | %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 1, i32 0, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vmlsldaxvaq_s16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load <8 x i16>, ptr %b.addr, align 8 # | %5 = load <8 x i16>, ptr %c.addr, align 8 # | %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 1, i32 1, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vmlsldavaxq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load <4 x i32>, ptr %b.addr, align 8 # | %5 = load <4 x i32>, ptr %c.addr, align 8 # | %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 1, i32 1, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vrmlaldavhaq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, al # | ... # `---data was truncated (10240/58468) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000561223c7657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561223c73515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561223c76cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcc6d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcc6d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcc6d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcc6d631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561223c0c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561223c0c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561223bf0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005612238a0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056122389fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcc6d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcc6d6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcc6d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056122389fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c (2979 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettm_e8w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 0, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.sf.vsettm.i64(i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettm_e8w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 0, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettm_e8w4(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 0, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettm_e16w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 1, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettm_e16w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 1, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettm_e16w4(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 1, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettm_e32w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 2, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettm_e32w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 2, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettm_e64w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 3, i64 1) # | ret i64 %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055927a63857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055927a635515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055927a638cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff57af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff57af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff57af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff57af1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055927a5ce24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055927a5ce096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055927a5b2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055927a262176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055927a261e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff57af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff57af1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff57af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055927a261d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c (2980 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -disable-O0-optnone -emit-llvm -Qn /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2 | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -disable-O0-optnone -emit-llvm -Qn /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @test_vlenb() #0 { # | entry: # | %0 = call i32 @llvm.read_register.i32(metadata !4) # | ret i32 %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare i32 @llvm.read_register.i32(metadata) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | # | !0 = !{i32 1, !"target-abi", !"ilp32d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"vlenb"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2 # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2 # | #0 0x000055dccbb4257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055dccbb3f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055dccbb42cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faa48733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faa4878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faa48733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faa4871b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dccbad824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055dccbad8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055dccbabcf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055dccb76c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055dccb76be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007faa4871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faa4871d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faa4871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dccb76bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-vls-subscript-ops.c (2981 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-subscript-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local signext i8 @subscript_int8( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca i64, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <32 x i8> %0, i64 %1 # | ret i8 %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local zeroext i8 @subscript_uint8( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca i64, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <32 x i8> %0, i64 %1 # | ret i8 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local signext i16 @subscript_int16( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca i64, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <16 x i16> %0, i64 %1 # | ret i16 %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local zeroext i16 @subscript_uint16( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca i64, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <16 x i16> %0, i64 %1 # | ret i16 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local signext i32 @subscript_int32( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i32>, align 8 # | %b.addr = alloca i64, align 8 # | %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %a.coerce, i64 0) # | store <8 x i32> %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <8 x i32>, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <8 x i32> %0, i64 %1 # | ret i32 %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local signext i32 @subscript_uint32( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i32>, align 8 # | %b.addr = alloca i64, align 8 # | %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %a.coerce, i64 0) # | store <8 x i32> %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <8 x i32>, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <8 x i32> %0, i64 %1 # | ret i32 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local i64 @subscript_int64( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i64>, align 8 # | %b.addr = alloca i64, align 8 # | %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %a.coerce, i64 0) # | store <4 x i64> %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <4 x i64>, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <4 x i64> %0, i64 %1 # | ret i64 %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local i64 @subscript_uint64( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i64>, align 8 # | %b.addr = alloca i64, align 8 # | %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %a.coerce, i64 0) # | store <4 x i64> %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <4 x i64>, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <4 x i64> %0, i64 %1 # | ret i64 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local float @subscript_float32( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x float>, align 8 # | %b.addr = alloca i64, align 8 # | %a = call <8 x float> @llvm.vector.extract.v8f32.nxv2f32( %a.coerce, i64 0) # | store <8 x float> %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <8 x float>, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <8 x float> %0, i64 %1 # | ret float %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x float> @llvm.vector.extract.v8f32.nxv2f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local double @subscript_float64( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x double>, align 8 # | %b.addr = alloca i64, align 8 # | %a = call <4 x double> @llvm.vector.extract.v4f64.nxv1f64( %a.coerce, i64 0) # | store <4 x double> %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <4 x double>, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <4 x double> %0, i64 %1 # | ret double %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x double> @llvm.vector.extract.v4f64.nxv1f64(, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,4) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x00005614b44a657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005614b44a3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005614b44a6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc5c8449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc5c84a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc5c8449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc5c8431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005614b443c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005614b443c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005614b4420f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005614b40d0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005614b40cfe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc5c8432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc5c84330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc5c84330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005614b40cfd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c (2982 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsm4k.nxv1i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv1i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsm4k.nxv2i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv2i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsm4k.nxv4i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv4i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsm4k.nxv8i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv8i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsm4k.nxv16i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv16i32.i64.i64(, , i64 immarg, i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056413e94357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056413e940515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056413e943cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcc85333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcc8538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcc85333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcc8531b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056413e8d924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056413e8d9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056413e8bdf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056413e56d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056413e56ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcc8531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcc8531d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcc8531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056413e56cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c (2983 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16mf4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16mf2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m1_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m8_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f32mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f32m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv2f32.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f32m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv2f32.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv2f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define # | ... # `---data was truncated (10240/37564) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005626ebbe057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005626ebbdd515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005626ebbe0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd00c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd00c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd00c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd00c431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005626ebb7624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005626ebb76096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005626ebb5af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005626eb80a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005626eb809e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd00c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd00c4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd00c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005626eb809d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c (2984 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_i32mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_i32m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_u32mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_u32m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055777dd8c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055777dd89515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055777dd8ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdce3933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdce398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdce3933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdce391b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055777dd2224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055777dd22096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055777dd06f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055777d9b6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055777d9b5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fdce391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdce391d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdce391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055777d9b5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/dup.c (2985 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/dup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vdupq_n_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | %.splatinsert = insertelement <8 x half> poison, half %0, i64 0 # | %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer # | ret <8 x half> %.splat # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vdupq_n_f32(float noundef %a) #0 { # | entry: # | %a.addr = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | %0 = load float, ptr %a.addr, align 4 # | %.splatinsert = insertelement <4 x float> poison, float %0, i64 0 # | %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer # | ret <4 x float> %.splat # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdupq_n_s8(i8 noundef signext %a) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | store i8 %a, ptr %a.addr, align 1 # | %0 = load i8, ptr %a.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %0, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | ret <16 x i8> %.splat # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdupq_n_s16(i16 noundef signext %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %0, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | ret <8 x i16> %.splat # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vdupq_n_s32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %0, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | ret <4 x i32> %.splat # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdupq_n_u8(i8 noundef zeroext %a) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | store i8 %a, ptr %a.addr, align 1 # | %0 = load i8, ptr %a.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %0, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | ret <16 x i8> %.splat # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdupq_n_u16(i16 noundef zeroext %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %0, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | ret <8 x i16> %.splat # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vdupq_n_u32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %0, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | ret <4 x i32> %.splat # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vdupq_m_n_f16(<8 x half> noundef %inactive, half noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca half, align 2 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store half %a, ptr %a.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load half, ptr %a.addr, align 2 # | %.splatinsert = insertelement <8 x half> poison, half %3, i64 0 # | %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer # | %4 = load <8 x half>, ptr %inactive.addr, align 8 # | %5 = select <8 x i1> %2, <8 x half> %.splat, <8 x half> %4 # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vdupq_m_n_f32(<4 x float> noundef %inactive, float noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca float, align 4 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store float %a, ptr %a.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load float, ptr %a.addr, align 4 # | %.splatinsert = insertelement <4 x float> poison, float %3, i64 0 # | %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer # | %4 = load <4 x float>, ptr %inactive.addr, align 8 # | %5 = select <4 x i1> %2, <4 x float> %.splat, <4 x float> %4 # | ret <4 x float> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdupq_m_n_s8(<16 x i8> noundef %inactive, i8 noundef signext %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca i8, align 1 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store i8 %a, ptr %a.addr, align 1 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1) # | %3 = load i8, ptr %a.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %3, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %4 = load <16 x i8>, ptr %inactive.addr, align 8 # | %5 = select <16 x i1> %2, <16 x i8> %.splat, <16 x i8> %4 # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdupq_m_n_s16(<8 x i16> noundef %inactive, i16 noundef signext %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store i16 %a, ptr %a.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load i16, ptr %a.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %3, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = select <8 x i1> %2, <8 x i16> %.splat, <8 x i16> %4 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vdupq_m_n_s32(<4 x i32> noundef %inactive, i32 noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load i32, ptr %a.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %3, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %4 = load <4 x i32>, ptr %inactive.addr, align 8 # | %5 = select <4 x i1> %2, <4 x i32> %.splat, <4 x i32> %4 # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdupq_m_n_u8(<16 x i8> noundef %inactive, i8 noundef zeroext %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca i8, align 1 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store i8 %a, ptr %a.addr, align 1 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1) # | %3 = load i8, ptr %a.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %3, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %4 = load <16 x i8>, ptr %inactive.addr, align 8 # | %5 = select <16 x i1> %2, <16 x i8> %.splat, <16 x i8> %4 # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdupq_m_n_u16(<8 x i16> noundef %inactive, i16 noundef zeroext %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store i16 %a, ptr %a.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load i16, ptr %a.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %3, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = select <8 x i1> %2, # | ... # `---data was truncated (10240/17297) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>' # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<> # | #0 0x0000555a4450b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555a44508515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555a4450bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd112533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd11258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd112533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd11251b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555a444a124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555a444a1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555a44485f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555a44135176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555a44134e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd11251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd11251d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd11251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555a44134d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c (2986 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ta # | ... # `---data was truncated (10240/47488) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005613992ca57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005613992c7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005613992cacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4ed6a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4ed6a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4ed6a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4ed6a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000056139926024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561399260096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561399244f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561398ef4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561398ef3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4ed6a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4ed6a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4ed6a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561398ef3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c (2987 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055580cc9457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055580cc91515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055580cc94cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f13e8733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f13e878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f13e8733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f13e871b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055580cc2a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055580cc2a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055580cc0ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055580c8be176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055580c8bde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f13e871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f13e871d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f13e871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055580c8bdd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c (2988 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c (2989 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vect # | ... # `---data was truncated (10240/31946) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005641fe88d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005641fe88a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005641fe88dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f11c3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f11c338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f11c3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f11c331b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005641fe82324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005641fe823096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005641fe807f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005641fe4b7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005641fe4b6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f11c331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f11c331d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f11c331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005641fe4b6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-vls-shift-ops.c (2990 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-shift-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @lshift_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %shl = shl <32 x i8> %0, %1 # | store <32 x i8> %shl, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv8i8.v32i8( poison, <32 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8i8.v32i8(, <32 x i8>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @rshift_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %shr = ashr <32 x i8> %0, %1 # | store <32 x i8> %shr, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv8i8.v32i8( poison, <32 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @lshift_u8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %shl = shl <32 x i8> %0, %1 # | store <32 x i8> %shl, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv8i8.v32i8( poison, <32 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @rshift_u8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %shr = lshr <32 x i8> %0, %1 # | store <32 x i8> %shr, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv8i8.v32i8( poison, <32 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @lshift_i16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i16>, align 8 # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca <16 x i16>, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %b.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store <16 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load <16 x i16>, ptr %b.addr, align 8 # | %shl = shl <16 x i16> %0, %1 # | store <16 x i16> %shl, ptr %retval, align 8 # | %2 = load <16 x i16>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv4i16.v16i16( poison, <16 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4i16.v16i16(, <16 x i16>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @rshift_i16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i16>, align 8 # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca <16 x i16>, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %b.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store <16 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load <16 x i16>, ptr %b.addr, align 8 # | %shr = ashr <16 x i16> %0, %1 # | store <16 x i16> %shr, ptr %retval, align 8 # | %2 = load <16 x i16>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv4i16.v16i16( poison, <16 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @lshift_u16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i16>, align 8 # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca <16 x i16>, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %b.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store <16 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load <16 x i16>, ptr %b.addr, align 8 # | %shl = shl <16 x i16> %0, %1 # | store <16 x i16> %shl, ptr %retval, align 8 # | %2 = load <16 x i16>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv4i16.v16i16( poison, <16 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @rshift_u16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i16>, align 8 # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca <16 x i16>, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %b.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store <16 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load <16 x i16>, ptr %b.addr, align 8 # | %shr = lshr <16 x i16> %0, %1 # | store <16 x i16> %shr, ptr %retval, align 8 # | %2 = load <16 x i16>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv4i16.v16i16( poison, <16 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @lshift_i32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i32>, align 8 # | %a.addr = alloca <8 x i32>, align 8 # | %b.addr = alloca <8 x i32>, align 8 # | %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %a.coerce, i64 0) # | %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %b.coerce, i64 0) # | store <8 x i32> %a, ptr %a.addr, align 8 # | store <8 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i32>, ptr %b.addr, align 8 # | %shl = shl <8 x i32> %0, %1 # | store <8 x i32> %shl, ptr %retval, align 8 # | %2 = load <8 x i32>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv2i32.v8i32( poison, <8 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2i32.v8i32(, <8 x i32>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @rshift_i32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %r # | ... # `---data was truncated (10240/50943) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x0000559d67c0657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559d67c03515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559d67c06cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc852049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc8520a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc852049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc852031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559d67b9c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559d67b9c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559d67b80f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559d67830176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559d6782fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc852032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc8520330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc8520330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559d6782fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c (2991 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c (2992 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32mf2x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_i32mf2x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_i32m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_u32mf2x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_u32m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563fc41f257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563fc41ef515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563fc41f2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1d68b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1d68b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1d68b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1d68aed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563fc418824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563fc4188096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563fc416cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563fc3e1c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563fc3e1be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1d68aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1d68aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1d68aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563fc3e1bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c (2993 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b1_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv64i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b2_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv32i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b4_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv16i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b8_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv8i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b16_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv4i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv4i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b32_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv2i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv2i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b64_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv1i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv1i1.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556dbc3ca57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556dbc3c7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556dbc3cacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe6dd049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe6dd0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe6dd049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe6dd031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556dbc36024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556dbc360096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556dbc344f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556dbbff4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556dbbff3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe6dd032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe6dd0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe6dd0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556dbbff3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c (2994 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8), pt # | ... # `---data was truncated (10240/19484) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f6eee4957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f6eee46515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f6eee49cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb5fe133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb5fe18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb5fe133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb5fe11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f6eeddf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f6eeddf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f6eedc3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f6eea73176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f6eea72e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb5fe11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb5fe11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb5fe11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f6eea72d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c (2995 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_f64m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_i64m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_u64m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_f64m1x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_i64m1x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_u64m1x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005654bb0e157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005654bb0de515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005654bb0e1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fac1ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fac1eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fac1ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fac1ea31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005654bb07724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005654bb077096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005654bb05bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005654bad0b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005654bad0ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fac1ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fac1ea330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fac1ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005654bad0ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c (2996 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056077346457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560773461515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560773464cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe306133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe30618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe306133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe30611b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005607733fa24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005607733fa096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005607733def49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056077308e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056077308de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe30611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe30611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe30611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056077308dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c (2997 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16mf4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16mf4( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16mf2( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16m1( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16m2( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | s # | ... # `---data was truncated (10240/58326) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ccd44ad57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ccd44aa515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ccd44adcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fda09333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fda0938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fda09333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fda0931b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ccd444324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ccd4443096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ccd4427f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ccd40d7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ccd40d6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fda0931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fda0931d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fda0931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ccd40d6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c (2998 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1f64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv2f64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv4f64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv8f64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1i64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv2i64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv4i64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv8i64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_u64m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1i64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_u64m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv2i64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_u64m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv4i64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_u64m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv8i64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c (2999 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16mf4_bf16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16mf2_bf16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16m1_bf16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16m2_bf16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16m4_bf16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16m8_bf16m8( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16mf4_bf16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16mf2_bf16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16m1_bf16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16m2_bf16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16m4_bf16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16m8_bf16m8( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16mf4_i16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16mf2_i16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m1_i16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m2_i16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m4_i16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m8_i16m8( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16mf4_u16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16mf2_u16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m1_u16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m2_u16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m4_u16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 # | ... # `---data was truncated (10240/11237) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005607600ce57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005607600cb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005607600cecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007effa4e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007effa4e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007effa4e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007effa4e03507 abort ./stdlib/abort.c:85:3 # | #7 0x000056076006424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560760064096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560760048f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056075fcf8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056075fcf7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007effa4e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007effa4e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007effa4e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056075fcf7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c (3000 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_v # | ... # `---data was truncated (10240/216258) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005623cc50d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005623cc50a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005623cc50dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb51b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb51b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb51b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb51b031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005623cc4a324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005623cc4a3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005623cc487f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005623cc137176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005623cc136e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb51b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb51b0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb51b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005623cc136d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c (3001 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf8_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf2_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m1_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m2_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m8_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i16mf4_i32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64( # | ... # `---data was truncated (10240/51185) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b398c4f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b398c4c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b398c4fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa9ff333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa9ff38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa9ff333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa9ff31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b398be524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b398be5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b398bc9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b398879176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b398878e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa9ff31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa9ff31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa9ff31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b398878d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c (3002 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m1x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m1x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m1x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_ # | ... # `---data was truncated (10240/10440) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cc7d46e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cc7d46b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cc7d46ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f70fe705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f70fe75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f70fe705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f70fe6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cc7d40424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cc7d404096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cc7d3e8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cc7d098176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cc7d097e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f70fe6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f70fe6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f70fe6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cc7d097d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c (3003 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c (3004 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv8f32.nxv8f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f32.nxv8f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv16f32.nxv16f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16f32.nxv16f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, al # | ... # `---data was truncated (10240/30861) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561c44d5057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561c44d4d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561c44d50cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd950933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd95098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd950933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd95091b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561c44ce624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561c44ce6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561c44ccaf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561c4497a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561c44979e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd95091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd95091d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd95091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561c44979d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c (3005 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f14d7aa57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f14d7a7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f14d7aacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3ead905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3ead95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3ead905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3ead8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f14d74024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f14d740096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f14d724f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f14d3d4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f14d3d3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3ead8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3ead8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3ead8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f14d3d3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c (3006 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 7) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 7) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { targ # | ... # `---data was truncated (10240/21111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f09c08e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f09c08b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f09c08ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f06fc305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f06fc35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f06fc305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f06fc2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f09c02424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f09c024096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f09c008f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f09bcb8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f09bcb7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f06fc2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f06fc2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f06fc2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f09bcb7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c (3007 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store # | ... # `---data was truncated (10240/29296) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005631ec58657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005631ec583515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005631ec586cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f05e5a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f05e5aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f05e5a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f05e5a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005631ec51c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005631ec51c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005631ec500f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005631ec1b0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005631ec1afe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f05e5a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f05e5a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f05e5a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005631ec1afd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c (3008 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32mf2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32mf2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32mf2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32mf2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32m2x4_m( %mask, ptr noun # | ... # `---data was truncated (10240/17567) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556dbc09c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556dbc099515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556dbc09ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd27d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd27d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd27d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd27d11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556dbc03224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556dbc032096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556dbc016f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556dbbcc6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556dbbcc5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd27d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd27d11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd27d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556dbbcc5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c (3009 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv1f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c (3010 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_bf16m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv32bf16.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare @llvm.riscv.sf.vtmv.v.t.nxv32bf16.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_f16m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv32f16.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare @llvm.riscv.sf.vtmv.v.t.nxv32f16.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_f32m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv16f32.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare @llvm.riscv.sf.vtmv.v.t.nxv16f32.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_f64m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv8f64.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare @llvm.riscv.sf.vtmv.v.t.nxv8f64.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_i8m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_i16m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv32i16.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare @llvm.riscv.sf.vtmv.v.t.nxv32i16.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_i32m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv16i32.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare @llvm.riscv.sf.vtmv.v.t.nxv16i32.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_i64m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv8i64.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare @llvm.riscv.sf.vtmv.v.t.nxv8i64.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_u8m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_u16m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv32i16.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_u32m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv16i32.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_u64m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv8i64.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_f8e4m3m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_f8e5m2m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfofp8min,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvfhmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvfhmin1p0_zvfofp8min0p9_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056299a9ed57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056299a9ea515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056299a9edcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd5cfd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd5cfd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd5cfd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd5cfd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056299a98324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056299a983096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056299a967f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056299a617176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056299a616e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd5cfd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd5cfd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd5cfd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056299a616d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c (3011 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv8i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv8i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv16i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv16i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv32i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv32i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv64i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv64i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xandesvsintload,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xandesvsintload5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005604f698c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005604f6989515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005604f698ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc92c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc92c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc92c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc92c631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005604f692224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005604f6922096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005604f6906f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005604f65b6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005604f65b5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc92c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc92c6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc92c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005604f65b5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c (3012 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf8x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf4x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf8x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf4x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055950d51d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055950d51a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055950d51dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe2a441bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe2a44725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe2a441ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe2a4403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055950d4b324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055950d4b3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055950d497f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055950d147176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055950d146e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe2a4404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe2a44050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe2a44050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055950d146d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c (3013 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8mf8x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8mf4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_u8mf8x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_u8mf4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_u8mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_u8m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) % # | ... # `---data was truncated (10240/27994) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055beb94a657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055beb94a3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055beb94a6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f918bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f918bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f918bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f918bd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055beb943c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055beb943c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055beb9420f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055beb90d0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055beb90cfe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f918bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f918bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f918bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055beb90cfd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c (3014 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv1i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv2i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv4i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv8i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv16i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fac76b257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fac76af515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fac76b2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f992e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f992e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f992e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f992e231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fac764824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fac7648096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fac762cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fac72dc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fac72dbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f992e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f992e2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f992e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fac72dbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c (3015 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557f3d02b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557f3d028515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557f3d02bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe1cd049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe1cd0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe1cd049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe1cd031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557f3cfc124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557f3cfc1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557f3cfa5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557f3cc55176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557f3cc54e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe1cd032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe1cd0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe1cd0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557f3cc54d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c (3016 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m1x # | ... # `---data was truncated (10240/25695) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b5fdb2b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b5fdb28515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b5fdb2bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8d7cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8d7cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8d7cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8d7cb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b5fdac124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b5fdac1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b5fdaa5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b5fd755176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b5fd754e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8d7cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8d7cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8d7cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b5fd754d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmaxnmaq.c (3017 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmaxnmaq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %0) # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %2) # | %4 = call <8 x half> @llvm.maxnum.v8f16(<8 x half> %1, <8 x half> %3) # | ret <8 x half> %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.fabs.v8f16(<8 x half>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.maxnum.v8f16(<8 x half>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmaq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %0) # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %2) # | %4 = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %1, <4 x float> %3) # | ret <4 x float> %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.fabs.v4f32(<4 x float>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmaq_m_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x half> @llvm.arm.mve.vmaxnma.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vmaxnma.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmaq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x float> @llvm.arm.mve.vmaxnma.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4) # | ret <4 x float> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.vmaxnma.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>) #2 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005573397f957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005573397f6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005573397f9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa96521bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa9652725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa96521ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa965203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055733978f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055733978f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557339773f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557339423176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557339422e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa965204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa9652050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa9652050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557339422d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c (3018 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d9a6d8957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d9a6d86515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d9a6d89cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcefed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcefed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcefed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcefed1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d9a6d1f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d9a6d1f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d9a6d03f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d9a69b3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d9a69b2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcefed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcefed1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcefed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d9a69b2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c (3019 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste32_f32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.sf.vste32.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste32_i32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste32_u32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056332af9857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056332af95515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056332af98cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f12a3d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f12a3d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f12a3d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f12a3d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056332af2e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056332af2e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056332af12f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056332abc2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056332abc1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f12a3d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f12a3d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f12a3d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056332abc1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c (3020 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16mf4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1f16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv2f16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv4f16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv8f16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv16f16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv32f16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv32f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16mf4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1i16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv2i16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv4i16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv8i16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv16i16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_ # | ... # `---data was truncated (10240/35087) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005577d810657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005577d8103515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005577d8106cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f47d2305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f47d235c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f47d2305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f47d22ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005577d809c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005577d809c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005577d8080f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005577d7d30176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005577d7d2fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f47d22eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f47d22ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f47d22ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005577d7d2fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/distributed-thin-lto/backend-skip.ll (3021 of 27911) ******************** TEST 'Clang :: CodeGen/distributed-thin-lto/backend-skip.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 6 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/backend-skip.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/backend-skip.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/backend-skip.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/backend-skip.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/backend-skip.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/backend-skip.ll # | #0 0x0000559b0104c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559b01049515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559b0104ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe73bf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe73bf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe73bf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe73beed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559b00fe224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559b00fe2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559b00fc6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559b00c76176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559b00c75e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe73beeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe73beef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe73beef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559b00c75d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vandq.c (3022 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vandq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vandq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = and <16 x i8> %0, %1 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vandq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = and <8 x i16> %0, %1 # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vandq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = and <4 x i32> %0, %1 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vandq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = bitcast <4 x float> %2 to <4 x i32> # | %4 = and <4 x i32> %1, %3 # | %5 = bitcast <4 x i32> %4 to <4 x float> # | ret <4 x float> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vandq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.and.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.and.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vandq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vandq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vandq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = bitcast <8 x half> %0 to <8 x i16> # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = bitcast <8 x half> %2 to <8 x i16> # | %4 = load i16, ptr %p.addr, align 2 # | %5 = zext i16 %4 to i32 # | %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5) # | %7 = load <8 x half>, ptr %inactive.addr, align 8 # | %8 = bitcast <8 x half> %7 to <8 x i16> # | %9 = call <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8) # | %10 = bitcast <8 x i16> %9 to <8 x half> # | ret <8 x half> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vandq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.and.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vandq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vandq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vandq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = bitcast <4 x float> %2 to <4 x i32> # | %4 = load i16, ptr %p.addr, align 2 # | %5 = zext i16 %4 to i32 # | %6 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %5) # | %7 = call <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x # | ... # `---data was truncated (10240/10901) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055773a25157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055773a24e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055773a251cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe3d5449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe3d54a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe3d5449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe3d5431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055773a1e724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055773a1e7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055773a1cbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557739e7b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557739e7ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe3d5432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe3d54330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe3d54330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557739e7ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c (3023 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056426f76d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056426f76a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056426f76dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc62b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc62b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc62b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc62b31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056426f70324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056426f703096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056426f6e7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056426f397176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056426f396e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc62b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc62b31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc62b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056426f396d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c (3024 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16mf4x6(ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16mf2x6(ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16m1x6(ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16m1x6_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005580fbed957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005580fbed6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005580fbed9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd75ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd75eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd75ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd75ea31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005580fbe6f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005580fbe6f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005580fbe53f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005580fbb03176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005580fbb02e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd75ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd75ea330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd75ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005580fbb02d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c (3025 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005617438f857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005617438f5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005617438f8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8cb1249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8cb12a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8cb1249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8cb1231507 abort ./stdlib/abort.c:85:3 # | #7 0x000056174388e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056174388e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561743872f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561743522176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561743521e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8cb1232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8cb12330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8cb12330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561743521d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c (3026 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv16f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv16f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv32f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv32f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32mf2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv1f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32m1( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv2f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32m2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv4f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv4f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32m4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv8f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv8f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c (3027 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmclr_m_b1(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmclr.nxv64i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmclr.nxv64i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmclr_m_b2(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmclr.nxv32i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmclr.nxv32i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmclr_m_b4(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmclr.nxv16i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmclr.nxv16i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmclr_m_b8(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmclr.nxv8i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmclr.nxv8i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmclr_m_b16(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmclr.nxv4i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmclr.nxv4i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmclr_m_b32(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmclr.nxv2i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmclr.nxv2i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmclr_m_b64(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmclr.nxv1i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmclr.nxv1i1.i64(i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f5ee8b157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f5ee8ae515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f5ee8b1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f022b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f022b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f022b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f022b031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f5ee84724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f5ee847096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f5ee82bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f5ee4db176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f5ee4dae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f022b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f022b0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f022b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f5ee4dad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c (3028 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f64m1x3(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c (3029 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005637b0bfa57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005637b0bf7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005637b0bfacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f339e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f339e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f339e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f339e631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005637b0b9024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005637b0b90096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005637b0b74f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005637b0824176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005637b0823e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f339e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f339e6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f339e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005637b0823d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c (3030 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv2i16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv4i16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv8i16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv16i16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv32i16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i32.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv2i32.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv4i32.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv8i32.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i32.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv16i32.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv16i32.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i64.nxv1i32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , # | ... # `---data was truncated (10240/28571) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cdb5cc257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cdb5cbf515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cdb5cc2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4d14449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4d144a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4d14449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4d14431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cdb5c5824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cdb5c58096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cdb5c3cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cdb58ec176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cdb58ebe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4d14432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4d144330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4d144330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cdb58ebd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c (3031 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff # | ... # `---data was truncated (10240/54702) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b38068e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b38068b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b38068ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc4c8533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc4c858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc4c8533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc4c851b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b38062424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b380624096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b380608f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b3802b8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b3802b7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc4c851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc4c851d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc4c851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b3802b7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c (3032 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf8x5_tum(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c (3033 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | d # | ... # `---data was truncated (10240/95223) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560cf8dbe57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560cf8dbb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560cf8dbecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0844d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0844d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0844d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0844d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560cf8d5424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560cf8d54096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560cf8d38f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560cf89e8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560cf89e7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0844d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0844d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0844d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560cf89e7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c (3034 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | % # | ... # `---data was truncated (10240/47698) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cad96cd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cad96ca515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cad96cdcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f83fa41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f83fa4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f83fa41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f83fa403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cad966324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cad9663096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cad9647f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cad92f7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cad92f6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f83fa404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f83fa4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f83fa4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cad92f6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c (3035 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c (3036 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv1bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv2bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv4bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv8bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv16bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv32bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv32bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.mask.nxv1bf16.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.mask.nxv2bf16.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.mask.nxv4bf16.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.mask.nxv8bf16.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | s # | ... # `---data was truncated (10240/12680) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f29dba957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f29dba6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f29dba9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbda8049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbda80a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbda8049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbda8031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f29db3f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f29db3f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f29db23f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f29d7d3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f29d7d2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbda8032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbda80330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbda80330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f29d7d2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c (3037 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_i64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_i64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_u64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_u64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m1x3_tum( %mask, target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m2x3_tum( %mask, target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, # | ... # `---data was truncated (10240/32133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557961c9d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557961c9a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557961c9dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f13b4849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f13b48a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f13b4849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f13b4831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557961c3324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557961c33096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557961c17f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005579618c7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005579618c6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f13b4832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f13b48330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f13b48330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005579618c6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c (3038 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16m8(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i16.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i16.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c (3039 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_f16mf4x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_f16mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_f16m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_f16m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_i16mf4x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_i16mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_i16m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_i16m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_u16mf4x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_u16mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_ # | ... # `---data was truncated (10240/26936) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d0e86c657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d0e86c3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d0e86c6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7f36c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7f36ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7f36c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7f36c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d0e865c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d0e865c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d0e8640f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d0e82f0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d0e82efe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7f36c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7f36c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7f36c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d0e82efd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminnmq.c (3040 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminnmq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = call <8 x half> @llvm.minnum.v8f16(<8 x half> %0, <8 x half> %1) # | ret <8 x half> %2 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.minnum.v8f16(<8 x half>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = call <4 x float> @llvm.minnum.v4f32(<4 x float> %0, <4 x float> %1) # | ret <4 x float> %2 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x half>, ptr %inactive.addr, align 8 # | %6 = call <8 x half> @llvm.arm.mve.min.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> %5) # | ret <8 x half> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.min.predicated.v8f16.v8i1(<8 x half>, <8 x half>, i32, <8 x i1>, <8 x half>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x float>, ptr %inactive.addr, align 8 # | %6 = call <4 x float> @llvm.arm.mve.min.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.min.predicated.v4f32.v4i1(<4 x float>, <4 x float>, i32, <4 x i1>, <4 x float>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x half> @llvm.arm.mve.min.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> undef) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmq_x_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x float> @llvm.arm.mve.min.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> undef) # | ret <4 x float> %5 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055887173f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055887173c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055887173fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7414649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f74146a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7414649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7414631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005588716d524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005588716d5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005588716b9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558871369176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558871368e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7414632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f74146330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f74146330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558871368d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmulltq.c (3041 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmulltq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulltq_int_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1, i32 1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8>, <16 x i8>, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulltq_int_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmulltq_int_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1, i32 1) # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32>, <4 x i32>, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulltq_poly_p16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulltq_int_m_s8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 0, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulltq_int_m_u16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 1, i32 1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmulltq_int_m_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <2 x i64>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <2 x i64> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3) # | %5 = load <2 x i64>, ptr %inactive.addr, align 8 # | %6 = call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %1, i32 0, i32 1, <2 x i1> %4, <2 x i64> %5) # | ret <2 x i64> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v2i1(<4 x i32>, <4 x i32>, i32, i32, <2 x i1>, <2 x i64>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulltq_poly_m_p8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulltq_int_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 1, i32 1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulltq_int_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 0, i32 1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmulltq_int_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | # | ... # `---data was truncated (10240/11851) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556be689457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556be6891515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556be6894cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc177533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc17758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc177533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc17751b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556be682a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556be682a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556be680ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556be64be176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556be64bde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc17751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc17751d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc17751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556be64bdd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c (3042 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i6 # | ... # `---data was truncated (10240/47604) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055770e48757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055770e484515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055770e487cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f766cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f766cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f766cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f766cf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055770e41d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055770e41d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055770e401f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055770e0b1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055770e0b0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f766cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f766cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f766cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055770e0b0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c (3043 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_i64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_u64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_f64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 6) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_i64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 6) %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_u64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c (3044 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.mask.nxv1f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv1f16.i64(, , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c (3045 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16mf4_tu( %vd, %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv1bf16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv1bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16mf2_tu( %vd, %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv2bf16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv2bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16m1_tu( %vd, %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv4bf16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv4bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16m2_tu( %vd, %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv8bf16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv8bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m4_tu( %vd, %vs2, %vs1, # | ... # `---data was truncated (10240/62087) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f9227a257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f92279f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f9227a2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe124a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe124aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe124a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe124a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f92273824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f922738096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f92271cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f9223cc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f9223cbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe124a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe124a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe124a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f9223cbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c (3046 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16mf4_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16mf4_f32mf2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16mf2_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16mf2_f32m1( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16m1_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16m1_f32m2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16m2_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16m2_f32m4( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.bf16.nxv # | ... # `---data was truncated (10240/51702) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005622c71a557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005622c71a2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005622c71a5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5b69933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5b6998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5b69933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5b6991b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005622c713b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005622c713b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005622c711ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005622c6dcf176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005622c6dcee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5b6991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5b6991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5b6991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005622c6dced81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c (3047 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16mf2_bf16mf4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1bf16.nxv2bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1bf16.nxv2bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m1_bf16mf4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1bf16.nxv4bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1bf16.nxv4bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m1_bf16mf2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2bf16.nxv4bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2bf16.nxv4bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m2_bf16mf4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1bf16.nxv8bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1bf16.nxv8bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m2_bf16mf2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2bf16.nxv8bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2bf16.nxv8bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m2_bf16m1( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv8bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv8bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m4_bf16mf4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m4_bf16mf2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m4_bf16m1( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m4_bf16m2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m8_bf16mf4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m8_bf16mf2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m8_bf16m1( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m8_bf16m2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m8_bf16m4(< # | ... # `---data was truncated (10240/11404) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ce7b1e457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ce7b1e1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ce7b1e4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fddae249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fddae2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fddae249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fddae231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ce7b17a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ce7b17a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ce7b15ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ce7ae0e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ce7ae0de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fddae232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fddae2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fddae2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ce7ae0dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c (3048 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv16f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv1f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv2f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv4f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv8f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c (3049 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_f32mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1f32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_f32m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2f32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_f32m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4f32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_f32m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8f32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_f32m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv16f32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv16f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_i32mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_i32m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_i32m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4i32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_i32m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8i32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_i32m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, p # | ... # `---data was truncated (10240/33198) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055638559157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055638558e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556385591cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f46a8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f46a818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f46a8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f46a811b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055638552724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556385527096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055638550bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005563851bb176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005563851bae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f46a811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f46a811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f46a811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005563851bad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c (3050 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf4x6(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf2x6(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16m1x6(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16m1x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b78926657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b789263515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b789266cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f74d1933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f74d198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f74d1933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f74d191b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b7891fc24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b7891fc096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b7891e0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b788e90176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b788e8fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f74d191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f74d191d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f74d191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b788e8fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c (3051 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005627a600257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005627a5fff515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005627a6002cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f76c081bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f76c08725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f76c081ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f76c0803507 abort ./stdlib/abort.c:85:3 # | #7 0x00005627a5f9824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005627a5f98096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005627a5f7cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005627a5c2c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005627a5c2be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f76c0804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f76c08050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f76c08050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005627a5c2bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c (3052 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_e4m3_e5m2_w4_f8e4m3m8_f8e5m2m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.e4m3.e5m2.i64.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.e4m3.e5m2.i64.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e3cc93057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e3cc92d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e3cc930cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8fac249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8fac2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8fac249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8fac231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e3cc8c624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e3cc8c6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e3cc8aaf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e3cc55a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e3cc559e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8fac232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8fac2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8fac2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e3cc559d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c (3053 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr % # | ... # `---data was truncated (10240/67150) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561adf94857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561adf945515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561adf948cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f71cb049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f71cb0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f71cb049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f71cb031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561adf8de24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561adf8de096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561adf8c2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561adf572176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561adf571e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f71cb032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f71cb0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f71cb0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561adf571d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vldr.c (3054 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vldr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrwq_gather_base_wb_s32(ptr noundef %addr) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | store ptr %addr, ptr %addr.addr, align 4 # | %0 = load ptr, ptr %addr.addr, align 4 # | %1 = load <4 x i32>, ptr %0, align 8 # | %2 = call { <4 x i32>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4i32.v4i32(<4 x i32> %1, i32 80) # | %3 = extractvalue { <4 x i32>, <4 x i32> } %2, 1 # | store <4 x i32> %3, ptr %0, align 8 # | %4 = extractvalue { <4 x i32>, <4 x i32> } %2, 0 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare { <4 x i32>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4i32.v4i32(<4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vldrwq_gather_base_wb_f32(ptr noundef %addr) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | store ptr %addr, ptr %addr.addr, align 4 # | %0 = load ptr, ptr %addr.addr, align 4 # | %1 = load <4 x i32>, ptr %0, align 8 # | %2 = call { <4 x float>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4f32.v4i32(<4 x i32> %1, i32 64) # | %3 = extractvalue { <4 x float>, <4 x i32> } %2, 1 # | store <4 x i32> %3, ptr %0, align 8 # | %4 = extractvalue { <4 x float>, <4 x i32> } %2, 0 # | ret <4 x float> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare { <4 x float>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4f32.v4i32(<4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vldrdq_gather_base_wb_z_u64(ptr noundef %addr, i16 noundef zeroext %p) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store ptr %addr, ptr %addr.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %addr.addr, align 4 # | %1 = load <2 x i64>, ptr %0, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3) # | %5 = call { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v2i64.v2i64.v2i1(<2 x i64> %1, i32 656, <2 x i1> %4) # | %6 = extractvalue { <2 x i64>, <2 x i64> } %5, 1 # | store <2 x i64> %6, ptr %0, align 8 # | %7 = extractvalue { <2 x i64>, <2 x i64> } %5, 0 # | ret <2 x i64> %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v2i64.v2i64.v2i1(<2 x i64>, i32, <2 x i1>) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056047915a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560479157515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056047915acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5b5fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5b5fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5b5fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5b5fd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005604790f024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005604790f0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005604790d4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560478d84176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560478d83e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5b5fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5b5fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5b5fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560478d83d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c (3055 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv16f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv16f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m8_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv32f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv32f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32mf2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv1f32.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv1f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32m1_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv2f32.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv2f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32m2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c (3056 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf8_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf4_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf2_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m1_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m2_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m4_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m8_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u16mf4_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync # | ... # `---data was truncated (10240/62063) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558be145c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558be1459515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558be145ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff9b7533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff9b758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff9b7533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff9b751b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558be13f224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558be13f2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558be13d6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558be1086176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558be1085e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff9b751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff9b751d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff9b751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558be1085d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c (3057 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne # | ... # `---data was truncated (10240/18668) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f70690857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f706905515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f706908cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f95cc649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f95cc6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f95cc649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f95cc631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f70689e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f70689e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f706882f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f706532176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f706531e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f95cc632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f95cc6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f95cc6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f706531d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c (3058 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret < # | ... # `---data was truncated (10240/34430) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555a0a49757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555a0a494515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555a0a497cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fda91933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fda9198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fda91933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fda9191b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555a0a42d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555a0a42d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555a0a411f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555a0a0c1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555a0a0c0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fda9191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fda9191d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fda9191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555a0a0c0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c (3059 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv1i64.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv2i64.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv4i64.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv8i64.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m8_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m1_tumu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call # | ... # `---data was truncated (10240/18217) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e9acc5457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e9acc51515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e9acc54cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0d3c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0d3c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0d3c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0d3c631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e9acbea24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e9acbea096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e9acbcef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e9ac87e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e9ac87de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0d3c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0d3c6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0d3c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e9ac87dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c (3060 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv1bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv2bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv4bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv8bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m4_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv16bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m8_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv32bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(, , bfloat, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d4e8cf857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d4e8cf5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d4e8cf8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb8f9249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb8f92a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb8f9249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb8f9231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d4e8c8e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d4e8c8e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d4e8c72f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d4e8922176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d4e8921e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb8f9232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb8f92330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb8f92330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d4e8921d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c (3061 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563a7315657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563a73153515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563a73156cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0fa7f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0fa7f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0fa7f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0fa7eed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563a730ec24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563a730ec096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563a730d0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563a72d80176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563a72d7fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0fa7eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0fa7eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0fa7eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563a72d7fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c (3062 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv32i16.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz # | ... # `---data was truncated (10240/58675) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b2ef72657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b2ef723515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b2ef726cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faa89d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faa89d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faa89d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faa89d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b2ef6bc24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b2ef6bc096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b2ef6a0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b2ef350176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b2ef34fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007faa89d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faa89d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faa89d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b2ef34fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c (3063 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Fun # | ... # `---data was truncated (10240/40883) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ae9a6f157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ae9a6ee515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ae9a6f1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3e10f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3e10f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3e10f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3e10eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ae9a68724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ae9a687096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ae9a66bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ae9a31b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ae9a31ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3e10eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3e10eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3e10eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ae9a31ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c (3064 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564b9183b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564b91838515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564b9183bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5b54e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5b54ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5b54e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5b54e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564b917d124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564b917d1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564b917b5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564b91465176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564b91464e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5b54e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5b54e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5b54e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564b91464d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c (3065 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv1f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local # | ... # `---data was truncated (10240/51412) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056522f61157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056522f60e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056522f611cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4f6e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4f6e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4f6e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4f6e71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056522f5a724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056522f5a7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056522f58bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056522f23b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056522f23ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4f6e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4f6e71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4f6e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056522f23ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-crc32.c (3066 of 27911) ******************** TEST 'Clang :: CodeGen/arm-crc32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-gnueabi -target-feature +crc -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-gnueabi -target-feature +crc -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8-none-linux-gnueabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32b(i32 noundef %a, i8 noundef signext %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i8, align 1 # | store i32 %a, ptr %a.addr, align 4 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i8, ptr %b.addr, align 1 # | %2 = zext i8 %1 to i32 # | %3 = call i32 @llvm.arm.crc32b(i32 %0, i32 %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.crc32b(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32cb(i32 noundef %a, i8 noundef signext %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i8, align 1 # | store i32 %a, ptr %a.addr, align 4 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i8, ptr %b.addr, align 1 # | %2 = zext i8 %1 to i32 # | %3 = call i32 @llvm.arm.crc32cb(i32 %0, i32 %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.crc32cb(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32h(i32 noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i16, ptr %b.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call i32 @llvm.arm.crc32h(i32 %0, i32 %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.crc32h(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32ch(i32 noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i16, ptr %b.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call i32 @llvm.arm.crc32ch(i32 %0, i32 %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.crc32ch(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32w(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.arm.crc32w(i32 %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.crc32w(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32cw(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.arm.crc32cw(i32 %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.crc32cw(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32d(i32 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i64, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i64, ptr %b.addr, align 8 # | %2 = trunc i64 %1 to i32 # | %3 = lshr i64 %1, 32 # | %4 = trunc i64 %3 to i32 # | %5 = call i32 @llvm.arm.crc32w(i32 %0, i32 %2) # | %6 = call i32 @llvm.arm.crc32w(i32 %5, i32 %4) # | ret i32 %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32cd(i32 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i64, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i64, ptr %b.addr, align 8 # | %2 = trunc i64 %1 to i32 # | %3 = lshr i64 %1, 32 # | %4 = trunc i64 %3 to i32 # | %5 = call i32 @llvm.arm.crc32cw(i32 %0, i32 %2) # | %6 = call i32 @llvm.arm.crc32cw(i32 %5, i32 %4) # | ret i32 %6 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8-a,+crc,-thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1} # | !llvm.ident = !{!2} # | # | !0 = !{i32 1, !"target-abi", !"aapcs-linux"} # | !1 = !{i32 1, !"min_enum_size", i32 4} # | !2 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562d44d3c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562d44d39515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562d44d3ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1008649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f10086a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1008649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1008631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562d44cd224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562d44cd2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562d44cb6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562d44966176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562d44965e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1008632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f10086330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f10086330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562d44965d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c (3067 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1f64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2f64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4f64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8f64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | defi # | ... # `---data was truncated (10240/48385) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005612cd2cd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005612cd2ca515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005612cd2cdcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6d6a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6d6a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6d6a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6d6a31b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005612cd26324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005612cd263096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005612cd247f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005612ccef7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005612ccef6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6d6a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6d6a31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6d6a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005612ccef6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c (3068 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | # | ... # `---data was truncated (10240/12216) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560f3e56c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560f3e569515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560f3e56ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0059c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0059ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0059c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0059c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560f3e50224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560f3e502096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560f3e4e6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560f3e196176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560f3e195e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0059c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0059c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0059c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560f3e195d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c (3069 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c (3070 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_f64m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_i64m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_u64m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_f64m1x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_i64m1x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_u64m1x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005595df87b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005595df878515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005595df87bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007febefb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007febefb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007febefb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007febefb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005595df81124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005595df811096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005595df7f5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005595df4a5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005595df4a4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007febefb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007febefb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007febefb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005595df4a4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c (3071 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_i8mf8x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_i8mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_i8mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_i8m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_u8mf8x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_u8mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_u8mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_u8m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_i8mf8x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, al # | ... # `---data was truncated (10240/21566) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563096a1a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563096a17515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563096a1acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe411e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe411ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe411e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe411e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005630969b024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005630969b0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563096994f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563096644176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563096643e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe411e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe411e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe411e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563096643d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c (3072 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16mf4x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16mf2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16m1x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16m2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16mf4x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16mf2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16m1x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tu # | ... # `---data was truncated (10240/17844) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b1cc95857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b1cc955515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b1cc958cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4fd5649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4fd56a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4fd5649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4fd5631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b1cc8ee24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b1cc8ee096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b1cc8d2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b1cc582176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b1cc581e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4fd5632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4fd56330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4fd56330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b1cc581d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c (3073 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte16_bf16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vlte16.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte16_f16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte16_i16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte16_u16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvfbfmin,+zvfhmin,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfhmin1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005564dd3f757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005564dd3f4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005564dd3f7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc7be449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc7be4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc7be449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc7be431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005564dd38d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005564dd38d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005564dd371f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005564dd021176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005564dd020e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc7be432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc7be4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc7be4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005564dd020d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c (3074 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_f64m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_i64m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_u64m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_f64m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_i64m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_u64m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b602dfc57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b602df9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b602dfccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7342d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7342d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7342d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7342ced507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b602d9224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b602d92096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b602d76f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b602a26176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b602a25e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7342ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7342cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7342cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b602a25d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c (3075 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, a # | ... # `---data was truncated (10240/30276) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005575ea8e757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005575ea8e4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005575ea8e7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb66c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb66c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb66c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb66c631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005575ea87d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005575ea87d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005575ea861f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005575ea511176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005575ea510e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb66c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb66c6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb66c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005575ea510d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c (3076 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056089ca5457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056089ca51515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056089ca54cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa1e2a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa1e2a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa1e2a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa1e2a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000056089c9ea24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056089c9ea096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056089c9cef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056089c67e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056089c67de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa1e2a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa1e2a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa1e2a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056089c67dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c (3077 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_i64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_i64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_u64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_u64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m1x3_tum( %mask, target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", # | ... # `---data was truncated (10240/40860) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056320ff4057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056320ff3d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056320ff40cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1d45d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1d45d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1d45d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1d45d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056320fed624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056320fed6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056320febaf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056320fb6a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056320fb69e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1d45d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1d45d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1d45d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056320fb69d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c (3078 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005615a0f6857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005615a0f65515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005615a0f68cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4f3dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4f3dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4f3dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4f3dc31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005615a0efe24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005615a0efe096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005615a0ee2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005615a0b92176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005615a0b91e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4f3dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4f3dc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4f3dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005615a0b91d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c (3079 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m1_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | # | ... # `---data was truncated (10240/26460) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a57eabc57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a57eab9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a57eabccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd10fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd10fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd10fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd10fb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a57ea5224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a57ea52096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a57ea36f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a57e6e6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a57e6e5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd10fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd10fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd10fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a57e6e5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c (3080 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055caabb0457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055caabb01515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055caabb04cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb00c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb00c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb00c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb00c231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055caaba9a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055caaba9a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055caaba7ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055caab72e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055caab72de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb00c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb00c2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb00c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055caab72dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c (3081 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf8x8_tum( %mas # | ... # `---data was truncated (10240/43111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563a1cc1f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563a1cc1c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563a1cc1fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5ce5b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5ce5b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5ce5b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5ce5b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563a1cbb524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563a1cbb5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563a1cb99f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563a1c849176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563a1c848e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5ce5b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5ce5b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5ce5b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563a1c848d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c (3082 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c (3083 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005598d534c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005598d5349515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005598d534ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1ba5e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1ba5ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1ba5e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1ba5e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005598d52e224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005598d52e2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005598d52c6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005598d4f76176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005598d4f75e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1ba5e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1ba5e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1ba5e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005598d4f75d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c (3084 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf8x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf4x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv16i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv16i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf8x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf4x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c (3085 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_f32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_f32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_i32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_i32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_u32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_u32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_f32mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_f32m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounw # | ... # `---data was truncated (10240/15952) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559a6548f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559a6548c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559a6548fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f871e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f871e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f871e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f871e51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559a6542524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559a65425096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559a65409f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559a650b9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559a650b8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f871e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f871e51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f871e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559a650b8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/attr-counted-by-issue200014.c (3086 of 27911) ******************** TEST 'Clang :: CodeGen/attr-counted-by-issue200014.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 11 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -O0 -Wno-missing-declarations -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c --check-prefix=FRONTEND # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -O0 -Wno-missing-declarations -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | %struct.annotated_flex = type { i64, i8, [0 x i8] } # | # | @gaf = global { i64, i8, [15 x i8] } { i64 10, i8 0, [15 x i8] c"i am very long\00" }, align 8 # | @sink = external global i64, align 8 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @local_fam(i64 noundef %n) #0 { # | entry: # | %n.addr = alloca i64, align 8 # | %af = alloca %struct.annotated_flex, align 8 # | store i64 %n, ptr %n.addr, align 8 # | %count = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 0 # | %0 = load i64, ptr %n.addr, align 8 # | store i64 %0, ptr %count, align 8 # | %induce_padding = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 1 # | store i8 0, ptr %induce_padding, align 8 # | %1 = getelementptr i8, ptr %af, i64 9 # | call void @llvm.memset.p0.i64(ptr align 1 %1, i8 0, i64 7, i1 false) # | %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2 # | %arraydecay = getelementptr inbounds [0 x i8], ptr %fam, i64 0, i64 0 # | %2 = ptrtoint ptr %arraydecay to i64 # | store i64 %2, ptr @sink, align 8 # | %fam1 = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2 # | %arraydecay2 = getelementptr inbounds [0 x i8], ptr %fam1, i64 0, i64 0 # | %counted_by.gep = getelementptr inbounds i8, ptr %af, i64 0 # | %counted_by.load = load i64, ptr %counted_by.gep, align 4 # | %flexible_array_member_size = mul nuw i64 %counted_by.load, 1 # | %3 = icmp sgt i64 %flexible_array_member_size, -1 # | %4 = select i1 %3, i64 %flexible_array_member_size, i64 0 # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.memset.p0.i64(ptr writeonly captures(none), i8, i64, i1 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @local_subscript(i64 noundef %n) #0 { # | entry: # | %n.addr = alloca i64, align 8 # | %af = alloca %struct.annotated_flex, align 8 # | store i64 %n, ptr %n.addr, align 8 # | %count = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 0 # | %0 = load i64, ptr %n.addr, align 8 # | store i64 %0, ptr %count, align 8 # | %induce_padding = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 1 # | store i8 0, ptr %induce_padding, align 8 # | %1 = getelementptr i8, ptr %af, i64 9 # | call void @llvm.memset.p0.i64(ptr align 1 %1, i8 0, i64 7, i1 false) # | %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2 # | %arrayidx = getelementptr inbounds [0 x i8], ptr %fam, i64 0, i64 2 # | %2 = ptrtoint ptr %arrayidx to i64 # | store i64 %2, ptr @sink, align 8 # | %fam1 = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2 # | %arrayidx2 = getelementptr inbounds [0 x i8], ptr %fam1, i64 0, i64 2 # | %counted_by.gep = getelementptr inbounds i8, ptr %af, i64 0 # | %counted_by.load = load i64, ptr %counted_by.gep, align 4 # | %flexible_array_member_size = mul nuw i64 %counted_by.load, 1 # | %result = sub nuw i64 %flexible_array_member_size, 2 # | %3 = icmp sgt i64 %result, -1 # | %4 = and i1 true, %3 # | %5 = select i1 %4, i64 %result, i64 0 # | ret i64 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @local_addrof(i64 noundef %n) #0 { # | entry: # | %n.addr = alloca i64, align 8 # | %af = alloca %struct.annotated_flex, align 8 # | store i64 %n, ptr %n.addr, align 8 # | %count = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 0 # | %0 = load i64, ptr %n.addr, align 8 # | store i64 %0, ptr %count, align 8 # | %induce_padding = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 1 # | store i8 0, ptr %induce_padding, align 8 # | %1 = getelementptr i8, ptr %af, i64 9 # | call void @llvm.memset.p0.i64(ptr align 1 %1, i8 0, i64 7, i1 false) # | %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2 # | %2 = ptrtoint ptr %fam to i64 # | store i64 %2, ptr @sink, align 8 # | %fam1 = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2 # | %3 = call i64 @llvm.objectsize.i64.p0(ptr %fam1, i1 false, i1 true, i1 true) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.objectsize.i64.p0(ptr, i1 immarg, i1 immarg, i1 immarg) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @global_fam() #0 { # | entry: # | %counted_by.load = load i64, ptr @gaf, align 4 # | %flexible_array_member_size = mul nuw i64 %counted_by.load, 1 # | %0 = icmp sgt i64 %flexible_array_member_size, -1 # | %1 = select i1 %0, i64 %flexible_array_member_size, i64 0 # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @global_subscript() #0 { # | entry: # | %counted_by.load = load i64, ptr @gaf, align 4 # | %flexible_array_member_size = mul nuw i64 %counted_by.load, 1 # | %result = sub nuw i64 %flexible_array_member_size, 3 # | %0 = icmp sgt i64 %result, -1 # | %1 = and i1 true, %0 # | %2 = select i1 %1, i64 %result, i64 0 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @global_addrof() #0 { # | entry: # | %0 = call i64 @llvm.objectsize.i64.p0(ptr getelementptr inbounds nuw (i8, ptr @gaf, i64 9), i1 false, i1 true, i1 true) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @ptr_fam(ptr noundef %p) #0 { # | entry: # | %p.addr = alloca ptr, align 8 # | store ptr %p, ptr %p.addr, align 8 # | %0 = load ptr, ptr %p.addr, align 8 # | %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %0, i32 0, i32 2 # | %arraydecay = getelementptr inbounds [0 x i8], ptr %fam, i64 0, i64 0 # | %1 = load ptr, ptr %p.addr, align 8 # | %counted_by.gep = getelementptr inbounds i8, ptr %1, i64 0 # | %counted_by.load = load i64, ptr %counted_by.gep, align 4 # | %flexible_array_member_size = mul nuw i64 %counted_by.load, 1 # | %2 = icmp sgt i64 %flexible_array_member_size, -1 # | %3 = select i1 %2, i64 %flexible_array_member_size, i64 0 # | ret i64 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @ptr_subscript(ptr noundef %p) #0 { # | entry: # | %p.addr = alloca ptr, align 8 # | store ptr %p, ptr %p.addr, align 8 # | %0 = load ptr, ptr %p.addr, align 8 # | %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %0, i32 0, i32 2 # | %arrayidx = getelementptr inbounds [0 x i8], ptr %fam, i64 0, i64 3 # | %1 = load ptr, ptr %p.addr, align 8 # | %counted_by.gep = getelementptr inbounds i8, ptr %1, i64 0 # | %counted_by.load = load i64, ptr %counted_by.gep, align 4 # | %flexible_array_member_size = mul nuw i64 %counted_by.load, 1 # | %result = sub nuw i64 %flexible_array_member_size, 3 # | %2 = icmp sgt i64 %result, -1 # | %3 = and i1 true, %2 # | %4 = select i1 %3, i64 %result, i64 0 # | ret i64 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @ptr_addrof(ptr noundef %p) #0 { # | entry: # | %p.addr = alloca ptr, align 8 # | store ptr %p, ptr %p.addr, align 8 # | %0 = load ptr, ptr %p.addr, align 8 # | %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %0, i32 0, i32 2 # | %1 = call i64 @llvm.objectsize.i64.p0(ptr %fam, i1 false, i1 true, i1 true) # | ret i64 %1 # | } # | # | attributes #0 = { noinline nounwind "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000555d9216c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555d92169515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555d9216ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f617ee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f617eea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f617ee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f617ee31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555d9210224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555d92102096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555d920e6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555d91d96176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555d91d95e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f617ee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f617ee330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f617ee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555d91d95d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c --check-prefix=FRONTEND # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c --check-prefix=FRONTEND # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c (3087 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_f32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_f32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_i32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_i32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_u32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_u32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_f32mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_f32m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vsca # | ... # `---data was truncated (10240/15944) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f5a288c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f5a2889515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f5a288ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f859fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f859fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f859fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f859fe31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f5a282224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f5a2822096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f5a2806f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f5a24b6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f5a24b5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f859fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f859fe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f859fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f5a24b5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c (3088 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load # | ... # `---data was truncated (10240/29062) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fba29dc57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fba29d9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fba29dccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2736c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2736ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2736c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2736c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fba297224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fba2972096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fba2956f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fba2606176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fba2605e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2736c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2736c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2736c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fba2605d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c (3089 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv8bf16.p0.nxv8i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target # | ... # `---data was truncated (10240/10700) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005589bbfdb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005589bbfd8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005589bbfdbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbae181bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbae18725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbae181ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbae1803507 abort ./stdlib/abort.c:85:3 # | #7 0x00005589bbf7124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005589bbf71096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005589bbf55f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005589bbc05176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005589bbc04e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbae1804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbae18050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbae18050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005589bbc04d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c (3090 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf4x6(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf2x6(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16m1x6(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16m1x6_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bc52c7157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bc52c6e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bc52c71cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2719105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f271915c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2719105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f27190ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bc52c0724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bc52c07096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bc52bebf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bc5289b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bc5289ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f27190eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f27190ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f27190ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bc5289ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c (3091 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf4x4_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf2x4_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16m1x4_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16m2x4_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556d57aae57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556d57aab515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556d57aaecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd568c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd568ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd568c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd568c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556d57a4424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556d57a44096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556d57a28f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556d576d8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556d576d7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd568c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd568c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd568c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556d576d7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c (3092 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_e4m3_e4m3_w4_f8e4m3m8_f8e4m3m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564d62c2157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564d62c1e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564d62c21cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8e6ed05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8e6ed5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8e6ed05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8e6eced507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564d62bb724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564d62bb7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564d62b9bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564d6284b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564d6284ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8e6eceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8e6ecef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8e6ecef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564d6284ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqsubq.c (3093 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqsubq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqsubq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %0, <16 x i8> %1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i8> @llvm.usub.sat.v16i8(<16 x i8>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqsubq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %0, <8 x i16> %1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqsubq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %0, <4 x i32> %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x i32> @llvm.usub.sat.v4i32(<4 x i32>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqsubq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.qsub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.qsub.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqsubq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.qsub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.qsub.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqsubq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.qsub.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.qsub.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqsubq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %0, <16 x i8> %.splat) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqsubq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %0, <8 x i16> %.splat) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqsubq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %0, <4 x i32> %.splat) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqsubq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.qsub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqsubq_m_n_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.qsub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, i32 1, <8 x i1> %4, <8 # | ... # `---data was truncated (10240/12015) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564eaed1a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564eaed17515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564eaed1acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6d6bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6d6bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6d6bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6d6bd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564eaecb024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564eaecb0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564eaec94f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564eae944176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564eae943e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6d6bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6d6bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6d6bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564eae943d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/zksed.c (3094 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/zksed.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zksed -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c -check-prefix=RV32ZKSED # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zksed -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sm4ks(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | %2 = call i32 @llvm.riscv.sm4ks(i32 %0, i32 %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sm4ks(i32, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sm4ed(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | %2 = call i32 @llvm.riscv.sm4ed(i32 %0, i32 %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sm4ed(i32, i32, i32 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zksed" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_zksed1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560ac7f9f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560ac7f9c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560ac7f9fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f63fd649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f63fd6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f63fd649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f63fd631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560ac7f3524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560ac7f35096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560ac7f19f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560ac7bc9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560ac7bc8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f63fd632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f63fd6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f63fd6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560ac7bc8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c -check-prefix=RV32ZKSED # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c -check-prefix=RV32ZKSED # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c (3095 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_f32mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_f32m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_i32mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_i32m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_u32mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_u32m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_f32mf2x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_f32m1x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_i32mf2x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_i32m1x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry # | ... # `---data was truncated (10240/14002) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cb619c657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cb619c3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cb619c6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2314733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f231478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2314733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f231471b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cb6195c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cb6195c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cb61940f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cb615f0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cb615efe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f231471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f231471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f231471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cb615efd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c (3096 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv16f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv1f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv2f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv4f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv8f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c (3097 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load # | ... # `---data was truncated (10240/29128) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dfbe59e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055dfbe59b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055dfbe59ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3636449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f36364a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3636449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3636431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dfbe53424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055dfbe534096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055dfbe518f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055dfbe1c8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055dfbe1c7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3636432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f36364330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f36364330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dfbe1c7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c (3098 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf8x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv1i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv1i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf4x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8m1x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8m2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv16i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv16i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_u8mf8x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv1i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_u8mf4x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %ba # | ... # `---data was truncated (10240/15594) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005641b032757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005641b0324515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005641b0327cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3e43933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3e4398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3e43933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3e4391b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005641b02bd24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005641b02bd096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005641b02a1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005641aff51176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005641aff50e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3e4391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3e4391d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3e4391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005641aff50d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c (3099 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f64m1x4(ptr noundef %base, %binde # | ... # `---data was truncated (10240/99754) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564cdf06857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564cdf065515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564cdf068cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb51b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb51b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb51b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb51b11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564cdeffe24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564cdeffe096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564cdefe2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564cdec92176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564cdec91e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb51b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb51b11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb51b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564cdec91d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c (3100 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ab6d42f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ab6d42c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ab6d42fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f403c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f403c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f403c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f403c631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ab6d3c524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ab6d3c5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ab6d3a9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ab6d059176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ab6d058e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f403c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f403c6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f403c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ab6d058d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c (3101 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv2i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv4i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv8i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv16i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv32i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv32i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv64i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv64i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv2i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv4i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv8i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv16i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr # | ... # `---data was truncated (10240/26240) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005567604b057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005567604ad515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005567604b0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fda51049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fda510a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fda51049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fda51031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055676044624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556760446096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055676042af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005567600da176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005567600d9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fda51032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fda510330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fda510330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005567600d9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c (3102 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_i32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_i32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_u32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_u32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32mf2x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedof # | ... # `---data was truncated (10240/40734) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a8b1d2d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a8b1d2a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a8b1d2dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f143d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f143d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f143d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f143d431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a8b1cc324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a8b1cc3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a8b1ca7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a8b1957176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a8b1956e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f143d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f143d4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f143d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a8b1956d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-vls-compare-ops.c (3103 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-compare-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %cmp = icmp eq <32 x i8> %0, %1 # | %sext = sext <32 x i1> %cmp to <32 x i8> # | store <32 x i8> %sext, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv8i8.v32i8( poison, <32 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8i8.v32i8(, <32 x i8>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_i16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i16>, align 8 # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca <16 x i16>, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %b.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store <16 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load <16 x i16>, ptr %b.addr, align 8 # | %cmp = icmp eq <16 x i16> %0, %1 # | %sext = sext <16 x i1> %cmp to <16 x i16> # | store <16 x i16> %sext, ptr %retval, align 8 # | %2 = load <16 x i16>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv4i16.v16i16( poison, <16 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4i16.v16i16(, <16 x i16>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_i32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i32>, align 8 # | %a.addr = alloca <8 x i32>, align 8 # | %b.addr = alloca <8 x i32>, align 8 # | %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %a.coerce, i64 0) # | %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %b.coerce, i64 0) # | store <8 x i32> %a, ptr %a.addr, align 8 # | store <8 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i32>, ptr %b.addr, align 8 # | %cmp = icmp eq <8 x i32> %0, %1 # | %sext = sext <8 x i1> %cmp to <8 x i32> # | store <8 x i32> %sext, ptr %retval, align 8 # | %2 = load <8 x i32>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv2i32.v8i32( poison, <8 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2i32.v8i32(, <8 x i32>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_i64( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <4 x i64>, align 8 # | %a.addr = alloca <4 x i64>, align 8 # | %b.addr = alloca <4 x i64>, align 8 # | %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %a.coerce, i64 0) # | %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %b.coerce, i64 0) # | store <4 x i64> %a, ptr %a.addr, align 8 # | store <4 x i64> %b, ptr %b.addr, align 8 # | %0 = load <4 x i64>, ptr %a.addr, align 8 # | %1 = load <4 x i64>, ptr %b.addr, align 8 # | %cmp = icmp eq <4 x i64> %0, %1 # | %sext = sext <4 x i1> %cmp to <4 x i64> # | store <4 x i64> %sext, ptr %retval, align 8 # | %2 = load <4 x i64>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv1i64.v4i64( poison, <4 x i64> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv1i64.v4i64(, <4 x i64>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_u8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %cmp = icmp eq <32 x i8> %0, %1 # | %sext = sext <32 x i1> %cmp to <32 x i8> # | store <32 x i8> %sext, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv8i8.v32i8( poison, <32 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_u16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i16>, align 8 # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca <16 x i16>, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %b.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store <16 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load <16 x i16>, ptr %b.addr, align 8 # | %cmp = icmp eq <16 x i16> %0, %1 # | %sext = sext <16 x i1> %cmp to <16 x i16> # | store <16 x i16> %sext, ptr %retval, align 8 # | %2 = load <16 x i16>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv4i16.v16i16( poison, <16 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_u32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i32>, align 8 # | %a.addr = alloca <8 x i32>, align 8 # | %b.addr = alloca <8 x i32>, align 8 # | %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %a.coerce, i64 0) # | %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %b.coerce, i64 0) # | store <8 x i32> %a, ptr %a.addr, align 8 # | store <8 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i32>, ptr %b.addr, align 8 # | %cmp = icmp eq <8 x i32> %0, %1 # | %sext = sext <8 x i1> %cmp to <8 x i32> # | store <8 x i32> %sext, ptr %retval, align 8 # | %2 = load <8 x i32>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv2i32.v8i32( poison, <8 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_u64( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <4 x i64>, align 8 # | %a.addr = alloca <4 x i64>, align 8 # | %b.addr = alloca <4 x i64>, align 8 # | %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %a.coerce, i64 0) # | %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %b.coerce, i64 0) # | store <4 x i64> %a, ptr %a.addr, align 8 # | store <4 x i64> %b, ptr %b.addr, align 8 # | %0 = load <4 x i64>, ptr %a.addr, align 8 # | %1 = load <4 x i64>, ptr %b.addr, align 8 # | %cmp = icmp eq <4 x i64> %0, %1 # | %sext = sext <4 x i1> %cmp to <4 x i64> # | store <4 x i64> %sext, ptr %retval, align 8 # | %2 = load <4 x i64>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv1i64.v4i64( poison, <4 x i64> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_f32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i32>, align 8 # | %a.addr = alloca <8 x float>, align 8 # | %b.addr = alloca <8 x float>, align 8 # | %a = call <8 x float> @llvm.vector.extract.v8f32.nxv2f32( %a.coerce, i64 0) # | %b = call <8 x float> # | ... # `---data was truncated (10240/63117) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x000056179ced257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056179cecf515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056179ced2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f964981bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f96498725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f964981ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9649803507 abort ./stdlib/abort.c:85:3 # | #7 0x000056179ce6824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056179ce68096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056179ce4cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056179cafc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056179cafbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9649804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f96498050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f96498050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056179cafbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c (3104 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_f16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_f16mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_f16m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_f16m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_i16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_i16mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_i16m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_i16m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_u16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store tar # | ... # `---data was truncated (10240/30818) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559734e7f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559734e7c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559734e7fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fed3f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fed3f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fed3f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fed3f831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559734e1524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559734e15096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559734df9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559734aa9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559734aa8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fed3f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fed3f8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fed3f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559734aa8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c (3105 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560afe83757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560afe834515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560afe837cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff288d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff288d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff288d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff288d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560afe7cd24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560afe7cd096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560afe7b1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560afe461176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560afe460e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff288d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff288d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff288d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560afe460d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c (3106 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055868c13b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055868c138515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055868c13bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe783f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe783f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe783f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe783f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055868c0d124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055868c0d1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055868c0b5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055868bd65176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055868bd64e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe783f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe783f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe783f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055868bd64d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c (3107 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretur # | ... # `---data was truncated (10240/20190) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fd4566c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fd45669515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fd4566ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffb5cd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffb5cd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffb5cd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffb5cced507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fd4560224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fd45602096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fd455e6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fd45296176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fd45295e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ffb5cceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffb5ccef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffb5ccef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fd45295d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c (3108 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_i64m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_i64m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_u64m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_u64m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560b7bc1557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560b7bc12515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560b7bc15cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9dadf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9dadf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9dadf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9dadf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560b7bbab24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560b7bbab096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560b7bb8ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560b7b83f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560b7b83ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9dadf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9dadf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9dadf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560b7b83ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c (3109 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %v # | ... # `---data was truncated (10240/23064) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b237c7e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b237c7b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b237c7ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa73b849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa73b8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa73b849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa73b831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b237c1424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b237c14096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b237bf8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b2378a8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b2378a7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa73b832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa73b8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa73b8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b2378a7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c (3110 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558af940857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558af9405515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558af9408cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7bb9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7bb9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7bb9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7bb9f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558af939e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558af939e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558af9382f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558af9032176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558af9031e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7bb9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7bb9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7bb9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558af9031d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c (3111 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff # | ... # `---data was truncated (10240/54702) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005587c4c7957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005587c4c76515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005587c4c79cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff6e9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff6e9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff6e9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff6e9b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005587c4c0f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005587c4c0f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005587c4bf3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005587c48a3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005587c48a2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff6e9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff6e9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff6e9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005587c48a2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c (3112 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_u32mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_u32m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_u32m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 # | ... # `---data was truncated (10240/24058) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cba96a557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cba96a2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cba96a5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2336b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2336b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2336b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2336b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cba963b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cba963b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cba961ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cba92cf176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cba92cee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2336b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2336b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2336b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cba92ced81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c (3113 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ec45c4457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ec45c41515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ec45c44cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9357b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9357b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9357b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9357b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ec45bda24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ec45bda096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ec45bbef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ec4586e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ec4586de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9357b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9357b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9357b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ec4586dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c (3114 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64( %1, %2, %0, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64( %1, %2, %0, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64( %1, %2, %0, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, a # | ... # `---data was truncated (10240/43486) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f1ff61657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f1ff613515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f1ff616cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd915333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd91538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd915333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd91531b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f1ff5ac24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f1ff5ac096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f1ff590f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f1ff240176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f1ff23fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd91531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd91531d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd91531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f1ff23fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c (3115 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willr # | ... # `---data was truncated (10240/44361) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f9477e357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f9477e0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f9477e3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb626333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb62638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb626333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb62631b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f94777924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f947779096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f94775df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f94740d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f94740ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb62631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb62631d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb62631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f94740cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c (3116 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0. # | ... # `---data was truncated (10240/87884) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e94426157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e94425e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e944261cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb36741bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb3674725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb36741ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb367403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e9441f724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e9441f7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e9441dbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e943e8b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e943e8ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb367404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb3674050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb3674050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e943e8ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c (3117 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16mf4x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16mf2x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16mf4x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16mf2x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16mf4x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16mf2x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16mf4x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16m1x8_m( %mask, ptr noundef %base, i64 # | ... # `---data was truncated (10240/17523) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b31bc7d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b31bc7a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b31bc7dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2d7aa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2d7aaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2d7aa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2d7aa31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b31bc1324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b31bc13096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b31bbf7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b31b8a7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b31b8a6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2d7aa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2d7aa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2d7aa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b31b8a6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c (3118 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005641aa52f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005641aa52c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005641aa52fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2046649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f20466a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2046649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2046631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005641aa4c524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005641aa4c5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005641aa4a9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005641aa159176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005641aa158e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2046632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f20466330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f20466330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005641aa158d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c (3119 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u64m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u64m1( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv1i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u64m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u64m2( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u64m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u64m4( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u64m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u64m8( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u64m1_m( %mask, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load , ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.mask.nxv1i64.nxv1i64.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u64m1_m( %mask, %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load i64, ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.mask.nxv1i64.i6 # | ... # `---data was truncated (10240/18619) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d9eec8357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d9eec80515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d9eec83cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcb52249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcb522a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcb52249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcb52231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d9eec1924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d9eec19096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d9eebfdf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d9ee8ad176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d9ee8ace93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcb52232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcb522330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcb522330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d9ee8acd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c (3120 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_ffb(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %__a.addr.i = alloca i64, align 8 # | %__b.addr.i = alloca i64, align 8 # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | store i64 %0, ptr %__a.addr.i, align 8 # | store i64 %1, ptr %__b.addr.i, align 8 # | %2 = load i64, ptr %__a.addr.i, align 8 # | %3 = load i64, ptr %__b.addr.i, align 8 # | %4 = call i64 @llvm.riscv.nds.ffb.i64(i64 %2, i64 %3) # | ret i64 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_ffzmism(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %__a.addr.i = alloca i64, align 8 # | %__b.addr.i = alloca i64, align 8 # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | store i64 %0, ptr %__a.addr.i, align 8 # | store i64 %1, ptr %__b.addr.i, align 8 # | %2 = load i64, ptr %__a.addr.i, align 8 # | %3 = load i64, ptr %__b.addr.i, align 8 # | %4 = call i64 @llvm.riscv.nds.ffzmism.i64(i64 %2, i64 %3) # | ret i64 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_ffmism(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %__a.addr.i = alloca i64, align 8 # | %__b.addr.i = alloca i64, align 8 # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | store i64 %0, ptr %__a.addr.i, align 8 # | store i64 %1, ptr %__b.addr.i, align 8 # | %2 = load i64, ptr %__a.addr.i, align 8 # | %3 = load i64, ptr %__b.addr.i, align 8 # | %4 = call i64 @llvm.riscv.nds.ffmism.i64(i64 %2, i64 %3) # | ret i64 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_flmism(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %__a.addr.i = alloca i64, align 8 # | %__b.addr.i = alloca i64, align 8 # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | store i64 %0, ptr %__a.addr.i, align 8 # | store i64 %1, ptr %__b.addr.i, align 8 # | %2 = load i64, ptr %__a.addr.i, align 8 # | %3 = load i64, ptr %__b.addr.i, align 8 # | %4 = call i64 @llvm.riscv.nds.flmism.i64(i64 %2, i64 %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i64 @llvm.riscv.nds.ffb.i64(i64, i64) #1 # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i64 @llvm.riscv.nds.ffzmism.i64(i64, i64) #1 # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i64 @llvm.riscv.nds.ffmism.i64(i64, i64) #1 # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i64 @llvm.riscv.nds.flmism.i64(i64, i64) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xandesperf" } # | attributes #1 = { nounwind speculatable memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_xandesperf5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555cc1a0c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555cc1a09515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555cc1a0ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb66c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb66c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb66c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb66c431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555cc19a224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555cc19a2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555cc1986f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555cc1636176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555cc1635e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb66c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb66c4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb66c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555cc1635d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c (3121 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf8x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf4x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf2x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf8x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf4x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf2x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf8x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf4x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = c # | ... # `---data was truncated (10240/16451) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056554420257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005655441ff515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000565544202cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7250f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7250f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7250f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7250f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056554419824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000565544198096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056554417cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000565543e2c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000565543e2be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7250f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7250f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7250f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565543e2bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c (3122 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", # | ... # `---data was truncated (10240/19492) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056461d30657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056461d303515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056461d306cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6995733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f699578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6995733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f699571b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056461d29c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056461d29c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056461d280f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056461cf30176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056461cf2fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f699571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f699571d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f699571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056461cf2fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c (3123 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_f64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_i64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_u64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563544eff57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563544efc515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563544effcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4e16905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4e1695c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4e16905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4e168ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563544e9524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563544e95096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563544e79f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563544b29176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563544b28e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4e168eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4e168ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4e168ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563544b28d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c (3124 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6), pt # | ... # `---data was truncated (10240/19484) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564de3d9057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564de3d8d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564de3d90cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efca7b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efca7b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efca7b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efca7aed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564de3d2624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564de3d26096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564de3d0af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564de39ba176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564de39b9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efca7aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efca7aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efca7aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564de39b9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c (3125 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e3f4b2b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e3f4b28515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e3f4b2bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f775ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f775ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f775ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f775ad1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e3f4ac124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e3f4ac1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e3f4aa5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e3f4755176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e3f4754e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f775ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f775ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f775ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e3f4754d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c (3126 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c (3127 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf8x7_tum( %mas # | ... # `---data was truncated (10240/43111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ad21d2057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ad21d1d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ad21d20cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa317e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa317ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa317e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa317e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ad21cb624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ad21cb6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ad21c9af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ad2194a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ad21949e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa317e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa317e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa317e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ad21949d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c (3128 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f43719d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f43719a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f43719dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f93d5733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f93d578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f93d5733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f93d571b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f43713324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f437133096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f437117f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f436dc7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f436dc6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f93d571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f93d571d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f93d571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f436dc6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c (3129 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e90ef6257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e90ef5f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e90ef62cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff01681bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff0168725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff01681ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff016803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e90eef824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e90eef8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e90eedcf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e90eb8c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e90eb8be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff016804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff0168050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff0168050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e90eb8bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c (3130 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6), pt # | ... # `---data was truncated (10240/19484) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ac8d59557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ac8d592515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ac8d595cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0137b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0137b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0137b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0137b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ac8d52b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ac8d52b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ac8d50ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ac8d1bf176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ac8d1bee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0137b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0137b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0137b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ac8d1bed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c (3131 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m1x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl # | ... # `---data was truncated (10240/27434) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e5c71f057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e5c71ed515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e5c71f0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f82b5c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f82b5c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f82b5c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f82b5c03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e5c718624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e5c7186096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e5c716af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e5c6e1a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e5c6e19e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f82b5c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f82b5c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f82b5c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e5c6e19d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c (3132 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c (3133 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf8x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv1i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv1i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf4x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8m1x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8m2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv16i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv16i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_u8mf8x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv1i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_u8mf4x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %ba # | ... # `---data was truncated (10240/15594) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fb0984657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fb09843515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fb09846cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6e1f449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6e1f4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6e1f449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6e1f431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fb097dc24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fb097dc096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fb097c0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fb09470176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fb0946fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6e1f432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6e1f4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6e1f4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fb0946fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c (3134 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16mf4x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16mf2x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16mf4x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16mf2x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_u16mf4x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("ri # | ... # `---data was truncated (10240/13634) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e4ae66357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e4ae660515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e4ae663cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1b46849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1b468a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1b46849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1b46831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e4ae5f924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e4ae5f9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e4ae5ddf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e4ae28d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e4ae28ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1b46832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1b468330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1b468330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e4ae28cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c (3135 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv1f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align # | ... # `---data was truncated (10240/29111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005637f5ff857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005637f5ff5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005637f5ff8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbbd2505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbbd255c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbbd2505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbbd24ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005637f5f8e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005637f5f8e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005637f5f72f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005637f5c22176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005637f5c21e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbbd24eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbbd24ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbbd24ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005637f5c21d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c (3136 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561c918a557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561c918a2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561c918a5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4f14e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4f14e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4f14e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4f14e03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561c9183b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561c9183b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561c9181ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561c914cf176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561c914cee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4f14e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4f14e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4f14e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561c914ced81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c (3137 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005598fdbf557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005598fdbf2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005598fdbf5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbabd733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbabd78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbabd733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbabd71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005598fdb8b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005598fdb8b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005598fdb6ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005598fd81f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005598fd81ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbabd71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbabd71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbabd71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005598fd81ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c (3138 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557b5daee57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557b5daeb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557b5daeecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb3d141bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb3d14725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb3d141ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb3d1403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557b5da8424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557b5da84096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557b5da68f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557b5d718176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557b5d717e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb3d1404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb3d14050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb3d14050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557b5d717d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/mozilla-ms-inline-asm.c (3139 of 27911) ******************** TEST 'Clang :: CodeGen/mozilla-ms-inline-asm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c -triple i386-apple-darwin10 -fasm-blocks -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=strip -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c -triple i386-apple-darwin10 -fasm-blocks -emit-llvm -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c" # | target datalayout = "e-m:o-p:32:32-p270:32:32-p271:32:32-p272:64:64-i128:128-f64:32:64-f80:128-n8:16:32-S128" # | target triple = "i386-apple-darwin10" # | # | ; Function Attrs: noinline nounwind optnone # | define void @invoke_copy_to_stack() #0 { # | entry: # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define void @invoke(ptr noundef %that, i32 noundef %methodIndex, i32 noundef %paramCount, ptr noundef %params) #0 { # | entry: # | %that.addr = alloca ptr, align 4 # | %methodIndex.addr = alloca i32, align 4 # | %paramCount.addr = alloca i32, align 4 # | %params.addr = alloca ptr, align 4 # | store ptr %that, ptr %that.addr, align 4 # | store i32 %methodIndex, ptr %methodIndex.addr, align 4 # | store i32 %paramCount, ptr %paramCount.addr, align 4 # | store ptr %params, ptr %params.addr, align 4 # | call void asm sideeffect inteldialect "mov edx,$1\0A\09test edx,edx\0A\09jz L__MSASMLABEL_.${:uid}__noparams\0A\09mov eax,edx\0A\09shl eax,$$3\0A\09sub esp,eax\0A\09mov ecx,esp\0A\09push $0\0A\09call ${2:P}\0A\09L__MSASMLABEL_.${:uid}__noparams:\0A\09mov ecx,$3\0A\09push ecx\0A\09mov edx,[ecx]\0A\09mov eax,$4\0A\09call dword ptr[edx + eax * $$4]\0A\09mov esp,ebp\0A\09pop ebp\0A\09ret", "=*m,*m,*m,*m,*m,~{eax},~{ebp},~{ecx},~{edx},~{flags},~{esp},~{dirflag},~{fpsr},~{flags}"(ptr elementtype(ptr) %params.addr, ptr elementtype(i32) %paramCount.addr, ptr elementtype(void (...)) @invoke_copy_to_stack, ptr elementtype(ptr) %that.addr, ptr elementtype(i32) %methodIndex.addr) #1, !srcloc !2 # | ret void # | } # | # | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+x87" } # | attributes #1 = { nounwind } # | # | !llvm.module.flags = !{!0} # | !llvm.ident = !{!1} # | # | !0 = !{i32 1, !"NumRegisterParameters", i32 0} # | !1 = !{!"clang version 24.0.0"} # | !2 = !{i64 1623} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=strip -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=strip -S # | #0 0x0000556104c7d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556104c7a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556104c7dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa704449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa7044a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa704449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa704431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556104c1324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556104c13096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556104bf7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005561048a7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005561048a6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa704432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa7044330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa7044330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005561048a6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c (3140 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e3d0f3e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e3d0f3b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e3d0f3ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f701121bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f70112725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f701121ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7011203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e3d0ed424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e3d0ed4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e3d0eb8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e3d0b68176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e3d0b67e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7011204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f70112050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f70112050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e3d0b67d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c (3141 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_f16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_f16mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_f16m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_f16m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_i16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_i16mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_i16m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_i16m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_u16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | s # | ... # `---data was truncated (10240/30826) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562c3859457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562c38591515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562c38594cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f25f9449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f25f94a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f25f9449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f25f9431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562c3852a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562c3852a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562c3850ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562c381be176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562c381bde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f25f9432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f25f94330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f25f94330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562c381bdd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c (3142 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005589aaa6057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005589aaa5d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005589aaa60cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb23501bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb2350725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb23501ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb235003507 abort ./stdlib/abort.c:85:3 # | #7 0x00005589aa9f624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005589aa9f6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005589aa9daf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005589aa68a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005589aa689e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb235004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb2350050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb2350050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005589aa689d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c (3143 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_f64m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1f64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_f64m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2f64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_f64m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4f64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_f64m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8f64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_i64m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_i64m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_i64m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_i64m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_u64m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_u64m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_u64m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_u64m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_f64m1_m( %mask, ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca # | ... # `---data was truncated (10240/22898) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005653020c157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005653020be515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005653020c1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f647041bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f64704725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f647041ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6470403507 abort ./stdlib/abort.c:85:3 # | #7 0x000056530205724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000565302057096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056530203bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000565301ceb176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000565301ceae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6470404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f64704050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f64704050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565301cead81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c (3144 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16mf4x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16mf2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m1x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m4x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16mf4x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16mf2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16m1x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | # | ... # `---data was truncated (10240/19083) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005609d84b857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005609d84b5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005609d84b8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f32d0733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f32d078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f32d0733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f32d071b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005609d844e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005609d844e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005609d8432f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005609d80e2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005609d80e1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f32d071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f32d071d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f32d071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005609d80e1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c (3145 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_i8mf8x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_i8mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_i8mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_i8m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_i8m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_u8mf8x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_u8mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_u8mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_u8m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/26713) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559ebe0af57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000559ebe0ac515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000559ebe0afcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcb3b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcb3b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcb3b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcb3b91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559ebe04524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000559ebe045096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000559ebe029f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000559ebdcd9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000559ebdcd8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcb3b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcb3b91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcb3b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559ebdcd8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c (3146 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_u32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | ... # `---data was truncated (10240/60691) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cce8b7857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055cce8b75515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055cce8b78cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd1fa649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd1fa6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd1fa649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd1fa631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cce8b0e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055cce8b0e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055cce8af2f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055cce87a2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055cce87a1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd1fa632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd1fa6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd1fa6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cce87a1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-neon-numeric-maxmin.c (3147 of 27911) ******************** TEST 'Clang :: CodeGen/arm-neon-numeric-maxmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8-unknown-linux-gnueabihf" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vmaxnm_f32(<2 x float> noundef %a, <2 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vmaxnm_v.i = bitcast <8 x i8> %2 to <2 x float> # | %vmaxnm_v1.i = bitcast <8 x i8> %3 to <2 x float> # | %vmaxnm_v2.i = call <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float> %vmaxnm_v.i, <2 x float> %vmaxnm_v1.i) # | %vmaxnm_v3.i = bitcast <2 x float> %vmaxnm_v2.i to <8 x i8> # | store <8 x i8> %vmaxnm_v3.i, ptr %ref.tmp.i, align 8 # | %4 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %4, ptr %__ret.i, align 8 # | %5 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vmaxnmq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__p1.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %vmaxnmq_v.i = bitcast <16 x i8> %2 to <4 x float> # | %vmaxnmq_v1.i = bitcast <16 x i8> %3 to <4 x float> # | %vmaxnmq_v2.i = call <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float> %vmaxnmq_v.i, <4 x float> %vmaxnmq_v1.i) # | %vmaxnmq_v3.i = bitcast <4 x float> %vmaxnmq_v2.i to <16 x i8> # | store <16 x i8> %vmaxnmq_v3.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %4, ptr %__ret.i, align 8 # | %5 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vminnm_f32(<2 x float> noundef %a, <2 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vminnm_v.i = bitcast <8 x i8> %2 to <2 x float> # | %vminnm_v1.i = bitcast <8 x i8> %3 to <2 x float> # | %vminnm_v2.i = call <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float> %vminnm_v.i, <2 x float> %vminnm_v1.i) # | %vminnm_v3.i = bitcast <2 x float> %vminnm_v2.i to <8 x i8> # | store <8 x i8> %vminnm_v3.i, ptr %ref.tmp.i, align 8 # | %4 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %4, ptr %__ret.i, align 8 # | %5 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vminnmq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__p1.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %vminnmq_v.i = bitcast <16 x i8> %2 to <4 x float> # | %vminnmq_v1.i = bitcast <16 x i8> %3 to <4 x float> # | %vminnmq_v2.i = call <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float> %vminnmq_v.i, <4 x float> %vminnmq_v1.i) # | %vminnmq_v3.i = bitcast <4 x float> %vminnmq_v2.i to <16 x i8> # | store <16 x i8> %vminnmq_v3.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %4, ptr %__ret.i, align 8 # | %5 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float>, <2 x float>) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float>, <4 x float>) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float>, <2 x float>) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float>, <4 x float>) #1 # | # | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a57" "target-features"="+aes,+armv8-a,+crc,+d32,+dsp,+fp-armv8,+fp-armv8d16,+fp-armv8d16sp,+fp-armv8sp,+fp16,+fp64,+hwdiv,+hwdiv-arm,+neon,+sha2,+thumb-mode,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp,+vfp4,+vfp4d16,+vfp4d16sp,+vfp4sp" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1} # | !llvm.ident = !{!2} # | # | !0 = !{i32 1, !"target-abi", !"aapcs-linux"} # | !1 = !{i32 1, !"min_enum_size", i32 4} # | !2 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055c29167c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c291679515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c29167ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbb15133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbb1518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbb15133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbb1511b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c29161224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c291612096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c2915f6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c2912a6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c2912a5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbb1511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbb1511d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbb1511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c2912a5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c (3148 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056351479557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563514792515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563514795cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe0c9649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe0c96a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe0c9649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe0c9631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056351472b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056351472b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056351470ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005635143bf176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005635143bee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe0c9632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe0c96330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe0c96330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005635143bed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c (3149 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16mf4_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16mf4_f32mf2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16mf2_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16mf2_f32m1( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16m1_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16m1_f32m2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16m2_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16m2_f32m4( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac # | ... # `---data was truncated (10240/51796) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560dde47357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560dde470515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560dde473cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f831fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f831fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f831fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f831fd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560dde40924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560dde409096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560dde3edf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560dde09d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560dde09ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f831fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f831fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f831fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560dde09cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c (3150 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf8_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf4_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf2_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m1_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m2_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m4_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m8_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u16mf4_u32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv2i # | ... # `---data was truncated (10240/51303) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560fcc80e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560fcc80b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560fcc80ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fac12049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fac120a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fac12049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fac12031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560fcc7a424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560fcc7a4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560fcc788f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560fcc438176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560fcc437e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fac12032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fac120330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fac120330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560fcc437d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/thinlto_embed_bitcode.ll (3151 of 27911) ******************** TEST 'Clang :: CodeGen/thinlto_embed_bitcode.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 6 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/Inputs/start-lib1.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_embed_bitcode.ll.tmp1.bc # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/Inputs/start-lib1.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_embed_bitcode.ll.tmp1.bc # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/Inputs/start-lib1.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_embed_bitcode.ll.tmp1.bc # | #0 0x00005596fbb8e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005596fbb8b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005596fbb8ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc09e21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc09e2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc09e21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc09e203507 abort ./stdlib/abort.c:85:3 # | #7 0x00005596fbb2424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005596fbb24096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005596fbb08f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005596fb7b8176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005596fb7b7e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc09e204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc09e2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc09e2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005596fb7b7d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c (3152 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557059a1057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557059a0d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557059a10cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2fa7133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2fa718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2fa7133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2fa711b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005570599a624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005570599a6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055705998af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055705963a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557059639e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2fa711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2fa711d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2fa711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557059639d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c (3153 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560fa4eff57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560fa4efc515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560fa4effcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1008a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1008aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1008a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1008a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560fa4e9524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560fa4e95096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560fa4e79f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560fa4b29176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560fa4b28e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1008a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1008a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1008a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560fa4b28d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c (3154 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("ri # | ... # `---data was truncated (10240/47480) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005579f4f8b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005579f4f88515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005579f4f8bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f94cca1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f94cca725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f94cca1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f94cca03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005579f4f2124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005579f4f21096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005579f4f05f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005579f4bb5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005579f4bb4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f94cca04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f94cca050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f94cca050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005579f4bb4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c (3155 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory( # | ... # `---data was truncated (10240/40661) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f74997657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f749973515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f749976cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f53bbc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f53bbc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f53bbc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f53bbc03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f74990c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f74990c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f7498f0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f7495a0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f74959fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f53bbc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f53bbc050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f53bbc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f74959fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c (3156 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_u16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_u16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c (3157 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16mf4(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16mf2(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m1(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m2(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m4(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m8(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv32bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv32bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16mf4_m( %vm, ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.mask.nxv1bf16.p0.i64( %2, ptr %1, %0, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.mask.nxv1bf16.p0.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16mf2_m( %vm, ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.mask.nxv2bf16.p0.i64( %2, ptr %1, %0, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.mask.nxv2bf16.p0.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m1_m( %vm, ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.mask.nxv4bf16.p0.i64( %2, ptr %1, %0, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.mask.nxv4bf16.p0.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m2_m( %vm, ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.mask.nxv8bf16.p0.i64( %2, ptr %1, %0, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.mask.nxv8bf16.p0.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m4_m( %vm, ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store # | ... # `---data was truncated (10240/12644) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556803ea057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556803e9d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556803ea0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f89d1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f89d1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f89d1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f89d1d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556803e3624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556803e36096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556803e1af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556803aca176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556803ac9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f89d1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f89d1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f89d1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556803ac9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c (3158 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_f64m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_i64m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_u64m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056120d5e457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056120d5e1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056120d5e4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4709849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f47098a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4709849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4709831507 abort ./stdlib/abort.c:85:3 # | #7 0x000056120d57a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056120d57a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056120d55ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056120d20e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056120d20de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4709832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f47098330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f47098330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056120d20dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c (3159 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d3ebff957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d3ebff6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d3ebff9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbca3533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbca358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbca3533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbca351b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d3ebf8f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d3ebf8f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d3ebf73f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d3ebc23176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d3ebc22e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbca351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbca351d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbca351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d3ebc22d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c (3160 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16mf4(half noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load half, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv1f16.i64( poison, half %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv1f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16mf2(half noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load half, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv2f16.i64( poison, half %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv2f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m1(half noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load half, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv4f16.i64( poison, half %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv4f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m2(half noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load half, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv8f16.i64( poison, half %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv8f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m4(half noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load half, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv16f16.i64( poison, half %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv16f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m8(half noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load half, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv32f16.i64( poison, half %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv32f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32mf2(float noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load float, ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv1f32.i64( poison, float %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv1f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m1(float noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load float, ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv2f32.i64( poison, float %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv2f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m2(float noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load float, ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv4f32.i64( poison, float %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv4f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m4(float noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load float, ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv8f32.i64( poison, float %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv8f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m8(float noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load float, ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv16f32.i64( poison, float %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv16f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f64m1(double noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca double, align 8 # | %vl.addr = alloca i64, align 8 # | store double %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load double, ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv1f64.i64( poison, double %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv1f64.i64(, double, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f64m2(double noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca double, align 8 # | %vl.addr = alloca i64, align 8 # | store double %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load double, ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv2f64.i64( poison, double %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv2f64.i64(, double, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f64m4(double noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca double, align 8 # | %vl.addr = alloca i64, align 8 # | store double %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load double, ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv4f64.i64( poison, double %0, i64 %1) # | # | ... # `---data was truncated (10240/30849) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005603cbdf257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005603cbdef515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005603cbdf2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff9b1a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff9b1a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff9b1a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff9b1a03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005603cbd8824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005603cbd88096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005603cbd6cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005603cba1c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005603cba1be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff9b1a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff9b1a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff9b1a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005603cba1bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c (3161 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16mf4x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16mf2x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16m1x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16m2x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16m1x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16m2x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca targ # | ... # `---data was truncated (10240/11920) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fc4b99257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fc4b98f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fc4b992cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3294a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3294aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3294a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3294a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fc4b92824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fc4b928096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fc4b90cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fc4b5bc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fc4b5bbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3294a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3294a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3294a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fc4b5bbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c (3162 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e602e0c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e602e09515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e602e0ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe0c8905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe0c895c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe0c8905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe0c88ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e602da224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e602da2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e602d86f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e602a36176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e602a35e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe0c88eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe0c88ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe0c88ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e602a35d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c (3163 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005600bb4b257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005600bb4af515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005600bb4b2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcb39e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcb39ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcb39e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcb39e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005600bb44824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005600bb448096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005600bb42cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005600bb0dc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005600bb0dbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcb39e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcb39e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcb39e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005600bb0dbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c (3164 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_f16mf4x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_f16mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_f16m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_i16mf4x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_i16mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_i16m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_u16mf4x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_u16mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_u16m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_f16mf4x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsse # | ... # `---data was truncated (10240/20441) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556ec198c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556ec1989515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556ec198ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff9d4d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff9d4d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff9d4d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff9d4ced507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556ec192224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556ec1922096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556ec1906f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556ec15b6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556ec15b5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff9d4ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff9d4cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff9d4cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556ec15b5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c (3165 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_f64m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_i64m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_u64m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_f64m1x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_i64m1x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_u64m1x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b13f6ab57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b13f6a8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b13f6abcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fea8d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fea8d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fea8d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fea8d71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b13f64124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b13f641096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b13f625f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b13f2d5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b13f2d4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fea8d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fea8d71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fea8d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b13f2d4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/AArch64/neon/fullfp16.c (3166 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon/fullfp16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c --check-prefixes=ALL,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vaddh_f16(half noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %__s1 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | store half %b, ptr %b.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %b.addr, align 2 # | store half %1, ptr %__s1, align 2 # | %2 = load half, ptr %__s0, align 2 # | %3 = load half, ptr %__s1, align 2 # | %vaddh = fadd half %2, %3 # | store half %vaddh, ptr %ref.tmp, align 2 # | %4 = load half, ptr %ref.tmp, align 2 # | store half %4, ptr %__ret, align 2 # | %5 = load half, ptr %__ret, align 2 # | store half %5, ptr %tmp, align 2 # | %6 = load half, ptr %tmp, align 2 # | ret half %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vsubh_f16(half noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %__s1 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | store half %b, ptr %b.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %b.addr, align 2 # | store half %1, ptr %__s1, align 2 # | %2 = load half, ptr %__s0, align 2 # | %3 = load half, ptr %__s1, align 2 # | %vsubh = fsub half %2, %3 # | store half %vsubh, ptr %ref.tmp, align 2 # | %4 = load half, ptr %ref.tmp, align 2 # | store half %4, ptr %__ret, align 2 # | %5 = load half, ptr %__ret, align 2 # | store half %5, ptr %tmp, align 2 # | %6 = load half, ptr %tmp, align 2 # | ret half %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vmulh_f16(half noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %__s1 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | store half %b, ptr %b.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %b.addr, align 2 # | store half %1, ptr %__s1, align 2 # | %2 = load half, ptr %__s0, align 2 # | %3 = load half, ptr %__s1, align 2 # | %vmulh = fmul half %2, %3 # | store half %vmulh, ptr %ref.tmp, align 2 # | %4 = load half, ptr %ref.tmp, align 2 # | store half %4, ptr %__ret, align 2 # | %5 = load half, ptr %__ret, align 2 # | store half %5, ptr %tmp, align 2 # | %6 = load half, ptr %tmp, align 2 # | ret half %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vdivh_f16(half noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %__s1 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | store half %b, ptr %b.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %b.addr, align 2 # | store half %1, ptr %__s1, align 2 # | %2 = load half, ptr %__s0, align 2 # | %3 = load half, ptr %__s1, align 2 # | %vdivh = fdiv half %2, %3 # | store half %vdivh, ptr %ref.tmp, align 2 # | %4 = load half, ptr %ref.tmp, align 2 # | store half %4, ptr %__ret, align 2 # | %5 = load half, ptr %__ret, align 2 # | store half %5, ptr %tmp, align 2 # | %6 = load half, ptr %tmp, align 2 # | ret half %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vmaxh_f16(half noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %__s1 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | store half %b, ptr %b.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %b.addr, align 2 # | store half %1, ptr %__s1, align 2 # | %2 = load half, ptr %__s0, align 2 # | %3 = load half, ptr %__s1, align 2 # | %vmax = call half @llvm.aarch64.neon.fmax.f16(half %2, half %3) # | store half %vmax, ptr %ref.tmp, align 2 # | %4 = load half, ptr %ref.tmp, align 2 # | store half %4, ptr %__ret, align 2 # | %5 = load half, ptr %__ret, align 2 # | store half %5, ptr %tmp, align 2 # | %6 = load half, ptr %tmp, align 2 # | ret half %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.aarch64.neon.fmax.f16(half, half) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vmaxnmh_f16(half noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %__s1 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | store half %b, ptr %b.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %b.addr, align 2 # | store half %1, ptr %__s1, align 2 # | %2 = load half, ptr %__s0, align 2 # | %3 = load half, ptr %__s1, align 2 # | %vmaxnm = call half @llvm.aarch64.neon.fmaxnm.f16(half %2, half %3) # | store half %vmaxnm, ptr %ref.tmp, align 2 # | %4 = load half, ptr %ref.tmp, align 2 # | store half %4, ptr %__ret, align 2 # | %5 = load half, ptr %__ret, align 2 # | store half %5, ptr %tmp, align 2 # | %6 = load half, ptr %tmp, align 2 # | ret half %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.aarch64.neon.fmaxnm.f16(half, half) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vminh_f16(half noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %__s1 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | store half %b, ptr %b.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %b.addr, align 2 # | store half %1, ptr %__s1, align 2 # | %2 = load half, ptr %__s0, align 2 # | %3 = load half, ptr %__s1, align 2 # | %vmin = call half @llvm.aarch64.neon.fmin.f16(half %2, half %3) # | store half %vmin, ptr %ref.tmp, align 2 # | %4 = load half, ptr %ref.tmp, align 2 # | store half %4, ptr %__ret, align 2 # | %5 = load half, ptr %__ret, align 2 # | store half %5, ptr %tmp, align 2 # | %6 = load half, ptr %tmp, align 2 # | ret half %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.aarch64.neon.fmin.f16(half, half) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vminnmh_f16(half noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %__s1 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | store half %b, ptr %b.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %b.addr, align 2 # | store half %1, ptr %__s1, align 2 # | %2 = load half, ptr %__s0, align 2 # | %3 = load half, ptr %__s1, align 2 # | %vminnm = call half @llvm.aarch64.neon.fminnm.f16(half %2, half %3) # | store half %vminnm, ptr %ref.tmp, align 2 # | %4 = load half, ptr %ref.tmp, align 2 # | store half %4, ptr %__ret, align 2 # | %5 = load half, ptr %__ret, align 2 # | store half %5, ptr %tmp, align 2 # | %6 = load half, ptr %tmp, align 2 # | ret half %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.aarch64.neon.fminnm.f16(half, half) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vceqzh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %2 = fcmp oeq half %1, 0.000000e+00 # | %vceqz = sext i1 %2 to i16 # | store i16 %vceqz, ptr %ref.tmp, align 2 # | %3 = load i16, ptr %ref.tmp, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | ret i16 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vabsh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %vabs = call half @llvm.fabs.f16(half %1) # | store half %vabs, ptr %ref.tmp, align 2 # | %2 = load half, ptr %ref.tmp, align 2 # | store half %2, ptr %__ret, align 2 # | %3 = load half, ptr %__ret, align 2 # | store half %3, ptr %tmp, align 2 # | %4 = load half, ptr %tmp, align 2 # | ret half %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare half @llvm.fabs.f16(half) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vabdh_f16(half noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %__s1 = all # | ... # `---data was truncated (10240/27802) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056398545157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056398544e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563985451cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f40f221bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f40f22725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f40f221ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f40f2203507 abort ./stdlib/abort.c:85:3 # | #7 0x00005639853e724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005639853e7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005639853cbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056398507b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056398507ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f40f2204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f40f22050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f40f22050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056398507ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c --check-prefixes=ALL,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c --check-prefixes=ALL,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c (3167 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 6) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 6) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("risc # | ... # `---data was truncated (10240/21103) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555956da157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555956d9e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555956da1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2d9b105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2d9b15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2d9b105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2d9b0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555956d3724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555956d37096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555956d1bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005559569cb176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005559569cae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2d9b0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2d9b0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2d9b0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005559569cad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c (3168 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16m1x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b1a0d0357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b1a0d00515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b1a0d03cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f73a5533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f73a558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f73a5533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f73a551b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b1a0c9924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b1a0c99096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b1a0c7df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b1a092d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b1a092ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f73a551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f73a551d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f73a551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b1a092cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c (3169 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055661d62357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055661d620515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055661d623cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe968a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe968aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe968a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe968a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055661d5b924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055661d5b9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055661d59df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055661d24d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055661d24ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe968a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe968a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe968a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055661d24cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c (3170 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_i32mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_i32m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_u32mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_u32m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_i32mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_i32m1x8_m( %mask, ptr noundef % # | ... # `---data was truncated (10240/14001) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e7d614a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e7d6147515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e7d614acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6f4821bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6f482725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6f4821ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6f48203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e7d60e024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e7d60e0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e7d60c4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e7d5d74176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e7d5d73e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6f48204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6f482050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6f482050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e7d5d73d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c (3171 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32mf2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m1( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m4( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m8( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32mf2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m1_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Functio # | ... # `---data was truncated (10240/13657) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c5bc75f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c5bc75c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c5bc75fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4cf4e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4cf4ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4cf4e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4cf4e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c5bc6f524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c5bc6f5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c5bc6d9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c5bc389176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c5bc388e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4cf4e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4cf4e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4cf4e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c5bc388d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c (3172 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m1x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m2x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005631a692d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005631a692a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005631a692dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa114933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa11498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa114933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa11491b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005631a68c324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005631a68c3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005631a68a7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005631a6557176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005631a6556e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa11491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa11491d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa11491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005631a6556d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c (3173 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32mf2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv1f32.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1f32.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m1_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv2f32.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2f32.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv4f32.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv4f32.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv8f32.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv8f32.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv16f32.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv16f32.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32mf2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv1i32.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1i32.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m1_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv2i32.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2i32.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv4i32.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv4i32.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstrid # | ... # `---data was truncated (10240/17118) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d169e2c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d169e29515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d169e2ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007eff86e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007eff86ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007eff86e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007eff86e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d169dc224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d169dc2096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d169da6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d169a56176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d169a55e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007eff86e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007eff86e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007eff86e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d169a55d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c (3174 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv64i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv64i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv32i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv32i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv16i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv16i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv8i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv8i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv4i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv4i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv2i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv2i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv1i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv1i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsif.mask.nxv64i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsif.mask.nxv32i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsif.mask.nxv16i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsif.mask.nxv8i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b16_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsif.mask.nxv4i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback n # | ... # `---data was truncated (10240/13031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dd0d93957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055dd0d936515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055dd0d939cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f25b4133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f25b418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f25b4133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f25b411b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dd0d8cf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055dd0d8cf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055dd0d8b3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055dd0d563176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055dd0d562e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f25b411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f25b411d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f25b411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dd0d562d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c (3175 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3 # | ... # `---data was truncated (10240/64366) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005601e2ba657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005601e2ba3515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005601e2ba6cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f385ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f385ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f385ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f385ef1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005601e2b3c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005601e2b3c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005601e2b20f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005601e27d0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005601e27cfe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f385ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f385ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f385ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005601e27cfd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c (3176 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret < # | ... # `---data was truncated (10240/34430) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005601025d557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005601025d2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005601025d5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4c37505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4c3755c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4c37505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4c374ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056010256b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056010256b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056010254ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005601021ff176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005601021fee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4c374eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4c374ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4c374ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005601021fed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c (3177 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005582fac7657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005582fac73515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005582fac76cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f54b0049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f54b00a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f54b0049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f54b0031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005582fac0c24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005582fac0c096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005582fabf0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005582fa8a0176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005582fa89fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f54b0032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f54b00330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f54b00330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005582fa89fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c (3178 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_f32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_f32m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_f32m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_f32m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_i32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_i32m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_i32m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_i32m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_u32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | ... # `---data was truncated (10240/30866) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557d540ab57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557d540a8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557d540abcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8e7d705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8e7d75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8e7d705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8e7d6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557d5404124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557d54041096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557d54025f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557d53cd5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557d53cd4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8e7d6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8e7d6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8e7d6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557d53cd4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c (3179 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16mf4_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16mf4_f32mf2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16mf2_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16mf2_f32m1( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16m1_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16m1_f32m2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16m2_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16m2_f32m4( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.bf16.nxv8bf16.i6 # | ... # `---data was truncated (10240/51694) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005618d53b557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005618d53b2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005618d53b5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5499b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5499b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5499b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5499b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005618d534b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005618d534b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005618d532ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005618d4fdf176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005618d4fdee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5499b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5499b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5499b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005618d4fded81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c (3180 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounw # | ... # `---data was truncated (10240/12658) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005580555db57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005580555d8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005580555dbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe2a7f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe2a7f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe2a7f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe2a7eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055805557124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558055571096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558055555f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558055205176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558055204e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe2a7eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe2a7eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe2a7eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558055204d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c (3181 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16mf4x2(ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16mf2x2(ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16m1x2(ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16m2x2(ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16m4x2(ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16m1x2_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16m2x2_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , al # | ... # `---data was truncated (10240/13263) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eccffc257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055eccffbf515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055eccffc2cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe7af105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe7af15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe7af105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe7af0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eccff5824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055eccff58096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055eccff3cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055eccfbec176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055eccfbebe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe7af0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe7af0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe7af0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eccfbebd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c (3182 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8mf8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8mf4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv32i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv64i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8mf8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8mf4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv32i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | # | ... # `---data was truncated (10240/25279) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bc42aa557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bc42aa2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bc42aa5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa62101bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa6210725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa62101ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa621003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bc42a3b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bc42a3b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bc42a1ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bc426cf176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bc426cee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa621004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa6210050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa6210050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bc426ced81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c (3183 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf2 # | ... # `---data was truncated (10240/54694) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e3fc4fb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e3fc4f8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e3fc4fbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fae04e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fae04ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fae04e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fae04e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e3fc49124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e3fc491096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e3fc475f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e3fc125176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e3fc124e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fae04e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fae04e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fae04e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e3fc124d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c (3184 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_f64m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_i64m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_u64m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_f64m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_i64m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_u64m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560f6250357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560f62500515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560f62503cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd724933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd72498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd724933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd72491b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560f6249924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560f62499096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560f6247df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560f6212d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560f6212ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd72491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd72491d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd72491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560f6212cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c (3185 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_u16mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_u16mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_u16m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, pt # | ... # `---data was truncated (10240/24016) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005641134dd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005641134da515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005641134ddcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f50f9649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f50f96a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f50f9649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f50f9631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056411347324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564113473096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564113457f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564113107176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564113106e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f50f9632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f50f96330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f50f96330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564113106d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c (3186 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte64_f64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vlte64.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte64_i64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte64_u64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f90dbb757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f90dbb4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f90dbb7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f00f6933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f00f698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f00f6933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f00f691b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f90db4d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f90db4d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f90db31f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f90d7e1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f90d7e0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f00f691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f00f691d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f00f691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f90d7e0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c (3187 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_f32mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_f32m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_f32m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_f32m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_i32mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_i32m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_i32m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_i32m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_u32mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_u32m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | # | ... # `---data was truncated (10240/26984) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005628ebd7c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005628ebd79515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005628ebd7ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f71bc249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f71bc2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f71bc249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f71bc231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005628ebd1224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005628ebd12096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005628ebcf6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005628eb9a6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005628eb9a5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f71bc232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f71bc2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f71bc2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005628eb9a5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c (3188 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willr # | ... # `---data was truncated (10240/44361) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b5353b457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b5353b1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b5353b4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6cffc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6cffca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6cffc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6cffc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b53534a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b53534a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b53532ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b534fde176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b534fdde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6cffc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6cffc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6cffc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b534fddd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c (3189 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none # | ... # `---data was truncated (10240/61673) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005613d39f457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005613d39f1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005613d39f4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7d57b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7d57b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7d57b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7d57b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005613d398a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005613d398a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005613d396ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005613d361e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005613d361de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7d57b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7d57b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7d57b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005613d361dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c (3190 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16mf4x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16mf2x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16m1x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16m1x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e9404cb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e9404c8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e9404cbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efddf249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efddf2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efddf249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efddf231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e94046124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e940461096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e940445f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e9400f5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e9400f4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efddf232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efddf2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efddf2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e9400f4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c (3191 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055addc05d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055addc05a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055addc05dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbb0da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbb0daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbb0da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbb0da31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055addbff324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055addbff3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055addbfd7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055addbc87176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055addbc86e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbb0da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbb0da330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbb0da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055addbc86d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c (3192 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005596524f557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005596524f2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005596524f5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6254f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6254f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6254f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6254f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055965248b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055965248b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055965246ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055965211f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055965211ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6254f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6254f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6254f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055965211ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c (3193 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c (3194 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple # | ... # `---data was truncated (10240/31938) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562c01e6057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562c01e5d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562c01e60cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffa29105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffa2915c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffa29105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffa290ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562c01df624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562c01df6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562c01ddaf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562c01a8a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562c01a89e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ffa290eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffa290ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffa290ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562c01a89d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c (3195 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16m8(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i16.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i16.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c (3196 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e0cbe1757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e0cbe14515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e0cbe17cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1e96c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1e96c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1e96c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1e96c03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e0cbdad24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e0cbdad096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e0cbd91f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e0cba41176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e0cba40e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1e96c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1e96c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1e96c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e0cba40d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c (3197 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_f32mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1f32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_f32m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2f32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_f32m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4f32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_f32m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8f32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_f32m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16f32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_i32mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_i32m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_i32m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_i32m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_i32m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_u32mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_u32m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i32.p0.i64( %1, # | ... # `---data was truncated (10240/28354) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dede6cd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055dede6ca515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055dede6cdcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbc64849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbc648a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbc64849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbc64831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dede66324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055dede663096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055dede647f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055dede2f7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055dede2f6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbc64832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbc648330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbc648330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dede2f6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/packed-structure.c (3198 of 27911) ******************** TEST 'Clang :: CodeGen/packed-structure.c' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/packed-structure.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=strip -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/packed-structure.c.tmp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/packed-structure.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/packed-structure.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/packed-structure.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64" # | # | %struct.s0 = type { i32, i32 } # | %struct.s1 = type { i32, i32 } # | %struct.s2 = type { i32, i32 } # | %struct.s3 = type <{ i16, i32, [10 x i8] }> # | # | @s0_align_x = global i32 4, align 4 # | @s0_align_y = global i32 1, align 4 # | @s0_align = global i32 4, align 4 # | @s1_align_x = global i32 1, align 4 # | @s1_align_y = global i32 1, align 4 # | @s1_align = global i32 1, align 4 # | @s2_align_x = global i32 2, align 4 # | @s2_align_y = global i32 2, align 4 # | @s2_align = global i32 2, align 4 # | @s3_1 = global i32 1, align 4 # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local i32 @s0_load_x(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %x = getelementptr inbounds nuw %struct.s0, ptr %0, i32 0, i32 0 # | %1 = load i32, ptr %x, align 4 # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local i32 @s0_load_y(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %y = getelementptr inbounds nuw %struct.s0, ptr %0, i32 0, i32 1 # | %1 = load i32, ptr %y, align 4 # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @s0_copy(ptr noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca ptr, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 8 # | %0 = load ptr, ptr %b.addr, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 4 %0, ptr align 4 %1, i64 8, i1 false) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.memcpy.p0.p0.i64(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i64, i1 immarg) #1 # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local i32 @s1_load_x(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %x = getelementptr inbounds nuw %struct.s1, ptr %0, i32 0, i32 0 # | %1 = load i32, ptr %x, align 1 # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local i32 @s1_load_y(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %y = getelementptr inbounds nuw %struct.s1, ptr %0, i32 0, i32 1 # | %1 = load i32, ptr %y, align 1 # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @s1_copy(ptr noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca ptr, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 8 # | %0 = load ptr, ptr %b.addr, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 1 %0, ptr align 1 %1, i64 8, i1 false) # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local i32 @s2_load_x(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %x = getelementptr inbounds nuw %struct.s2, ptr %0, i32 0, i32 0 # | %1 = load i32, ptr %x, align 2 # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local i32 @s2_load_y(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %y = getelementptr inbounds nuw %struct.s2, ptr %0, i32 0, i32 1 # | %1 = load i32, ptr %y, align 2 # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @s2_copy(ptr noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca ptr, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 8 # | %0 = load ptr, ptr %b.addr, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 2 %0, ptr align 2 %1, i64 8, i1 false) # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local i32 @test3(ptr noundef %ptr) #0 { # | entry: # | %ptr.addr = alloca ptr, align 8 # | store ptr %ptr, ptr %ptr.addr, align 8 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %anInt = getelementptr inbounds nuw %struct.s3, ptr %0, i32 0, i32 1 # | %1 = load i32, ptr %anInt, align 2 # | ret i32 %1 # | } # | # | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=strip -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/packed-structure.c.tmp # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=strip -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/packed-structure.c.tmp # | #0 0x00005635e0f3f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005635e0f3c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005635e0f3fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f967cb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f967cb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f967cb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f967caed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005635e0ed524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005635e0ed5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005635e0eb9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005635e0b69176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005635e0b68e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f967caeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f967caef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f967caef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005635e0b68d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c (3199 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055944c16f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055944c16c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055944c16fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8566049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f85660a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8566049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8566031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055944c10524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055944c105096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055944c0e9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055944bd99176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055944bd98e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8566032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f85660330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f85660330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055944bd98d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c (3200 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf1.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv1i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf1.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv2i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf1.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv4i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf1.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv8i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf1.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv16i32.i64.i64(, , i64 immarg, i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005583ec8aa57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005583ec8a7515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005583ec8aacbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6688133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f668818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6688133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f668811b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005583ec84024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005583ec840096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005583ec824f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005583ec4d4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005583ec4d3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f668811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f668811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f668811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005583ec4d3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c (3201 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16m1x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a13eb3657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a13eb33515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a13eb36cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5268c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5268ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5268c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5268c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a13eacc24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a13eacc096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a13eab0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a13e760176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a13e75fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5268c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5268c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5268c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a13e75fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c (3202 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste8_i8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste8.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.sf.vste8.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste8_u8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste8.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005625d631957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005625d6316515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005625d6319cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2ac1449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2ac14a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2ac1449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2ac1431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005625d62af24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005625d62af096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005625d6293f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005625d5f43176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005625d5f42e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2ac1432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2ac14330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2ac14330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005625d5f42d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c (3203 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ta # | ... # `---data was truncated (10240/47488) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e4fe41b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e4fe418515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e4fe41bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f735ef05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f735ef5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f735ef05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f735eeed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e4fe3b124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e4fe3b1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e4fe395f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e4fe045176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e4fe044e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f735eeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f735eeef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f735eeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e4fe044d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c (3204 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16mf4_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m4_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m8_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f32mf2_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f32m1_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f32m2_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv1f64.nxv4f32.i64( poison, %0, %1, i64 7, i64 %2 # | ... # `---data was truncated (10240/50524) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560589f3057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560589f2d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560589f30cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f217cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f217cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f217cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f217cb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560589ec624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560589ec6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560589eaaf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560589b5a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560589b59e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f217cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f217cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f217cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560589b59d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c (3205 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16mf4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv16f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv16f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv32f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv32f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_i16mf4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_i16mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_i16m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4i16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_i16m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align # | ... # `---data was truncated (10240/39586) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056062024557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560620242515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560620245cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3603d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3603d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3603d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3603d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005606201db24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005606201db096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005606201bff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056061fe6f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056061fe6ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3603d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3603d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3603d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056061fe6ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c (3206 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16mf4_i8mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16mf2_i8mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m1_i8mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m2_i8m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m4_i8m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m8_i8m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16mf4_u8mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16mf2_u8mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m1_u8mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m2_u8m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm # | ... # `---data was truncated (10240/53200) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565201cb557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000565201cb2515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000565201cb5cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4cc5333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4cc538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4cc5333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4cc531b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565201c4b24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000565201c4b096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000565201c2ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005652018df176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005652018dee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4cc531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4cc531d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4cc531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005652018ded81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c (3207 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_f64m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1f64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_f64m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2f64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_f64m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4f64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_f64m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8f64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_i64m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_i64m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_i64m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_i64m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_u64m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_u64m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1 # | ... # `---data was truncated (10240/26772) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005612853c057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005612853bd515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005612853c0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f58b3049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f58b30a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f58b3049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f58b3031507 abort ./stdlib/abort.c:85:3 # | #7 0x000056128535624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561285356096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056128533af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561284fea176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561284fe9e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f58b3032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f58b30330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f58b30330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561284fe9d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c (3208 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16mf4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f64m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f64m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv2f64.nxv4f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2f64.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f64m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv4f64.nxv8f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4f64.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @ # | ... # `---data was truncated (10240/35774) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fe2c42557b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fe2c422515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fe2c425cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb295e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb295ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb295e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb295e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fe2c3bb24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fe2c3bb096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fe2c39ff49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fe2c04f176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fe2c04ee93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb295e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb295e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb295e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fe2c04ed81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c (3209 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f05926357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f059260515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f059263cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efc4d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efc4d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efc4d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efc4d31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f0591f924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f0591f9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f0591ddf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f058e8d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f058e8ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efc4d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efc4d31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efc4d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f058e8cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c (3210 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a67440757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a674404515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a674407cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe4cd81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe4cd8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe4cd81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe4cd803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a67439d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a67439d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a674381f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a674031176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a674030e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe4cd804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe4cd8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe4cd8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a674030d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c (3211 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557a2717357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557a27170515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557a27173cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7280533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f728058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7280533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f728051b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557a2710924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557a27109096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557a270edf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557a26d9d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557a26d9ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f728051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f728051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f728051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557a26d9cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c (3212 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr # | ... # `---data was truncated (10240/29202) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557e45ce057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557e45cdd515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557e45ce0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0d45049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0d450a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0d45049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0d45031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557e45c7624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557e45c76096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557e45c5af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557e4590a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557e45909e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f0d45032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0d450330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0d450330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557e45909d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c (3213 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_u64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c (3214 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_f32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_f32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_i32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_i32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_u32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_u32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_f32mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_f32m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vsca # | ... # `---data was truncated (10240/15944) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005646b4b1957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005646b4b16515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005646b4b19cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe85e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe85e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe85e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe85e031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005646b4aaf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005646b4aaf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005646b4a93f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005646b4743176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005646b4742e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe85e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe85e0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe85e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005646b4742d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm_acle_swp.c (3215 of 27911) ******************** TEST 'Clang :: CodeGen/arm_acle_swp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple thumbv7m-none-eabi -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c -check-prefix=ATOMIC # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple thumbv7m-none-eabi -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv7m-unknown-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_swp(i32 noundef %x, ptr noundef %p) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__p.addr.i = alloca ptr, align 4 # | %__v.i = alloca i32, align 4 # | %.atomictmp.i = alloca i32, align 4 # | %atomic-temp.i = alloca i32, align 4 # | %x.addr = alloca i32, align 4 # | %p.addr = alloca ptr, align 4 # | store i32 %x, ptr %x.addr, align 4 # | store ptr %p, ptr %p.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %1 = load ptr, ptr %p.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store ptr %1, ptr %__p.addr.i, align 4 # | %2 = load ptr, ptr %__p.addr.i, align 4 # | %3 = load i32, ptr %__x.addr.i, align 4 # | store i32 %3, ptr %.atomictmp.i, align 4 # | %4 = load i32, ptr %.atomictmp.i, align 4 # | %5 = atomicrmw volatile xchg ptr %2, i32 %4 monotonic, align 4 # | store i32 %5, ptr %atomic-temp.i, align 4 # | %6 = load i32, ptr %atomic-temp.i, align 4 # | store i32 %6, ptr %__v.i, align 4 # | %7 = load i32, ptr %__v.i, align 4 # | ret i32 %7 # | } # | # | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv7-m,+thumb-mode" } # | # | !llvm.module.flags = !{!0, !1, !2, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"aapcs"} # | !1 = !{i32 1, !"min_enum_size", i32 4} # | !2 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !3 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005598e350e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005598e350b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005598e350ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1a84049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1a840a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1a84049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1a84031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005598e34a424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005598e34a4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005598e3488f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005598e3138176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005598e3137e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1a84032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1a840330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1a840330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005598e3137d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c -check-prefix=ATOMIC # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c -check-prefix=ATOMIC # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c (3216 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557f97b1457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557f97b11515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557f97b14cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbeec333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbeec38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbeec333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbeec31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557f97aaa24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557f97aaa096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557f97a8ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557f9773e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557f9773de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fbeec31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbeec31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbeec31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557f9773dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c (3217 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf4_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf2_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.mask.nxv2bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.mask.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m1_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c (3218 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf8x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m1x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv32i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv32i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8mf8x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8mf4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8mf2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align # | ... # `---data was truncated (10240/14145) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005592e027457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005592e0271515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005592e0274cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1814b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1814b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1814b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1814b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005592e020a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005592e020a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005592e01eef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005592dfe9e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005592dfe9de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1814b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1814b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1814b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005592dfe9dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c (3219 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_i32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_i32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_u32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_u32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32mf2x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedof # | ... # `---data was truncated (10240/40734) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558cab2f157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558cab2ee515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558cab2f1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff07af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff07af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff07af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff07af1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558cab28724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558cab287096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558cab26bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558caaf1b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558caaf1ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007ff07af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff07af1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff07af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558caaf1ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGenCoroutines/pr65054.cpp (3220 of 27911) ******************** TEST 'Clang :: CodeGenCoroutines/pr65054.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 -O0 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes='sroa,mem2reg,simplifycfg' -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp --check-prefix=CHECK-O0 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 -O0 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | %struct.MyTask = type { %"struct.std::coroutine_handle" } # | %"struct.std::coroutine_handle" = type { ptr } # | %"struct.std::suspend_always" = type { i8 } # | %struct.Awaiter = type { ptr } # | %"struct.std::coroutine_handle.0" = type { %"struct.std::coroutine_handle" } # | # | $_ZN6MyTask12promise_type17get_return_objectEv = comdat any # | # | $_ZN6MyTask12promise_type15initial_suspendEv = comdat any # | # | $_ZNSt14suspend_always11await_readyEv = comdat any # | # | $_ZNSt14suspend_always13await_suspendESt16coroutine_handleIvE = comdat any # | # | $_ZNSt16coroutine_handleIN6MyTask12promise_typeEE12from_addressEPv = comdat any # | # | $_ZNSt14suspend_always12await_resumeEv = comdat any # | # | $_ZN6MyTask12promise_type15await_transformERKi = comdat any # | # | $_ZN7Awaiter11await_readyEv = comdat any # | # | $_ZNKSt16coroutine_handleIvE7addressEv = comdat any # | # | $_ZN7Awaiter12await_resumeEv = comdat any # | # | $_ZN6MyTask12promise_type13final_suspendEv = comdat any # | # | $_ZNSt16coroutine_handleIN6MyTask12promise_typeEE12from_promiseERS1_ = comdat any # | # | $_ZNSt16coroutine_handleIN6MyTask12promise_typeEEC1Ev = comdat any # | # | $_ZNSt16coroutine_handleIN6MyTask12promise_typeEEC2Ev = comdat any # | # | $_ZNSt16coroutine_handleIvEC2Ev = comdat any # | # | @g_array = global [32 x i32] zeroinitializer, align 16 # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local ptr @_Z6FooBarv() #0 { # | entry: # | %retval = alloca %struct.MyTask, align 8 # | %undef.agg.tmp = alloca %"struct.std::suspend_always", align 1 # | %undef.agg.tmp19 = alloca %"struct.std::suspend_always", align 1 # | %call = call noalias noundef nonnull ptr @_Znwm(i64 noundef 64) #6 # | store ptr @_Z6FooBarv.resume, ptr %call, align 8 # | %0 = select i1 true, ptr @_Z6FooBarv.destroy, ptr @_Z6FooBarv.cleanup # | %destroy.addr = getelementptr inbounds i8, ptr %call, i64 8 # | store ptr %0, ptr %destroy.addr, align 8 # | %ref.tmp.reload.addr = getelementptr inbounds i8, ptr %call, i64 18 # | %__range1.reload.addr = getelementptr inbounds i8, ptr %call, i64 24 # | %__begin1.reload.addr = getelementptr inbounds i8, ptr %call, i64 32 # | %__end1.reload.addr = getelementptr inbounds i8, ptr %call, i64 40 # | %x.reload.addr = getelementptr inbounds i8, ptr %call, i64 48 # | %ref.tmp4.reload.addr = getelementptr inbounds i8, ptr %call, i64 56 # | %ref.tmp18.reload.addr = getelementptr inbounds i8, ptr %call, i64 19 # | %__promise.reload.addr = getelementptr inbounds i8, ptr %call, i64 16 # | %call1 = call ptr @_ZN6MyTask12promise_type17get_return_objectEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise.reload.addr) # | %coerce.dive = getelementptr inbounds nuw %struct.MyTask, ptr %retval, i32 0, i32 0 # | %coerce.dive2 = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %coerce.dive, i32 0, i32 0 # | store ptr %call1, ptr %coerce.dive2, align 8 # | call void @_ZN6MyTask12promise_type15initial_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise.reload.addr) # | %call3 = call noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp.reload.addr) #7 # | br i1 %call3, label %init.ready, label %CoroSave # | # | CoroSave: ; preds = %entry # | %index.addr39 = getelementptr inbounds i8, ptr %call, i64 17 # | store i8 0, ptr %index.addr39, align 1 # | call void @_Z6FooBarv.__await_suspend_wrapper__init(ptr %ref.tmp.reload.addr, ptr %call) #7 # | br label %AfterCoroEnd # | # | init.ready: ; preds = %entry # | call void @_ZNSt14suspend_always12await_resumeEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp.reload.addr) #7 # | store ptr @g_array, ptr %__range1.reload.addr, align 8 # | store ptr @g_array, ptr %__begin1.reload.addr, align 8 # | store ptr getelementptr inbounds nuw (i8, ptr @g_array, i64 128), ptr %__end1.reload.addr, align 8 # | br label %for.cond # | # | for.cond: ; preds = %for.inc, %init.ready # | %1 = load ptr, ptr %__begin1.reload.addr, align 8 # | %2 = load ptr, ptr %__end1.reload.addr, align 8 # | %cmp = icmp ne ptr %1, %2 # | br i1 %cmp, label %for.body, label %coro.final # | # | for.body: ; preds = %for.cond # | %3 = load ptr, ptr %__begin1.reload.addr, align 8 # | store ptr %3, ptr %x.reload.addr, align 8 # | %4 = load ptr, ptr %x.reload.addr, align 8, !nonnull !1, !align !2 # | %call5 = call ptr @_ZN6MyTask12promise_type15await_transformERKi(ptr noundef nonnull align 1 dereferenceable(1) %__promise.reload.addr, ptr noundef nonnull align 4 dereferenceable(4) %4) # | %coerce.dive6 = getelementptr inbounds nuw %struct.Awaiter, ptr %ref.tmp4.reload.addr, i32 0, i32 0 # | store ptr %call5, ptr %coerce.dive6, align 8 # | %call7 = call noundef zeroext i1 @_ZN7Awaiter11await_readyEv(ptr noundef nonnull align 8 dereferenceable(8) %ref.tmp4.reload.addr) # | br i1 %call7, label %await.ready, label %CoroSave27 # | # | CoroSave27: ; preds = %for.body # | %index.addr40 = getelementptr inbounds i8, ptr %call, i64 17 # | store i8 1, ptr %index.addr40, align 1 # | %5 = call ptr @_Z6FooBarv.__await_suspend_wrapper__await(ptr %ref.tmp4.reload.addr, ptr %call) # | %6 = getelementptr inbounds { ptr, ptr }, ptr %5, i32 0, i32 0 # | %7 = load ptr, ptr %6, align 8 # | call void %7(ptr %5) # | br label %AfterCoroEnd # | # | await.ready: ; preds = %for.body # | call void @_ZN7Awaiter12await_resumeEv(ptr noundef nonnull align 8 dereferenceable(8) %ref.tmp4.reload.addr) # | %cond = icmp eq i32 0, 0 # | %cond26 = icmp eq i32 0, 0 # | br i1 %cond26, label %for.inc, label %coro.final # | # | for.inc: ; preds = %await.ready # | %8 = load ptr, ptr %__begin1.reload.addr, align 8 # | %incdec.ptr = getelementptr inbounds nuw i32, ptr %8, i32 1 # | store ptr %incdec.ptr, ptr %__begin1.reload.addr, align 8 # | br label %for.cond # | # | coro.final: ; preds = %await.ready, %for.cond # | call void @_ZN6MyTask12promise_type13final_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise.reload.addr) #7 # | %call20 = call noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp18.reload.addr) #7 # | br i1 %call20, label %final.ready, label %CoroSave31 # | # | CoroSave31: ; preds = %coro.final # | store ptr null, ptr %call, align 8 # | call void @_Z6FooBarv.__await_suspend_wrapper__final(ptr %ref.tmp18.reload.addr, ptr %call) #7 # | br label %AfterCoroEnd # | # | final.ready: ; preds = %coro.final # | call void @_ZNSt14suspend_always12await_resumeEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp18.reload.addr) #7 # | %9 = icmp ne ptr %call, null # | br i1 %9, label %coro.free, label %AfterCoroEnd # | # | coro.free: ; preds = %final.ready # | call void @_ZdlPvm(ptr noundef %call, i64 noundef 64) #7 # | br label %AfterCoroEnd # | # | AfterCoroEnd: ; preds = %coro.free, %final.ready, %CoroSave27, %CoroSave31, %CoroSave # | %coerce.dive24 = getelementptr inbounds nuw %struct.MyTask, ptr %retval, i32 0, i32 0 # | %coerce.dive25 = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %coerce.dive24, i32 0, i32 0 # | %10 = load ptr, ptr %coerce.dive25, align 8 # | ret ptr %10 # | } # | # | ; Function Attrs: nobuiltin allocsize(0) # | declare noundef nonnull ptr @_Znwm(i64 noundef) #1 # | # | ; Function Attrs: mustprogress noinline nounwind # | define linkonce_odr ptr @_ZN6MyTask12promise_type17get_return_objectEv(ptr noundef nonnull align 1 dereferenceable(1) %this) #0 comdat align 2 { # | entry: # | %retval = alloca %struct.MyTask, align 8 # | %this.addr = alloca ptr, align 8 # | %ref.tmp = alloca %"struct.std::coroutine_handle.0", align 8 # | store ptr %this, ptr %this.addr, align 8 # | %this1 = load ptr, ptr %this.addr, align 8 # | %h = getelementptr inbounds nuw %struct.MyTask, ptr %retval, i32 0, i32 0 # | %call = call ptr @_ZNSt16coroutine_handleIN6MyTask12promise_typeEE12from_promiseERS1_(ptr noundef nonnull align 1 dereferenceable(1) %this1) # | %coerce.dive = getelementptr inbounds nuw %"struct.std::coroutine_handle.0", ptr %ref.tmp, i32 0, i32 0 # | %coerce.dive2 = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %coerce.dive, i32 0, i32 0 # | store ptr %call, ptr %coerce.dive2, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 8 %h, ptr align 8 %ref.tmp, i64 8, i1 false) # | %coerce.dive3 = getelementptr inbounds nuw %struct.MyTask, ptr %retval, i32 0, i32 0 # | %coerce.dive4 = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %coerce.dive3, i32 0, i32 0 # | %0 = load ptr, ptr %coerce.dive4, align 8 # | ret ptr %0 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define linkonce_odr void @_ZN6MyTask12promise_type15initial_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %this) #0 comdat align 2 { # | entry: # | %this.addr = alloca ptr, align 8 # | store ptr %this, ptr %this.addr, align 8 # | %this1 = load ptr, ptr %this.addr, align 8 # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define linkonce_odr noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %this) #0 comdat align 2 { # | entry: # | %this.addr = alloca ptr, align 8 # | store ptr %this, ptr %this.addr, align 8 # | %this1 = load ptr, ptr %this.addr, align 8 # | ret i1 false # | } # | # | ; Function Attrs: alwaysinline mustprogress nounwind # | define internal void @_Z6FooBarv.__await_suspend_wrapper__init(ptr noundef nonnull %0, ptr noundef %1) #2 { # | entry: # | %.addr = alloca ptr, align 8 # | %.addr1 = alloca ptr, align 8 # | %agg.tmp = alloca %"struct.std::coroutine_handle", align 8 # | %ref.tmp = alloca %"struct.std::coroutine_handle.0", align 8 # | store ptr %0, ptr %.addr, align 8 # | store ptr %1, ptr %.addr1, align 8 # | %2 = load ptr, ptr %.addr, align 8 # | %3 = load ptr, ptr %.addr1, align 8 # | %call = call ptr @_ZNSt16coroutine_handleIN6MyTask12promise_typeEE12from_addressEPv(ptr noundef %3) #7 # | # | ... # `---data was truncated (10240/37953) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=sroa,mem2reg,simplifycfg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=sroa,mem2reg,simplifycfg -S # | #0 0x0000562786f0e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562786f0b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562786f0ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f557cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f557cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f557cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f557cc31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562786ea424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562786ea4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562786e88f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562786b38176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562786b37e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f557cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f557cc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f557cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562786b37d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp --check-prefix=CHECK-O0 # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp --check-prefix=CHECK-O0 # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c (3221 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_f64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_i64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_u64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_f64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_i64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_u64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560a593a757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560a593a4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560a593a7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f782c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f782c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f782c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f782c51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560a5933d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560a5933d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560a59321f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560a58fd1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560a58fd0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f782c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f782c51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f782c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560a58fd0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c (3222 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv1f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv1f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local # | ... # `---data was truncated (10240/51412) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e62cc3157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e62cc2e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e62cc31cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7a3e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7a3e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7a3e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7a3e71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e62cbc724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e62cbc7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e62cbabf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e62c85b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e62c85ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f7a3e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7a3e71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7a3e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e62c85ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c (3223 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m1x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function # | ... # `---data was truncated (10240/22115) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c5fb25957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c5fb256515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c5fb259cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fddb8b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fddb8b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fddb8b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fddb8b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c5fb1ef24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c5fb1ef096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c5fb1d3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c5fae83176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c5fae82e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fddb8b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fddb8b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fddb8b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c5fae82d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c (3224 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | % # | ... # `---data was truncated (10240/14613) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557c581b357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557c581b0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557c581b3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3f6f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3f6f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3f6f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3f6f31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557c5814924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557c58149096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557c5812df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557c57ddd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557c57ddce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3f6f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3f6f31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3f6f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557c57ddcd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c (3225 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562baf57b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562baf578515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562baf57bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f56e1333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f56e138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f56e1333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f56e131b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562baf51124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562baf511096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562baf4f5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562baf1a5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562baf1a4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f56e131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f56e131d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f56e131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562baf1a4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c (3226 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretur # | ... # `---data was truncated (10240/20190) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c604a0057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c6049fd515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c604a00cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5bb681bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5bb68725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5bb681ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5bb6803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c60499624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c604996096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c60497af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c60462a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c604629e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5bb6804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5bb68050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5bb68050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c604629d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c (3227 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005580ae00d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005580ae00a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005580ae00dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd2c7b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd2c7b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd2c7b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd2c7b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005580adfa324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005580adfa3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005580adf87f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005580adc37176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005580adc36e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd2c7b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd2c7b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd2c7b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005580adc36d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c (3228 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005569a409257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005569a408f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005569a4092cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd4ef849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd4ef8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd4ef849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd4ef831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005569a402824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005569a4028096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005569a400cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005569a3cbc176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005569a3cbbe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd4ef832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd4ef8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd4ef8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005569a3cbbd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c (3229 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m1x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function # | ... # `---data was truncated (10240/22115) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f340c1957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f340c16515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f340c19cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe62a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe62a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe62a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe62a71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f340baf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f340baf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f340b93f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f340843176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f340842e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe62a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe62a71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe62a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f340842d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c (3230 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_u64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_u64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv # | ... # `---data was truncated (10240/53548) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055673f4c457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055673f4c1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055673f4c4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3f2e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3f2e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3f2e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3f2e51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055673f45a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055673f45a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055673f43ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055673f0ee176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055673f0ede93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3f2e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3f2e51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3f2e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055673f0edd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c (3231 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m1x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | s # | ... # `---data was truncated (10240/24381) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560dc2d4957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560dc2d46515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560dc2d49cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5182d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5182d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5182d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5182d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560dc2cdf24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560dc2cdf096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560dc2cc3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560dc2973176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560dc2972e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5182d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5182d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5182d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560dc2972d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c (3232 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv16bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv32bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf4_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load , ptr %vs1.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vpaire.mask.nxv1bf16.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , # | ... # `---data was truncated (10240/32646) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005620b951157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005620b950e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005620b9511cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f95c9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f95c9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f95c9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f95c9f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005620b94a724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005620b94a7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005620b948bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005620b913b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005620b913ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f95c9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f95c9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f95c9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005620b913ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c (3233 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005573a5f8a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005573a5f87515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005573a5f8acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd092905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd09295c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd092905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd0928ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005573a5f2024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005573a5f20096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005573a5f04f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005573a5bb4176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005573a5bb3e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd0928eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd0928ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd0928ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005573a5bb3d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c (3234 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv1f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv2f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv4f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv8f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv8f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv16f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c (3235 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16mf4x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16mf2x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16m1x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16m2x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16m1x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16m2x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("risc # | ... # `---data was truncated (10240/11912) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e48e4b857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e48e4b5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e48e4b8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8cfec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8cfeca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8cfec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8cfec31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e48e44e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e48e44e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e48e432f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e48e0e2176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e48e0e1e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8cfec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8cfec330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8cfec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e48e0e1d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c (3236 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_u16mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_u16mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_u16m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16mf4x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.v # | ... # `---data was truncated (10240/20439) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c68a14457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c68a141515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c68a144cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2ebbb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2ebbb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2ebbb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2ebbb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c68a0da24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c68a0da096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c68a0bef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c689d6e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c689d6de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2ebbb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2ebbb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2ebbb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c689d6dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c (3237 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_f64m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_i64m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_u64m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055737498c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557374989515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055737498ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f507381bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f50738725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f507381ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5073803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055737492224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557374922096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557374906f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005573745b6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005573745b5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5073804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f50738050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f50738050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005573745b5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c (3238 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | ... # `---data was truncated (10240/29304) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b65409357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b654090515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b654093cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3b24849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3b248a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3b24849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3b24831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b65402924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b654029096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b65400df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b653cbd176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b653cbce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f3b24832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3b248330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3b248330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b653cbcd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c (3239 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c (3240 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055deb2e6457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055deb2e61515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055deb2e64cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f543d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f543d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f543d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f543d431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055deb2dfa24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055deb2dfa096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055deb2ddef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055deb2a8e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055deb2a8de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f543d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f543d4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f543d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055deb2a8dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c (3241 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16mf4x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16mf2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16mf4x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16mf2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_u16mf4x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_u16mf2x3_m( %mask, ptr nound # | ... # `---data was truncated (10240/13515) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056364583657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563645833515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563645836cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6a2eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6a2eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6a2eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6a2eb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005636457cc24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005636457cc096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005636457b0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563645460176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056364545fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6a2eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6a2eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6a2eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056364545fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c (3242 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555bc92ed57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555bc92ea515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555bc92edcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f76d8f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f76d8f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f76d8f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f76d8f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555bc928324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555bc9283096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555bc9267f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555bc8f17176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555bc8f16e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f76d8f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f76d8f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f76d8f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555bc8f16d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c (3243 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_i8mf8x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_i8mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_i8mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_i8m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_u8mf8x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_u8mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_u8mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_u8m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_i8mf8x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, al # | ... # `---data was truncated (10240/21566) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fa443b157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055fa443ae515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055fa443b1cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2ec1905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2ec195c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2ec1905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2ec18ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fa4434724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055fa44347096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055fa4432bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055fa43fdb176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055fa43fdae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f2ec18eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2ec18ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2ec18ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fa43fdad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c (3244 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv4i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv4i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv8i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv8i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv16i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv16i32.i64(, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e6e835e57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e6e835b515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e6e835ecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fab44f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fab44f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fab44f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fab44f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e6e82f424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e6e82f4096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e6e82d8f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e6e7f88176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e6e7f87e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fab44f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fab44f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fab44f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e6e7f87d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c (3245 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_f32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_f32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_i32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_i32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_u32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_u32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_f32mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_f32m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vsca # | ... # `---data was truncated (10240/15944) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005618f55d857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005618f55d5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005618f55d8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdd85733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdd8578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdd85733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdd8571b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005618f556e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005618f556e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005618f5552f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005618f5202176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005618f5201e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fdd8571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdd8571d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdd8571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005618f5201d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c (3246 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf8x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf8x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf8x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf4x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c (3247 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noca # | ... # `---data was truncated (10240/40803) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f61ee7257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f61ee6f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f61ee72cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5ce6333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5ce638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5ce6333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5ce631b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f61ee0824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f61ee08096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f61edecf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f61ea9c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f61ea9be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5ce631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5ce631d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5ce631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f61ea9bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c (3248 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @ # | ... # `---data was truncated (10240/60228) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c27cd0d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055c27cd0a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055c27cd0dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f658bf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f658bf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f658bf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f658beed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c27cca324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055c27cca3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055c27cc87f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055c27c937176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055c27c936e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f658beeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f658beef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f658beef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c27c936d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c (3249 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16mf4_i8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16mf2_i8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m1_i8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m2_i8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m4_i8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m8_i8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16mf4_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16mf2_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m1_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m2_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m4_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m8_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c (3250 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf4_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf2_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m1_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv4bf16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv4bf16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m2_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv8bf16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv8bf16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m4_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv16bf16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv16bf16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m8_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv32bf16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv32bf16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055db895e357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055db895e0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055db895e3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9cc0049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9cc00a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9cc0049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9cc0031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055db8957924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055db89579096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055db8955df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055db8920d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055db8920ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9cc0032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9cc00330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9cc00330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055db8920cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c (3251 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16mf4( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv1bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16mf2( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv2bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m1( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv4bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m2( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv8bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m4( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv16bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m8( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv32bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(, , bfloat, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ae1d55957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ae1d556515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ae1d559cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f23f3249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f23f32a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f23f3249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f23f3231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ae1d4ef24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ae1d4ef096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ae1d4d3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ae1d183176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ae1d182e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f23f3232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f23f32330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f23f32330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ae1d182d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c (3252 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16mf4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055df903f057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055df903ed515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055df903f0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f31a2705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f31a275c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f31a2705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f31a26ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055df9038624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055df90386096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055df9036af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055df9001a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055df90019e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f31a26eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f31a26ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f31a26ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055df90019d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c (3253 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c (3254 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_f32mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_f32m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_i32mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_i32m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_u32mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_u32m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_f32mf2x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_f32m1x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_i32mf2x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_i32m1x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/14010) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ced5db457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055ced5db1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055ced5db4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0595133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f059518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0595133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f059511b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ced5d4a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055ced5d4a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055ced5d2ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055ced59de176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055ced59dde93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f059511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f059511d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f059511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ced59ddd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c (3255 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i32.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv2i32.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv4i32.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv8i32.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv16i32.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i64.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv2i64.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv4i64.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv8i64.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv1i32.nxv1i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv1i32.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv2i32.nxv2i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv2i32.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv4i32.nxv4 # | ... # `---data was truncated (10240/17503) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056401333d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056401333a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056401333dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8f1461bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8f146725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8f1461ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8f14603507 abort ./stdlib/abort.c:85:3 # | #7 0x00005640132d324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005640132d3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005640132b7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564012f67176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564012f66e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8f14604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8f146050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8f146050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564012f66d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c (3256 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, al # | ... # `---data was truncated (10240/26756) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e68826057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e68825d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e688260cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f60e1533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f60e158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f60e1533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f60e151b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e6881f624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e6881f6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e6881daf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e687e8a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e687e89e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f60e151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f60e151d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f60e151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e687e89d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c (3257 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range( # | ... # `---data was truncated (10240/12227) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558994dac57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558994da9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558994daccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5dcfe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5dcfea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5dcfe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5dcfe31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558994d4224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558994d42096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558994d26f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005589949d6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005589949d5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5dcfe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5dcfe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5dcfe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005589949d5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c (3258 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 % # | ... # `---data was truncated (10240/29210) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055607045957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556070456515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556070459cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6244305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f624435c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6244305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f62442ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005560703ef24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005560703ef096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005560703d3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556070083176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556070082e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f62442eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f62442ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f62442ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556070082d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c (3259 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv16bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv32bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf4_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load , ptr %vs1.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vpairo.mask.nxv1bf16.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , # | ... # `---data was truncated (10240/32646) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555c4db6a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555c4db67515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555c4db6acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8685449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f86854a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8685449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8685431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555c4db0024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555c4db00096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555c4dae4f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555c4d794176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555c4d793e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8685432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f86854330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f86854330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555c4d793d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c (3260 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16mf4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv1f16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1f16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16mf2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv2f16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv2f16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m1_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv4f16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv4f16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv8f16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv8f16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv16f16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv16f16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv32f16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv32f16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_i16mf4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv1i16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1i16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_i16mf2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv2i16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractva # | ... # `---data was truncated (10240/22708) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056548552257b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056548551f515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000565485522cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f335cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f335cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f335cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f335cd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005654854b824d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005654854b8096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056548549cf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056548514c176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056548514be93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f335cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f335cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f335cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056548514bd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c (3261 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562951adb57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562951ad8515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562951adbcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f948c01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f948c0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f948c01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f948c003507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562951a7124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562951a71096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562951a55f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562951705176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562951704e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f948c004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f948c0050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f948c0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562951704d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c (3262 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16mf4_i8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16mf2_i8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m1_i8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m2_i8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m4_i8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m8_i8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16mf4_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16mf2_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m1_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m2_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m4_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m8_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llv # | ... # `---data was truncated (10240/59779) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e6fd72057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055e6fd71d515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055e6fd720cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb511f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb511f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb511f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb511f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e6fd6b624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055e6fd6b6096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055e6fd69af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055e6fd34a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055e6fd349e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb511f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb511f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb511f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e6fd349d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/distributed-thin-lto/basic.ll (3263 of 27911) ******************** TEST 'Clang :: CodeGen/distributed-thin-lto/basic.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/basic.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/basic.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/basic.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/basic.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/basic.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/basic.ll # | #0 0x000055873902b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558739028515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055873902bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe00fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe00fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe00fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe00fd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558738fc124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000558738fc1096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558738fa5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558738c55176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558738c54e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe00fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe00fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe00fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558738c54d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c (3264 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_i32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_i32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_u32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_u32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32mf2x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, # | ... # `---data was truncated (10240/40726) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555ed0df357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555ed0df0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555ed0df3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9f63b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9f63b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9f63b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9f63aed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555ed0d8924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555ed0d89096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555ed0d6df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555ed0a1d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555ed0a1ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9f63aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9f63aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9f63aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555ed0a1cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbkx.c (3265 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbkx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkx -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c -check-prefix=RV32ZBKX # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkx -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @xperm8_32(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.xperm8.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @xperm4_32(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.xperm4.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.xperm8.i32(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.xperm4.i32(i32, i32) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbkx" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_zbkx1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557a93c5457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557a93c51515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557a93c54cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4163733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f416378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4163733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f416371b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557a93bea24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557a93bea096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557a93bcef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557a9387e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557a9387de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f416371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f416371d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f416371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557a9387dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c -check-prefix=RV32ZBKX # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c -check-prefix=RV32ZBKX # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c (3266 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounw # | ... # `---data was truncated (10240/12658) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a8536f057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055a8536ed515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055a8536f0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5ec7849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5ec78a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5ec7849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5ec7831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a85368624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055a853686096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055a85366af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055a85331a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055a853319e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f5ec7832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5ec78330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5ec78330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a853319d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c (3267 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_i64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_i64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_u64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_u64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m1x3_tum( %mask, target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("r # | ... # `---data was truncated (10240/36023) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b6e94c457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b6e94c1515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b6e94c4cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9cccf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9cccf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9cccf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9cccf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b6e945a24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b6e945a096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b6e943ef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b6e90ee176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b6e90ede93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f9cccf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9cccf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9cccf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b6e90edd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c (3268 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_f16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_f16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_f16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_i16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_i16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_i16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_u16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_u16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_u16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c (3269 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005616cfb8b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005616cfb88515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005616cfb8bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f51f6c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f51f6ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f51f6c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f51f6c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005616cfb2124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005616cfb21096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005616cfb05f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005616cf7b5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005616cf7b4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f51f6c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f51f6c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f51f6c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005616cf7b4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c (3270 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf4_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load , ptr %vs1.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, pt # | ... # `---data was truncated (10240/32701) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564ca351a57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564ca3517515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564ca351acbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdcc5449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdcc54a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdcc5449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdcc5431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564ca34b024d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564ca34b0096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564ca3494f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564ca3144176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564ca3143e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fdcc5432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdcc54330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdcc54330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564ca3143d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c (3271 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_f64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_f64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_i64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_i64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_u64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_u64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_f64m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_f64m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Functi # | ... # `---data was truncated (10240/15986) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556fdd32f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000556fdd32c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000556fdd32fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcf57449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcf574a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcf57449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcf57431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556fdd2c524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000556fdd2c5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000556fdd2a9f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000556fdcf59176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000556fdcf58e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fcf57432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcf574330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcf574330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556fdcf58d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c (3272 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16mf4x7(ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16mf2x7(ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16m1x7(ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16m1x7_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b98679157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b98678e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b986791cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd80a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd80a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd80a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd80a31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b98672724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b986727096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b98670bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b9863bb176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b9863bae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd80a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd80a31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd80a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b9863bad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c (3273 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16mf4_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16mf4_f32mf2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16mf2_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16mf2_f32m1( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16m1_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16m1_f32m2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16m2_f32m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16m2_f32m4( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16m4_f32m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv16f32.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv16f32.nxv16bf16.nxv16bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16m4_f32m8( %v # | ... # `---data was truncated (10240/43948) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d1bf47957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d1bf476515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d1bf479cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feba5905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feba595c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feba5905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feba58ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d1bf40f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d1bf40f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d1bf3f3f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d1bf0a3176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d1bf0a2e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007feba58eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feba58ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feba58ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d1bf0a2d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c (3274 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv2i16.nxv2i32.i64.i64( po # | ... # `---data was truncated (10240/50898) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f9ec0cd57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f9ec0ca515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f9ec0cdcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdacb733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdacb78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdacb733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdacb71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f9ec06324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f9ec063096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f9ec047f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f9ebcf7176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f9ebcf6e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fdacb71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdacb71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdacb71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f9ebcf6d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c (3275 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | ... # `---data was truncated (10240/20149) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563c984cf57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563c984cc515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563c984cfcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd8b681bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd8b68725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd8b681ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd8b6803507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563c9846524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563c98465096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563c98449f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563c980f9176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563c980f8e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd8b6804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd8b68050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd8b68050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563c980f8d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c (3276 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16mf4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16mf4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.r # | ... # `---data was truncated (10240/33423) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564d5dc6c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564d5dc69515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564d5dc6ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f626a01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f626a0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f626a01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f626a003507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564d5dc0224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564d5dc02096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564d5dbe6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000564d5d896176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000564d5d895e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f626a004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f626a0050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f626a0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564d5d895d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c (3277 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_i32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_i32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_u32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_u32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32mf2x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("ri # | ... # `---data was truncated (10240/32023) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f518d7b57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f518d78515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f518d7bcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd01881bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd0188725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd01881ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd018803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f518d1124d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f518d11096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f518cf5f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f5189a5176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f5189a4e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd018804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd0188050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd0188050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f5189a4d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c (3278 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv # | ... # `---data was truncated (10240/25519) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562f03fee57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000562f03feb515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000562f03feecbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efc6ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efc6eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efc6ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efc6ea31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562f03f8424d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000562f03f84096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000562f03f68f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000562f03c18176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000562f03c17e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007efc6ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efc6ea330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efc6ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562f03c17d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c (3279 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf4x5_tumu( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | ... # `---data was truncated (10240/18506) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055be6074457b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055be60741515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055be60744cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6040533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f604058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6040533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f604051b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055be606da24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055be606da096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055be606bef49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055be6036e176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055be6036de93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f604051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f604051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f604051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055be6036dd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c (3280 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, # | ... # `---data was truncated (10240/23056) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560242de857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560242de5515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560242de8cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1f43c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1f43ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1f43c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1f43c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560242d7e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560242d7e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560242d62f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560242a12176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560242a11e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f1f43c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1f43c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1f43c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560242a11d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c (3281 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m1_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv1f64.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1f64.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv2f64.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2f64.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv4f64.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv4f64.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv8f64.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv8f64.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m1_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv1i64.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1i64.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv2i64.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2i64.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv4i64.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv4i64.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv8i64.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv8i64.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_u64m1_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.ad # | ... # `---data was truncated (10240/13903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555c0a74d57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555c0a74a515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555c0a74dcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faffa61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faffa6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faffa61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faffa603507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555c0a6e324d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555c0a6e3096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555c0a6c7f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555c0a377176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555c0a376e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007faffa604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faffa6050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faffa6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555c0a376d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c (3282 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf8x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_u8mf8x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_u8mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_u8mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vec # | ... # `---data was truncated (10240/27595) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055da17b7c57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055da17b79515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055da17b7ccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe5b0449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe5b04a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe5b0449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe5b0431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055da17b1224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055da17b12096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055da17af6f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055da177a6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055da177a5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fe5b0432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe5b04330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe5b04330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055da177a5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c (3283 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b8ac7e957b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055b8ac7e6515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055b8ac7e9cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7722933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f772298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7722933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f772291b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b8ac77f24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055b8ac77f096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055b8ac763f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055b8ac413176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055b8ac412e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f772291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f772291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f772291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b8ac412d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbb.c (3284 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c -check-prefix=RV32ZBB # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @orc_b_32(i32 noundef %a) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.orc.b.i32(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @clz_32(i32 noundef %a) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @ctz_32(i32 noundef %a) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.cttz.i32(i32 %1, i1 false) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @cpop_32(i32 noundef %a) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.ctpop.i32(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.orc.b.i32(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.ctlz.i32(i32, i1 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.cttz.i32(i32, i1 immarg) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.ctpop.i32(i32) #2 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbb" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_zbb1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005563ec19157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005563ec18e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005563ec191cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc50c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc50c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc50c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc50c91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005563ec12724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005563ec127096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005563ec10bf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005563ebdbb176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005563ebdbae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fc50c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc50c91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc50c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005563ebdbad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c -check-prefix=RV32ZBB # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c -check-prefix=RV32ZBB # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/distributed-thin-lto/supports-hot-cold-new.ll (3285 of 27911) ******************** TEST 'Clang :: CodeGen/distributed-thin-lto/supports-hot-cold-new.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 8 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/supports-hot-cold-new.ll >/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/supports-hot-cold-new.ll.tmp.o # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/supports-hot-cold-new.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/supports-hot-cold-new.ll # | #0 0x000055d3ae40357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055d3ae400515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055d3ae403cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb989649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb9896a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb989649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb989631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d3ae39924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055d3ae399096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055d3ae37df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055d3ae02d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055d3ae02ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb989632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb9896330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb9896330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d3ae02cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c (3286 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_f64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_i64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_u64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_f64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_i64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_u64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558699a0857b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000558699a05515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000558699a08cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f78c2133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f78c218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f78c2133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f78c211b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055869999e24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055869999e096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000558699982f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000558699632176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000558699631e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f78c211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f78c211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f78c211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558699631d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c (3287 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560a68ec357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000560a68ec0515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000560a68ec3cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6b37b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6b37b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6b37b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6b37b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560a68e5924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000560a68e59096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000560a68e3df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000560a68aed176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000560a68aece93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6b37b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6b37b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6b37b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560a68aecd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c (3288 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i32.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv2i32.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv4i32.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv8i32.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv16i32.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i64.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv2i64.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv4i64.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv8i64.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv1i32.nxv1i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv1i32.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv2i32.nxv2i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv2i32.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv4i32.nxv4i8.i64(< # | ... # `---data was truncated (10240/17495) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564983cb757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000564983cb4515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000564983cb7cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb0eb533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb0eb58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb0eb533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb0eb51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564983c4d24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000564983c4d096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000564983c31f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005649838e1176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005649838e0e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fb0eb51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb0eb51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb0eb51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005649838e0d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c (3289 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055caf6f4357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055caf6f40515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055caf6f43cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8f6c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8f6c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8f6c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8f6c91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055caf6ed924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055caf6ed9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055caf6ebdf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055caf6b6d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055caf6b6ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8f6c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8f6c91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8f6c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055caf6b6cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c (3290 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load , ptr %vs1.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m1_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load , ptr %vs1.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr # | ... # `---data was truncated (10240/27541) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bf1ac8357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055bf1ac80515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055bf1ac83cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8487a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8487aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8487a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8487a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bf1ac1924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055bf1ac19096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055bf1abfdf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055bf1a8ad176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055bf1a8ace93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8487a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8487a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8487a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bf1a8acd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c (3291 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563637f4157b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000563637f3e515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000563637f41cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6d31733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6d3178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6d31733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6d3171b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563637ed724d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000563637ed7096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000563637ebbf49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000563637b6b176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000563637b6ae93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f6d3171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6d3171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6d3171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563637b6ad81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c (3292 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv8i8.nxv8i8.i64(, , , , i # | ... # `---data was truncated (10240/63579) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005618a7e6757b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x00005618a7e64515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x00005618a7e67cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa4eef05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa4eef5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa4eef05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa4eeeed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005618a7dfd24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x00005618a7dfd096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x00005618a7de1f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x00005618a7a91176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x00005618a7a90e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fa4eeeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa4eeeef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa4eeeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005618a7a90d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c (3293 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq # | ... # `---data was truncated (10240/18668) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555d32f2357b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000555d32f20515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000555d32f23cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fda75105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fda7515c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fda75105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fda750ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555d32eb924d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000555d32eb9096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000555d32e9df49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000555d32b4d176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000555d32b4ce93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fda750eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fda750ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fda750ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555d32b4cd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c (3294 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16mf4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561b2280f57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000561b2280c515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000561b2280fcbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4d53d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4d53d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4d53d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4d53d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561b227a524d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000561b227a5096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000561b22789f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000561b22439176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000561b22438e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f4d53d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4d53d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4d53d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561b22438d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/distributed-thin-lto/cfi.ll (3295 of 27911) ******************** TEST 'Clang :: CodeGen/distributed-thin-lto/cfi.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi.ll # | #0 0x000056429cfe057b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000056429cfdd515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000056429cfe0cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd823b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd823b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd823b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd823b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056429cf7624d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000056429cf76096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000056429cf5af49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000056429cc0a176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000056429cc09e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007fd823b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd823b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd823b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056429cc09d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c (3296 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv2i16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv4i16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv8i16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv16i16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv32i16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i32.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv2i32.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv4i32.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv8i32.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i32.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv16i32.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv16i32.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i64.nxv1i32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op # | ... # `---data was truncated (10240/28563) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f9faaac57b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x000055f9faaa9515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x000055f9faaaccbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8b97133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8b9718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8b97133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8b9711b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f9faa4224d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x000055f9faa42096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x000055f9faa26f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x000055f9fa6d6176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x000055f9fa6d5e93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f8b9711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8b9711d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8b9711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f9fa6d5d81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20.. 30.. 40. FAIL: Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c (3613 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ffb(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__a.addr.i = alloca i32, align 4 # | %__b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__a.addr.i, align 4 # | store i32 %1, ptr %__b.addr.i, align 4 # | %2 = load i32, ptr %__a.addr.i, align 4 # | %3 = load i32, ptr %__b.addr.i, align 4 # | %4 = call i32 @llvm.riscv.nds.ffb.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ffzmism(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__a.addr.i = alloca i32, align 4 # | %__b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__a.addr.i, align 4 # | store i32 %1, ptr %__b.addr.i, align 4 # | %2 = load i32, ptr %__a.addr.i, align 4 # | %3 = load i32, ptr %__b.addr.i, align 4 # | %4 = call i32 @llvm.riscv.nds.ffzmism.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ffmism(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__a.addr.i = alloca i32, align 4 # | %__b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__a.addr.i, align 4 # | store i32 %1, ptr %__b.addr.i, align 4 # | %2 = load i32, ptr %__a.addr.i, align 4 # | %3 = load i32, ptr %__b.addr.i, align 4 # | %4 = call i32 @llvm.riscv.nds.ffmism.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_flmism(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__a.addr.i = alloca i32, align 4 # | %__b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__a.addr.i, align 4 # | store i32 %1, ptr %__b.addr.i, align 4 # | %2 = load i32, ptr %__a.addr.i, align 4 # | %3 = load i32, ptr %__b.addr.i, align 4 # | %4 = call i32 @llvm.riscv.nds.flmism.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i32 @llvm.riscv.nds.ffb.i32(i32, i32) #1 # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i32 @llvm.riscv.nds.ffzmism.i32(i32, i32) #1 # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i32 @llvm.riscv.nds.ffmism.i32(i32, i32) #1 # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i32 @llvm.riscv.nds.flmism.i32(i32, i32) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+xandesperf" } # | attributes #1 = { nounwind speculatable memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_xandesperf5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557f7d94657b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2357b) # | #1 0x0000557f7d943515 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a20515) # | #2 0x0000557f7d946cbb SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5179133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f517918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5179133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f517911b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557f7d8dc24d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b924d) # | #8 0x0000557f7d8dc096 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b9096) # | #9 0x0000557f7d8c0f49 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599df49) # | #10 0x0000557f7d570176 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d176) # | #11 0x0000557f7d56fe93 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce93) # | #12 0x00007f517911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f517911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f517911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557f7d56fd81 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cd81) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.. ******************** Failed Tests (3297): Clang :: CodeGen/2005-06-15-ExpandGotoInternalProblem.c Clang :: CodeGen/2005-09-24-AsmUserPrefix.c Clang :: CodeGen/2008-07-17-no-emit-on-error.c Clang :: CodeGen/AArch64/atomic-hint-template.cpp Clang :: CodeGen/AArch64/bf16-dotprod-intrinsics.c Clang :: CodeGen/AArch64/bf16-getset-intrinsics.c Clang :: CodeGen/AArch64/bf16-lane-intrinsics.c Clang :: CodeGen/AArch64/bf16-reinterpret-intrinsics.c Clang :: CodeGen/AArch64/builtin-shufflevector-fp8.c Clang :: CodeGen/AArch64/f16f32dot-intrinsics.c Clang :: CodeGen/AArch64/fp8-cast.c Clang :: CodeGen/AArch64/fp8-extract.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c Clang :: CodeGen/AArch64/neon-2velem.c Clang :: CodeGen/AArch64/neon-3v.c Clang :: CodeGen/AArch64/neon-dot-product.c Clang :: CodeGen/AArch64/neon-extract.c Clang :: CodeGen/AArch64/neon-fma.c Clang :: CodeGen/AArch64/neon-fp16fml.c Clang :: CodeGen/AArch64/neon-intrinsics-constrained.c Clang :: CodeGen/AArch64/neon-intrinsics.c Clang :: CodeGen/AArch64/neon-ldst-one-rcpc3.c Clang :: CodeGen/AArch64/neon-misc-constrained.c Clang :: CodeGen/AArch64/neon-misc.c Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem.c Clang :: CodeGen/AArch64/neon-shifts.c Clang :: CodeGen/AArch64/neon-tbl.c Clang :: CodeGen/AArch64/neon-vcmla.c Clang :: CodeGen/AArch64/neon-vcombine.c Clang :: CodeGen/AArch64/neon-vget-hilo.c Clang :: CodeGen/AArch64/neon-vsqadd-float-conversion.c Clang :: CodeGen/AArch64/neon/add.c Clang :: CodeGen/AArch64/neon/bf16-getset.c Clang :: CodeGen/AArch64/neon/conversion-fullfp16.c Clang :: CodeGen/AArch64/neon/f16-getset.c Clang :: CodeGen/AArch64/neon/fullfp16-constrained.c Clang :: CodeGen/AArch64/neon/fullfp16.c Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16.c Clang :: CodeGen/AArch64/neon/fused-multiply-constrained.c Clang :: CodeGen/AArch64/neon/fused-multiply.c Clang :: CodeGen/AArch64/neon/getset.c Clang :: CodeGen/AArch64/neon/intrinsics-constrained.c Clang :: CodeGen/AArch64/neon/intrinsics.c Clang :: CodeGen/AArch64/neon/load.c Clang :: CodeGen/AArch64/neon/perm.c Clang :: CodeGen/AArch64/neon/rounding-v8.5.c Clang :: CodeGen/AArch64/neon/rounding.c Clang :: CodeGen/AArch64/neon/store.c Clang :: CodeGen/AArch64/neon/subtraction.c Clang :: CodeGen/AArch64/neon/vpaddl.c Clang :: CodeGen/AArch64/neon/widen.c Clang :: CodeGen/AArch64/poly128.c Clang :: CodeGen/AArch64/poly64.c Clang :: CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp Clang :: CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c Clang :: CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_add.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_and.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_div.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_index.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_max.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_min.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_not.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c Clang :: CodeGen/AArch64/sve-vector-arith-ops.c Clang :: CodeGen/AArch64/sve-vector-bitwise-ops.c Clang :: CodeGen/AArch64/sve-vector-compare-ops.c Clang :: CodeGen/AArch64/sve-vector-shift-ops.c Clang :: CodeGen/AArch64/sve-vector-subscript-ops.c Clang :: CodeGen/AArch64/sve-vls-arith-ops.c Clang :: CodeGen/AArch64/sve-vls-bitwise-ops.c Clang :: CodeGen/AArch64/sve-vls-compare-ops.c Clang :: CodeGen/AArch64/sve-vls-shift-ops.c Clang :: CodeGen/AArch64/sve-vls-subscript-ops.c Clang :: CodeGen/AArch64/sve/addv.c Clang :: CodeGen/AArch64/sve/andv.c Clang :: CodeGen/AArch64/sve/dup.c Clang :: CodeGen/AArch64/sve/eorv.c Clang :: CodeGen/AArch64/sve/len.c Clang :: CodeGen/AArch64/sve/maxnmv.c Clang :: CodeGen/AArch64/sve/maxv.c Clang :: CodeGen/AArch64/sve/minnmv.c Clang :: CodeGen/AArch64/sve/minv.c Clang :: CodeGen/AArch64/sve/nand.c Clang :: CodeGen/AArch64/sve/nor.c Clang :: CodeGen/AArch64/sve/orn.c Clang :: CodeGen/AArch64/sve/orv.c Clang :: CodeGen/AArch64/sve/pfalse.c Clang :: CodeGen/AArch64/sve/recpe.c Clang :: CodeGen/AArch64/sve/recps.c Clang :: CodeGen/AArch64/sve/rsqrte.c Clang :: CodeGen/AArch64/sve/rsqrts.c Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c Clang :: CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c Clang :: CodeGen/AArch64/v8.1a-neon-intrinsics.c Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics.c Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics.c Clang :: CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c Clang :: CodeGen/AArch64/v8.6a-neon-intrinsics.c Clang :: CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c Clang :: CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c Clang :: CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c Clang :: CodeGen/RISCV/builtin-cpu-is.c Clang :: CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c Clang :: CodeGen/RISCV/riscv-xandesbfhcvt.c Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c Clang :: CodeGen/RISCV/riscv-xandesperf-rv32.c Clang :: CodeGen/RISCV/riscv-xandesperf-rv64.c Clang :: CodeGen/RISCV/riscv-xcvalu-c-api.c Clang :: CodeGen/RISCV/riscv-xcvalu.c Clang :: CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c Clang :: CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c Clang :: CodeGen/RISCV/rvb-intrinsics/zbb.c Clang :: CodeGen/RISCV/rvb-intrinsics/zbc.c Clang :: CodeGen/RISCV/rvb-intrinsics/zbkb.c Clang :: CodeGen/RISCV/rvb-intrinsics/zbkc.c Clang :: CodeGen/RISCV/rvb-intrinsics/zbkx.c Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c Clang :: CodeGen/RISCV/rvk-intrinsics/zksed.c Clang :: CodeGen/RISCV/rvk-intrinsics/zksh.c Clang :: CodeGen/RISCV/rvp-intrinsics.c Clang :: CodeGen/RISCV/rvv-builtin-reduce-ops.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c Clang :: CodeGen/RISCV/rvv-vls-arith-ops.c Clang :: CodeGen/RISCV/rvv-vls-bitwise-ops.c Clang :: CodeGen/RISCV/rvv-vls-compare-ops.c Clang :: CodeGen/RISCV/rvv-vls-shift-ops.c Clang :: CodeGen/RISCV/rvv-vls-subscript-ops.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c Clang :: CodeGen/SystemZ/zvector.c Clang :: CodeGen/WebAssembly/builtins-table-externref.c Clang :: CodeGen/WebAssembly/builtins-table-funcref.c Clang :: CodeGen/X86/avx-cmp-builtins.c Clang :: CodeGen/X86/avx-shuffle-builtins.c Clang :: CodeGen/X86/bfloat16-convert-half.c Clang :: CodeGen/X86/sse.c Clang :: CodeGen/aapcs-bitfield.c Clang :: CodeGen/arm-bf16-convert-intrinsics.c Clang :: CodeGen/arm-bf16-dotprod-intrinsics.c Clang :: CodeGen/arm-bf16-params-returns.c Clang :: CodeGen/arm-bf16-reinterpret-intrinsics.c Clang :: CodeGen/arm-cde-gpr.c Clang :: CodeGen/arm-cde-reinterpret.c Clang :: CodeGen/arm-cde-vec.c Clang :: CodeGen/arm-cde-vfp.c Clang :: CodeGen/arm-crc32.c Clang :: CodeGen/arm-mfp8.c Clang :: CodeGen/arm-mve-intrinsics/absneg.c Clang :: CodeGen/arm-mve-intrinsics/admin.c Clang :: CodeGen/arm-mve-intrinsics/bitwise-imm.c Clang :: CodeGen/arm-mve-intrinsics/compare.c Clang :: CodeGen/arm-mve-intrinsics/cplusplus.cpp Clang :: CodeGen/arm-mve-intrinsics/dup.c Clang :: CodeGen/arm-mve-intrinsics/get-set-lane.c Clang :: CodeGen/arm-mve-intrinsics/idup.c Clang :: CodeGen/arm-mve-intrinsics/load-store.c Clang :: CodeGen/arm-mve-intrinsics/predicates.c Clang :: CodeGen/arm-mve-intrinsics/reinterpret.c Clang :: CodeGen/arm-mve-intrinsics/scalar-shifts.c Clang :: CodeGen/arm-mve-intrinsics/scatter-gather.c Clang :: CodeGen/arm-mve-intrinsics/ternary.c Clang :: CodeGen/arm-mve-intrinsics/vabavq.c Clang :: CodeGen/arm-mve-intrinsics/vabdq.c Clang :: CodeGen/arm-mve-intrinsics/vadc.c Clang :: CodeGen/arm-mve-intrinsics/vaddq.c Clang :: CodeGen/arm-mve-intrinsics/vaddv.c Clang :: CodeGen/arm-mve-intrinsics/vandq.c Clang :: CodeGen/arm-mve-intrinsics/vbicq.c Clang :: CodeGen/arm-mve-intrinsics/vbrsrq.c Clang :: CodeGen/arm-mve-intrinsics/vcaddq.c Clang :: CodeGen/arm-mve-intrinsics/vclz.c Clang :: CodeGen/arm-mve-intrinsics/vcmlaq.c Clang :: CodeGen/arm-mve-intrinsics/vcmulq.c Clang :: CodeGen/arm-mve-intrinsics/vcvt.c Clang :: CodeGen/arm-mve-intrinsics/vcvt_anpm.c Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm.c Clang :: CodeGen/arm-mve-intrinsics/vector-shift-var.c Clang :: CodeGen/arm-mve-intrinsics/veorq.c Clang :: CodeGen/arm-mve-intrinsics/vhaddq.c Clang :: CodeGen/arm-mve-intrinsics/vhcaddq.c Clang :: CodeGen/arm-mve-intrinsics/vhsubq.c Clang :: CodeGen/arm-mve-intrinsics/vld24.c Clang :: CodeGen/arm-mve-intrinsics/vldr.c Clang :: CodeGen/arm-mve-intrinsics/vmaxaq.c Clang :: CodeGen/arm-mve-intrinsics/vmaxnmaq.c Clang :: CodeGen/arm-mve-intrinsics/vmaxnmq.c Clang :: CodeGen/arm-mve-intrinsics/vmaxq.c Clang :: CodeGen/arm-mve-intrinsics/vminaq.c Clang :: CodeGen/arm-mve-intrinsics/vminnmaq.c Clang :: CodeGen/arm-mve-intrinsics/vminnmq.c Clang :: CodeGen/arm-mve-intrinsics/vminq.c Clang :: CodeGen/arm-mve-intrinsics/vminvq.c Clang :: CodeGen/arm-mve-intrinsics/vmldav.c Clang :: CodeGen/arm-mve-intrinsics/vmlldav.c Clang :: CodeGen/arm-mve-intrinsics/vmovl.c Clang :: CodeGen/arm-mve-intrinsics/vmovn.c Clang :: CodeGen/arm-mve-intrinsics/vmulhq.c Clang :: CodeGen/arm-mve-intrinsics/vmullbq.c Clang :: CodeGen/arm-mve-intrinsics/vmulltq.c Clang :: CodeGen/arm-mve-intrinsics/vmulq.c Clang :: CodeGen/arm-mve-intrinsics/vornq.c Clang :: CodeGen/arm-mve-intrinsics/vorrq.c Clang :: CodeGen/arm-mve-intrinsics/vqaddq.c Clang :: CodeGen/arm-mve-intrinsics/vqdmlad.c Clang :: CodeGen/arm-mve-intrinsics/vqdmulhq.c Clang :: CodeGen/arm-mve-intrinsics/vqdmullbq.c Clang :: CodeGen/arm-mve-intrinsics/vqdmulltq.c Clang :: CodeGen/arm-mve-intrinsics/vqmovn.c Clang :: CodeGen/arm-mve-intrinsics/vqrdmulhq.c Clang :: CodeGen/arm-mve-intrinsics/vqsubq.c Clang :: CodeGen/arm-mve-intrinsics/vrev.c Clang :: CodeGen/arm-mve-intrinsics/vrhaddq.c Clang :: CodeGen/arm-mve-intrinsics/vrmulhq.c Clang :: CodeGen/arm-mve-intrinsics/vrnd.c Clang :: CodeGen/arm-mve-intrinsics/vshlc.c Clang :: CodeGen/arm-mve-intrinsics/vsubq.c Clang :: CodeGen/arm-neon-directed-rounding-constrained.c Clang :: CodeGen/arm-neon-directed-rounding.c Clang :: CodeGen/arm-neon-dot-product.c Clang :: CodeGen/arm-neon-endianness.c Clang :: CodeGen/arm-neon-fma.c Clang :: CodeGen/arm-neon-numeric-maxmin.c Clang :: CodeGen/arm-neon-shifts.c Clang :: CodeGen/arm-neon-vcadd.c Clang :: CodeGen/arm-neon-vcvtX.c Clang :: CodeGen/arm-neon-vget.c Clang :: CodeGen/arm-neon-vld.c Clang :: CodeGen/arm-neon-vst.c Clang :: CodeGen/arm-poly-add.c Clang :: CodeGen/arm-v8.1a-neon-intrinsics.c Clang :: CodeGen/arm-v8.2a-neon-intrinsics-generic.c Clang :: CodeGen/arm-v8.2a-neon-intrinsics.c Clang :: CodeGen/arm-v8.6a-neon-intrinsics.c Clang :: CodeGen/arm-vector_type-params-returns.c Clang :: CodeGen/arm64-crc32.c Clang :: CodeGen/arm64-lanes.c Clang :: CodeGen/arm64_vcopy.c Clang :: CodeGen/arm64_vcreate.c Clang :: CodeGen/arm64_vdupq_n_f64.c Clang :: CodeGen/arm_acle.c Clang :: CodeGen/arm_acle_swp.c Clang :: CodeGen/arm_neon_intrinsics.c Clang :: CodeGen/attr-counted-by-issue200014.c Clang :: CodeGen/builtin-align.c Clang :: CodeGen/builtins-arm-exclusive.c Clang :: CodeGen/builtins-arm.c Clang :: CodeGen/builtins-arm64.c Clang :: CodeGen/builtins-loongarch.c Clang :: CodeGen/builtins-riscv.c Clang :: CodeGen/cx-complex-range-real.c Clang :: CodeGen/cx-complex-range.c Clang :: CodeGen/distributed-thin-lto/backend-skip.ll Clang :: CodeGen/distributed-thin-lto/basic.ll Clang :: CodeGen/distributed-thin-lto/cfi-devirt.ll Clang :: CodeGen/distributed-thin-lto/cfi.ll Clang :: CodeGen/distributed-thin-lto/newpm.ll Clang :: CodeGen/distributed-thin-lto/objc-contract-pass.ll Clang :: CodeGen/distributed-thin-lto/supports-hot-cold-new.ll Clang :: CodeGen/linker-diagnostic.ll Clang :: CodeGen/memcmp-inline-builtin-to-asm.c Clang :: CodeGen/mozilla-ms-inline-asm.c Clang :: CodeGen/packed-structure.c Clang :: CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll Clang :: CodeGen/thinlto-funcattr-prop.ll Clang :: CodeGen/thinlto-multi-module.ll Clang :: CodeGen/thinlto-opaque-typed-mix.ll Clang :: CodeGen/thinlto_backend.ll Clang :: CodeGen/thinlto_backend_local_name_conflict.ll Clang :: CodeGen/thinlto_embed_bitcode.ll Clang :: CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu Clang :: CodeGenCXX/aarch64-sve-vector-conditional-op.cpp Clang :: CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp Clang :: CodeGenCXX/attr-musttail.cpp Clang :: CodeGenCXX/ctor-globalopt.cpp Clang :: CodeGenCXX/inline-then-fold-variadics.cpp Clang :: CodeGenCXX/thinlto_public_type_test_distributed.ll Clang :: CodeGenCXX/virtual-base-ctor.cpp Clang :: CodeGenCoroutines/coro-gro4.cpp Clang :: CodeGenCoroutines/pr65054.cpp Clang :: CodeGenHIP/offload-pgo-sections.hip Clang :: CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl Clang :: Modules/pr93497.cppm Testing Time: 159.67s Total Discovered Tests: 55927 Skipped : 37 (0.07%) Unsupported : 1675 (2.99%) Passed : 50889 (90.99%) Expectedly Failed: 29 (0.05%) Failed : 3297 (5.90%) FAILED: gen/clang/test/run-lit python3 bin/llvm-lit -sv ../../clang/test ninja: build stopped: subcommand failed. Command '['ninja', '-C', 'out/gn', 'check-clang']' returned non-zero exit status 1.